Lines Matching refs:AHB3SMENR

3459 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1…
3461 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()              SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN)
3463 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE()             SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SME…
3465 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE()             SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SME…
3467 #define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1S…
3469 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE()             SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SME…
3471 #define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE()            SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SM…
3473 #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE()            SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SM…
3475 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPI…
3477 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()             CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSM…
3479 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE()            CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4S…
3481 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE()            CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1S…
3483 #define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA…
3485 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE()            CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1S…
3487 #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE()           CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2…
3489 #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE()           CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4…