Lines Matching +full:fail +full:- +full:fast
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
73 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
74 …UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt …
75 …SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt …
76 …DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt …
77 …PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt …
78 …SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt …
134 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
159 … uint32_t RESERVED5[4]; /*!< Reserved, 0x30 - 0x3C */
161 … uint32_t RESERVED6[23];/*!< Reserved, 0x44 - 0x9C */
164 … uint32_t RESERVED9[3]; /*!< Reserved, 0xA8 - 0xB0 */
204 …uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 …
277 …ED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */
281 …ED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */
294 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
299 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
304 * @brief Inter-integrated Circuit Interface
362 …__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset:…
363 …__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset:…
364 …__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset:…
365 …__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset:…
366 …__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset:…
367 …__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset:…
368 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */
369 …__IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset:…
370 …__IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset:…
371 …t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
372 …__IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset:…
373 …__IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset:…
374 …t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */
389 … Address offset: 0x10-0x14 */
393 …__IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, …
424 … Address offset: 0xA0-0x104 */
426 … Address offset: 0x10C-0x144 */
448 * @brief Real-Time Clock
466 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
518 …SCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
524 …served, Address offset: 0x2C-0xFC */
525 …__IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
526 …__IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
527 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
528 …__IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
549 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
555 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
656 …__IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4…
660 * @brief Inter-Processor Communication
664 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
665 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
666 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
667 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
668 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
669 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
670 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
671 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
691 …4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
696 …4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
697 …8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
698 …8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
701 …2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
704 …10]; /*!< Reserved, Address offset: 0x98 - 0xBC */
707 …2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
720 …uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03F…
721 …__IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F…
729 …__IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h…
730 …__IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h…
739 …_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/
878 #define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identificati…
1503 … ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1602 … CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data regist…
3018 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3019 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3022 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Mont…
3025 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3026 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3027 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3028 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base …
3029 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3030 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3033 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output stor…
3034 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3035 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3036 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base…
3037 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3040 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3041 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3042 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3043 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3044 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3045 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3046 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' o…
3047 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3048 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3051 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3052 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3053 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3054 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last…
3055 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3056 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3057 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3058 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3061 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3062 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3063 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3064 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3065 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3066 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3067 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3070 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3073 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3074 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3075 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3076 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3077 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3078 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k val…
3079 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3080 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3081 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3082 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, pr…
3083 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3086 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3087 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3088 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3089 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3090 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3093 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3094 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3095 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3096 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3097 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3098 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3099 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3100 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3101 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3102 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, pa…
3103 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, pa…
3104 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3105 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3108 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3111 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3112 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CR…
3113 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CR…
3114 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv …
3115 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3116 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3117 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base …
3120 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3123 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3124 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3125 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3126 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3129 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3132 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3133 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3134 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3137 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3140 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3141 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3142 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3145 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3148 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3149 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3150 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3153 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3156 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3157 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3158 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3161 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3164 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3165 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3166 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3167 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3170 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3173 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3174 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3175 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3178 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3181 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3182 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3183 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3184 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3187 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3190 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3191 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3192 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3193 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3196 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3199 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3200 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3201 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3202 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3205 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3270 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programmin…
3273 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programmin…
3314 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programmin…
3337 …CC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail …
3340 … FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail …
3540 #define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast progra…
3543 #define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast progra…
3575 #define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast progra…
5133 /* Inter-integrated Circuit Interface (I2C) */
5210 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
5213 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
5242 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
5404 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
5409 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
5478 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-P…
5502 … PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */
5520 … PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5534 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-U…
5539 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< Wake-Up polarit…
5542 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 […
5545 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 […
5606 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regul…
5609 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regul…
5622 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up F…
5625 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up P…
5628 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up P…
5680 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up…
5683 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up…
5686 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up…
5689 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up…
5692 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up…
5695 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up…
5698 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up…
5701 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up…
5704 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up…
5707 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up…
5710 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-U…
5713 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-U…
5716 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-U…
5719 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-U…
5722 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-U…
5727 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Do…
5730 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Do…
5733 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Do…
5736 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Do…
5739 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Do…
5742 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Do…
5745 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Do…
5748 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Do…
5751 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Do…
5754 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Do…
5757 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-D…
5760 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-D…
5763 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-D…
5766 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-D…
5771 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up…
5774 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up…
5777 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up…
5780 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up…
5783 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up…
5786 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up…
5789 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up…
5792 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up…
5795 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up…
5798 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up…
5803 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Do…
5806 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Do…
5809 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Do…
5812 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Do…
5815 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Do…
5818 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Do…
5821 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Do…
5824 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Do…
5827 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Do…
5832 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-U…
5835 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-U…
5840 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-D…
5843 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-D…
5848 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Pin PE4 Pull-Up…
5853 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Pin PE4 Pull-Do…
5858 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up…
5863 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Do…
5888 … PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */
5902 … PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5906 #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-U…
7016 /* Real-Time Clock (RTC) */
7144 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Time-stamp inte…
7246 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-rel…
7490 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< Use a 8-second …
7493 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< Use a 16-second…
7519 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< RTC_TAMPx pull-…
7552 … RTC_ALRMASSR_MASKSS_Msk /*!< Alarm A mask the most-significant bits star…
7564 … RTC_ALRMBSSR_MASKSS_Msk /*!< Alarm B mask the most-significant bits star…
8336 …6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8339 …7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8342 …8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8345 …9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8348 … SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) dri…
8661 …r SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) ************…
8699 …r SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) ************…
8707 …SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) ************…
8785 …SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) ************…
8855 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
8861 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
9114 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
9139 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
9156 /*----------------------------------------------------------------------------*/
9194 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
9219 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
9236 /*----------------------------------------------------------------------------*/
9268 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
9287 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
9379 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-relo…
9428 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9446 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
9449 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
9479 …BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
9482 …DTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
9761 /* Inter-Processor Communication Controller (IPCC) */
10136 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - …
10145 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
10170 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - …
10191 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit…
10235 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate…
10238 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10243 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-…
10257 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power…
10260 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Se…
10299 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10355 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate…
10420 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate…
10423 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate…
10535 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
10551 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
10685 /*********************** UART Instances : Half-Duplex mode ********************/
10692 /*********************** UART Instances : Wake-up from Stop mode **************/
10914 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/