Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
18 * This software component is licensed by ST under BSD 3-Clause license,
21 * opensource.org/licenses/BSD-3-Clause
51 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
52 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
53 …HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt …
54 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
55 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
56 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
57 …SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt …
58 …DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt …
59 …PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt …
60 …SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt …
152 …CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt …
155 …SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt …
206 …WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins …
223 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
226 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
232 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
235 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
242 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
276 …__IO uint32_t PCSEL; /*!< ADC pre-channel selection, A…
289 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
294 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
299 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
320 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1…
330 __IO uint32_t CTR; /*!< ART accelerator - control register */
362 …[4]; /*!< Reserved, 0x030 - 0x03C */
371 …[8]; /*!< Reserved, 0x060 - 0x07C */
398 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
428 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
496 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
497 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
498 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
499 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
500 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
501 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
502 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
503 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
504 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
701 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
702 …t32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
703 …t32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
718 …__IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Addre…
719 …uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B …
739 … /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
749 …uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB …
750 … /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
751 … /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
752 …uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 …
753 … /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
754 …uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF …
756 …uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B …
760 …__IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Addre…
761 …uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 …
773 …uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F …
775 …uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF …
782 … /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
1017 * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
1018 * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
1068 …__IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Addr…
1087 …__IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Addr…
1096 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1105 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1143 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1144 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1159 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1164 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1186 …CR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1193 …uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 …
1195 …uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC …
1218 * @brief Inter-integrated Circuit Interface
1263 …ved20[4]; /* Reserved Address offset: 20h-2Ch */
1270 …ved48[2]; /* Reserved Address offset: 48h-4Ch */
1271 …MEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1272 …MEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1273 …MEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1274 …MEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1275 …UFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1276 …UFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1277 …UFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1278 …HTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1280 …UFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1281 …UFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1282 …UFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1283 …UFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1288 * @brief LCD-TFT Display Controller
1293 …uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 …
1299 …uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 …
1313 * @brief LCD-TFT Display layer x Controller
1403 …uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC …
1424 …uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C …
1450 …uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C A…
1455 * @brief Real-Time Clock
1473 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
1520 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1538 * @brief SPDIF-RX Interface
1577 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1582 …uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C …
1584 …uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 …
1605 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
1606 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
1615 …2_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1644 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1646 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1692 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1698 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
2034 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
2063 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2069 * @brief USB_OTG_IN_Endpoint-Specific_Register
2080 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2085 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2095 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
2137 … Address offset: 0x00-0x1FCC */
2138 …__IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, …
2142 …__IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, …
2143 …__IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, …
2144 …__IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, …
2145 …__IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, …
2146 …__IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, …
2147 …__IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, …
2148 …__IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, …
2149 …__IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, …
2150 … Address offset: 0x2000-0x2004 */
2151 …__IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing function…
2152 … Address offset: 0x200C-0x2020 */
2153 …__IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 regis…
2155 …__IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modific…
2156 … Address offset: 0x2030-0x2104 */
2157 …__IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modificati…
2158 … Address offset: 0x210C-0x3004 */
2159 …__IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing function…
2160 … Address offset: 0x300C-0x3020 */
2161 …__IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 regis…
2163 …__IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modific…
2164 … Address offset: 0x3030-0x3104 */
2165 …__IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modificati…
2166 … Address offset: 0x310C-0x4004 */
2167 …__IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functio…
2168 … Address offset: 0x400C-0x5004 */
2169 …__IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing function…
2170 … Address offset: 0x500C-0x6004 */
2171 …__IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing function…
2172 … Address offset: 0x600C-0x7004 */
2173 …__IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing function…
2174 … Address offset: 0x700C-0x8004 */
2175 …__IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing function…
2176 … Address offset: 0x800C-0x8020 */
2177 …__IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 regis…
2179 …__IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modific…
2180 … Address offset: 0x8030-0x8104 */
2181 …__IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modificati…
2182 … Address offset: 0x810C-0x42020 */
2183 …__IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 regi…
2184 …__IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification re…
2185 … Address offset: 0x4202C-0x420FC */
2186 …__IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, …
2187 …__IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, …
2188 …__IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modificatio…
2189 … Address offset: 0x4210C-0x430FC */
2190 …__IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, …
2191 …__IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, …
2192 …__IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modificatio…
2193 … Address offset: 0x4310C-0x44020 */
2194 …__IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 regi…
2195 …__IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification re…
2196 … Address offset: 0x4402C-0x440FC */
2197 …__IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, …
2198 …__IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, …
2199 …__IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modificatio…
2200 … Address offset: 0x4410C-0x450FC */
2201 …__IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, …
2202 …__IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, …
2203 …__IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modificatio…
2204 … Address offset: 0x4510C-0x460FC */
2205 …__IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, …
2206 …__IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, …
2207 …__IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modificatio…
2208 … Address offset: 0x4610C-0x470FC */
2209 …__IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, …
2210 …__IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, …
2211 …__IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modificatio…
2212 … Address offset: 0x4710C-0x480FC */
2213 …__IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, …
2214 …__IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, …
2215 …__IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modificatio…
2230 …UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2232 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI-…
2233 … (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge …
3143 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3146 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3149 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3152 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
3978 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4239 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
4719 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
4722 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
5561 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5626 /* HDMI-CEC (CEC) */
5683 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
5689 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
5713 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
5716 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
5724 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
5730 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
5754 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
5757 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
5775 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
6001 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-…
6006 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-…
6011 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-b…
6016 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-…
6021 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-…
6026 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-b…
6031 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
6034 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
6039 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
6042 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
6047 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
6050 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
6381 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
6384 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6420 …_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6423 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion…
6630 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
6938 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap …
6970 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet spe…
6979 … ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6991 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit ma…
7015 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Pa…
7018 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Pa…
7038 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP …
7060 …wards all control frames except Pause packets to application even if they fail the Address Filter …
7063 …ARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter …
7166 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-…
7169 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7175 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLA…
7200 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7236 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7272 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quan…
7382 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up …
7385 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FI…
7388 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Pa…
7394 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Pa…
7400 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Pa…
7408 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7411 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet fi…
7469 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Vers…
7472 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined …
7526 …R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7529 …0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7532 …R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7544 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Ti…
7556 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-u…
7568 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Suppo…
7612 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestam…
7835 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset…
8057 … ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8060 … ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8089 /* Bit definition for Ethernet MAC Sub-second Increment Register */
8092 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Incre…
8095 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond …
8105 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-second…
8118 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-secon…
8194 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timesta…
8199 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timesta…
8387 …MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
8390 … ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8434 …QDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8438 … ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deact…
8441 … ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activ…
8507 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned B…
9517 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sam…
9932 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Verti…
9935 …PE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enabl…
9938 …E DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enabl…
9941 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Verti…
9944 …E DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enab…
9947 … DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enab…
9950 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-…
9953 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Comma…
10143 …_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
10269 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-P…
10304 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-…
10644 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Recep…
10696 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Tran…
10749 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read…
10802 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read …
10855 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Writ…
10912 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write…
10965 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around…
11037 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Con…
11045 …R_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
11079 …R_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
11163 …R_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
11191 …R_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
11389 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Sp…
11392 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Pow…
11395 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit …
11398 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit E…
11495 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Sp…
11498 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Pow…
11501 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit …
11504 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit E…
11601 … DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
11604 …PRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
11607 …R1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
11610 …IR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
11749 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Verti…
11752 …BPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enabl…
11755 …PE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enabl…
11758 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Verti…
11761 …PE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enab…
11764 … DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enab…
11770 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Comma…
11951 …R_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
12077 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-P…
12112 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-…
12336 … DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on …
12339 …0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on …
12342 …1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on …
12357 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enabl…
12360 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLK…
12363 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLK…
12366 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSP…
12369 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HST…
12372 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZ…
12375 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPX…
12378 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSE…
12381 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPX…
12384 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLK…
12389 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Tran…
12399 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Tran…
12409 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power trans…
12419 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power trans…
12433 …RXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensat…
12443 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Tran…
12453 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Tran…
12463 …PM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
12467 …LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering …
12478 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
12506 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
12534 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
12562 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
12591 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
12619 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
12647 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
12675 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
12704 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
13926 #define DUAL_BANK /* Dual-bank Flash */
13989 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program …
14039 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program …
14169 #define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 b…
14172 #define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 b…
14181 …SLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status …
14208 …AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start statu…
14211 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-o…
14224 …M7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
14227 …M7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
14232 …M4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */
14235 …M4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */
14374 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
14382 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
14433 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
14441 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
14752 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
16350 /* Inter-integrated Circuit Interface (I2C) */
16424 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
16427 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
16456 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
16618 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
16623 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
16918 /* LCD-TFT Display Controller (LTDC) */
16962 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
17393 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
17705 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
17834 … /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
17869 … /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
20112 /* Real-Time Clock (RTC) */
20871 /* SPDIF-RX Interface */
20907 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
20971 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
21688 …KFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
21770 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail…
21773 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail In…
21827 …AILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
21947 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
21953 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
22041 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
22132 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
22135 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
22150 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
22532 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode …
22535 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode …
22538 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode …
22541 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode …
22544 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mo…
22547 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mo…
22550 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mo…
22553 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mo…
22871 #define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk /*!<Cortex-M4 LOCKUP…
22880 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP…
22918 …G_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
22956 #define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk /*!< Boot Cortex-M4 …
22959 #define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk /*!< Boot Cortex-M7 …
22968 #define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk /*!< Boot Cortex-M7 …
22972 #define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk /*!< Boot Cortex-M7 …
22976 #define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk /*!< Boot Cortex-M4 …
22982 #define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk /*!< Boot Cortex-M4 …
23117 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
23123 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
23371 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
23396 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
23413 /*----------------------------------------------------------------------------*/
23452 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
23477 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
23494 /*----------------------------------------------------------------------------*/
23597 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
23646 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
23664 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
23667 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
23722 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
23741 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
24331 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
24340 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
24365 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
24389 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
24433 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
24436 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
24441 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
24455 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
24458 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
24497 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
24558 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
24617 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
24620 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
24890 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
24906 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
25401 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull…
25508 …MISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
25511 …_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
27070 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
27098 …EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
27115 …EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
27132 …EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
27149 …EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
27166 …EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
27939 …DATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
28018 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
28021 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
28024 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
28027 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
28051 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
28054 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
28068 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
28079 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
28130 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
28169 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
28234 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
28237 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
28240 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
28251 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
28257 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
28402 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
28791 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
29069 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
29362 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
29796 /******************** TIM Instances : Advanced-control timers *****************/
29800 /******************** TIM Instances : Advanced-control timers *****************/
30185 /********************* UART Instances : Half-Duplex mode **********************/
30217 /****************** UART Instances : Wake-up from Stop mode *******************/