Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
18 * This software component is licensed by ST under BSD 3-Clause license,
21 * opensource.org/licenses/BSD-3-Clause
51 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
52 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
53 …HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt …
54 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
55 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
56 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
57 …SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt …
58 …DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt …
59 …PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt …
60 …SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt …
150 …CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt …
153 …SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt …
188 …WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins …
216 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
218 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
225 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
254 …__IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, A…
267 …uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C …
272 …uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C …
277 …uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C …
298 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1…
332 …[4]; /*!< Reserved, 0x030 - 0x03C */
341 …[8]; /*!< Reserved, 0x060 - 0x07C */
368 …[2]; /*!< Reserved, 0x0E8 - 0x0EC */
398 …__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x…
476 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
477 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
478 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
479 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
480 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
481 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
482 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
483 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
484 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
548 __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */
550 …__IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC …
591 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
593 __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */
711 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
712 …t32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
713 …t32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
934 * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
935 * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
984 …__IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Addr…
1011 … BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1020 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1058 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1059 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1074 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1079 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1101 …CR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1109 …uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 …
1111 …uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC …
1120 …VED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */
1133 * @brief Inter-integrated Circuit Interface
1166 * @brief LCD-TFT Display Controller
1171 …uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 …
1177 …uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 …
1191 * @brief LCD-TFT Display layer x Controller
1281 …uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC …
1302 …uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C …
1308 * @brief Real-Time Clock
1326 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
1373 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1391 * @brief SPDIF-RX Interface
1430 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1435 …uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C …
1437 …uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 …
1458 …__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-…
1459 …__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-…
1464 …uint32_t Reserved[12]; /* Reserved Address offset: 110h-1…
1493 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1495 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1541 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1547 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1688 …__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address o…
1689 …__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address o…
1690 …__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address o…
1691 …__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address o…
1719 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1722 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1723 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1732 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1859 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1888 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1894 * @brief USB_OTG_IN_Endpoint-Specific_Register
1905 …uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1910 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1920 …uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1…
1967 …ED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1970 …ED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1976 …ED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1982 …ED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1988 …ED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1990 …ED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1992 …ED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1998 …ED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
2000 …ED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
2006 …ED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
2008 …ED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
2010 …ED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */
2027 …PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */
2074 … Address offset: 0x00-0x1FCC */
2075 …__IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, …
2079 …__IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, …
2080 …__IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, …
2081 …__IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, …
2082 …__IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, …
2083 …__IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, …
2084 …__IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, …
2085 …__IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, …
2086 …__IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, …
2087 … Address offset: 0x2000-0x2004 */
2088 …__IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing function…
2089 … Address offset: 0x200C-0x2020 */
2090 …__IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 regis…
2092 …__IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modific…
2093 … Address offset: 0x2030-0x2104 */
2094 …__IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modificati…
2095 … Address offset: 0x210C-0x3004 */
2096 …__IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing function…
2097 … Address offset: 0x300C-0x3020 */
2098 …__IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 regis…
2100 …__IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modific…
2101 … Address offset: 0x3030-0x3104 */
2102 …__IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modificati…
2103 … Address offset: 0x310C-0x4004 */
2104 …__IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functio…
2105 … Address offset: 0x400C-0x5004 */
2106 …__IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing function…
2107 … Address offset: 0x500C-0x6004 */
2108 …__IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing function…
2109 … Address offset: 0x600C-0x7004 */
2110 …__IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing function…
2111 … Address offset: 0x700C-0x8004 */
2112 …__IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing function…
2113 … Address offset: 0x800C-0x8020 */
2114 …__IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 regis…
2116 …__IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modific…
2117 … Address offset: 0x8030-0x8104 */
2118 …__IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modificati…
2119 … Address offset: 0x810C-0x9004 */
2120 …__IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing function…
2121 … Address offset: 0x900C-0x9020 */
2122 …__IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 regis…
2123 … Address offset: 0x9028-0x9104 */
2124 …__IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modificati…
2125 … Address offset: 0x910C-0x42020 */
2126 …__IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 regi…
2127 …__IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification re…
2128 … Address offset: 0x4202C-0x420FC */
2129 …__IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, …
2130 …__IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, …
2131 …__IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modificatio…
2132 … Address offset: 0x4210C-0x430FC */
2133 …__IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, …
2134 …__IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, …
2135 …__IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modificatio…
2136 … Address offset: 0x4310C-0x44020 */
2137 …__IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 regi…
2138 …__IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification re…
2139 … Address offset: 0x4402C-0x440FC */
2140 …__IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, …
2141 …__IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, …
2142 …__IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modificatio…
2143 … Address offset: 0x4410C-0x450FC */
2144 …__IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, …
2145 …__IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, …
2146 …__IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modificatio…
2147 … Address offset: 0x4510C-0x460FC */
2148 …__IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, …
2149 …__IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, …
2150 …__IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modificatio…
2151 … Address offset: 0x4610C-0x470FC */
2152 …__IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, …
2153 …__IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, …
2154 …__IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modificatio…
2170 …L) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */
2171 …L) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */
2172 …BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */
2174 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI-…
2175 … (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge …
3104 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift…
3107 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift…
3110 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift…
3113 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift…
4044 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
4292 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
4772 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-match…
4775 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-match…
5614 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core…
5679 /* HDMI-CEC (CEC) */
5736 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
5742 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
5766 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
5769 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
5777 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
5783 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
5807 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
5810 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
5889 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data registe…
6234 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-…
6239 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-…
6244 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-b…
6249 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-…
6254 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-…
6259 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-b…
6264 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-…
6267 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-…
6272 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-…
6275 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-…
6280 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-b…
6283 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-b…
6614 …FFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offse…
6617 … DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6653 …_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6656 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion…
6863 …_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting co…
7171 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap …
7203 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet spe…
7212 … ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
7224 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit ma…
7248 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Pa…
7251 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Pa…
7271 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP …
7293 …wards all control frames except Pause packets to application even if they fail the Address Filter …
7296 …ARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter …
7399 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-…
7402 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7408 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLA…
7433 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7469 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN …
7505 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quan…
7615 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up …
7618 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FI…
7621 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Pa…
7627 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Pa…
7633 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Pa…
7641 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7644 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet fi…
7702 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Vers…
7705 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined …
7759 …R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7762 …0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7765 …R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7777 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Ti…
7789 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-u…
7801 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Suppo…
7845 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestam…
8068 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset…
8290 … ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
8293 … ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
8322 /* Bit definition for Ethernet MAC Sub-second Increment Register */
8325 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Incre…
8328 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond …
8338 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-second…
8351 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-secon…
8427 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timesta…
8432 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timesta…
8620 …MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
8623 … ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8667 …QDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8671 … ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deact…
8674 … ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activ…
8740 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned B…
9750 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sam…
11119 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program …
11169 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program …
11296 …SLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status …
11320 …AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start statu…
11323 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-o…
11336 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 b…
11339 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 b…
11411 …ZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
11421 …_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
11428 …_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
11597 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
11605 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11656 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
11664 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11975 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
13258 /* Inter-integrated Circuit Interface (I2C) */
13332 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
13335 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
13364 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
13526 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
13531 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
13574 /* LCD-TFT Display Controller (LTDC) */
13618 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT control…
14049 … MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
14411 … OTFDEC_REG_CONFIGR_REG_EN_Msk /*!< Region on-the-fly decryption enab…
14429 …FIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk /*!< Region key 8-bit CRC */
14482 … OTFDEC_ISR_XONEIF_Msk /*!< Execute-only Error Interrupt …
14495 … OTFDEC_ICR_XONEIF_Msk /*!< Execute-only Error Interrupt …
14508 … OTFDEC_IER_XONEIE_Msk /*!< Execute-only Error Interrupt …
14541 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up…
14659 … /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
16857 /* Real-Time Clock (RTC) */
17616 /* SPDIF-RX Interface */
17652 … SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchron…
17716 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error …
18433 …KFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
18515 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail…
18518 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail In…
18572 …AILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
18692 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode …
18698 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polyn…
18786 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Dat…
18877 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet availa…
18880 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space …
18895 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet availa…
19044 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode …
19047 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode …
19050 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode …
19053 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode …
19056 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mo…
19059 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mo…
19062 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mo…
19065 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mo…
19076 #define SYSCFG_PMCR_I2C5_FMP SYSCFG_PMCR_I2C5_FMP_Msk /*!< I2C5 Fast mode …
19377 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP…
19412 …G_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
19535 #define SYSCFG_UR17_TCM_AXI_CFG SYSCFG_UR17_TCM_AXI_CFG_Msk /*!< ITCM-RAM / AXI-…
19695 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
19701 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
19949 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
19974 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
19991 /*----------------------------------------------------------------------------*/
20030 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
20055 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
20072 /*----------------------------------------------------------------------------*/
20175 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-relo…
20224 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
20242 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
20245 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
20300 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
20319 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
20772 #define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode …
21397 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - B…
21406 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
21431 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - B…
21455 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit …
21499 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate …
21502 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
21507 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-O…
21521 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power …
21524 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Sel…
21563 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
21624 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate …
21683 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate …
21686 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate …
21956 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
21972 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
22247 …DATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
22326 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral se…
22329 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral se…
22332 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral se…
22335 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral se…
22359 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid…
22362 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid…
22376 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only…
22387 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length …
22438 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeou…
22477 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on progra…
22542 … USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed …
22545 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
22548 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
22559 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power c…
22565 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resum…
22710 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SE…
23099 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up dete…
23377 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed devic…
23670 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SE…
24125 /******************** TIM Instances : Advanced-control timers *****************/
24129 /******************** TIM Instances : Advanced-control timers *****************/
24571 /********************* UART Instances : Half-Duplex mode **********************/
24609 /****************** UART Instances : Wake-up from Stop mode *******************/