1537   EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0);
3292   DCDC->EN_SET    = DCDC_EN_EN;  in EMU_DCDCBoostInit()
3294   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_DCDCBoostInit()
3301   DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK))  in EMU_DCDCBoostInit()
3303   DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT)  in EMU_DCDCBoostInit()
3305   DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT)  in EMU_DCDCBoostInit()
3336   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_EM01BoostPeakCurrentSet()
3344   BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL,  in EMU_EM01BoostPeakCurrentSet()
3414   DCDC->EN_SET = DCDC_EN_EN;  in EMU_DCDCModeSet()
3416   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_DCDCModeSet()
3427     currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT;  in EMU_DCDCModeSet()
3431       DCDC->CTRL_CLR = DCDC_CTRL_MODE;  in EMU_DCDCModeSet()
3432       while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) {  in EMU_DCDCModeSet()
3441     DCDC->EN_CLR = DCDC_EN_EN;  in EMU_DCDCModeSet()
3444     while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) {  in EMU_DCDCModeSet()
3451       DCDC->IF_CLR = DCDC_IF_REGULATION;  in EMU_DCDCModeSet()
3452       DCDC->CTRL_SET = DCDC_CTRL_MODE;  in EMU_DCDCModeSet()
3454       while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) {  in EMU_DCDCModeSet()
3490   DCDC->EN_SET    = DCDC_EN_EN;  in EMU_DCDCInit()
3492   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_DCDCInit()
3507   DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK  in EMU_DCDCInit()
3512   DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK))  in EMU_DCDCInit()
3515   DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT)  in EMU_DCDCInit()
3517   DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT)  in EMU_DCDCInit()
3560   bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0);  in EMU_EM01PeakCurrentSet()
3561   DCDC->EN_SET = DCDC_EN_EN;  in EMU_EM01PeakCurrentSet()
3564   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_EM01PeakCurrentSet()
3576   BUS_RegMaskedWrite(&DCDC->EM01CTRL0,  in EMU_EM01PeakCurrentSet()
3582     DCDC->EN_CLR = DCDC_EN_EN;  in EMU_EM01PeakCurrentSet()
3620   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_DCDCSetPFMXModePeakCurrent()
3628   DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK)  in EMU_DCDCSetPFMXModePeakCurrent()
3659   dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0);  in EMU_DCDCSetPFMXTimeoutMaxCtrl()
3667   DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK)  in EMU_DCDCSetPFMXTimeoutMaxCtrl()