179   primDescr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;  in DMA_Prepare()
185     descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;  in DMA_Prepare()
216     DMA->CHUSEBURSTS = chBit;  in DMA_Prepare()
218     DMA->CHUSEBURSTC = chBit;  in DMA_Prepare()
222     DMA->CHALTC = chBit;  in DMA_Prepare()
224     DMA->CHALTS = chBit;  in DMA_Prepare()
270   pending  = DMA->IF;  in DMA_IRQHandler()
271   pending &= DMA->IEN;  in DMA_IRQHandler()
278   prio        = DMA->CHPRIS;  in DMA_IRQHandler()
286         DMA_DESCRIPTOR_TypeDef *descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);  in DMA_IRQHandler()
291         DMA->IFC = chmask;  in DMA_IRQHandler()
375   DMA->CHENS   = chBit; /* Enable the channel. */  in DMA_ActivateAuto()
376   DMA->CHSWREQ = chBit; /* Activate with the software request. */  in DMA_ActivateAuto()
436   DMA->CHENS = 1 << channel;  in DMA_ActivateBasic()
520   DMA->CHENS = 1 << channel;  in DMA_ActivatePingPong()
574   descr = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE) + channel;  in DMA_ActivateScatterGather()
581   descr->DSTEND = (uint32_t *)((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)  in DMA_ActivateScatterGather()
631   DMA->CHALTC = chBit;  in DMA_ActivateScatterGather()
634   DMA->CHENS = chBit;  in DMA_ActivateScatterGather()
639     DMA->CHSWREQ = chBit;  in DMA_ActivateScatterGather()
669   descr               = (DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE);  in DMA_CfgChannel()
674     DMA->CHPRIS = 1 << channel;  in DMA_CfgChannel()
676     DMA->CHPRIC = 1 << channel;  in DMA_CfgChannel()
680   DMA->CH[channel].CTRL = cfg->select;  in DMA_CfgChannel()
684     DMA->IFC = (1 << channel);  in DMA_CfgChannel()
685     BUS_RegBitWrite(&(DMA->IEN), channel, 1);  in DMA_CfgChannel()
687     BUS_RegBitWrite(&(DMA->IEN), channel, 0);  in DMA_CfgChannel()
740     descr = (DMA_DESCRIPTOR_TypeDef *)DMA->CTRLBASE;  in DMA_CfgDescr()
742     descr = (DMA_DESCRIPTOR_TypeDef *)DMA->ALTCTRLBASE;  in DMA_CfgDescr()
781       DMA->LOOP0 = (cfg->enable    << _DMA_LOOP0_EN_SHIFT)  in DMA_CfgLoop()
785       DMA->LOOP1 = (cfg->enable    << _DMA_LOOP1_EN_SHIFT)  in DMA_CfgLoop()
812   DMA->RECT0 = (cfg->dstStride   << _DMA_RECT0_DSTSTRIDE_SHIFT)  in DMA_CfgRect()
915     DMA->CHENS = 1 << channel;  in DMA_ChannelEnable()
917     DMA->CHENC = 1 << channel;  in DMA_ChannelEnable()
939   return (bool)((DMA->CHENS >> channel) & 1);  in DMA_ChannelEnabled()
961     BUS_RegBitWrite(&DMA->CHREQMASKC, channel, 1);  in DMA_ChannelRequestEnable()
963     BUS_RegBitWrite(&DMA->CHREQMASKS, channel, 1);  in DMA_ChannelRequestEnable()
1008   DMA->IEN = DMA_IEN_ERR;  in DMA_Init()
1013   DMA->CTRLBASE = (uint32_t)(init->controlBlock);  in DMA_Init()
1016   DMA->CONFIG = ((uint32_t)(init->hprot) << _DMA_CONFIG_CHPROT_SHIFT)  in DMA_Init()
1087     descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->CTRLBASE)) + channel;  in DMA_RefreshPingPong()
1089     descr = ((DMA_DESCRIPTOR_TypeDef *)(DMA->ALTCTRLBASE)) + channel;  in DMA_RefreshPingPong()
1112     DMA->CHUSEBURSTS = chBit;  in DMA_RefreshPingPong()
1114     DMA->CHUSEBURSTC = chBit;  in DMA_RefreshPingPong()
1143   DMA->CONFIG      = _DMA_CONFIG_RESETVALUE;  in DMA_Reset()
1144   DMA->CHUSEBURSTC = _DMA_CHUSEBURSTC_MASK;  in DMA_Reset()
1145   DMA->CHREQMASKC  = _DMA_CHREQMASKC_MASK;  in DMA_Reset()
1146   DMA->CHENC       = _DMA_CHENC_MASK;  in DMA_Reset()
1147   DMA->CHALTC      = _DMA_CHALTC_MASK;  in DMA_Reset()
1148   DMA->CHPRIC      = _DMA_CHPRIC_MASK;  in DMA_Reset()
1149   DMA->ERRORC      = DMA_ERRORC_ERRORC;  in DMA_Reset()
1150   DMA->IEN         = _DMA_IEN_RESETVALUE;  in DMA_Reset()
1151   DMA->IFC         = _DMA_IFC_MASK;  in DMA_Reset()
1155     DMA->CH[i].CTRL = _DMA_CH_CTRL_RESETVALUE;  in DMA_Reset()