203 void QSPI_Init(QSPI_TypeDef * qspi, const QSPI_Init_TypeDef * init);
204 void QSPI_ReadConfig(QSPI_TypeDef * qspi, const QSPI_ReadConfig_TypeDef * config);
205 void QSPI_WriteConfig(QSPI_TypeDef * qspi, const QSPI_WriteConfig_TypeDef * config);
206 void QSPI_ExecStigCmd(QSPI_TypeDef * qspi, const QSPI_StigCmd_TypeDef * stigCmd);
215 __STATIC_INLINE void QSPI_WaitForIdle(QSPI_TypeDef * qspi)  in QSPI_WaitForIdle()  argument
217   while ((qspi->CONFIG & _QSPI_CONFIG_IDLE_MASK) == 0)  in QSPI_WaitForIdle()
232 __STATIC_INLINE uint16_t QSPI_GetWriteLevel(QSPI_TypeDef * qspi)  in QSPI_GetWriteLevel()  argument
234   return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK)  in QSPI_GetWriteLevel()
249 __STATIC_INLINE uint16_t QSPI_GetReadLevel(QSPI_TypeDef * qspi)  in QSPI_GetReadLevel()  argument
251   return (qspi->SRAMFILL & _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK)  in QSPI_GetReadLevel()
265 __STATIC_INLINE void QSPI_Enable(QSPI_TypeDef * qspi, bool enable)  in QSPI_Enable()  argument
267   BUS_RegBitWrite(&qspi->CONFIG, _QSPI_CONFIG_ENBSPI_SHIFT, enable ? 1 : 0);  in QSPI_Enable()
280 __STATIC_INLINE uint32_t QSPI_IntGet(QSPI_TypeDef * qspi)  in QSPI_IntGet()  argument
282   return qspi->IRQSTATUS;  in QSPI_IntGet()
295 __STATIC_INLINE void QSPI_IntClear(QSPI_TypeDef * qspi, uint32_t flags)  in QSPI_IntClear()  argument
297   qspi->IRQSTATUS = flags;  in QSPI_IntClear()
310 __STATIC_INLINE void QSPI_IntEnable(QSPI_TypeDef * qspi, uint32_t flags)  in QSPI_IntEnable()  argument
312   qspi->IRQMASK = flags & (~_QSPI_IRQMASK_MASK);  in QSPI_IntEnable()
325 __STATIC_INLINE void QSPI_IntDisable(QSPI_TypeDef * qspi, uint32_t flags)  in QSPI_IntDisable()  argument
327   qspi->IRQMASK = ~flags & (~_QSPI_IRQMASK_MASK);  in QSPI_IntDisable()