3622   uint32_t calReg;  in vmonCalibratedThreshold()  local
3627       calReg = DEVINFO->VMONCAL0;  in vmonCalibratedThreshold()
3628       tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3630              + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3632       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3634               + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK)  in vmonCalibratedThreshold()
3638       calReg = DEVINFO->VMONCAL0;  in vmonCalibratedThreshold()
3639       tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3641              + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3643       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3645               + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK)  in vmonCalibratedThreshold()
3649       calReg = DEVINFO->VMONCAL1;  in vmonCalibratedThreshold()
3650       tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3652              + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3654       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3656               + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK)  in vmonCalibratedThreshold()
3660       calReg = DEVINFO->VMONCAL1;  in vmonCalibratedThreshold()
3661       tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3663              + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3665       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3667               + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK)  in vmonCalibratedThreshold()
3672       calReg = DEVINFO->VMONCAL2;  in vmonCalibratedThreshold()
3673       tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3675              + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3677       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3679               + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK)  in vmonCalibratedThreshold()
3685       calReg = DEVINFO->VMONCAL2;  in vmonCalibratedThreshold()
3686       tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3688              + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK)  in vmonCalibratedThreshold()
3690       tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK)  in vmonCalibratedThreshold()
3692               + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK)  in vmonCalibratedThreshold()