54 static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) {  in set_raw_irq_handler_and_unlock()  argument
56     get_vtable()[VTABLE_FIRST_IRQ + num] = handler;  in set_raw_irq_handler_and_unlock()
61 void irq_set_enabled(uint num, bool enabled) {  in irq_set_enabled()  argument
62     check_irq_param(num);  in irq_set_enabled()
64     irq_set_mask_n_enabled(num / 32, 1u << (num % 32), enabled);  in irq_set_enabled()
67 bool pico_irq_is_enabled(uint num) {  in pico_irq_is_enabled()  argument
68     check_irq_param(num);  in pico_irq_is_enabled()
70     return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)));  in pico_irq_is_enabled()
72     return 0 != (hazard3_irqarray_read(RVCSR_MEIEA_OFFSET, num / 16) & (1u << (num % 16)));  in pico_irq_is_enabled()
74     return 0 != (nvic_hw->iser[num/32] & (1 << num % 32));  in pico_irq_is_enabled()
117 void irq_set_pending(uint num) {  in irq_set_pending()  argument
118     check_irq_param(num);  in irq_set_pending()
122     hazard3_irqarray_set(RVCSR_MEIFA_OFFSET, num / 16, 1u << (num % 16));  in irq_set_pending()
125     *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;  in irq_set_pending()
127     nvic_hw->ispr[num/32] = 1 << (num % 32);  in irq_set_pending()
214 irq_handler_t irq_get_vtable_handler(uint num) {  in irq_get_vtable_handler()  argument
215     check_irq_param(num);  in irq_get_vtable_handler()
216     return get_vtable()[VTABLE_FIRST_IRQ + num];  in irq_get_vtable_handler()
219 void irq_set_exclusive_handler(uint num, irq_handler_t handler) {  in irq_set_exclusive_handler()  argument
220     check_irq_param(num);  in irq_set_exclusive_handler()
224     __unused irq_handler_t current = irq_get_vtable_handler(num);  in irq_set_exclusive_handler()
226     set_raw_irq_handler_and_unlock(num, handler, save);  in irq_set_exclusive_handler()
232 irq_handler_t irq_get_exclusive_handler(uint num) {  in irq_get_exclusive_handler()  argument
233     check_irq_param(num);  in irq_get_exclusive_handler()
237     irq_handler_t current = irq_get_vtable_handler(num);  in irq_get_exclusive_handler()
356 void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {  in irq_add_shared_handler()  argument
357     check_irq_param(num);  in irq_add_shared_handler()
361     irq_set_exclusive_handler(num, handler);  in irq_add_shared_handler()
369     irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num];  in irq_add_shared_handler()
448     set_raw_irq_handler_and_unlock(num, vtable_handler, save);  in irq_add_shared_handler()
470 void irq_remove_handler(uint num, irq_handler_t handler) {  in irq_remove_handler()  argument
474     irq_handler_t vtable_handler = get_vtable()[VTABLE_FIRST_IRQ + num];  in irq_remove_handler()
482             bool was_enabled = pico_irq_is_enabled(num);  in irq_remove_handler()
483             irq_set_enabled(num, false);  in irq_remove_handler()
499             hard_assert(!exception || exception == num + VTABLE_FIRST_IRQ);  in irq_remove_handler()
567             irq_set_enabled(num, was_enabled);  in irq_remove_handler()
575     set_raw_irq_handler_and_unlock(num, vtable_handler, save);  in irq_remove_handler()
587 void irq_set_priority(uint num, uint8_t hardware_priority) {  in irq_set_priority()  argument
588     check_irq_param(num);  in irq_set_priority()
595     hazard3_irqarray_clear(RVCSR_MEIPRA_OFFSET, num / 4, 0xfu << (4 * (num % 4)));  in irq_set_priority()
596     hazard3_irqarray_set(RVCSR_MEIPRA_OFFSET, num / 4, hardware_priority << (4 * (num % 4)));  in irq_set_priority()
598     io_rw_32 *p = nvic_ipr0() + (num >> 2);  in irq_set_priority()
600     *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));  in irq_set_priority()
604 uint irq_get_priority(uint num) {  in irq_get_priority()  argument
605     check_irq_param(num);  in irq_get_priority()
607     uint16_t priority_row = (uint16_t) hazard3_irqarray_read(RVCSR_MEIPRA_OFFSET, num / 4u);  in irq_get_priority()
608     uint8_t priority_4bit = (priority_row >> (4 * (num % 4))) & 0xfu;  in irq_get_priority()
612     io_rw_32 *p = nvic_ipr0() + (num >> 2);  in irq_get_priority()
613     return (uint8_t)(*p >> (8 * (num & 3u)));  in irq_get_priority()