Lines Matching refs:n
78 static inline void irq_set_mask_n_enabled_internal(uint n, uint32_t mask, bool enabled) { in irq_set_mask_n_enabled_internal() argument
79 invalid_params_if(HARDWARE_IRQ, n * 32u >= ((NUM_IRQS + 31u) & ~31u)); in irq_set_mask_n_enabled_internal()
82 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
83 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
84 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
85 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
87 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
88 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
91 ((void)n); in irq_set_mask_n_enabled_internal()
101 nvic_hw->icpr[n] = mask; in irq_set_mask_n_enabled_internal()
102 nvic_hw->iser[n] = mask; in irq_set_mask_n_enabled_internal()
104 nvic_hw->icer[n] = mask; in irq_set_mask_n_enabled_internal()
113 void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled) { in irq_set_mask_n_enabled() argument
114 irq_set_mask_n_enabled_internal(n, mask, enabled); in irq_set_mask_n_enabled()