56 qspi_set_cs_state(QSPIC_TYPE qspi_id, bool state)  in qspi_set_cs_state()  argument
59         qspi_id->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk;  in qspi_set_cs_state()
61         qspi_id->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk;  in qspi_set_cs_state()
66 qspi_write8_data(QSPIC_TYPE qspi_id, int8_t data)  in qspi_write8_data()  argument
68     volatile uint8_t *reg8 = (uint8_t *)&qspi_id->QSPIC_WRITEDATA_REG;  in qspi_write8_data()
74 qspi_read8_data(QSPIC_TYPE qspi_id)  in qspi_read8_data()  argument
76     volatile uint8_t *reg8 = (uint8_t *)&qspi_id->QSPIC_READDATA_REG;  in qspi_read8_data()
82 qspi_write(QSPIC_TYPE qspi_id, const uint8_t *wbuf, size_t wlen)  in qspi_write()  argument
84 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in qspi_write()
86     qspi_set_cs_state(qspi_id, true);  in qspi_write()
89         qspi_write8_data(qspi_id, wbuf[i]);  in qspi_write()
92     qspi_set_cs_state(qspi_id, false);  in qspi_write()
96 qspi_transact(QSPIC_TYPE qspi_id, const uint8_t *wbuf, size_t wlen, uint8_t *rbuf, size_t rlen)  in qspi_transact()  argument
98 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in qspi_transact()
100     qspi_set_cs_state(qspi_id, true);  in qspi_transact()
103         qspi_write8_data(qspi_id, wbuf[i]);  in qspi_transact()
107         rbuf[i] = qspi_read8_data(qspi_id);  in qspi_transact()
110     qspi_set_cs_state(qspi_id, false);  in qspi_transact()
114 da1469x_qspi_set_bus_mode(QSPIC_TYPE qspi_id, qspi_bus_mode_t mode)  in da1469x_qspi_set_bus_mode()  argument
116 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in da1469x_qspi_set_bus_mode()
118     qspi_id->QSPIC_CTRLBUS_REG = mode;  in da1469x_qspi_set_bus_mode()
123         qspi_id->QSPIC_CTRLMODE_REG |= (QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk |  in da1469x_qspi_set_bus_mode()
129         qspi_id->QSPIC_CTRLMODE_REG &= ~(QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk |  in da1469x_qspi_set_bus_mode()
136 da1469x_qspi_memory_jedec_reset(QSPIC_TYPE qspi_id)  in da1469x_qspi_memory_jedec_reset()  argument
138 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in da1469x_qspi_memory_jedec_reset()
141     da1469x_qspi_set_bus_mode(qspi_id, QSPI_BUS_MODE_SINGLE);  in da1469x_qspi_memory_jedec_reset()
145     qspi_write(qspi_id, (const uint8_t *)&cmd, 1);  in da1469x_qspi_memory_jedec_reset()
147     qspi_write(qspi_id, (const uint8_t *)&cmd, 1);  in da1469x_qspi_memory_jedec_reset()
153     da1469x_qspi_set_bus_mode(qspi_id, QSPI_BUS_MODE_QUAD);  in da1469x_qspi_memory_jedec_reset()
155     qspi_write(qspi_id, (const uint8_t *)&cmd, 1);  in da1469x_qspi_memory_jedec_reset()
157     qspi_write(qspi_id, (const uint8_t *)&cmd, 1);  in da1469x_qspi_memory_jedec_reset()
161 da1469x_qspi_memory_jedec_read_id(QSPIC_TYPE qspi_id, qspi_memory_id_t *id)  in da1469x_qspi_memory_jedec_read_id()  argument
163 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in da1469x_qspi_memory_jedec_read_id()
168     da1469x_qspi_set_bus_mode(qspi_id, QSPI_BUS_MODE_SINGLE);  in da1469x_qspi_memory_jedec_read_id()
171     qspi_transact(qspi_id, (const uint8_t *)cmd, sizeof(cmd), response, sizeof(*id));  in da1469x_qspi_memory_jedec_read_id()
175 da1469x_qspi_enter_exit_qpi_mode(QSPIC_TYPE qspi_id, bool enter, uint8_t cmd)  in da1469x_qspi_enter_exit_qpi_mode()  argument
177 	assert((qspi_id->QSPIC_CTRLMODE_REG & QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk) == 0);  in da1469x_qspi_enter_exit_qpi_mode()
179 	da1469x_qspi_set_bus_mode(qspi_id, enter ? QSPI_BUS_MODE_SINGLE : QSPI_BUS_MODE_QUAD);  in da1469x_qspi_enter_exit_qpi_mode()
180     qspi_write(qspi_id, (const uint8_t *)&cmd, 1);  in da1469x_qspi_enter_exit_qpi_mode()
184 da1469x_qspi_set_read_pipe_delay(QSPIC_TYPE qspi_id, uint8_t delay)  in da1469x_qspi_set_read_pipe_delay()  argument
186     uint32_t qspic_ctrlmode_reg = qspi_id->QSPIC_CTRLMODE_REG;  in da1469x_qspi_set_read_pipe_delay()
189     qspi_id->QSPIC_CTRLMODE_REG = qspic_ctrlmode_reg;  in da1469x_qspi_set_read_pipe_delay()
193 da1469x_qspi_set_cs_delay(QSPIC_TYPE qspi_id, uint32_t sys_clock_freq,  in da1469x_qspi_set_cs_delay()  argument
202     uint32_t reg = qspi_id->QSPIC_BURSTCMDB_REG;  in da1469x_qspi_set_cs_delay()
204     qspi_id->QSPIC_BURSTCMDB_REG = reg;  in da1469x_qspi_set_cs_delay()
206     reg = qspi_id->QSPIC_ERASECMDB_REG;  in da1469x_qspi_set_cs_delay()
208     qspi_id->QSPIC_ERASECMDB_REG = reg;  in da1469x_qspi_set_cs_delay()