Lines Matching refs:Value
609 DmaTcdList[0u].Value = 0u; /* dummy src address read, it will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
610 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.CMD; /* dest address write*/ in Spi_Ip_CmdDmaTcdSGInit()
611 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_CmdDmaTcdSGInit()
612 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
613 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
614 DmaTcdList[5u].Value = 2u; /* bytes to transfer for each request */ in Spi_Ip_CmdDmaTcdSGInit()
615 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_CmdDmaTcdSGInit()
616 DmaTcdList[7u].Value = 0u; /* dummy iteration count will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
617 …DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be u… in Spi_Ip_CmdDmaTcdSGInit()
649 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_TxDmaTcdSGInit()
650 …DmaTcdList[2u].Value = 1u; /* dummy src offset is 1 byte, will be updated latter according to fra… in Spi_Ip_TxDmaTcdSGInit()
651 …DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte src transfer size, will be upd… in Spi_Ip_TxDmaTcdSGInit()
652 …DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte dest transfer size, will be… in Spi_Ip_TxDmaTcdSGInit()
653 …DmaTcdList[5u].Value = 1u; /* dummy bytes to transfer for each request, will be updated latter a… in Spi_Ip_TxDmaTcdSGInit()
654 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_TxDmaTcdSGInit()
655 …DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter according to number of… in Spi_Ip_TxDmaTcdSGInit()
656 …DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be upd… in Spi_Ip_TxDmaTcdSGInit()
657 …DmaTcdList[9u].Value = 0u; /* dummy no src address modulo, will be updated latter Base on transfe… in Spi_Ip_TxDmaTcdSGInit()
658 DmaTcdList[0u].Value = 0u; /* dummy src address read, will be updated latter Base on TxBuffer */ in Spi_Ip_TxDmaTcdSGInit()
688 DmaTcdList[1u].Value = 1u; /* src offset is 1 byte */ in Spi_Ip_TxDmaTcdSGConfig()
689 DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */ in Spi_Ip_TxDmaTcdSGConfig()
690 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte dest transfer size */ in Spi_Ip_TxDmaTcdSGConfig()
691 DmaTcdList[4u].Value = 1u; /* bytes to transfer for each request */ in Spi_Ip_TxDmaTcdSGConfig()
695 DmaTcdList[1u].Value = 2u; /* src offset is 2 bytes */ in Spi_Ip_TxDmaTcdSGConfig()
696 DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_TxDmaTcdSGConfig()
697 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_TxDmaTcdSGConfig()
698 DmaTcdList[4u].Value = 2u; /* bytes to transfer for each request */ in Spi_Ip_TxDmaTcdSGConfig()
700 DmaTcdList[5u].Value = State->ExpectedFifoWrites; /* iteration count */ in Spi_Ip_TxDmaTcdSGConfig()
701 DmaTcdList[6u].Value = DisHwReq; /* disable hardware request when major loop complete */ in Spi_Ip_TxDmaTcdSGConfig()
702 DmaTcdList[7u].Value = 0u; /* no src address modulo */ in Spi_Ip_TxDmaTcdSGConfig()
706 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[TCDSGIndex].DefaultDa… in Spi_Ip_TxDmaTcdSGConfig()
709 DmaTcdList[1u].Value = 0u; /* src offset is 0 byte */ in Spi_Ip_TxDmaTcdSGConfig()
713 DmaTcdList[7u].Value = 2u; /* data is 4 bytes, src address modulo is 2 bits */ in Spi_Ip_TxDmaTcdSGConfig()
718 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_TxDmaTcdSGConfig()
742 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_RxDmaTcdSGInit()
743 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_RxDmaTcdSGInit()
744 …DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte src transfer size, will be upd… in Spi_Ip_RxDmaTcdSGInit()
745 …DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte dest transfer size, will be… in Spi_Ip_RxDmaTcdSGInit()
746 …DmaTcdList[5u].Value = 1u; /* dummy 1 byte to transfer for each request, will be updated latter … in Spi_Ip_RxDmaTcdSGInit()
747 …DmaTcdList[6u].Value = 1u; /* dummy dest offset is 1 byte, will be updated latter Base on frame si… in Spi_Ip_RxDmaTcdSGInit()
748 …DmaTcdList[1u].Value = 0u; /* dummy dest address write, will be updated latter Base on RxBuffer… in Spi_Ip_RxDmaTcdSGInit()
749 …DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter Base on number of fram… in Spi_Ip_RxDmaTcdSGInit()
750 …DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be upd… in Spi_Ip_RxDmaTcdSGInit()
780 DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
781 DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte dest transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
782 DmaTcdList[3u].Value = 1u; /* 1 byte to transfer for each request */ in Spi_Ip_RxDmaTcdSGConfig()
783 DmaTcdList[4u].Value = 1u; /* dest offset is 1 bytes */ in Spi_Ip_RxDmaTcdSGConfig()
787 DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
788 DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
789 DmaTcdList[3u].Value = 2u; /* 2 bytes to transfer for each request */ in Spi_Ip_RxDmaTcdSGConfig()
790 DmaTcdList[4u].Value = 2u; /* dest offset is 2 bytes */ in Spi_Ip_RxDmaTcdSGConfig()
794 DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
795 DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes dest transfer size */ in Spi_Ip_RxDmaTcdSGConfig()
796 DmaTcdList[3u].Value = 4u; /* 4 bytes to transfer for each request */ in Spi_Ip_RxDmaTcdSGConfig()
797 DmaTcdList[4u].Value = 4u; /* dest offset is 4 bytes */ in Spi_Ip_RxDmaTcdSGConfig()
802 … DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Spi_Ip_u32DiscardData; /* dest address write*/ in Spi_Ip_RxDmaTcdSGConfig()
803 DmaTcdList[4u].Value = 0u; /* dest offset is 0 bytes */ in Spi_Ip_RxDmaTcdSGConfig()
807 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->RxBuffer; /* dest address write*/ in Spi_Ip_RxDmaTcdSGConfig()
809 DmaTcdList[5u].Value = State->ExpectedFifoReads; /* iteration count */ in Spi_Ip_RxDmaTcdSGConfig()
810 DmaTcdList[6u].Value = DisHwReq; /* disable hardware request when major loop complete */ in Spi_Ip_RxDmaTcdSGConfig()
811 …DmaTcdList[7u].Value = DisHwReq; /* Enable Major interrupt at the end of transfer sequence(meannin… in Spi_Ip_RxDmaTcdSGConfig()
835 DmaTcdList[0u].Value = CmdAdd; /* src address read */ in Spi_Ip_CmdDmaTcdSGConfig()
836 DmaTcdList[1u].Value = Iter; /* iteration count */ in Spi_Ip_CmdDmaTcdSGConfig()
837 DmaTcdList[2u].Value = DisHwReq; /* disable hardware request when major loop complete */ in Spi_Ip_CmdDmaTcdSGConfig()
869 Tcds[2].Value = 0u; /* Enable HW Request */ in Spi_Ip_DmaCmdConfigAndStart()
878 Tcds[0].Value = (Dma_Ip_uintPtrType)&State->PushrCmds[1]; /* SOURCE_ADDRESS */ in Spi_Ip_DmaCmdConfigAndStart()
879 Tcds[1].Value = (uint32)State->NbCmds - 1u; /* MAJORLOOP */ in Spi_Ip_DmaCmdConfigAndStart()
880 Tcds[2].Value = 1u; /* Disable HW Request */ in Spi_Ip_DmaCmdConfigAndStart()
882 Tcds[3].Value = 2; in Spi_Ip_DmaCmdConfigAndStart()
890 Tcds[2].Value = 1u; /* Disable HW Request */ in Spi_Ip_DmaCmdConfigAndStart()
922 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_DmaConfig()
925 DmaTcdList[2u].Value = 1u; /* src offset is 1 byte */ in Spi_Ip_DmaConfig()
926 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */ in Spi_Ip_DmaConfig()
927 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte dest transfer size */ in Spi_Ip_DmaConfig()
928 DmaTcdList[5u].Value = 1u; /* bytes to transfer for each request */ in Spi_Ip_DmaConfig()
932 DmaTcdList[2u].Value = 2u; /* src offset is 2 bytes */ in Spi_Ip_DmaConfig()
933 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_DmaConfig()
934 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_DmaConfig()
935 DmaTcdList[5u].Value = 2u; /* bytes to transfer for each request */ in Spi_Ip_DmaConfig()
937 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_DmaConfig()
938 DmaTcdList[7u].Value = 1u; /* disable hardware request when major loop complete */ in Spi_Ip_DmaConfig()
939 DmaTcdList[8u].Value = 0u; /* no src address modulo */ in Spi_Ip_DmaConfig()
943 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->ExternalDevice->DeviceParams->DefaultData; /* s… in Spi_Ip_DmaConfig()
946 DmaTcdList[2u].Value = 0u; /* src offset is 0 byte */ in Spi_Ip_DmaConfig()
950 DmaTcdList[8u].Value = 2u; /* data is 4 bytes, src address modulo is 2 bits */ in Spi_Ip_DmaConfig()
955 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_DmaConfig()
959 DmaTcdList[9u].Value = 0u; /* No adjust DADD when major loop completed */ in Spi_Ip_DmaConfig()
964 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_DmaConfig()
965 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_DmaConfig()
968 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */ in Spi_Ip_DmaConfig()
969 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte dest transfer size */ in Spi_Ip_DmaConfig()
970 DmaTcdList[5u].Value = 1u; /* 1 byte to transfer for each request */ in Spi_Ip_DmaConfig()
971 DmaTcdList[6u].Value = 1u; /* dest offset is 1 bytes */ in Spi_Ip_DmaConfig()
975 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_DmaConfig()
976 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_DmaConfig()
977 DmaTcdList[5u].Value = 2u; /* 2 bytes to transfer for each request */ in Spi_Ip_DmaConfig()
978 DmaTcdList[6u].Value = 2u; /* dest offset is 2 bytes */ in Spi_Ip_DmaConfig()
982 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */ in Spi_Ip_DmaConfig()
983 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes dest transfer size */ in Spi_Ip_DmaConfig()
984 DmaTcdList[5u].Value = 4u; /* 4 bytes to transfer for each request */ in Spi_Ip_DmaConfig()
985 DmaTcdList[6u].Value = 4u; /* dest offset is 4 bytes */ in Spi_Ip_DmaConfig()
990 … DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Spi_Ip_u32DiscardData; /* dest address write*/ in Spi_Ip_DmaConfig()
991 DmaTcdList[6u].Value = 0u; /* dest offset is 0 bytes */ in Spi_Ip_DmaConfig()
995 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)State->RxBuffer; /* dest address write*/ in Spi_Ip_DmaConfig()
997 DmaTcdList[7u].Value = 1u; /* disable hardware request when major loop complete */ in Spi_Ip_DmaConfig()
1000 DmaTcdList[8u].Value = 0u; /* No adjust DADD when major loop completed */ in Spi_Ip_DmaConfig()
1039 Tcd.Value = NumberDmaIterWrite; in Spi_Ip_DmaTxRxUpdateLoop()
1042 Tcd.Value = NumberDmaIterRead; in Spi_Ip_DmaTxRxUpdateLoop()
1062 .Value = IrqEn in Spi_Ip_DmaAsyncStart()
1885 DmaTcdList[0u].Value = 1u; in Spi_Ip_DmaFastConfig()