Lines Matching refs:State
259 static uint16 Spi_Ip_WriteCmdFifo(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_WriteCmdFifo() argument
266 if (NumberOfCmdWrites > State->ExpectedCmdFifoWrites) in Spi_Ip_WriteCmdFifo()
268 NumberOfCmdWrites = State->ExpectedCmdFifoWrites; in Spi_Ip_WriteCmdFifo()
272 if (State->Pushr0RepeatIndex < State->Pushr0Repeat) in Spi_Ip_WriteCmdFifo()
274 State->Pushr0RepeatIndex++; in Spi_Ip_WriteCmdFifo()
278 State->NbCmdsIndex++; in Spi_Ip_WriteCmdFifo()
281 DevAssert(State->NbCmdsIndex < 3u); in Spi_Ip_WriteCmdFifo()
283 Base->PUSHR.FIFO.CMD = State->PushrCmds[State->NbCmdsIndex]; in Spi_Ip_WriteCmdFifo()
284 State->ExpectedCmdFifoWrites--; in Spi_Ip_WriteCmdFifo()
300 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TransferProcess() local
305 if (SPI_IP_BUSY == State->Status) in Spi_Ip_TransferProcess()
327 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_TransferProcess()
330 if (State->ExpectedCmdFifoWrites != 0u) in Spi_Ip_TransferProcess()
332 (void)Spi_Ip_WriteCmdFifo(State, Base); in Spi_Ip_TransferProcess()
342 if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex)) in Spi_Ip_TransferProcess()
344 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_TransferProcess()
346 if(State->CurrentTxFifoSlot != 0u) in Spi_Ip_TransferProcess()
348 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance); in Spi_Ip_TransferProcess()
350 State->CurrentTxFifoSlot = 0u; in Spi_Ip_TransferProcess()
354 if ((State->RxIndex == State->ExpectedFifoReads) || ((boolean)TRUE == ErrorFlag)) in Spi_Ip_TransferProcess()
357 if(((boolean)TRUE == ErrorFlag) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_TransferProcess()
424 static void Spi_Ip_UpdateCtarAndPushr(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_UpdateCtarAndPushr() argument
426 const Spi_Ip_ExternalDeviceType *Dev = State->ExternalDevice; in Spi_Ip_UpdateCtarAndPushr()
434 DevAssert(State->NbCmds > 0u); in Spi_Ip_UpdateCtarAndPushr()
438 CtarSrc = Dev->Ctar[State->ClockMode]; in Spi_Ip_UpdateCtarAndPushr()
446 if (State->PhyUnitConfig->SlaveMode) in Spi_Ip_UpdateCtarAndPushr()
453 for (i = 0u; i < State->NbCmds; i++) { in Spi_Ip_UpdateCtarAndPushr()
459 SPI_CTARE_DTCP(State->DTCPValue[i]); in Spi_Ip_UpdateCtarAndPushr()
460 State->PushrCmds[i] = (uint16)(((PushrCmd32 & (~SPI_PUSHR_CTAS_MASK)) | in Spi_Ip_UpdateCtarAndPushr()
464 if ((State->PushrCmds[i - 1u] & SPI_IP_PUSHR_CONT_MASK_U16) != 0u) in Spi_Ip_UpdateCtarAndPushr()
466 State->PushrCmds[i - 1u] &= ~SPI_IP_PUSHR_CONT_MASK_U16; in Spi_Ip_UpdateCtarAndPushr()
484 static void Spi_Ip_PrepareTransfer(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint16 NbBytes) in Spi_Ip_PrepareTransfer() argument
490 Spi_Ip_CalculateFifoWords(State->ExternalDevice->DeviceParams->FrameSize, NbBytes, in Spi_Ip_PrepareTransfer()
512 State->RxIndex = 0u; in Spi_Ip_PrepareTransfer()
513 State->TxIndex = 0u; in Spi_Ip_PrepareTransfer()
514 State->NbCmdsIndex = 0; in Spi_Ip_PrepareTransfer()
515 State->Pushr0RepeatIndex = 0; in Spi_Ip_PrepareTransfer()
516 State->NbCmds = 1u; in Spi_Ip_PrepareTransfer()
518 if ((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_PrepareTransfer()
521 if (TRUE == State->KeepCs) in Spi_Ip_PrepareTransfer()
527 State->DTCPValue[0] = 1; in Spi_Ip_PrepareTransfer()
528 State->Pushr0Repeat = Frames; in Spi_Ip_PrepareTransfer()
529 State->ExpectedCmdFifoWrites = State->Pushr0Repeat; in Spi_Ip_PrepareTransfer()
531 … if (((State->ExternalDevice->PushrCmd & SPI_IP_PUSHR_CONT_MASK_U16) != 0u) && (Frames > 1u)) in Spi_Ip_PrepareTransfer()
533 State->Pushr0Repeat--; in Spi_Ip_PrepareTransfer()
534 State->DTCPValue[1] = 1; in Spi_Ip_PrepareTransfer()
535 State->NbCmds++; in Spi_Ip_PrepareTransfer()
543 State->DTCPValue[0] = Frames % SPI_IP_CTARE_DTCP_MAX_U16; in Spi_Ip_PrepareTransfer()
544 State->Pushr0Repeat = 1u; in Spi_Ip_PrepareTransfer()
545 State->DTCPValue[1] = 0u; in Spi_Ip_PrepareTransfer()
555 State->DTCPValue[0] = SPI_IP_CTARE_DTCP_MAX_U16; in Spi_Ip_PrepareTransfer()
556 State->Pushr0Repeat = Frames / SPI_IP_CTARE_DTCP_MAX_U16; in Spi_Ip_PrepareTransfer()
557 State->DTCPValue[1] = Frames % SPI_IP_CTARE_DTCP_MAX_U16; in Spi_Ip_PrepareTransfer()
558 State->NbCmds++; in Spi_Ip_PrepareTransfer()
567 if (State->DTCPValue[State->NbCmds - 1u] > 1u) in Spi_Ip_PrepareTransfer()
569 State->DTCPValue[State->NbCmds - 1u]--; in Spi_Ip_PrepareTransfer()
570 State->DTCPValue[State->NbCmds] = 1u; in Spi_Ip_PrepareTransfer()
571 State->NbCmds++; in Spi_Ip_PrepareTransfer()
574 State->ExpectedCmdFifoWrites = State->Pushr0Repeat + State->NbCmds - 1u; in Spi_Ip_PrepareTransfer()
577 State->ExpectedFifoWrites = NbBytes / TxBytesPerWord; in Spi_Ip_PrepareTransfer()
578 State->ExpectedFifoReads = NbBytes / RxBytesPerWord; in Spi_Ip_PrepareTransfer()
580 Spi_Ip_UpdateCtarAndPushr(State, Base); in Spi_Ip_PrepareTransfer()
594 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_CmdDmaTcdSGInit() local
619 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->NumTxCmdDmaSGId; TCDSGIndex++) in Spi_Ip_CmdDmaTcdSGInit()
622 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyUni… in Spi_Ip_CmdDmaTcdSGInit()
626 …(void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyU… in Spi_Ip_CmdDmaTcdSGInit()
633 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TxDmaTcdSGInit() local
660 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TCDSGIndex++) in Spi_Ip_TxDmaTcdSGInit()
663 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitCo… in Spi_Ip_TxDmaTcdSGInit()
669 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TxDmaTcdSGConfig() local
673 State->TxIndex = State->ExpectedFifoWrites; in Spi_Ip_TxDmaTcdSGConfig()
686 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_TxDmaTcdSGConfig()
700 DmaTcdList[5u].Value = State->ExpectedFifoWrites; /* iteration count */ in Spi_Ip_TxDmaTcdSGConfig()
703 if(NULL_PTR == State->TxBuffer) in Spi_Ip_TxDmaTcdSGConfig()
706 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[TCDSGIndex].DefaultDa… in Spi_Ip_TxDmaTcdSGConfig()
707 if(State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_TxDmaTcdSGConfig()
718 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_TxDmaTcdSGConfig()
721 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitCo… in Spi_Ip_TxDmaTcdSGConfig()
727 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_RxDmaTcdSGInit() local
752 for(TCDSGIndex = 0u; TCDSGIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TCDSGIndex++) in Spi_Ip_RxDmaTcdSGInit()
755 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitCo… in Spi_Ip_RxDmaTcdSGInit()
761 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_RxDmaTcdSGConfig() local
765 State->RxIndex = State->ExpectedFifoReads; in Spi_Ip_RxDmaTcdSGConfig()
778 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_RxDmaTcdSGConfig()
785 else if (State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_RxDmaTcdSGConfig()
799 if(NULL_PTR == State->RxBuffer) in Spi_Ip_RxDmaTcdSGConfig()
807 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->RxBuffer; /* dest address write*/ in Spi_Ip_RxDmaTcdSGConfig()
809 DmaTcdList[5u].Value = State->ExpectedFifoReads; /* iteration count */ in Spi_Ip_RxDmaTcdSGConfig()
814 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitCo… in Spi_Ip_RxDmaTcdSGConfig()
827 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_CmdDmaTcdSGConfig() local
839 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxCmdDmaChannel, TCDSGId, DmaT… in Spi_Ip_CmdDmaTcdSGConfig()
851 static void Spi_Ip_DmaCmdConfigAndStart(const Spi_Ip_StateStructureType* State) in Spi_Ip_DmaCmdConfigAndStart() argument
854 …[0] = { DMA_IP_CH_SET_SOURCE_ADDRESS , (Dma_Ip_uintPtrType)&State->PushrCmds[0]… in Spi_Ip_DmaCmdConfigAndStart()
855 [1] = { DMA_IP_CH_SET_MAJORLOOP_COUNT , State->Pushr0Repeat }, in Spi_Ip_DmaCmdConfigAndStart()
867 if (State->NbCmds > 1u) in Spi_Ip_DmaCmdConfigAndStart()
870 (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxCmdDmaChannel, in Spi_Ip_DmaCmdConfigAndStart()
871 State->PhyUnitConfig->TxCmdDmaSGId[0], in Spi_Ip_DmaCmdConfigAndStart()
876 …(void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyU… in Spi_Ip_DmaCmdConfigAndStart()
878 Tcds[0].Value = (Dma_Ip_uintPtrType)&State->PushrCmds[1]; /* SOURCE_ADDRESS */ in Spi_Ip_DmaCmdConfigAndStart()
879 Tcds[1].Value = (uint32)State->NbCmds - 1u; /* MAJORLOOP */ in Spi_Ip_DmaCmdConfigAndStart()
883 (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxCmdDmaChannel, in Spi_Ip_DmaCmdConfigAndStart()
884 State->PhyUnitConfig->TxCmdDmaSGId[1], in Spi_Ip_DmaCmdConfigAndStart()
891 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxCmdDmaChannel, in Spi_Ip_DmaCmdConfigAndStart()
895 (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxCmdDmaChannel, in Spi_Ip_DmaCmdConfigAndStart()
907 static void Spi_Ip_DmaConfig(const Spi_Ip_StateStructureType* State,const SPI_Type *Base) in Spi_Ip_DmaConfig() argument
923 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_DmaConfig()
940 if(NULL_PTR == State->TxBuffer) in Spi_Ip_DmaConfig()
943 …DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&State->ExternalDevice->DeviceParams->DefaultData; /* s… in Spi_Ip_DmaConfig()
944 if(State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_DmaConfig()
955 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)State->TxBuffer; /* src address read */ in Spi_Ip_DmaConfig()
961 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 10u); in Spi_Ip_DmaConfig()
966 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_DmaConfig()
973 else if (State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_DmaConfig()
987 if(NULL_PTR == State->RxBuffer) in Spi_Ip_DmaConfig()
995 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)State->RxBuffer; /* dest address write*/ in Spi_Ip_DmaConfig()
1002 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 9u); in Spi_Ip_DmaConfig()
1012 static void Spi_Ip_DmaTxRxUpdateLoop(Spi_Ip_StateStructureType* State) in Spi_Ip_DmaTxRxUpdateLoop() argument
1014 uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_DmaTxRxUpdateLoop()
1028 if (State->ExternalDevice->DeviceParams->FrameSize > 16u) in Spi_Ip_DmaTxRxUpdateLoop()
1036 State->TxIndex += NumberDmaIterWrite; in Spi_Ip_DmaTxRxUpdateLoop()
1037 State->RxIndex += NumberDmaIterRead; in Spi_Ip_DmaTxRxUpdateLoop()
1040 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, &Tcd, 1u); in Spi_Ip_DmaTxRxUpdateLoop()
1043 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, &Tcd, 1u); in Spi_Ip_DmaTxRxUpdateLoop()
1046 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQ… in Spi_Ip_DmaTxRxUpdateLoop()
1047 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQ… in Spi_Ip_DmaTxRxUpdateLoop()
1058 static void Spi_Ip_DmaAsyncStart(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint32 IrqEn) in Spi_Ip_DmaAsyncStart() argument
1065 (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, &Tcd, 1u); in Spi_Ip_DmaAsyncStart()
1067 if ((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_DmaAsyncStart()
1070 Spi_Ip_DmaCmdConfigAndStart(State); in Spi_Ip_DmaAsyncStart()
1073 Spi_Ip_DmaConfig(State, Base); in Spi_Ip_DmaAsyncStart()
1075 Spi_Ip_DmaTxRxUpdateLoop(State); in Spi_Ip_DmaAsyncStart()
1099 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_WriteTxFifo() local
1110 if(NULL_PTR != State->TxBuffer) in Spi_Ip_WriteTxFifo()
1112 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_WriteTxFifo()
1120 LastIdx = ((uint32)State->TxIndex + NumberOfWrites) * Factor; in Spi_Ip_WriteTxFifo()
1121 for (Idx = State->TxIndex * Factor; Idx < LastIdx; Idx += Factor) in Spi_Ip_WriteTxFifo()
1123 if(State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_WriteTxFifo()
1125 Data = State->TxBuffer[Idx]; in Spi_Ip_WriteTxFifo()
1129 Data = *((const uint16*)&State->TxBuffer[Idx]); in Spi_Ip_WriteTxFifo()
1138 if(State->ExternalDevice->DeviceParams->FrameSize > 16u) in Spi_Ip_WriteTxFifo()
1142 Data = (uint16)(State->ExternalDevice->DeviceParams->DefaultData >> Factor); in Spi_Ip_WriteTxFifo()
1146 Data = (uint16)State->ExternalDevice->DeviceParams->DefaultData; in Spi_Ip_WriteTxFifo()
1151 State->TxIndex += NumberOfWrites; in Spi_Ip_WriteTxFifo()
1168 Spi_Ip_StateStructureType* const State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ReceiveData() local
1176 if (State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_ReceiveData()
1180 else if (State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_ReceiveData()
1190 if (LimitedNumberOfReads > (State->ExpectedFifoReads - State->RxIndex)) in Spi_Ip_ReceiveData()
1192 LimitedNumberOfReads = State->ExpectedFifoReads - State->RxIndex; in Spi_Ip_ReceiveData()
1194 if(NULL_PTR != State->RxBuffer) in Spi_Ip_ReceiveData()
1196 LastIdx = ((uint32)State->RxIndex + LimitedNumberOfReads) * Factor; in Spi_Ip_ReceiveData()
1197 for (Idx = State->RxIndex * Factor; Idx < LastIdx; Idx += Factor) in Spi_Ip_ReceiveData()
1200 if (State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_ReceiveData()
1202 State->RxBuffer[Idx] = (uint8)Data; in Spi_Ip_ReceiveData()
1204 else if (State->ExternalDevice->DeviceParams->FrameSize < 17u) in Spi_Ip_ReceiveData()
1206 *((uint16*)&State->RxBuffer[Idx]) = (uint16)Data; in Spi_Ip_ReceiveData()
1210 *((uint32*)&State->RxBuffer[Idx]) = Data; in Spi_Ip_ReceiveData()
1222 State->RxIndex += LimitedNumberOfReads; in Spi_Ip_ReceiveData()
1225 if (State->ExternalDevice->DeviceParams->FrameSize > 16u) in Spi_Ip_ReceiveData()
1227 State->CurrentTxFifoSlot += LimitedNumberOfReads * 2u; in Spi_Ip_ReceiveData()
1231 State->CurrentTxFifoSlot += LimitedNumberOfReads; in Spi_Ip_ReceiveData()
1245 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ChannelFinished() local
1250 State->Status = SPI_IP_FAULT; in Spi_Ip_ChannelFinished()
1255 State->Status = SPI_IP_IDLE; in Spi_Ip_ChannelFinished()
1259 if (NULL_PTR != State->Callback) in Spi_Ip_ChannelFinished()
1261 State->Callback(Instance, EventState); in Spi_Ip_ChannelFinished()
1277 static void Spi_Ip_AsyncStart(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_AsyncStart() argument
1282 uint16 RemainingWrites = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_AsyncStart()
1289 if ((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_AsyncStart()
1292 (void)Spi_Ip_WriteCmdFifo(State, Base); in Spi_Ip_AsyncStart()
1294 if (State->CurrentTxFifoSlot > RemainingWrites) in Spi_Ip_AsyncStart()
1296 State->CurrentTxFifoSlot = RemainingWrites; in Spi_Ip_AsyncStart()
1298 if (State->CurrentTxFifoSlot != 0u) in Spi_Ip_AsyncStart()
1300 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, State->ExternalDevice->Instance); in Spi_Ip_AsyncStart()
1302 State->CurrentTxFifoSlot = 0u; in Spi_Ip_AsyncStart()
1324 Spi_Ip_WriteTxFifo(NumberOfWrites, State->ExternalDevice->Instance); in Spi_Ip_AsyncStart()
1326 State->CurrentTxFifoSlot -= NumberOfWrites; in Spi_Ip_AsyncStart()
1367 if(State->PhyUnitConfig->DmaUsed) in Spi_Ip_CheckValidParameters()
1395 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_IrqDmaHandler() local
1400 if((NULL_PTR != State) && (SPI_IP_BUSY == State->Status)) in Spi_Ip_IrqDmaHandler()
1413 if (State->ExpectedFifoReads != State->RxIndex) in Spi_Ip_IrqDmaHandler()
1415 Spi_Ip_DmaTxRxUpdateLoop(State); in Spi_Ip_IrqDmaHandler()
1426 if(((boolean)TRUE == ErrorFlag) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_IrqDmaHandler()
1438 State->Status = SPI_IP_FAULT; in Spi_Ip_IrqDmaHandler()
1442 State->Status = SPI_IP_IDLE; in Spi_Ip_IrqDmaHandler()
1444 if (State->Callback != NULL_PTR) in Spi_Ip_IrqDmaHandler()
1448 State->Callback(Instance, SPI_IP_EVENT_FAULT); in Spi_Ip_IrqDmaHandler()
1452 State->Callback(Instance, SPI_IP_EVENT_END_TRANSFER); in Spi_Ip_IrqDmaHandler()
1488 Spi_Ip_StateStructureType* State; in Spi_Ip_Init() local
1496 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Init()
1499 DevAssert(State == NULL_PTR); in Spi_Ip_Init()
1502 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Init()
1503 State->PhyUnitConfig = PhyUnitConfigPtr; in Spi_Ip_Init()
1512 State->ClockMode = SPI_IP_NORMAL_CLOCK; in Spi_Ip_Init()
1514 State->KeepCs = (boolean)FALSE; in Spi_Ip_Init()
1520 if((boolean)TRUE == State->PhyUnitConfig->DmaUsed) in Spi_Ip_Init()
1529 State->Status = SPI_IP_IDLE; in Spi_Ip_Init()
1537 const Spi_Ip_StateStructureType* State; in Spi_Ip_DeInit() local
1544 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_DeInit()
1546 DevAssert(State != NULL_PTR); in Spi_Ip_DeInit()
1548 if (State->Status == SPI_IP_BUSY) in Spi_Ip_DeInit()
1569 static Spi_Ip_StatusType Spi_Ip_IntoBusyState(Spi_Ip_StateStructureType* State) in Spi_Ip_IntoBusyState() argument
1573 if (SPI_IP_BUSY == State->Status) in Spi_Ip_IntoBusyState()
1581 State->Status = SPI_IP_BUSY; in Spi_Ip_IntoBusyState()
1588 static boolean Spi_Ip_SyncReadWriteStep(Spi_Ip_StateStructureType *State, SPI_Type *Base, uint8 Ins… in Spi_Ip_SyncReadWriteStep() argument
1594 if (State->ExpectedCmdFifoWrites != 0u) in Spi_Ip_SyncReadWriteStep()
1596 if (Spi_Ip_WriteCmdFifo(State, Base) != 0u) in Spi_Ip_SyncReadWriteStep()
1612 if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex)) in Spi_Ip_SyncReadWriteStep()
1614 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_SyncReadWriteStep()
1616 if (State->CurrentTxFifoSlot != 0u) in Spi_Ip_SyncReadWriteStep()
1618 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance); in Spi_Ip_SyncReadWriteStep()
1620 State->CurrentTxFifoSlot = 0u; in Spi_Ip_SyncReadWriteStep()
1651 Spi_Ip_StateStructureType *State; in Spi_Ip_SyncTransmit() local
1663 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_SyncTransmit()
1666 Status = Spi_Ip_IntoBusyState(State); in Spi_Ip_SyncTransmit()
1674 State->TxBuffer = TxBuffer; in Spi_Ip_SyncTransmit()
1675 State->RxBuffer = RxBuffer; in Spi_Ip_SyncTransmit()
1676 State->ExternalDevice = ExternalDevice; in Spi_Ip_SyncTransmit()
1678 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_SyncTransmit()
1683 State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16; in Spi_Ip_SyncTransmit()
1687 StepDone = Spi_Ip_SyncReadWriteStep(State, Base, Instance); in Spi_Ip_SyncTransmit()
1691 if (State->RxIndex == State->ExpectedFifoReads) in Spi_Ip_SyncTransmit()
1706 if((SPI_IP_STATUS_SUCCESS != Status) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_SyncTransmit()
1726 Spi_Ip_StateStructureType* State; in Spi_Ip_AsyncTransmit() local
1733 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_AsyncTransmit()
1735 Status = Spi_Ip_IntoBusyState(State); in Spi_Ip_AsyncTransmit()
1739 State->TxBuffer = TxBuffer; in Spi_Ip_AsyncTransmit()
1740 State->RxBuffer = RxBuffer; in Spi_Ip_AsyncTransmit()
1741 State->Callback = EndCallback; in Spi_Ip_AsyncTransmit()
1743 State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16; in Spi_Ip_AsyncTransmit()
1744 State->ExternalDevice = ExternalDevice; in Spi_Ip_AsyncTransmit()
1746 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_AsyncTransmit()
1753 if((boolean)FALSE == State->PhyUnitConfig->DmaUsed) in Spi_Ip_AsyncTransmit()
1756 if (State->TransferMode == SPI_IP_POLLING) in Spi_Ip_AsyncTransmit()
1762 Spi_Ip_AsyncStart(State, Base); in Spi_Ip_AsyncTransmit()
1768 Spi_Ip_DmaAsyncStart(State, Base, (State->TransferMode == SPI_IP_POLLING) ? 0u : 1u); in Spi_Ip_AsyncTransmit()
1787 Spi_Ip_StateStructureType* State; in Spi_Ip_AsyncTransmitFast() local
1797 State = Spi_Ip_apxStateStructureArray[FastTransferCfg[0u].ExternalDevice->Instance]; in Spi_Ip_AsyncTransmitFast()
1799 DevAssert(NULL_PTR != State); in Spi_Ip_AsyncTransmitFast()
1800 DevAssert(State->TransferMode == SPI_IP_INTERRUPT); in Spi_Ip_AsyncTransmitFast()
1801 DevAssert(NumberOfTransfer <= State->PhyUnitConfig->MaxNumOfFastTransfer); in Spi_Ip_AsyncTransmitFast()
1823 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_AsyncTransmitFast()
1826 if (SPI_IP_BUSY == State->Status) in Spi_Ip_AsyncTransmitFast()
1834 State->Status = SPI_IP_BUSY; in Spi_Ip_AsyncTransmitFast()
1847 State->ExternalDevice = FastTransferCfg[0u].ExternalDevice; in Spi_Ip_AsyncTransmitFast()
1849 LsbValue = State->ExternalDevice->DeviceParams->Lsb ? 1UL : 0UL; in Spi_Ip_AsyncTransmitFast()
1850 State->Callback = EndCallback; in Spi_Ip_AsyncTransmitFast()
1852 State->KeepCs = (boolean)FALSE; in Spi_Ip_AsyncTransmitFast()
1856 …CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ(((uint32)Sta… in Spi_Ip_AsyncTransmitFast()
1858 …R[0u] = FastTransferCfg[0u].ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->ExternalDevice->D… in Spi_Ip_AsyncTransmitFast()
1860 …] = FastTransferCfg[0u].ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->ExternalDevice->D… in Spi_Ip_AsyncTransmitFast()
1877 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_DmaFastConfig() local
1890 State->RxIndex = 0u; in Spi_Ip_DmaFastConfig()
1891 State->TxIndex = 0u; in Spi_Ip_DmaFastConfig()
1892 State->TxBuffer = FastTransferCfg[Count].TxBuffer; in Spi_Ip_DmaFastConfig()
1893 State->RxBuffer = FastTransferCfg[Count].RxBuffer; in Spi_Ip_DmaFastConfig()
1894 if (State->ExternalDevice->DeviceParams->FrameSize < 9u) in Spi_Ip_DmaFastConfig()
1896 State->ExpectedFifoWrites = FastTransferCfg[Count].Length; in Spi_Ip_DmaFastConfig()
1900 State->ExpectedFifoWrites = FastTransferCfg[Count].Length/2u; in Spi_Ip_DmaFastConfig()
1902 State->ExpectedFifoReads = State->ExpectedFifoWrites; in Spi_Ip_DmaFastConfig()
1903 if (State->ExternalDevice->DeviceParams->FrameSize >16u) in Spi_Ip_DmaFastConfig()
1905 State->ExpectedFifoReads = State->ExpectedFifoWrites/2u; in Spi_Ip_DmaFastConfig()
1907 State->ExpectedCmdFifoWrites = State->ExpectedFifoReads; in Spi_Ip_DmaFastConfig()
1908 State->PhyUnitConfig->CmdDmaFast[Count].DefaultData = FastTransferCfg[Count].DefaultData; in Spi_Ip_DmaFastConfig()
1909 …State->PhyUnitConfig->CmdDmaFast[Count].DmaFastPushrCmd = FastTransferCfg[Count].ExternalDevice->P… in Spi_Ip_DmaFastConfig()
1910 …State->PhyUnitConfig->CmdDmaFast[Count].DmaFastPushrCmdLast = FastTransferCfg[Count].ExternalDevic… in Spi_Ip_DmaFastConfig()
1935 if(State->ExpectedCmdFifoWrites > 1u) in Spi_Ip_DmaFastConfig()
1938 State->PhyUnitConfig->TxCmdDmaSGId[CmdTCDSGIndex], in Spi_Ip_DmaFastConfig()
1939 … (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[Count].DmaFastPushrCmd, in Spi_Ip_DmaFastConfig()
1940 State->ExpectedCmdFifoWrites - 1u, in Spi_Ip_DmaFastConfig()
1946 State->PhyUnitConfig->TxCmdDmaSGId[CmdTCDSGIndex], in Spi_Ip_DmaFastConfig()
1947 … (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[Count].DmaFastPushrCmdLast, in Spi_Ip_DmaFastConfig()
1956 State->PhyUnitConfig->TxCmdDmaSGId[CmdTCDSGIndex], in Spi_Ip_DmaFastConfig()
1957 … (Dma_Ip_uintPtrType)&State->PhyUnitConfig->CmdDmaFast[Count].DmaFastPushrCmd, in Spi_Ip_DmaFastConfig()
1958 State->ExpectedCmdFifoWrites, in Spi_Ip_DmaFastConfig()
1963 State->ExpectedCmdFifoWrites = 0u; in Spi_Ip_DmaFastConfig()
1975 if (NumberOfTransfer < State->PhyUnitConfig->NumberRxSG) in Spi_Ip_DmaFastConfig()
1978 …(void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitCo… in Spi_Ip_DmaFastConfig()
1982 …(void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->TxCmdDmaChannel, State->PhyU… in Spi_Ip_DmaFastConfig()
1984 …(void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->TxDmaChannel, State->PhyUnit… in Spi_Ip_DmaFastConfig()
1986 …(void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->RxDmaChannel, State->PhyUnit… in Spi_Ip_DmaFastConfig()
1989 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQ… in Spi_Ip_DmaFastConfig()
1990 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxCmdDmaChannel, DMA_IP_CH_SET_HARDWARE_… in Spi_Ip_DmaFastConfig()
1991 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQ… in Spi_Ip_DmaFastConfig()
1997 const Spi_Ip_StateStructureType* State; in Spi_Ip_ManageBuffers() local
2005 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ManageBuffers()
2007 DevAssert(State != NULL_PTR); in Spi_Ip_ManageBuffers()
2009 if(SPI_IP_POLLING == State->TransferMode) in Spi_Ip_ManageBuffers()
2012 if((boolean)FALSE == State->PhyUnitConfig->DmaUsed) in Spi_Ip_ManageBuffers()
2021 … (void)Dma_Ip_GetLogicChannelStatus(State->PhyUnitConfig->RxDmaChannel, &DmaChannelStatus); in Spi_Ip_ManageBuffers()
2025 … (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_DONE); in Spi_Ip_ManageBuffers()
2040 Spi_Ip_StateStructureType* State; in Spi_Ip_UpdateTransferParam() local
2049 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateTransferParam()
2051 if (State->Status != SPI_IP_BUSY) in Spi_Ip_UpdateTransferParam()
2053 State->KeepCs = Param->KeepCs; in Spi_Ip_UpdateTransferParam()
2073 const Spi_Ip_StateStructureType* State; in Spi_Ip_UpdateFrameSize() local
2081 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateFrameSize()
2083 DevAssert(State != NULL_PTR); in Spi_Ip_UpdateFrameSize()
2086 if (State->Status != SPI_IP_BUSY) in Spi_Ip_UpdateFrameSize()
2099 const Spi_Ip_StateStructureType* State; in Spi_Ip_UpdateLsb() local
2105 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateLsb()
2107 DevAssert(State != NULL_PTR); in Spi_Ip_UpdateLsb()
2110 if (State->Status != SPI_IP_BUSY) in Spi_Ip_UpdateLsb()
2123 const Spi_Ip_StateStructureType* State; in Spi_Ip_UpdateDefaultTransmitData() local
2129 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateDefaultTransmitData()
2131 DevAssert(State != NULL_PTR); in Spi_Ip_UpdateDefaultTransmitData()
2134 if (State->Status != SPI_IP_BUSY) in Spi_Ip_UpdateDefaultTransmitData()
2147 Spi_Ip_StateStructureType* State; in Spi_Ip_UpdateTransferMode() local
2153 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_UpdateTransferMode()
2155 DevAssert(State != NULL_PTR); in Spi_Ip_UpdateTransferMode()
2158 if (State->Status != SPI_IP_BUSY) in Spi_Ip_UpdateTransferMode()
2160 State->TransferMode = Mode; in Spi_Ip_UpdateTransferMode()
2172 Spi_Ip_StateStructureType* State; in Spi_Ip_Cancel() local
2178 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Cancel()
2180 DevAssert(State != NULL_PTR); in Spi_Ip_Cancel()
2183 if(SPI_IP_BUSY == State->Status) in Spi_Ip_Cancel()
2190 if((boolean)TRUE == State->PhyUnitConfig->DmaUsed) in Spi_Ip_Cancel()
2193 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_R… in Spi_Ip_Cancel()
2195 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_Cancel()
2198 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxCmdDmaChannel, DMA_IP_CH_CLEAR_HARDWAR… in Spi_Ip_Cancel()
2200 …(void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_R… in Spi_Ip_Cancel()
2206 State->Status = SPI_IP_IDLE; in Spi_Ip_Cancel()
2222 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_IrqHandler() local
2225 if(NULL_PTR != State) in Spi_Ip_IrqHandler()
2257 const Spi_Ip_StateStructureType* State; in Spi_Ip_GetStatus() local
2263 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_GetStatus()
2264 if (State != NULL_PTR) in Spi_Ip_GetStatus()
2266 Status = State->Status; in Spi_Ip_GetStatus()
2274 Spi_Ip_StateStructureType* State; in Spi_Ip_SetClockMode() local
2280 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_SetClockMode()
2282 DevAssert(State != NULL_PTR); in Spi_Ip_SetClockMode()
2285 if (State->Status != SPI_IP_BUSY) in Spi_Ip_SetClockMode()
2287 State->ClockMode = ClockMode; in Spi_Ip_SetClockMode()