Lines Matching refs:Length
241 uint16 Length,
1344 uint16 Length, in Spi_Ip_CheckValidParameters() argument
1351 DevAssert(0u != Length); in Spi_Ip_CheckValidParameters()
1355 DevAssert((Length % 4u) == 0u); in Spi_Ip_CheckValidParameters()
1359 DevAssert((Length % 2u) == 0u); in Spi_Ip_CheckValidParameters()
1646 uint16 Length, in Spi_Ip_SyncTransmit() argument
1660 Spi_Ip_CheckValidParameters(ExternalDevice, Length, TxBuffer, RxBuffer, TimeOut); in Spi_Ip_SyncTransmit()
1678 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_SyncTransmit()
1721 uint16 Length, in Spi_Ip_AsyncTransmit() argument
1730 Spi_Ip_CheckValidParameters(ExternalDevice, Length, TxBuffer, RxBuffer, 1u); in Spi_Ip_AsyncTransmit()
1746 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_AsyncTransmit()
1806 DevAssert(0u != FastTransferCfg[Count].Length); in Spi_Ip_AsyncTransmitFast()
1809 DevAssert((FastTransferCfg[Count].Length % 4u) == 0u); in Spi_Ip_AsyncTransmitFast()
1813 DevAssert((FastTransferCfg[Count].Length % 2u) == 0u); in Spi_Ip_AsyncTransmitFast()
1817 DevAssert(SPI_IP_DMA_MAX_ITER_CNT_U16 >= FastTransferCfg[Count].Length); in Spi_Ip_AsyncTransmitFast()
1896 State->ExpectedFifoWrites = FastTransferCfg[Count].Length; in Spi_Ip_DmaFastConfig()
1900 State->ExpectedFifoWrites = FastTransferCfg[Count].Length/2u; in Spi_Ip_DmaFastConfig()