Lines Matching refs:Instance
200 static void Spi_Ip_TransferProcess(uint8 Instance);
202 static void Spi_Ip_CmdDmaTcdSGInit(uint8 Instance);
204 static void Spi_Ip_CmdDmaTcdSGConfig( uint8 Instance,
210 static void Spi_Ip_DmaFastConfig(uint8 Instance, const Spi_Ip_FastTransferType *FastTransferCfg, ui…
211 static void Spi_Ip_RxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq);
212 static void Spi_Ip_RxDmaTcdSGInit(uint8 Instance);
213 static void Spi_Ip_TxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq);
214 static void Spi_Ip_TxDmaTcdSGInit(uint8 Instance);
218 void Spi_Ip_SetUserAccess(uint8 Instance);
219 static void Spi_Ip_SetUserAccessAllowed(uint8 Instance);
225 uint8 Instance
230 uint8 Instance
234 uint8 Instance, boolean ErrorFlag
297 static void Spi_Ip_TransferProcess(uint8 Instance) in Spi_Ip_TransferProcess() argument
299 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TransferProcess()
300 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TransferProcess()
323 Spi_Ip_ReceiveData(NumberOfReads, Instance); in Spi_Ip_TransferProcess()
348 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance); in Spi_Ip_TransferProcess()
367 Spi_Ip_ChannelFinished(Instance, ErrorFlag); in Spi_Ip_TransferProcess()
591 static void Spi_Ip_CmdDmaTcdSGInit(uint8 Instance) in Spi_Ip_CmdDmaTcdSGInit() argument
593 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_CmdDmaTcdSGInit()
594 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_CmdDmaTcdSGInit()
630 static void Spi_Ip_TxDmaTcdSGInit(uint8 Instance) in Spi_Ip_TxDmaTcdSGInit() argument
632 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TxDmaTcdSGInit()
633 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TxDmaTcdSGInit()
667 static void Spi_Ip_TxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq) in Spi_Ip_TxDmaTcdSGConfig() argument
669 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_TxDmaTcdSGConfig()
724 static void Spi_Ip_RxDmaTcdSGInit(uint8 Instance) in Spi_Ip_RxDmaTcdSGInit() argument
726 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_RxDmaTcdSGInit()
727 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_RxDmaTcdSGInit()
759 static void Spi_Ip_RxDmaTcdSGConfig(uint8 Instance, uint8 TCDSGIndex, uint8 DisHwReq) in Spi_Ip_RxDmaTcdSGConfig() argument
761 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_RxDmaTcdSGConfig()
820 static void Spi_Ip_CmdDmaTcdSGConfig( uint8 Instance, in Spi_Ip_CmdDmaTcdSGConfig() argument
827 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_CmdDmaTcdSGConfig()
1096 uint8 Instance in Spi_Ip_WriteTxFifo() argument
1099 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_WriteTxFifo()
1100 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_WriteTxFifo()
1165 uint8 Instance in Spi_Ip_ReceiveData() argument
1168 Spi_Ip_StateStructureType* const State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ReceiveData()
1169 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_ReceiveData()
1243 static void Spi_Ip_ChannelFinished(uint8 Instance, boolean ErrorFlag) in Spi_Ip_ChannelFinished() argument
1245 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ChannelFinished()
1261 State->Callback(Instance, EventState); in Spi_Ip_ChannelFinished()
1300 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, State->ExternalDevice->Instance); in Spi_Ip_AsyncStart()
1324 Spi_Ip_WriteTxFifo(NumberOfWrites, State->ExternalDevice->Instance); in Spi_Ip_AsyncStart()
1365 DevAssert(Spi_Ip_apxStateStructureArray[ExternalDevice->Instance] != NULL_PTR); in Spi_Ip_CheckValidParameters()
1392 void Spi_Ip_IrqDmaHandler(uint8 Instance) in Spi_Ip_IrqDmaHandler() argument
1394 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqDmaHandler()
1395 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_IrqDmaHandler()
1448 State->Callback(Instance, SPI_IP_EVENT_FAULT); in Spi_Ip_IrqDmaHandler()
1452 State->Callback(Instance, SPI_IP_EVENT_END_TRANSFER); in Spi_Ip_IrqDmaHandler()
1469 void Spi_Ip_SetUserAccess(uint8 Instance) in Spi_Ip_SetUserAccess() argument
1471 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SetUserAccess()
1479 static void Spi_Ip_SetUserAccessAllowed(uint8 Instance) in Spi_Ip_SetUserAccessAllowed() argument
1481 OsIf_Trusted_Call1param(Spi_Ip_SetUserAccess, Instance); in Spi_Ip_SetUserAccessAllowed()
1490 uint8 Instance = 0u; in Spi_Ip_Init() local
1495 Instance = PhyUnitConfigPtr->Instance; in Spi_Ip_Init()
1496 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Init()
1497 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Init()
1501 … Spi_Ip_apxStateStructureArray[Instance] = &Spi_Ip_axStateStructure[PhyUnitConfigPtr->StateIndex]; in Spi_Ip_Init()
1502 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Init()
1505 Spi_Ip_SetUserAccessAllowed(Instance); in Spi_Ip_Init()
1517 Spi_Ip_TxDmaTcdSGInit(Instance); in Spi_Ip_Init()
1518 Spi_Ip_RxDmaTcdSGInit(Instance); in Spi_Ip_Init()
1522 Spi_Ip_CmdDmaTcdSGInit(Instance); in Spi_Ip_Init()
1526 Status = Spi_Ip_UpdateTransferMode(Instance, PhyUnitConfigPtr->TransferMode); in Spi_Ip_Init()
1534 Spi_Ip_StatusType Spi_Ip_DeInit(uint8 Instance) in Spi_Ip_DeInit() argument
1541 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_DeInit()
1543 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_DeInit()
1544 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_DeInit()
1564 Spi_Ip_apxStateStructureArray[Instance] = NULL_PTR; in Spi_Ip_DeInit()
1588 … boolean Spi_Ip_SyncReadWriteStep(Spi_Ip_StateStructureType *State, SPI_Type *Base, uint8 Instance) in Spi_Ip_SyncReadWriteStep() argument
1618 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance); in Spi_Ip_SyncReadWriteStep()
1634 Spi_Ip_ReceiveData(NumberOfReads, Instance); in Spi_Ip_SyncReadWriteStep()
1656 uint8 Instance = 0u; in Spi_Ip_SyncTransmit() local
1662 Instance = ExternalDevice->Instance; in Spi_Ip_SyncTransmit()
1663 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_SyncTransmit()
1665 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SyncTransmit()
1687 StepDone = Spi_Ip_SyncReadWriteStep(State, Base, Instance); in Spi_Ip_SyncTransmit()
1712 Spi_Ip_ChannelFinished(Instance, FALSE); in Spi_Ip_SyncTransmit()
1733 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_AsyncTransmit()
1734 Base = Spi_Ip_apxBases[ExternalDevice->Instance]; in Spi_Ip_AsyncTransmit()
1789 uint8 Instance = 0u; in Spi_Ip_AsyncTransmitFast() local
1797 State = Spi_Ip_apxStateStructureArray[FastTransferCfg[0u].ExternalDevice->Instance]; in Spi_Ip_AsyncTransmitFast()
1821 Instance = FastTransferCfg[0u].ExternalDevice->Instance; in Spi_Ip_AsyncTransmitFast()
1822 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_AsyncTransmitFast()
1823 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_AsyncTransmitFast()
1862 Spi_Ip_DmaFastConfig(Instance, FastTransferCfg, NumberOfTransfer); in Spi_Ip_AsyncTransmitFast()
1875 static void Spi_Ip_DmaFastConfig(uint8 Instance, const Spi_Ip_FastTransferType *FastTransferCfg, ui… in Spi_Ip_DmaFastConfig() argument
1877 Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_DmaFastConfig()
1937 Spi_Ip_CmdDmaTcdSGConfig( Instance, in Spi_Ip_DmaFastConfig()
1945 Spi_Ip_CmdDmaTcdSGConfig( Instance, in Spi_Ip_DmaFastConfig()
1955 Spi_Ip_CmdDmaTcdSGConfig( Instance, in Spi_Ip_DmaFastConfig()
1966 Spi_Ip_TxDmaTcdSGConfig(Instance, Count, DisHwRequest); in Spi_Ip_DmaFastConfig()
1969 Spi_Ip_RxDmaTcdSGConfig(Instance, Count, DisHwRequest); in Spi_Ip_DmaFastConfig()
1995 void Spi_Ip_ManageBuffers(uint8 Instance) in Spi_Ip_ManageBuffers() argument
2003 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_ManageBuffers()
2005 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_ManageBuffers()
2015 Spi_Ip_TransferProcess(Instance); in Spi_Ip_ManageBuffers()
2026 Spi_Ip_IrqDmaHandler(Instance); in Spi_Ip_ManageBuffers()
2046 DevAssert(NULL_PTR != Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]); in Spi_Ip_UpdateTransferParam()
2049 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateTransferParam()
2081 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateFrameSize()
2105 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateLsb()
2129 State = Spi_Ip_apxStateStructureArray[ExternalDevice->Instance]; in Spi_Ip_UpdateDefaultTransmitData()
2145 Spi_Ip_StatusType Spi_Ip_UpdateTransferMode(uint8 Instance, Spi_Ip_ModeType Mode) in Spi_Ip_UpdateTransferMode() argument
2151 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_UpdateTransferMode()
2153 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_UpdateTransferMode()
2169 void Spi_Ip_Cancel(uint8 Instance) in Spi_Ip_Cancel() argument
2175 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_Cancel()
2177 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Cancel()
2178 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_Cancel()
2219 void Spi_Ip_IrqHandler(uint8 Instance) in Spi_Ip_IrqHandler() argument
2221 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqHandler()
2222 const Spi_Ip_StateStructureType* State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_IrqHandler()
2232 Spi_Ip_TransferProcess(Instance); in Spi_Ip_IrqHandler()
2255 Spi_Ip_HwStatusType Spi_Ip_GetStatus(uint8 Instance) in Spi_Ip_GetStatus() argument
2261 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_GetStatus()
2263 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_GetStatus()
2272 Spi_Ip_StatusType Spi_Ip_SetClockMode(uint8 Instance, Spi_Ip_DualClockModeType ClockMode) in Spi_Ip_SetClockMode() argument
2278 DevAssert(Instance < SPI_INSTANCE_COUNT); in Spi_Ip_SetClockMode()
2280 State = Spi_Ip_apxStateStructureArray[Instance]; in Spi_Ip_SetClockMode()