342             if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_TransferProcess()
344                 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_TransferProcess()
346             if(State->CurrentTxFifoSlot != 0u)  in Spi_Ip_TransferProcess()
348                 Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance);  in Spi_Ip_TransferProcess()
350                 State->CurrentTxFifoSlot = 0u;  in Spi_Ip_TransferProcess()
1227         State->CurrentTxFifoSlot += LimitedNumberOfReads * 2u;  in Spi_Ip_ReceiveData()
1231         State->CurrentTxFifoSlot += LimitedNumberOfReads;  in Spi_Ip_ReceiveData()
1294         if (State->CurrentTxFifoSlot > RemainingWrites)  in Spi_Ip_AsyncStart()
1296             State->CurrentTxFifoSlot = RemainingWrites;  in Spi_Ip_AsyncStart()
1298         if (State->CurrentTxFifoSlot != 0u)  in Spi_Ip_AsyncStart()
1300             Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, State->ExternalDevice->Instance);  in Spi_Ip_AsyncStart()
1302             State->CurrentTxFifoSlot = 0u;  in Spi_Ip_AsyncStart()
1326         State->CurrentTxFifoSlot -= NumberOfWrites;  in Spi_Ip_AsyncStart()
1612     if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex))  in Spi_Ip_SyncReadWriteStep()
1614         State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex;  in Spi_Ip_SyncReadWriteStep()
1616     if (State->CurrentTxFifoSlot != 0u)  in Spi_Ip_SyncReadWriteStep()
1618         Spi_Ip_WriteTxFifo(State->CurrentTxFifoSlot, Instance);  in Spi_Ip_SyncReadWriteStep()
1620         State->CurrentTxFifoSlot = 0u;  in Spi_Ip_SyncReadWriteStep()
1683         State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16;  in Spi_Ip_SyncTransmit()
1743         State->CurrentTxFifoSlot = SPI_IP_FIFO_SIZE_U16;  in Spi_Ip_AsyncTransmit()