Lines Matching refs:Base
259 static uint16 Spi_Ip_WriteCmdFifo(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_WriteCmdFifo() argument
264 NumberOfCmdWrites = (uint16)((Base->SREX) & SPI_SREX_CMDCTR_MASK) >> SPI_SREX_CMDCTR_SHIFT; in Spi_Ip_WriteCmdFifo()
283 Base->PUSHR.FIFO.CMD = State->PushrCmds[State->NbCmdsIndex]; in Spi_Ip_WriteCmdFifo()
299 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TransferProcess() local
308 SrStatusRegister = Base->SR; in Spi_Ip_TransferProcess()
309 Base->SR &= 0xFFFF0000u; in Spi_Ip_TransferProcess()
319 NumberOfReads = (uint16)(((Base->SR) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT); in Spi_Ip_TransferProcess()
332 (void)Spi_Ip_WriteCmdFifo(State, Base); in Spi_Ip_TransferProcess()
361 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_TransferProcess()
365 Base->RSER = 0U; in Spi_Ip_TransferProcess()
424 static void Spi_Ip_UpdateCtarAndPushr(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_UpdateCtarAndPushr() argument
448 Base->MODE.CTAR_SLAVE[0] = CtarSrc | SPI_CTAR_SLAVE_FMSZ(CtarFrameSize); in Spi_Ip_UpdateCtarAndPushr()
454 Base->MODE.CTAR[i] = CtarSrc | in Spi_Ip_UpdateCtarAndPushr()
457 Base->CTARE[i] = Dev->Ctare | in Spi_Ip_UpdateCtarAndPushr()
484 static void Spi_Ip_PrepareTransfer(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint16 NbBytes) in Spi_Ip_PrepareTransfer() argument
580 Spi_Ip_UpdateCtarAndPushr(State, Base); in Spi_Ip_PrepareTransfer()
593 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_CmdDmaTcdSGInit() local
610 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.CMD; /* dest address write*/ in Spi_Ip_CmdDmaTcdSGInit()
632 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_TxDmaTcdSGInit() local
649 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_TxDmaTcdSGInit()
726 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_RxDmaTcdSGInit() local
742 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_RxDmaTcdSGInit()
907 static void Spi_Ip_DmaConfig(const Spi_Ip_StateStructureType* State,const SPI_Type *Base) in Spi_Ip_DmaConfig() argument
922 DmaTcdList[1u].Value = (Dma_Ip_uintPtrType)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_DmaConfig()
964 DmaTcdList[0u].Value = (Dma_Ip_uintPtrType)&Base->POPR; /* src address read */ in Spi_Ip_DmaConfig()
1058 static void Spi_Ip_DmaAsyncStart(Spi_Ip_StateStructureType* State, SPI_Type *Base, uint32 IrqEn) in Spi_Ip_DmaAsyncStart() argument
1073 Spi_Ip_DmaConfig(State, Base); in Spi_Ip_DmaAsyncStart()
1078 Base->RSER = SPI_RSER_CMDFFF_RE(1) | SPI_RSER_CMDFFF_DIRS(1) | in Spi_Ip_DmaAsyncStart()
1100 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_WriteTxFifo() local
1131 Base->PUSHR.FIFO.TX = Data; in Spi_Ip_WriteTxFifo()
1148 Base->PUSHR.FIFO.TX = Data; in Spi_Ip_WriteTxFifo()
1169 const SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_ReceiveData() local
1199 Data = Base->POPR; in Spi_Ip_ReceiveData()
1219 (void)Base->POPR; in Spi_Ip_ReceiveData()
1277 static void Spi_Ip_AsyncStart(Spi_Ip_StateStructureType* State, SPI_Type *Base) in Spi_Ip_AsyncStart() argument
1285 Base->RSER = SPI_RSER_TCF_RE(1) | SPI_RSER_TFUF_RE(1) | SPI_RSER_RFOF_RE(1); in Spi_Ip_AsyncStart()
1292 (void)Spi_Ip_WriteCmdFifo(State, Base); in Spi_Ip_AsyncStart()
1309 NumberOfWrites = (uint16)((Base->SR) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT; in Spi_Ip_AsyncStart()
1394 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqDmaHandler() local
1403 SrStatusRegister = Base->SR; in Spi_Ip_IrqDmaHandler()
1404 Base->SR &= 0xFFFF0000u; in Spi_Ip_IrqDmaHandler()
1430 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_IrqDmaHandler()
1434 Base->RSER = 0U; in Spi_Ip_IrqDmaHandler()
1471 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SetUserAccess() local
1473 SET_USER_ACCESS_ALLOWED((uint32)Base,SPI_IP_PROT_MEM_U32); in Spi_Ip_SetUserAccess()
1487 SPI_Type* Base; in Spi_Ip_Init() local
1497 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Init()
1508 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_Init()
1509 Base->MCR = PhyUnitConfigPtr->Mcr; in Spi_Ip_Init()
1536 SPI_Type* Base; in Spi_Ip_DeInit() local
1543 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_DeInit()
1555 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_DeInit()
1557 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_DeInit()
1558 Base->MCR = 0x4001u; in Spi_Ip_DeInit()
1559 Base->MODE.CTAR[0] = 0x78000000u; in Spi_Ip_DeInit()
1560 Base->SR = 0xFFFF0000u; in Spi_Ip_DeInit()
1561 Base->RSER = 0u; in Spi_Ip_DeInit()
1562 Base->CTARE[0] = 0x1u; in Spi_Ip_DeInit()
1588 static boolean Spi_Ip_SyncReadWriteStep(Spi_Ip_StateStructureType *State, SPI_Type *Base, uint8 Ins… in Spi_Ip_SyncReadWriteStep() argument
1596 if (Spi_Ip_WriteCmdFifo(State, Base) != 0u) in Spi_Ip_SyncReadWriteStep()
1623 if(((Base->MCR) & SPI_MCR_HALT_MASK) == SPI_MCR_HALT_MASK) in Spi_Ip_SyncReadWriteStep()
1625 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_SyncReadWriteStep()
1630 NumberOfReads = (uint16)(((Base->SR) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT); in Spi_Ip_SyncReadWriteStep()
1650 SPI_Type *Base; in Spi_Ip_SyncTransmit() local
1665 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_SyncTransmit()
1670 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_SyncTransmit()
1672 Base->SR = 0xFFFF0000u; in Spi_Ip_SyncTransmit()
1678 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_SyncTransmit()
1687 StepDone = Spi_Ip_SyncReadWriteStep(State, Base, Instance); in Spi_Ip_SyncTransmit()
1709 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_SyncTransmit()
1725 SPI_Type* Base; in Spi_Ip_AsyncTransmit() local
1734 Base = Spi_Ip_apxBases[ExternalDevice->Instance]; in Spi_Ip_AsyncTransmit()
1746 Spi_Ip_PrepareTransfer(State, Base, Length); in Spi_Ip_AsyncTransmit()
1748 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_AsyncTransmit()
1750 Base->SR &= 0xFFFF0000u; in Spi_Ip_AsyncTransmit()
1759 Base->RSER = 0U; in Spi_Ip_AsyncTransmit()
1762 Spi_Ip_AsyncStart(State, Base); in Spi_Ip_AsyncTransmit()
1768 Spi_Ip_DmaAsyncStart(State, Base, (State->TransferMode == SPI_IP_POLLING) ? 0u : 1u); in Spi_Ip_AsyncTransmit()
1773 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_AsyncTransmit()
1786 SPI_Type* Base; in Spi_Ip_AsyncTransmitFast() local
1822 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_AsyncTransmitFast()
1838 Base->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK; in Spi_Ip_AsyncTransmitFast()
1840 Base->SR &= 0xFFFF0000u; in Spi_Ip_AsyncTransmitFast()
1856 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar[State->ClockMode] | SPI_CTAR_FMSZ((… in Spi_Ip_AsyncTransmitFast()
1858 …Base->MODE.CTAR[0u] = FastTransferCfg[0u].ExternalDevice->Ctar | SPI_CTAR_FMSZ(((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1860 …Base->CTARE[0u] = FastTransferCfg[0u].ExternalDevice->Ctare | SPI_CTARE_FMSZE((((uint32)State->Ext… in Spi_Ip_AsyncTransmitFast()
1863 …Base->RSER = SPI_RSER_CMDFFF_RE(1u) | SPI_RSER_CMDFFF_DIRS(1u) | SPI_RSER_TFFF_RE(1u) | SPI_RSER_T… in Spi_Ip_AsyncTransmitFast()
1866 Base->MCR &= ~SPI_MCR_HALT_MASK; in Spi_Ip_AsyncTransmitFast()
2171 SPI_Type* Base; in Spi_Ip_Cancel() local
2177 Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_Cancel()
2186 Base->MCR |= SPI_MCR_HALT_MASK; in Spi_Ip_Cancel()
2188 Base->RSER = 0U; in Spi_Ip_Cancel()
2204 Base->MCR |= (SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK); in Spi_Ip_Cancel()
2221 SPI_Type* Base = Spi_Ip_apxBases[Instance]; in Spi_Ip_IrqHandler() local
2228 IrqFlags = Base->SR & (SPI_SR_TCF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK); in Spi_Ip_IrqHandler()
2229 … IrqFlags &= Base->RSER & (SPI_RSER_TCF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_TFUF_RE_MASK); in Spi_Ip_IrqHandler()
2243 Base->SR &= 0xFFFF0000u; in Spi_Ip_IrqHandler()