Lines Matching refs:base
559 typedef void (*xspi_transfer_callback_t)(XSPI_Type *base, xspi_handle_t *handle, status_t status, v…
803 uint32_t XSPI_GetInstance(XSPI_Type *base);
811 status_t XSPI_CheckAndClearError(XSPI_Type *base, uint32_t status);
822 void XSPI_Init(XSPI_Type *base, const xspi_config_t *ptrConfig);
841 void XSPI_Deinit(XSPI_Type *base);
852 void XSPI_UpdateLUT(XSPI_Type *base, uint8_t index, const uint32_t *cmd, uint8_t count);
860 static inline void XSPI_SetOTFADPrefetchBoundary(XSPI_Type *base, xspi_otfad_prefetch_boundary_t bo… in XSPI_SetOTFADPrefetchBoundary() argument
862 …base->SPTRCLR = (base->SPTRCLR & (~XSPI_SPTRCLR_OTFAD_BNDRY_MASK)) | XSPI_SPTRCLR_OTFAD_BNDRY(boun… in XSPI_SetOTFADPrefetchBoundary()
870 static inline void XSPI_UpdateByteOrder(XSPI_Type *base, xspi_byte_order_t byteOrder) in XSPI_UpdateByteOrder() argument
872 base->MCR = ((base->MCR) & (~XSPI_MCR_END_CFG_MASK)) | XSPI_MCR_END_CFG(byteOrder); in XSPI_UpdateByteOrder()
881 static inline void XSPI_EnableModule(XSPI_Type *base, bool enable) in XSPI_EnableModule() argument
885 base->MCR &= ~XSPI_MCR_MDIS_MASK; in XSPI_EnableModule()
889 base->MCR |= XSPI_MCR_MDIS_MASK; in XSPI_EnableModule()
901 static inline bool XSPI_CheckModuleEnabled(XSPI_Type *base) in XSPI_CheckModuleEnabled() argument
903 return ((base->MCR & XSPI_MCR_MDIS_MASK) == 0UL); in XSPI_CheckModuleEnabled()
913 void XSPI_ResetSfmAndAhbDomain(XSPI_Type *base);
920 static inline void XSPI_ResetTgQueue(XSPI_Type *base) in XSPI_ResetTgQueue() argument
922 base->MCR |= XSPI_MCR_IPS_TG_RST_MASK; in XSPI_ResetTgQueue()
930 static inline void XSPI_SoftwareReset(XSPI_Type *base) in XSPI_SoftwareReset() argument
932 XSPI_ResetTgQueue(base); in XSPI_SoftwareReset()
933 XSPI_ResetSfmAndAhbDomain(base); in XSPI_SoftwareReset()
944 static inline bool XSPI_CheckGlobalConfigLocked(XSPI_Type *base) in XSPI_CheckGlobalConfigLocked() argument
946 return (bool)((base->MGC & XSPI_MGC_GCLCK_MASK) != 0UL); in XSPI_CheckGlobalConfigLocked()
961 void XSPI_SetHyperBusX16Mode(XSPI_Type *base, xspi_hyper_bus_x16_mode_t x16Mode);
974 status_t XSPI_UpdateDeviceAddrMode(XSPI_Type *base, xspi_device_addr_mode_t addrMode);
988 static inline void XSPI_EnableVariableLatency(XSPI_Type *base, bool enable) in XSPI_EnableVariableLatency() argument
992 base->MCR |= XSPI_MCR_VAR_LAT_EN_MASK; in XSPI_EnableVariableLatency()
996 base->MCR &= ~XSPI_MCR_VAR_LAT_EN_MASK; in XSPI_EnableVariableLatency()
1010 static inline void XSPI_EnableDozeMode(XSPI_Type *base, bool enable) in XSPI_EnableDozeMode() argument
1014 base->MCR |= XSPI_MCR_DOZE_MASK; in XSPI_EnableDozeMode()
1018 base->MCR &= ~XSPI_MCR_DOZE_MASK; in XSPI_EnableDozeMode()
1031 static inline void XSPI_SetSignalOutputValue(XSPI_Type *base, uint32_t signalMask, bool outputLogic) in XSPI_SetSignalOutputValue() argument
1035 if (XSPI_CheckModuleEnabled(base)) in XSPI_SetSignalOutputValue()
1038 XSPI_EnableModule(base, false); in XSPI_SetSignalOutputValue()
1044 base->MCR |= signalMask; in XSPI_SetSignalOutputValue()
1049 base->MCR &= ~signalMask; in XSPI_SetSignalOutputValue()
1054 XSPI_EnableModule(base, true); in XSPI_SetSignalOutputValue()
1068 static inline void XSPI_EnableInvertedSerialClockOutput(XSPI_Type *base, bool enable) in XSPI_EnableInvertedSerialClockOutput() argument
1072 if (XSPI_CheckModuleEnabled(base)) in XSPI_EnableInvertedSerialClockOutput()
1075 XSPI_EnableModule(base, false); in XSPI_EnableInvertedSerialClockOutput()
1080 base->MCR |= XSPI_MCR_CKN_FA_EN_MASK; in XSPI_EnableInvertedSerialClockOutput()
1084 base->MCR &= ~XSPI_MCR_CKN_FA_EN_MASK; in XSPI_EnableInvertedSerialClockOutput()
1089 XSPI_EnableModule(base, true); in XSPI_EnableInvertedSerialClockOutput()
1102 void XSPI_UpdateDllValue( XSPI_Type *base, xspi_dll_config_t *ptrDllConfig,
1116 status_t XSPI_SetDataLearningConfig(XSPI_Type *base, xspi_data_learning_config_t *ptrDataLearningCo…
1126 static inline bool XSPI_CheckDataLearningFailure(XSPI_Type *base) in XSPI_CheckDataLearningFailure() argument
1128 return (bool)((base->DLSR_F[0] & XSPI_DLSR_F_DLPFF_MASK) == XSPI_DLSR_F_DLPFF_MASK); in XSPI_CheckDataLearningFailure()
1138 static inline void XSPI_GetDataLearningEdgeMatchSignature(XSPI_Type *base, uint8_t *posEdgeMatch, u… in XSPI_GetDataLearningEdgeMatchSignature() argument
1140 uint32_t tmp32 = base->DLSR_F[0]; in XSPI_GetDataLearningEdgeMatchSignature()
1162 status_t XSPI_SetDeviceConfig(XSPI_Type *base, xspi_device_config_t *devConfig);
1178 static inline void XSPI_EnableInterrupts(XSPI_Type *base, uint32_t mask) in XSPI_EnableInterrupts() argument
1180 base->RSER |= mask; in XSPI_EnableInterrupts()
1189 static inline void XSPI_DisableInterrupts(XSPI_Type *base, uint32_t mask) in XSPI_DisableInterrupts() argument
1191 base->RSER &= ~mask; in XSPI_DisableInterrupts()
1205 static inline void XSPI_EnableTxDMA(XSPI_Type *base, bool enable) in XSPI_EnableTxDMA() argument
1209 base->RSER |= XSPI_RSER_TBFDE_MASK; in XSPI_EnableTxDMA()
1213 base->RSER &= ~XSPI_RSER_TBFDE_MASK; in XSPI_EnableTxDMA()
1223 static inline void XSPI_EnableRxDMA(XSPI_Type *base, bool enable) in XSPI_EnableRxDMA() argument
1227 base->RSER |= XSPI_RSER_RBDDE_MASK; in XSPI_EnableRxDMA()
1231 base->RSER &= ~XSPI_RSER_RBDDE_MASK; in XSPI_EnableRxDMA()
1242 static inline uint32_t XSPI_GetTxFifoAddress(XSPI_Type *base) in XSPI_GetTxFifoAddress() argument
1244 return (uint32_t)&base->TBDR; in XSPI_GetTxFifoAddress()
1254 static inline uint32_t XSPI_GetRxFifoAddress(XSPI_Type *base) in XSPI_GetRxFifoAddress() argument
1256 return (uint32_t)&base->RBDR[0]; in XSPI_GetRxFifoAddress()
1272 static inline uint32_t XSPI_GetInterruptStatusFlags(XSPI_Type *base) in XSPI_GetInterruptStatusFlags() argument
1274 return base->ERRSTAT; in XSPI_GetInterruptStatusFlags()
1284 static inline bool XSPI_GetBusIdleStatus(XSPI_Type *base) in XSPI_GetBusIdleStatus() argument
1286 return (bool)(XSPI_SR_BUSY_MASK != (base->SR & XSPI_SR_BUSY_MASK)); in XSPI_GetBusIdleStatus()
1297 static inline bool XSPI_CheckAhbReadAccessAsserted(XSPI_Type *base) in XSPI_CheckAhbReadAccessAsserted() argument
1299 return (bool)((base->SR & XSPI_SR_AHB_ACC_MASK) != 0UL); in XSPI_CheckAhbReadAccessAsserted()
1310 static inline bool XSPI_CheckAhbWriteAccessAsserted(XSPI_Type *base) in XSPI_CheckAhbWriteAccessAsserted() argument
1312 return (bool)((base->SR & XSPI_SR_AWRACC_MASK) != 0UL); in XSPI_CheckAhbWriteAccessAsserted()
1328 static inline void XSPI_ResetTxRxBuffer(XSPI_Type *base, bool txFifo, bool rxFifo) in XSPI_ResetTxRxBuffer() argument
1332 base->MCR |= XSPI_MCR_CLR_TXF_MASK; in XSPI_ResetTxRxBuffer()
1336 base->MCR |= XSPI_MCR_CLR_RXF_MASK; in XSPI_ResetTxRxBuffer()
1345 static inline void XSPI_ClearTxBuffer(XSPI_Type *base) in XSPI_ClearTxBuffer() argument
1347 base->MCR |= XSPI_MCR_CLR_TXF_MASK; in XSPI_ClearTxBuffer()
1366 status_t XSPI_UpdateTxBufferWaterMark(XSPI_Type *base, uint32_t waterMark);
1376 static inline bool XSPI_CheckTxBuffLockOpen(XSPI_Type *base) in XSPI_CheckTxBuffLockOpen() argument
1378 return (bool)((base->FSMSTAT & XSPI_FSMSTAT_STATE_MASK) == XSPI_FSMSTAT_STATE(1UL)); in XSPI_CheckTxBuffLockOpen()
1387 static inline void XSPI_WriteTxBuffer(XSPI_Type *base, uint32_t data) in XSPI_WriteTxBuffer() argument
1389 base->TBDR = data; in XSPI_WriteTxBuffer()
1397 static inline void XSPI_ClearRxBuffer(XSPI_Type *base) in XSPI_ClearRxBuffer() argument
1399 base->MCR |= XSPI_MCR_CLR_RXF_MASK; in XSPI_ClearRxBuffer()
1415 static inline uint32_t XSPI_ReadRxBuffer(XSPI_Type *base, uint8_t fifoIndex) in XSPI_ReadRxBuffer() argument
1417 return base->RBDR[fifoIndex]; in XSPI_ReadRxBuffer()
1427 static inline void XSPI_TriggerRxBufferPopEvent(XSPI_Type *base) in XSPI_TriggerRxBufferPopEvent() argument
1429 base->FR = XSPI_FR_RBDF_MASK; in XSPI_TriggerRxBufferPopEvent()
1452 status_t XSPI_UpdateRxBufferWaterMark(XSPI_Type *base, uint32_t waterMark);
1462 static inline bool XSPI_CheckRxBufferWaterMarkExceed(XSPI_Type *base) in XSPI_CheckRxBufferWaterMarkExceed() argument
1464 return (bool)((base->FR & XSPI_FR_RBDF_MASK) == XSPI_FR_RBDF_MASK); in XSPI_CheckRxBufferWaterMarkExceed()
1474 static inline uint32_t XSPI_GetRxBufferAvailableBytesCount(XSPI_Type *base) in XSPI_GetRxBufferAvailableBytesCount() argument
1476 return ((base->RBSR & XSPI_RBSR_RDBFL_MASK) >> XSPI_RBSR_RDBFL_SHIFT) * 4UL; in XSPI_GetRxBufferAvailableBytesCount()
1486 static inline uint32_t XSPI_GetRxBufferRemovedBytesCount(XSPI_Type *base) in XSPI_GetRxBufferRemovedBytesCount() argument
1488 return ((base->RBSR & XSPI_RBSR_RDCTR_MASK) >> XSPI_RBSR_RDCTR_SHIFT) * 4UL; in XSPI_GetRxBufferRemovedBytesCount()
1498 void XSPI_SetSFPFradEALMode(XSPI_Type *base, xspi_exclusive_access_lock_mode_t ealMode, uint8_t fra…
1507 void XSPI_UpdateSFPConfig(XSPI_Type *base,
1519 static inline bool XSPI_CheckSFPFradEnabled(XSPI_Type *base) in XSPI_CheckSFPFradEnabled() argument
1521 return (bool)((base->MGC & XSPI_MGC_GVLDFRAD_MASK) != 0UL); in XSPI_CheckSFPFradEnabled()
1532 xspi_mdad_error_reason_t XSPI_GetMdadErrorReason(XSPI_Type *base, xspi_target_group_t tgId);
1541 void XSPI_GetFradLastTransactionsInfo(XSPI_Type *base, xspi_frad_transaction_info_t *ptrInfo, uint8…
1554 status_t XSPI_UpdateSFPArbitrationLockTimeoutCounter(XSPI_Type *base, uint32_t countValue);
1562 void XSPI_ClearTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId);
1572 void XSPI_GetTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId, xspi_tg_add_write_status_…
1580 void XSPI_UnlockIpAccessArbitration(XSPI_Type *base, xspi_target_group_t tgId);
1590 static inline bool XSPI_CheckIPAccessAsserted(XSPI_Type *base) in XSPI_CheckIPAccessAsserted() argument
1592 return (bool)((base->SR & XSPI_SR_IP_ACC_MASK) != 0UL); in XSPI_CheckIPAccessAsserted()
1600 static inline void XSPI_ClearIPAccessSeqPointer(XSPI_Type *base) in XSPI_ClearIPAccessSeqPointer() argument
1602 base->SPTRCLR |= XSPI_SPTRCLR_IPPTRC_MASK; in XSPI_ClearIPAccessSeqPointer()
1619 status_t XSPI_UpdateIPAccessTimeoutCounter(XSPI_Type *base, uint32_t countValue);
1629 static inline bool XSPI_CheckIPAccessGranted(XSPI_Type *base) in XSPI_CheckIPAccessGranted() argument
1631 return (bool)((base->FSMSTAT & XSPI_FSMSTAT_VLD_MASK) != 0UL); in XSPI_CheckIPAccessGranted()
1642 static inline bool XSPI_CheckIpWriteTriggered(XSPI_Type *base) in XSPI_CheckIpWriteTriggered() argument
1644 return (bool)((base->FSMSTAT & XSPI_FSMSTAT_STATE_MASK) == XSPI_FSMSTAT_STATE(2U)); in XSPI_CheckIpWriteTriggered()
1655 static inline bool XSPI_CheckIpReadTriggered(XSPI_Type *base) in XSPI_CheckIpReadTriggered() argument
1657 return (bool)((base->FSMSTAT & XSPI_FSMSTAT_STATE_MASK) == XSPI_FSMSTAT_STATE(3U)); in XSPI_CheckIpReadTriggered()
1674 status_t XSPI_StartIpAccess(XSPI_Type *base, uint32_t addr, uint8_t seqIndex,
1694 status_t XSPI_SetIpAccessConfig(XSPI_Type *base, xspi_ip_access_config_t *ptrIpAccessConfig);
1710 status_t XSPI_WriteBlocking(XSPI_Type *base, uint8_t *buffer, size_t size);
1726 status_t XSPI_ReadBlocking(XSPI_Type *base, uint8_t *buffer, size_t size);
1739 status_t XSPI_TransferBlocking(XSPI_Type *base, xspi_transfer_t *xfer);
1749 void XSPI_TransferCreateHandle(XSPI_Type *base,
1770 status_t XSPI_TransferNonBlocking(XSPI_Type *base, xspi_handle_t *handle, xspi_transfer_t *xfer);
1782 status_t XSPI_TransferGetCount(XSPI_Type *base, xspi_handle_t *handle, size_t *count);
1793 void XSPI_TransferAbort(XSPI_Type *base, xspi_handle_t *handle);
1809 static inline void XSPI_ClearAhbBuffer(XSPI_Type *base) in XSPI_ClearAhbBuffer() argument
1811 base->SPTRCLR |= XSPI_SPTRCLR_ABRT_CLR_MASK; in XSPI_ClearAhbBuffer()
1812 while ((base->SPTRCLR & XSPI_SPTRCLR_ABRT_CLR_MASK) != 0UL) in XSPI_ClearAhbBuffer()
1828 status_t XSPI_EnableAhbBufferWriteFlush(XSPI_Type *base, bool enable);
1843 status_t XSPI_SetAhbBufferConfig(XSPI_Type *base,
1862 status_t XSPI_UpdateAhbBufferSize(XSPI_Type *base, uint16_t buf0Size,
1876 xspi_ahb_sub_buffer_status_t XSPI_GetAhbSubBufferStatus(XSPI_Type *base, uint8_t ahbBufferId, uint8…
1883 static inline void XSPI_StartAhbBufferPerfMonitor(XSPI_Type *base) in XSPI_StartAhbBufferPerfMonitor() argument
1885 base->AHB_PERF_CTRL |= XSPI_AHB_PERF_CTRL_CNTSTART_MASK; in XSPI_StartAhbBufferPerfMonitor()
1895 void XSPI_EnableAhbBufferPerfMonitor(XSPI_Type *base, uint8_t ahbBufferId, uint8_t subBufferId);
1903 static inline void XSPI_DisableAhbBufferPerfMonitor(XSPI_Type *base, uint8_t ahbBufferId) in XSPI_DisableAhbBufferPerfMonitor() argument
1905 …base->AHB_PERF_CTRL &= (uint32_t)(~(uint32_t)(XSPI_AHB_PERF_CTRL_BUF0_EN_MASK << (uint32_t)(ahbBuf… in XSPI_DisableAhbBufferPerfMonitor()
1913 static inline void XSPI_StopAhbBufferPerfMonitor(XSPI_Type *base) in XSPI_StopAhbBufferPerfMonitor() argument
1915 base->AHB_PERF_CTRL |= XSPI_AHB_PERF_CTRL_CNTSTP_MASK; in XSPI_StopAhbBufferPerfMonitor()
1925 static inline void XSPI_GetAhbBufferPerfMonitorResult(XSPI_Type *base, in XSPI_GetAhbBufferPerfMonitorResult() argument
1931 tmp32 = (uint32_t)(base->AHB_PERF_BUF[ahbBufferId]); in XSPI_GetAhbBufferPerfMonitorResult()
1944 static inline bool XSPI_CheckAhbBufferPerfMonitorTimeCounterOverflow(XSPI_Type *base) in XSPI_CheckAhbBufferPerfMonitorTimeCounterOverflow() argument
1946 return (bool)((base->AHB_PERF_CTRL & XSPI_AHB_PERF_CTRL_TCNTO_MASK) != 0UL); in XSPI_CheckAhbBufferPerfMonitorTimeCounterOverflow()
1958 static inline bool XSPI_CheckAhbBufferPerfMonitorHitOverflow(XSPI_Type *base, uint8_t ahbBufferId) in XSPI_CheckAhbBufferPerfMonitorHitOverflow() argument
1960 …return (bool)((base->AHB_PERF_CTRL & (XSPI_AHB_PERF_CTRL_BUF0_HIT_OVF_MASK << (uint32_t)ahbBufferI… in XSPI_CheckAhbBufferPerfMonitorHitOverflow()
1972 static inline bool XSPI_CheckAhbBufferPerfMonitorMissOverflow(XSPI_Type *base, uint8_t ahbBufferId) in XSPI_CheckAhbBufferPerfMonitorMissOverflow() argument
1974 …return (bool)((base->AHB_PERF_CTRL & ((uint32_t)XSPI_AHB_PERF_CTRL_BUF0_MISS_OVF_MASK << (uint32_t… in XSPI_CheckAhbBufferPerfMonitorMissOverflow()
1984 static inline uint32_t XSPI_GetAhbBufferPerfMonitorTimeCounter(XSPI_Type *base) in XSPI_GetAhbBufferPerfMonitorTimeCounter() argument
1986 return base->AHB_PERF_TIME_CNT; in XSPI_GetAhbBufferPerfMonitorTimeCounter()
2006 status_t XSPI_SetAhbAccessSplitSize(XSPI_Type *base, xspi_ahb_split_size_t ahbSplitSize);
2031 status_t XSPI_SetAhbAccessBoundary(XSPI_Type *base, xspi_ahb_alignment_t alignment);
2044 status_t XSPI_SetAhbReadDataSeqId(XSPI_Type *base, uint8_t seqId);
2057 status_t XSPI_SetAhbWriteDataSeqId(XSPI_Type *base, uint8_t seqId);
2072 status_t XSPI_UpdateAhbHreadyTimeOutValue(XSPI_Type *base, uint16_t timeoutValue);
2089 status_t XSPI_SetAhbErrorPayload(XSPI_Type *base, uint32_t highPayload, uint32_t lowPayload);
2098 xspi_ahb_read_error_info_t XSPI_ReturnAhbReadErrorInfo(XSPI_Type *base);
2105 static inline void XSPI_ClearAhbAccessSeqPointer(XSPI_Type *base) in XSPI_ClearAhbAccessSeqPointer() argument
2107 base->SPTRCLR |= XSPI_SPTRCLR_BFPTRC_MASK; in XSPI_ClearAhbAccessSeqPointer()
2117 void XSPI_GetAhbRequestSuspendInfo(XSPI_Type *base, xspi_ahb_request_suspend_info_t *ptrSuspendInfo…
2127 static inline void XSPI_EnableAhbReadPrefetch(XSPI_Type *base, bool enable) in XSPI_EnableAhbReadPrefetch() argument
2131 base->SPTRCLR &= ~XSPI_SPTRCLR_PREFETCH_DIS_MASK; in XSPI_EnableAhbReadPrefetch()
2135 base->SPTRCLR |= XSPI_SPTRCLR_PREFETCH_DIS_MASK; in XSPI_EnableAhbReadPrefetch()
2170 status_t XSPI_BlockAccessAfterAhbWrite(XSPI_Type *base, bool blockSequentWrite, bool blockRead);
2185 status_t XSPI_SelectPPWFlagClearPolicy(XSPI_Type *base, xspi_ppw_flag_clear_policy_t policy);
2198 status_t XSPI_UpdatePageWaitTimeCounter(XSPI_Type *base, uint32_t countValue);
2213 status_t XSPI_SetAhbReadStatusRegSeqId(XSPI_Type *base, uint8_t seqId);
2225 static inline uint16_t XSPI_GetSFMStatusRegValue(XSPI_Type *base) in XSPI_GetSFMStatusRegValue() argument
2227 while ((base->PPW_RDSR & XSPI_PPW_RDSR_VALID_MASK) == 0UL) in XSPI_GetSFMStatusRegValue()
2231 return (uint16_t)(base->PPW_RDSR & XSPI_PPW_RDSR_RDSR_MASK); in XSPI_GetSFMStatusRegValue()
2245 status_t XSPI_SetSFMStatusRegInfo(XSPI_Type *base, xspi_device_status_reg_info_t *ptrStatusRegInfo);
2265 status_t XSPI_SetAhbAccessConfig(XSPI_Type *base, xspi_ahb_access_config_t *ptrAhbAccessConfig);