Lines Matching refs:base
55 typedef void (*xspi_isr_t)(XSPI_Type *base, xspi_handle_t *handle);
225 uint32_t XSPI_GetInstance(XSPI_Type *base) in XSPI_GetInstance() argument
232 if (MSDK_REG_SECURE_ADDR(s_xspiBases[instance]) == MSDK_REG_SECURE_ADDR(base)) in XSPI_GetInstance()
249 status_t XSPI_CheckAndClearError(XSPI_Type *base, uint32_t status) in XSPI_CheckAndClearError() argument
262 base->ERRSTAT |= (uint32_t)kXSPI_SequenceExecutionTimeoutFlag; in XSPI_CheckAndClearError()
270 base->ERRSTAT |= (uint32_t)kXSPI_FradMatchErrorFlag; in XSPI_CheckAndClearError()
274 base->ERRSTAT |= (uint32_t)kXSPI_FradnAccErrorFlag; in XSPI_CheckAndClearError()
281 base->IPSERROR |= XSPI_IPSERROR_CLR_MASK; in XSPI_CheckAndClearError()
290 base->TGSFARS |= XSPI_TGSFARS_CLR_MASK; in XSPI_CheckAndClearError()
294 base->TGIPCRS |= XSPI_TGIPCRS_CLR_MASK; in XSPI_CheckAndClearError()
303 base->MCR |= XSPI_MCR_CLR_RXF_MASK; in XSPI_CheckAndClearError()
304 base->MCR |= XSPI_MCR_CLR_TXF_MASK; in XSPI_CheckAndClearError()
320 void XSPI_Init(XSPI_Type *base, const xspi_config_t *ptrConfig) in XSPI_Init() argument
326 (void)CLOCK_EnableClock(s_xspiClock[XSPI_GetInstance(base)]); in XSPI_Init()
329 RESET_ReleasePeripheralReset(s_xspiResets[XSPI_GetInstance(base)]); in XSPI_Init()
332 XSPI_SoftwareReset(base); in XSPI_Init()
335 XSPI_EnableModule(base, false); in XSPI_Init()
338 XSPI_ClearAhbBuffer(base); in XSPI_Init()
339 XSPI_ClearTxBuffer(base); in XSPI_Init()
340 XSPI_ClearRxBuffer(base); in XSPI_Init()
343 tmp32 = base->FR; in XSPI_Init()
346 base->FR = tmp32; in XSPI_Init()
349 XSPI_EnableDozeMode(base, ptrConfig->enableDoze); in XSPI_Init()
351 base->MCR = ((base->MCR) & (~XSPI_MCR_END_CFG_MASK)) | XSPI_MCR_END_CFG(ptrConfig->byteOrder); in XSPI_Init()
355 (void)XSPI_SetAhbAccessConfig(base, ptrConfig->ptrAhbAccessConfig); in XSPI_Init()
360 (void)XSPI_SetIpAccessConfig(base, ptrConfig->ptrIpAccessConfig); in XSPI_Init()
364 XSPI_EnableModule(base, true); in XSPI_Init()
431 void XSPI_Deinit(XSPI_Type *base) in XSPI_Deinit() argument
433 XSPI_EnableModule(base, false); in XSPI_Deinit()
435 XSPI_SoftwareReset(base); in XSPI_Deinit()
447 void XSPI_UpdateLUT(XSPI_Type *base, uint8_t index, const uint32_t *cmd, uint8_t count) in XSPI_UpdateLUT() argument
455 while (!XSPI_GetBusIdleStatus(base)) in XSPI_UpdateLUT()
460 base->LUTKEY = XSPI_LUT_KEY_VAL; in XSPI_UpdateLUT()
461 base->LCKCR = 0x02; in XSPI_UpdateLUT()
463 lutBase = &base->LUT[index]; in XSPI_UpdateLUT()
470 base->LUTKEY = XSPI_LUT_KEY_VAL; in XSPI_UpdateLUT()
471 base->LCKCR = 0x01; in XSPI_UpdateLUT()
484 void XSPI_ResetSfmAndAhbDomain(XSPI_Type *base) in XSPI_ResetSfmAndAhbDomain() argument
487 XSPI_EnableModule(base, true); in XSPI_ResetSfmAndAhbDomain()
489 base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK; in XSPI_ResetSfmAndAhbDomain()
495 XSPI_EnableModule(base, false); in XSPI_ResetSfmAndAhbDomain()
496 base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK); in XSPI_ResetSfmAndAhbDomain()
502 XSPI_EnableModule(base, true); in XSPI_ResetSfmAndAhbDomain()
514 void XSPI_SetHyperBusX16Mode(XSPI_Type *base, xspi_hyper_bus_x16_mode_t x16Mode) in XSPI_SetHyperBusX16Mode() argument
518 if (XSPI_CheckModuleEnabled(base)) in XSPI_SetHyperBusX16Mode()
521 XSPI_EnableModule(base, false); in XSPI_SetHyperBusX16Mode()
524 base->MCR = ((base->MCR) & (~XSPI_MCR_X16_MODE_MASK)) | XSPI_MCR_X16_MODE(x16Mode); in XSPI_SetHyperBusX16Mode()
528 XSPI_EnableModule(base, true); in XSPI_SetHyperBusX16Mode()
541 void XSPI_UpdateDllValue(XSPI_Type *base, xspi_dll_config_t *ptrDllConfig, in XSPI_UpdateDllValue() argument
562 base->MCR |= XSPI_MCR_MDIS_MASK; in XSPI_UpdateDllValue()
563 base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) | XSPI_SMPR_DLLFSMPFA(tapNum)); in XSPI_UpdateDllValue()
564 base->MCR &= ~XSPI_MCR_MDIS_MASK; in XSPI_UpdateDllValue()
582 base->DLLCR[0] &= in XSPI_UpdateDllValue()
586 base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLV_DLL_BYPASS_MASK; in XSPI_UpdateDllValue()
588 base->DLLCR[0] |= in XSPI_UpdateDllValue()
592 base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK; in XSPI_UpdateDllValue()
594 while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) in XSPI_UpdateDllValue()
597 base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK; in XSPI_UpdateDllValue()
627 …base->DLLCR[0] &= ~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK | XSPI_DLLCR_SLV_DLY… in XSPI_UpdateDllValue()
631 base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK; in XSPI_UpdateDllValue()
633 … base->DLLCR[0] |= XSPI_DLLCR_DLLRES(resolutionValue) | XSPI_DLLCR_DLL_REFCNTR(refCounterValue) | in XSPI_UpdateDllValue()
637 base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK; in XSPI_UpdateDllValue()
638 base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK; in XSPI_UpdateDllValue()
639 base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK; in XSPI_UpdateDllValue()
640 while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) in XSPI_UpdateDllValue()
657 status_t XSPI_SetDataLearningConfig(XSPI_Type *base, xspi_data_learning_config_t *ptrDataLearningCo… in XSPI_SetDataLearningConfig() argument
661 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetDataLearningConfig()
666 if (XSPI_CheckIPAccessAsserted(base)) in XSPI_SetDataLearningConfig()
671 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetDataLearningConfig()
676 base->DLCR = ((base->DLCR) & ~(XSPI_DLCR_DLP_SEL_FA_MASK | XSPI_DLCR_DL_NONDLP_FLSH_MASK)) | in XSPI_SetDataLearningConfig()
680 base->DLPR = ptrDataLearningConfig->pattern; in XSPI_SetDataLearningConfig()
696 status_t XSPI_UpdateDeviceAddrMode(XSPI_Type *base, xspi_device_addr_mode_t addrMode) in XSPI_UpdateDeviceAddrMode() argument
698 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_UpdateDeviceAddrMode()
703 if (XSPI_CheckIPAccessAsserted(base)) in XSPI_UpdateDeviceAddrMode()
708 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_UpdateDeviceAddrMode()
715 base->SFACR = in XSPI_UpdateDeviceAddrMode()
716 … (base->SFACR & ~(XSPI_SFACR_WA_MASK | XSPI_SFACR_WA_4B_EN_MASK)) | XSPI_SFACR_WA(addrMode); in XSPI_UpdateDeviceAddrMode()
720 base->SFACR &= ~XSPI_SFACR_WA_MASK; in XSPI_UpdateDeviceAddrMode()
721 base->SFACR |= XSPI_SFACR_WA_4B_EN_MASK; in XSPI_UpdateDeviceAddrMode()
741 status_t XSPI_SetDeviceConfig(XSPI_Type *base, xspi_device_config_t *devConfig) in XSPI_SetDeviceConfig() argument
747 uint32_t instance = XSPI_GetInstance(base); in XSPI_SetDeviceConfig()
749 if (XSPI_CheckIPAccessAsserted(base)) in XSPI_SetDeviceConfig()
754 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetDeviceConfig()
759 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetDeviceConfig()
767 if (XSPI_CheckModuleEnabled(base)) in XSPI_SetDeviceConfig()
770 XSPI_EnableModule(base, false); in XSPI_SetDeviceConfig()
775 base->MCR |= XSPI_MCR_CKN_FA_EN_MASK; in XSPI_SetDeviceConfig()
779 base->MCR &= ~XSPI_MCR_CKN_FA_EN_MASK; in XSPI_SetDeviceConfig()
785 base->MCR &= ~XSPI_MCR_DQS_OUT_EN_MASK; in XSPI_SetDeviceConfig()
786 base->SFACR = (base->SFACR & ~XSPI_SFACR_PPWB_MASK) | XSPI_SFACR_PPWB(tmp8); in XSPI_SetDeviceConfig()
790 XSPI_SetHyperBusX16Mode(base, devConfig->interfaceSettings.hyperBusSettings.x16Mode); in XSPI_SetDeviceConfig()
795 …XSPI_EnableVariableLatency(base, devConfig->interfaceSettings.hyperBusSettings.enableVariableLaten… in XSPI_SetDeviceConfig()
796 base->MCR |= XSPI_MCR_DQS_OUT_EN_MASK; in XSPI_SetDeviceConfig()
797 base->SFACR = (base->SFACR & ~XSPI_SFACR_FORCE_A10_MASK) | in XSPI_SetDeviceConfig()
801 base->FLSHCR = ((base->FLSHCR) & ~(XSPI_FLSHCR_TCSS_MASK | XSPI_FLSHCR_TCSH_MASK)) | in XSPI_SetDeviceConfig()
806 base->SFACR = in XSPI_SetDeviceConfig()
807 …(base->SFACR & ~(XSPI_SFACR_WA_MASK | XSPI_SFACR_WA_4B_EN_MASK)) | XSPI_SFACR_WA(devConfig->addrMo… in XSPI_SetDeviceConfig()
811 base->SFACR |= XSPI_SFACR_WA_4B_EN_MASK; in XSPI_SetDeviceConfig()
814 base->SFACR = in XSPI_SetDeviceConfig()
815 (base->SFACR & ~(XSPI_SFACR_CAS_INTRLVD_MASK | XSPI_SFACR_CAS_MASK)) | in XSPI_SetDeviceConfig()
820 (void)XSPI_SetSFMStatusRegInfo(base, devConfig->ptrDeviceRegInfo); in XSPI_SetDeviceConfig()
830 base->FLSHCR = ((base->FLSHCR) & ~XSPI_FLSHCR_TDH_MASK) | in XSPI_SetDeviceConfig()
832 base->SFACR = ((base->SFACR) & ~XSPI_SFACR_BYTE_SWAP_MASK) | in XSPI_SetDeviceConfig()
834 base->MCR |= XSPI_MCR_DDR_EN_MASK; in XSPI_SetDeviceConfig()
838 base->MCR &= ~XSPI_MCR_DDR_EN_MASK; in XSPI_SetDeviceConfig()
843 base->SFAD[0][i] = s_xspiAmbaBase[instance] + XSPI_SFAD_TPAD(devConfig->deviceSize[i]); in XSPI_SetDeviceConfig()
846 …uint32_t tmp32 = (base->MCR) & ~(XSPI_MCR_DQS_FA_SEL_MASK | XSPI_MCR_DQS_EN_MASK | XSPI_MCR_DQS_LA… in XSPI_SetDeviceConfig()
855 base->MCR = tmp32; in XSPI_SetDeviceConfig()
857 base->SMPR &= ~(XSPI_SMPR_FSPHS_MASK | XSPI_SMPR_FSDLY_MASK); in XSPI_SetDeviceConfig()
861 base->SMPR |= XSPI_SMPR_FSPHS_MASK; in XSPI_SetDeviceConfig()
866 base->SMPR |= XSPI_SMPR_FSDLY_MASK; in XSPI_SetDeviceConfig()
869 XSPI_UpdateDllValue(base, &(devConfig->sampleClkConfig.dllConfig), enableDDR, enableX16Mode, in XSPI_SetDeviceConfig()
874 XSPI_EnableModule(base, true); in XSPI_SetDeviceConfig()
902 status_t XSPI_UpdateRxBufferWaterMark(XSPI_Type *base, uint32_t waterMark) in XSPI_UpdateRxBufferWaterMark() argument
907 if (XSPI_CheckIPAccessAsserted(base)) in XSPI_UpdateRxBufferWaterMark()
917 base->RBCT = XSPI_RBCT_WMRK((waterMark / 4UL) - 1UL); in XSPI_UpdateRxBufferWaterMark()
933 status_t XSPI_UpdateTxBufferWaterMark(XSPI_Type *base, uint32_t waterMark) in XSPI_UpdateTxBufferWaterMark() argument
936 if (XSPI_CheckIPAccessAsserted(base)) in XSPI_UpdateTxBufferWaterMark()
946 base->TBCT = XSPI_TBCT_WMRK((waterMark / 4UL) - 1UL); in XSPI_UpdateTxBufferWaterMark()
958 void XSPI_SetSFPFradEALMode(XSPI_Type *base, xspi_exclusive_access_lock_mode_t ealMode, uint8_t fra… in XSPI_SetSFPFradEALMode() argument
962 uint32_t fradWord3RegAddr = (uint32_t)base + fradWord3RegOffset[fradId]; in XSPI_SetSFPFradEALMode()
995 void XSPI_UpdateSFPConfig(XSPI_Type *base, in XSPI_UpdateSFPConfig() argument
1012 base->MGC |= (XSPI_MGC_GVLDMDAD_MASK | XSPI_MGC_GVLD_MASK); in XSPI_UpdateSFPConfig()
1017 tgMdadRegAddr = (uint32_t)base + s_tgMdadRegOffset[i]; in XSPI_UpdateSFPConfig()
1034 base->MGC |= (XSPI_MGC_GVLDFRAD_MASK | XSPI_MGC_GVLD_MASK); in XSPI_UpdateSFPConfig()
1047 fradWord0RegAddr = (uint32_t)base + fradWord0RegOffset[i]; in XSPI_UpdateSFPConfig()
1048 fradWord1RegAddr = (uint32_t)base + fradWord1RegOffset[i]; in XSPI_UpdateSFPConfig()
1049 fradWord2RegAddr = (uint32_t)base + fradWord2RegOffset[i]; in XSPI_UpdateSFPConfig()
1050 fradWord3RegAddr = (uint32_t)base + fradWord3RegOffset[i]; in XSPI_UpdateSFPConfig()
1057 … XSPI_SetSFPFradEALMode(base, ptrSfpFradConfig->fradConfig[i].exclusiveAccessLock, i); in XSPI_UpdateSFPConfig()
1075 base->MGC &= ~(XSPI_MGC_GVLDFRAD_MASK | XSPI_MGC_GVLDMDAD_MASK | XSPI_MGC_GVLD_MASK); in XSPI_UpdateSFPConfig()
1086 void XSPI_GetFradLastTransactionsInfo(XSPI_Type *base, xspi_frad_transaction_info_t *ptrInfo, uint8… in XSPI_GetFradLastTransactionsInfo() argument
1091 uint32_t fradWord4RegAddr = (uint32_t)base + fradWord4RegOffset[fradId]; in XSPI_GetFradLastTransactionsInfo()
1092 uint32_t fradWord5RegAddr = (uint32_t)base + fradWord5RegOffset[fradId]; in XSPI_GetFradLastTransactionsInfo()
1114 status_t XSPI_UpdateSFPArbitrationLockTimeoutCounter(XSPI_Type *base, uint32_t countValue) in XSPI_UpdateSFPArbitrationLockTimeoutCounter() argument
1116 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_UpdateSFPArbitrationLockTimeoutCounter()
1121 base->SFP_ARB_TIMEOUT = countValue; in XSPI_UpdateSFPArbitrationLockTimeoutCounter()
1140 status_t XSPI_UpdateIPAccessTimeoutCounter(XSPI_Type *base, uint32_t countValue) in XSPI_UpdateIPAccessTimeoutCounter() argument
1142 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_UpdateIPAccessTimeoutCounter()
1147 base->MTO = countValue; in XSPI_UpdateIPAccessTimeoutCounter()
1160 xspi_mdad_error_reason_t XSPI_GetMdadErrorReason(XSPI_Type *base, xspi_target_group_t tgId) in XSPI_GetMdadErrorReason() argument
1166 tmp8 = (uint8_t)((base->TGIPCRS & XSPI_TGIPCRS_ERR_MASK) >> XSPI_TGIPCRS_ERR_SHIFT); in XSPI_GetMdadErrorReason()
1170 tmp8 = (uint8_t)((base->SUB_REG_MDAM_ARRAY[0].TGIPCRS_SUB & XSPI_TGIPCRS_SUB_ERR_MASK) >> in XSPI_GetMdadErrorReason()
1183 void XSPI_ClearTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId) in XSPI_ClearTgAddrWriteStatus() argument
1185 uint32_t tgSfarsRegAddr = (uint32_t)base + (uint32_t)s_tgSfarsRegOffset[(uint8_t)(tgId)]; in XSPI_ClearTgAddrWriteStatus()
1198 void XSPI_GetTgAddrWriteStatus(XSPI_Type *base, xspi_target_group_t tgId, xspi_tg_add_write_status_… in XSPI_GetTgAddrWriteStatus() argument
1200 uint32_t tgSfarsRegAddr = (uint32_t)base + (uint32_t)s_tgSfarsRegOffset[(uint8_t)(tgId)]; in XSPI_GetTgAddrWriteStatus()
1214 void XSPI_UnlockIpAccessArbitration(XSPI_Type *base, xspi_target_group_t tgId) in XSPI_UnlockIpAccessArbitration() argument
1217 uint32_t tgIpcrRegAddr = (uint32_t)base + tgIpcrRegOffset[(uint8_t)tgId]; in XSPI_UnlockIpAccessArbitration()
1237 …XSPI_Type *base, uint32_t addr, uint8_t seqIndex, size_t byteSize, xspi_target_group_t tgId, bool … in XSPI_StartIpAccess() argument
1239 uint32_t tgSfarsRegAddr = (uint32_t)base + (uint32_t)s_tgSfarsRegOffset[(uint8_t)tgId]; in XSPI_StartIpAccess()
1240 uint32_t tgIpcrsRegAddr = (uint32_t)base + (uint32_t)s_tgIpcrsRegOffset[(uint8_t)tgId]; in XSPI_StartIpAccess()
1241 uint32_t sfpTgIpcrRegAddr = (uint32_t)base + (uint32_t)s_sfpTgIpcrRegOffset[(uint8_t)tgId]; in XSPI_StartIpAccess()
1242 uint32_t sfpTgIpSfarRegAddr = (uint32_t)base + (uint32_t)s_sfpTgIpSfarRegOffset[(uint8_t)tgId]; in XSPI_StartIpAccess()
1243 uint32_t tgMdadRegAddr = (uint32_t)base + (uint32_t)s_tgMdadRegOffset[(uint8_t)tgId]; in XSPI_StartIpAccess()
1249 mdadEnabled = (bool)((base->MGC & XSPI_MGC_GVLDMDAD_MASK) != 0UL); in XSPI_StartIpAccess()
1288 while (XSPI_CheckIPAccessGranted(base) == false) in XSPI_StartIpAccess()
1308 status_t XSPI_SetIpAccessConfig(XSPI_Type *base, xspi_ip_access_config_t *ptrIpAccessConfig) in XSPI_SetIpAccessConfig() argument
1314 XSPI_ClearIPAccessSeqPointer(base); in XSPI_SetIpAccessConfig()
1315 …XSPI_UpdateSFPConfig(base, ptrIpAccessConfig->ptrSfpMdadConfig, ptrIpAccessConfig->ptrSfpFradConfi… in XSPI_SetIpAccessConfig()
1316 …status = XSPI_UpdateSFPArbitrationLockTimeoutCounter(base, ptrIpAccessConfig->sfpArbitrationLockTi… in XSPI_SetIpAccessConfig()
1320 status = XSPI_UpdateIPAccessTimeoutCounter(base, ptrIpAccessConfig->ipAccessTimeoutValue); in XSPI_SetIpAccessConfig()
1337 status_t XSPI_WriteBlocking(XSPI_Type *base, uint8_t *buffer, size_t size) in XSPI_WriteBlocking() argument
1343 while (XSPI_CheckTxBuffLockOpen(base) == false) in XSPI_WriteBlocking()
1347 base->TBCT = 256UL - ((uint32_t)size / 4UL - 1UL); in XSPI_WriteBlocking()
1351 result = XSPI_CheckAndClearError(base, base->ERRSTAT); in XSPI_WriteBlocking()
1362 while (1UL == ((base->SR & XSPI_SR_TXFULL_MASK) >> XSPI_SR_TXFULL_SHIFT)) in XSPI_WriteBlocking()
1365 base->TBDR = *(uint32_t *)buffer; in XSPI_WriteBlocking()
1382 while (1UL == ((base->SR & XSPI_SR_TXFULL_MASK) >> XSPI_SR_TXFULL_SHIFT)) in XSPI_WriteBlocking()
1385 base->TBDR = tempVal; in XSPI_WriteBlocking()
1392 base->FR = XSPI_FR_TBFF_MASK; in XSPI_WriteBlocking()
1394 while (XSPI_CheckIPAccessAsserted(base)) in XSPI_WriteBlocking()
1412 status_t XSPI_ReadBlocking(XSPI_Type *base, uint8_t *buffer, size_t size) in XSPI_ReadBlocking() argument
1414 uint32_t rxWatermark = base->RBCT + 1UL; in XSPI_ReadBlocking()
1419 …while ((1UL != (base->SR & XSPI_SR_BUSY_MASK)) && (((base->SR & XSPI_SR_IP_ACC_MASK) >> XSPI_SR_IP… in XSPI_ReadBlocking()
1424 while ((base->SR & XSPI_SR_RXWE_MASK) == 0UL) in XSPI_ReadBlocking()
1426 if((base->ERRSTAT & XSPI_ERRSTAT_TO_ERR_MASK) != 0UL) in XSPI_ReadBlocking()
1428 base->ERRSTAT = XSPI_ERRSTAT_TO_ERR_MASK; in XSPI_ReadBlocking()
1435 if (XSPI_GetRxBufferAvailableBytesCount(base) != adjuestedSize) in XSPI_ReadBlocking()
1442 status = XSPI_CheckAndClearError(base, base->ERRSTAT); in XSPI_ReadBlocking()
1452 removedCount = XSPI_GetRxBufferRemovedBytesCount(base); in XSPI_ReadBlocking()
1455 *(uint32_t *)buffer = base->RBDR[i]; in XSPI_ReadBlocking()
1460 XSPI_TriggerRxBufferPopEvent(base); in XSPI_ReadBlocking()
1461 while ((XSPI_GetRxBufferRemovedBytesCount(base) - removedCount) != (rxWatermark * 4UL)) in XSPI_ReadBlocking()
1470 *(uint32_t *)buffer = base->RBDR[i]; in XSPI_ReadBlocking()
1480 uint32_t tempVal = base->RBDR[i]; in XSPI_ReadBlocking()
1493 XSPI_ClearRxBuffer(base); in XSPI_ReadBlocking()
1507 status_t XSPI_TransferBlocking(XSPI_Type *base, xspi_transfer_t *xfer) in XSPI_TransferBlocking() argument
1515 …status = XSPI_StartIpAccess(base, xfer->deviceAddress, xfer->seqIndex, dataSize, xfer->targetGroup, in XSPI_TransferBlocking()
1522 XSPI_ClearTxBuffer(base); in XSPI_TransferBlocking()
1524 status = XSPI_WriteBlocking(base, ptrBuffer, xfer->dataSize); in XSPI_TransferBlocking()
1532 XSPI_ClearRxBuffer(base); in XSPI_TransferBlocking()
1567 (void)XSPI_UpdateRxBufferWaterMark(base, rxBufferWaterMark); in XSPI_TransferBlocking()
1570 …XSPI_StartIpAccess(base, xfer->deviceAddress, xfer->seqIndex, transferSize, xfer->targetGroup, fal… in XSPI_TransferBlocking()
1575 status = XSPI_ReadBlocking(base, ptrBuffer, transferSize); in XSPI_TransferBlocking()
1578 XSPI_ResetTgQueue(base); in XSPI_TransferBlocking()
1579 XSPI_ResetSfmAndAhbDomain(base); in XSPI_TransferBlocking()
1592 … status = XSPI_StartIpAccess(base, xfer->deviceAddress, xfer->seqIndex, 0UL, xfer->targetGroup, in XSPI_TransferBlocking()
1601 while (!XSPI_GetBusIdleStatus(base)) in XSPI_TransferBlocking()
1607 status = XSPI_CheckAndClearError(base, base->ERRSTAT); in XSPI_TransferBlocking()
1608 while (XSPI_CheckIPAccessAsserted(base)) in XSPI_TransferBlocking()
1624 void XSPI_TransferCreateHandle(XSPI_Type *base, in XSPI_TransferCreateHandle() argument
1631 uint32_t instance = XSPI_GetInstance(base); in XSPI_TransferCreateHandle()
1659 status_t XSPI_TransferNonBlocking(XSPI_Type *base, xspi_handle_t *handle, xspi_transfer_t *xfer) in XSPI_TransferNonBlocking() argument
1679 …status = XSPI_StartIpAccess(base, xfer->deviceAddress, xfer->seqIndex, xfer->dataSize, xfer->targe… in XSPI_TransferNonBlocking()
1688 XSPI_ClearRxBuffer(base); in XSPI_TransferNonBlocking()
1689 …XSPI_EnableInterrupts(base, (uint32_t)kXSPI_RxBufferOverflowFlag | (uint32_t)kXSPI_RxBufferDrainFl… in XSPI_TransferNonBlocking()
1696 XSPI_ClearTxBuffer(base); in XSPI_TransferNonBlocking()
1697 …XSPI_EnableInterrupts(base, (uint32_t)kXSPI_TxBufferFillFlag | (uint32_t)kXSPI_TxBufferUnderrunFla… in XSPI_TransferNonBlocking()
1715 status_t XSPI_TransferGetCount(XSPI_Type *base, xspi_handle_t *handle, size_t *count) in XSPI_TransferGetCount() argument
1742 void XSPI_TransferAbort(XSPI_Type *base, xspi_handle_t *handle) in XSPI_TransferAbort() argument
1746 XSPI_DisableInterrupts(base, (uint32_t)kIrqFlags); in XSPI_TransferAbort()
1776 status_t XSPI_SetAhbAccessBoundary(XSPI_Type *base, xspi_ahb_alignment_t alignment) in XSPI_SetAhbAccessBoundary() argument
1779 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbAccessBoundary()
1784 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbAccessBoundary()
1789 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbAccessBoundary()
1794 base->BFGENCR = ((base->BFGENCR & ~(XSPI_BFGENCR_ALIGN_MASK)) | XSPI_BFGENCR_ALIGN(alignment)); in XSPI_SetAhbAccessBoundary()
1810 status_t XSPI_SetAhbReadDataSeqId(XSPI_Type *base, uint8_t seqId) in XSPI_SetAhbReadDataSeqId() argument
1812 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbReadDataSeqId()
1817 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbReadDataSeqId()
1822 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbReadDataSeqId()
1827 base->BFGENCR = ((base->BFGENCR & (~XSPI_BFGENCR_SEQID_MASK)) | XSPI_BFGENCR_SEQID(seqId)); in XSPI_SetAhbReadDataSeqId()
1842 status_t XSPI_SetAhbWriteDataSeqId(XSPI_Type *base, uint8_t seqId) in XSPI_SetAhbWriteDataSeqId() argument
1844 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbWriteDataSeqId()
1849 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbWriteDataSeqId()
1854 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbWriteDataSeqId()
1859 … base->BFGENCR = ((base->BFGENCR & (~XSPI_BFGENCR_SEQID_WR_MASK)) | XSPI_BFGENCR_SEQID_WR(seqId)); in XSPI_SetAhbWriteDataSeqId()
1876 status_t XSPI_SetAhbBufferConfig(XSPI_Type *base, in XSPI_SetAhbBufferConfig() argument
1899 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbBufferConfig()
1904 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbBufferConfig()
1909 (void)XSPI_UpdateAhbBufferSize(base, ptrBuffer0Config->bufferSize, ptrBuffer1Config->bufferSize, in XSPI_SetAhbBufferConfig()
1917 base->BUFCR[i] = in XSPI_SetAhbBufferConfig()
1923 base->BUFCR[i] |= XSPI_BUFCR_HP_EN(ahbBufferConfigs[i]->enaPri.enablePriority); in XSPI_SetAhbBufferConfig()
1928 base->BUFCR[i] |= XSPI_BUFCR_ALLMST(ahbBufferConfigs[i]->enaPri.enableAllMaster); in XSPI_SetAhbBufferConfig()
1934 base->BUFCR[i] &= ~XSPI_BUFCR_SUB_DIV_EN_MASK; in XSPI_SetAhbBufferConfig()
1945 base->BUFCR[i] |= XSPI_BUFCR_SUB_DIV_EN_MASK | in XSPI_SetAhbBufferConfig()
1958 base->BUF_ADDR_RANGE[i][j] = in XSPI_SetAhbBufferConfig()
1964 XSPI_EnableAhbBufferPerfMonitor(base, i, j); in XSPI_SetAhbBufferConfig()
1989 status_t XSPI_SetAhbAccessSplitSize(XSPI_Type *base, xspi_ahb_split_size_t ahbSplitSize) in XSPI_SetAhbAccessSplitSize() argument
1991 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbAccessSplitSize()
1996 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbAccessSplitSize()
2001 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbAccessSplitSize()
2008 base->BFGENCR &= ~XSPI_BFGENCR_SPLITEN_MASK; in XSPI_SetAhbAccessSplitSize()
2012 base->BFGENCR |= XSPI_BFGENCR_SPLITEN_MASK; in XSPI_SetAhbAccessSplitSize()
2013 …base->BFGENCR = (base->BFGENCR & (~XSPI_BFGENCR_AHBSSIZE_MASK)) | XSPI_BFGENCR_AHBSSIZE(ahbSplitSi… in XSPI_SetAhbAccessSplitSize()
2032 status_t XSPI_UpdateAhbHreadyTimeOutValue(XSPI_Type *base, uint16_t timeoutValue) in XSPI_UpdateAhbHreadyTimeOutValue() argument
2034 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_UpdateAhbHreadyTimeOutValue()
2039 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_UpdateAhbHreadyTimeOutValue()
2044 base->AHRDYTO = XSPI_AHRDYTO_HREADY_TO(timeoutValue); in XSPI_UpdateAhbHreadyTimeOutValue()
2064 status_t XSPI_SetAhbErrorPayload(XSPI_Type *base, uint32_t highPayload, uint32_t lowPayload) in XSPI_SetAhbErrorPayload() argument
2066 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbErrorPayload()
2071 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbErrorPayload()
2076 base->AHB_ERR_PAYLOAD_HI = highPayload; in XSPI_SetAhbErrorPayload()
2077 base->AHB_ERR_PAYLOAD_LO = lowPayload; in XSPI_SetAhbErrorPayload()
2089 xspi_ahb_read_error_info_t XSPI_ReturnAhbReadErrorInfo(XSPI_Type *base) in XSPI_ReturnAhbReadErrorInfo() argument
2093 errorInfo.errorAddr = base->AHB_RD_ERR_ADDR; in XSPI_ReturnAhbReadErrorInfo()
2094 errorInfo.errMasterId = (uint8_t)(base->AHB_RD_ERR_MID & XSPI_AHB_RD_ERR_MID_REMID_MASK); in XSPI_ReturnAhbReadErrorInfo()
2106 void XSPI_GetAhbRequestSuspendInfo(XSPI_Type *base, xspi_ahb_request_suspend_info_t *ptrSuspendInfo) in XSPI_GetAhbRequestSuspendInfo() argument
2110 tmp32 = base->SPNDST; in XSPI_GetAhbRequestSuspendInfo()
2126 ptrSuspendInfo->address = base->SPNDST_ADDR; in XSPI_GetAhbRequestSuspendInfo()
2142 status_t XSPI_EnableAhbBufferWriteFlush(XSPI_Type *base, bool enable) in XSPI_EnableAhbBufferWriteFlush() argument
2144 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_EnableAhbBufferWriteFlush()
2149 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_EnableAhbBufferWriteFlush()
2154 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_EnableAhbBufferWriteFlush()
2161 base->BFGENCR |= XSPI_BFGENCR_WR_FLUSH_EN_MASK; in XSPI_EnableAhbBufferWriteFlush()
2165 base->BFGENCR &= ~XSPI_BFGENCR_WR_FLUSH_EN_MASK; in XSPI_EnableAhbBufferWriteFlush()
2202 status_t XSPI_BlockAccessAfterAhbWrite(XSPI_Type *base, bool blockSequentWrite, bool blockRead) in XSPI_BlockAccessAfterAhbWrite() argument
2206 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_BlockAccessAfterAhbWrite()
2211 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_BlockAccessAfterAhbWrite()
2216 tmp32 = base->AWRCR; in XSPI_BlockAccessAfterAhbWrite()
2220 base->AWRCR = tmp32; in XSPI_BlockAccessAfterAhbWrite()
2238 status_t XSPI_SelectPPWFlagClearPolicy(XSPI_Type *base, xspi_ppw_flag_clear_policy_t policy) in XSPI_SelectPPWFlagClearPolicy() argument
2240 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SelectPPWFlagClearPolicy()
2245 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SelectPPWFlagClearPolicy()
2250 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SelectPPWFlagClearPolicy()
2257 base->BFGENCR |= XSPI_BFGENCR_PPWF_CLR_MASK; in XSPI_SelectPPWFlagClearPolicy()
2261 base->BFGENCR &= ~XSPI_BFGENCR_PPWF_CLR_MASK; in XSPI_SelectPPWFlagClearPolicy()
2278 status_t XSPI_UpdatePageWaitTimeCounter(XSPI_Type *base, uint32_t countValue) in XSPI_UpdatePageWaitTimeCounter() argument
2280 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_UpdatePageWaitTimeCounter()
2285 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_UpdatePageWaitTimeCounter()
2290 if ((base->FR & XSPI_FR_PPWF_MASK) != 0UL) in XSPI_UpdatePageWaitTimeCounter()
2295 base->PPWF_TCNT = countValue; in XSPI_UpdatePageWaitTimeCounter()
2313 status_t XSPI_SetAhbReadStatusRegSeqId(XSPI_Type *base, uint8_t seqId) in XSPI_SetAhbReadStatusRegSeqId() argument
2315 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbReadStatusRegSeqId()
2320 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbReadStatusRegSeqId()
2325 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbReadStatusRegSeqId()
2330 …base->BFGENCR = ((base->BFGENCR & (~XSPI_BFGENCR_SEQID_RDSR_MASK)) | XSPI_BFGENCR_SEQID_RDSR(seqId… in XSPI_SetAhbReadStatusRegSeqId()
2346 status_t XSPI_SetSFMStatusRegInfo(XSPI_Type *base, xspi_device_status_reg_info_t *ptrStatusRegInfo) in XSPI_SetSFMStatusRegInfo() argument
2350 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetSFMStatusRegInfo()
2355 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetSFMStatusRegInfo()
2360 if ((base->FR & XSPI_FR_PPWF_MASK) != 0UL) in XSPI_SetSFMStatusRegInfo()
2367 tmp32 = (base->PPW_RDSR) & in XSPI_SetSFMStatusRegInfo()
2374 base->PPW_RDSR = tmp32; in XSPI_SetSFMStatusRegInfo()
2393 XSPI_Type *base, uint16_t buf0Size, uint16_t buf1Size, uint16_t buf2Size, uint16_t buf3Size) in XSPI_UpdateAhbBufferSize() argument
2398 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_UpdateAhbBufferSize()
2403 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_UpdateAhbBufferSize()
2408 base->BUFIND[0] = XSPI_BUFIND_TPINDX(buf0Size); in XSPI_UpdateAhbBufferSize()
2409 base->BUFIND[1] = XSPI_BUFIND_TPINDX((uint32_t)buf0Size + (uint32_t)buf1Size); in XSPI_UpdateAhbBufferSize()
2410 …base->BUFIND[2] = XSPI_BUFIND_TPINDX((uint32_t)buf0Size + (uint32_t)buf1Size + (uint32_t)buf2Size); in XSPI_UpdateAhbBufferSize()
2428 xspi_ahb_sub_buffer_status_t XSPI_GetAhbSubBufferStatus(XSPI_Type *base, uint8_t ahbBufferId, uint8… in XSPI_GetAhbSubBufferStatus() argument
2434 tmp32 = base->AHB_BUF_STATUS; in XSPI_GetAhbSubBufferStatus()
2445 void XSPI_EnableAhbBufferPerfMonitor(XSPI_Type *base, uint8_t ahbBufferId, uint8_t subBufferId) in XSPI_EnableAhbBufferPerfMonitor() argument
2449 tmp32 = base->AHB_PERF_CTRL; in XSPI_EnableAhbBufferPerfMonitor()
2456 base->AHB_PERF_CTRL = tmp32; in XSPI_EnableAhbBufferPerfMonitor()
2472 status_t XSPI_SetAhbAccessConfig(XSPI_Type *base, xspi_ahb_access_config_t *ptrAhbAccessConfig) in XSPI_SetAhbAccessConfig() argument
2476 if (XSPI_CheckAhbReadAccessAsserted(base)) in XSPI_SetAhbAccessConfig()
2481 if (XSPI_CheckAhbWriteAccessAsserted(base)) in XSPI_SetAhbAccessConfig()
2486 if (XSPI_CheckGlobalConfigLocked(base)) in XSPI_SetAhbAccessConfig()
2492 …(void)XSPI_SetAhbBufferConfig(base, &(ptrAhbAccessConfig->buffer[0]), &(ptrAhbAccessConfig->buffer… in XSPI_SetAhbAccessConfig()
2494 (void)XSPI_SetAhbReadDataSeqId(base, ptrAhbAccessConfig->ARDSeqIndex); in XSPI_SetAhbAccessConfig()
2495 (void)XSPI_EnableAhbBufferWriteFlush(base, ptrAhbAccessConfig->enableAHBBufferWriteFlush); in XSPI_SetAhbAccessConfig()
2496 XSPI_EnableAhbReadPrefetch(base, ptrAhbAccessConfig->enableAHBPrefetch); in XSPI_SetAhbAccessConfig()
2497 (void)XSPI_SetAhbAccessSplitSize(base, ptrAhbAccessConfig->ahbSplitSize); in XSPI_SetAhbAccessConfig()
2498 (void)XSPI_SetAhbAccessBoundary(base, ptrAhbAccessConfig->ahbAlignment); in XSPI_SetAhbAccessConfig()
2500 base->AWRCR &= ~(XSPI_AWRCR_PPW_RD_DIS_MASK | XSPI_AWRCR_PPW_WR_DIS_MASK); in XSPI_SetAhbAccessConfig()
2504 …(void)XSPI_BlockAccessAfterAhbWrite(base, ptrAhbAccessConfig->ptrAhbWriteConfig->blockSequenceWrit… in XSPI_SetAhbAccessConfig()
2506 (void)XSPI_SelectPPWFlagClearPolicy(base, ptrAhbAccessConfig->ptrAhbWriteConfig->policy); in XSPI_SetAhbAccessConfig()
2508 …(void)XSPI_UpdatePageWaitTimeCounter(base, ptrAhbAccessConfig->ptrAhbWriteConfig->pageWaitTimeoutV… in XSPI_SetAhbAccessConfig()
2510 … base->BFGENCR = (base->BFGENCR & ~(XSPI_BFGENCR_SEQID_WR_MASK | XSPI_BFGENCR_SEQID_RDSR_MASK)) | in XSPI_SetAhbAccessConfig()
2516 (void)XSPI_SetAhbErrorPayload(base, ptrAhbAccessConfig->ahbErrorPayload.highPayload, in XSPI_SetAhbAccessConfig()