322     const enet_buffer_config_t *buffCfg = bufferConfig;  in ENET_TxDescriptorsInit()  local
324     if (buffCfg == NULL)  in ENET_TxDescriptorsInit()
330     if (buffCfg->txRingLen < ENET_MIN_RINGLEN)  in ENET_TxDescriptorsInit()
336         (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK;  in ENET_TxDescriptorsInit()
338         (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK;  in ENET_TxDescriptorsInit()
341         ((uint32_t)buffCfg->txRingLen - 1U) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK;  in ENET_TxDescriptorsInit()
344     txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign);  in ENET_TxDescriptorsInit()
345     for (j = 0; j < buffCfg->txRingLen; j++)  in ENET_TxDescriptorsInit()
367     const enet_buffer_config_t *buffCfg = bufferConfig;  in ENET_RxDescriptorsInit()  local
370     if (buffCfg == NULL)  in ENET_RxDescriptorsInit()
392     if (buffCfg->rxRingLen < ENET_MIN_RINGLEN)  in ENET_RxDescriptorsInit()
399         (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK;  in ENET_RxDescriptorsInit()
401         (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK;  in ENET_RxDescriptorsInit()
403         ((uint32_t)buffCfg->rxRingLen - 1U) & ENET_DMA_CH_DMA_CHX_RX_CONTROL2_RDRL_MASK;  in ENET_RxDescriptorsInit()
405 …reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_13_Y(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BIT…  in ENET_RxDescriptorsInit()
409     rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign);  in ENET_RxDescriptorsInit()
411     for (j = 0; j < buffCfg->rxRingLen; j++)  in ENET_RxDescriptorsInit()
423             rxbdPtr->rdes0 = buffCfg->rxBufferStartAddr[index];  in ENET_RxDescriptorsInit()
427                 rxbdPtr->rdes2 = buffCfg->rxBufferStartAddr[index + 1U];  in ENET_RxDescriptorsInit()