Lines Matching refs:mask
1299 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
1309 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
1325 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
1488 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_ClearStatusFlags() argument
1492 base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1496 base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1500 base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1502 base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_ClearStatusFlags()
1505 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) in FLEXCAN_ClearStatusFlags() argument
1508 base->ESR1 = mask; in FLEXCAN_ClearStatusFlags()
1544 static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_GetMbStatusFlags() argument
1546 static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) in FLEXCAN_GetMbStatusFlags()
1551 return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask; in FLEXCAN_GetMbStatusFlags()
1553 return (base->IFLAG1 & mask); in FLEXCAN_GetMbStatusFlags()
1567 static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_GetHigh64MbStatusFlags() argument
1576 return (tempflag & mask); in FLEXCAN_GetHigh64MbStatusFlags()
1589 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_ClearMbStatusFlags() argument
1591 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) in FLEXCAN_ClearMbStatusFlags()
1595 base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_ClearMbStatusFlags()
1596 base->IFLAG2 = (uint32_t)(mask >> 32); in FLEXCAN_ClearMbStatusFlags()
1598 base->IFLAG1 = mask; in FLEXCAN_ClearMbStatusFlags()
1611 static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_ClearHigh64MbStatusFlags() argument
1614 base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_ClearHigh64MbStatusFlags()
1617 base->IFLAG4 = (uint32_t)(mask >> 32U); in FLEXCAN_ClearHigh64MbStatusFlags()
1683 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_EnableInterrupts() argument
1685 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) in FLEXCAN_EnableInterrupts()
1691 base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); in FLEXCAN_EnableInterrupts()
1698 base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); in FLEXCAN_EnableInterrupts()
1704 base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask); in FLEXCAN_EnableInterrupts()
1709 base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask); in FLEXCAN_EnableInterrupts()
1714 base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask); in FLEXCAN_EnableInterrupts()
1719 …(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEna… in FLEXCAN_EnableInterrupts()
1736 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_DisableInterrupts() argument
1738 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) in FLEXCAN_DisableInterrupts()
1745 base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); in FLEXCAN_DisableInterrupts()
1752 base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); in FLEXCAN_DisableInterrupts()
1758 base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask); in FLEXCAN_DisableInterrupts()
1763 base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask); in FLEXCAN_DisableInterrupts()
1768 base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask); in FLEXCAN_DisableInterrupts()
1773 …~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEn… in FLEXCAN_DisableInterrupts()
1788 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_EnableMbInterrupts() argument
1790 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) in FLEXCAN_EnableMbInterrupts()
1796 base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_EnableMbInterrupts()
1797 base->IMASK2 |= (uint32_t)(mask >> 32); in FLEXCAN_EnableMbInterrupts()
1799 base->IMASK1 |= mask; in FLEXCAN_EnableMbInterrupts()
1813 static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_EnableHigh64MbInterrupts() argument
1818 base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_EnableHigh64MbInterrupts()
1821 base->IMASK4 |= (uint32_t)(mask >> 32U); in FLEXCAN_EnableHigh64MbInterrupts()
1836 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_DisableMbInterrupts() argument
1838 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) in FLEXCAN_DisableMbInterrupts()
1844 base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); in FLEXCAN_DisableMbInterrupts()
1845 base->IMASK2 &= ~((uint32_t)(mask >> 32)); in FLEXCAN_DisableMbInterrupts()
1847 base->IMASK1 &= ~mask; in FLEXCAN_DisableMbInterrupts()
1861 static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) in FLEXCAN_DisableHigh64MbInterrupts() argument
1866 base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); in FLEXCAN_DisableHigh64MbInterrupts()
1869 base->IMASK4 &= ~((uint32_t)(mask >> 32U)); in FLEXCAN_DisableHigh64MbInterrupts()