Lines Matching refs:base
114 #define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu)
115 #define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_M…
117 #define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_M…
170 typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
186 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
199 static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
211 static void FLEXCAN_Reset(CAN_Type *base);
222 static void FLEXCAN_GetSegments(CAN_Type *base,
241 static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx);
280 static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base);
291 static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint3…
303 static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64…
378 bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base) in FLEXCAN_IsInstanceHasFDMode() argument
381 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_IsInstanceHasFDMode()
383 base->MCR |= CAN_MCR_FDEN_MASK; in FLEXCAN_IsInstanceHasFDMode()
388 if (0U == (base->MCR & CAN_MCR_FDEN_MASK)) in FLEXCAN_IsInstanceHasFDMode()
391 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_IsInstanceHasFDMode()
397 base->MCR &= ~CAN_MCR_FDEN_MASK; in FLEXCAN_IsInstanceHasFDMode()
399 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_IsInstanceHasFDMode()
411 uint32_t FLEXCAN_GetInstance(CAN_Type *base) in FLEXCAN_GetInstance() argument
418 if (s_flexcanBases[instance] == base) in FLEXCAN_GetInstance()
437 void FLEXCAN_EnterFreezeMode(CAN_Type *base) in FLEXCAN_EnterFreezeMode() argument
447 base->MCR |= CAN_MCR_FRZ_MASK; in FLEXCAN_EnterFreezeMode()
450 if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) in FLEXCAN_EnterFreezeMode()
452 base->MCR &= ~CAN_MCR_MDIS_MASK; in FLEXCAN_EnterFreezeMode()
457 while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
463 if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) in FLEXCAN_EnterFreezeMode()
467 base->MCR |= CAN_MCR_HALT_MASK; in FLEXCAN_EnterFreezeMode()
472 while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
481 u32TempMCR = base->MCR; in FLEXCAN_EnterFreezeMode()
482 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode()
484 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
487 base->MCR |= CAN_MCR_SOFTRST_MASK; in FLEXCAN_EnterFreezeMode()
492 … while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
498 base->MCR = u32TempMCR; in FLEXCAN_EnterFreezeMode()
501 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode()
503 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
511 u32TempMCR = base->MCR; in FLEXCAN_EnterFreezeMode()
512 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode()
514 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
518 base->MCR |= CAN_MCR_SOFTRST_MASK; in FLEXCAN_EnterFreezeMode()
522 … while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
529 while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
535 base->MCR = u32TempMCR; in FLEXCAN_EnterFreezeMode()
538 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode()
540 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
545 void FLEXCAN_EnterFreezeMode(CAN_Type *base) in FLEXCAN_EnterFreezeMode() argument
555 base->MCR |= CAN_MCR_FRZ_MASK; in FLEXCAN_EnterFreezeMode()
556 base->MCR |= CAN_MCR_HALT_MASK; in FLEXCAN_EnterFreezeMode()
559 if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) in FLEXCAN_EnterFreezeMode()
561 base->MCR &= ~CAN_MCR_MDIS_MASK; in FLEXCAN_EnterFreezeMode()
566 while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) in FLEXCAN_EnterFreezeMode()
575 u32TempMCR = base->MCR; in FLEXCAN_EnterFreezeMode()
576 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode()
578 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
581 base->MCR |= CAN_MCR_SOFTRST_MASK; in FLEXCAN_EnterFreezeMode()
584 while (CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) in FLEXCAN_EnterFreezeMode()
589 base->MCR = u32TempMCR; in FLEXCAN_EnterFreezeMode()
592 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode()
594 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
599 void FLEXCAN_EnterFreezeMode(CAN_Type *base) in FLEXCAN_EnterFreezeMode() argument
602 base->MCR |= CAN_MCR_FRZ_MASK; in FLEXCAN_EnterFreezeMode()
603 base->MCR |= CAN_MCR_HALT_MASK; in FLEXCAN_EnterFreezeMode()
604 while (0U == (base->MCR & CAN_MCR_FRZACK_MASK)) in FLEXCAN_EnterFreezeMode()
617 void FLEXCAN_ExitFreezeMode(CAN_Type *base) in FLEXCAN_ExitFreezeMode() argument
621 FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | in FLEXCAN_ExitFreezeMode()
626 base->MCR &= ~CAN_MCR_HALT_MASK; in FLEXCAN_ExitFreezeMode()
627 base->MCR &= ~CAN_MCR_FRZ_MASK; in FLEXCAN_ExitFreezeMode()
630 while (0U != (base->MCR & CAN_MCR_FRZACK_MASK)) in FLEXCAN_ExitFreezeMode()
645 static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) in FLEXCAN_IsMbOccupied() argument
651 if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) in FLEXCAN_IsMbOccupied()
654 lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); in FLEXCAN_IsMbOccupied()
694 static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base) in FLEXCAN_GetFirstValidMb() argument
698 if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) in FLEXCAN_GetFirstValidMb()
700 firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); in FLEXCAN_GetFirstValidMb()
721 static void FLEXCAN_Reset(CAN_Type *base) in FLEXCAN_Reset() argument
726 assert(0U == (base->MCR & CAN_MCR_MDIS_MASK)); in FLEXCAN_Reset()
731 if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))) in FLEXCAN_Reset()
734 base->MCR &= ~CAN_MCR_DOZE_MASK; in FLEXCAN_Reset()
739 while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) in FLEXCAN_Reset()
744 base->MCR |= CAN_MCR_SOFTRST_MASK; in FLEXCAN_Reset()
746 while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK)) in FLEXCAN_Reset()
752 base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | in FLEXCAN_Reset()
753 … CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); in FLEXCAN_Reset()
755 base->MCR |= in FLEXCAN_Reset()
756 …RNEN_MASK | CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); in FLEXCAN_Reset()
761 base->CTRL1 = CAN_CTRL1_SMP_MASK; in FLEXCAN_Reset()
762 base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; in FLEXCAN_Reset()
766 base->CTRL2 |= CAN_CTRL2_WRMFRZ_MASK; in FLEXCAN_Reset()
773 base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; in FLEXCAN_Reset()
776 FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag); in FLEXCAN_Reset()
779 flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB)); in FLEXCAN_Reset()
783 for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) in FLEXCAN_Reset()
785 base->RXIMR[i] = 0x3FFFFFFF; in FLEXCAN_Reset()
789 base->RXMGMASK = 0x3FFFFFFF; in FLEXCAN_Reset()
791 base->RX14MASK = 0x3FFFFFFF; in FLEXCAN_Reset()
793 base->RX15MASK = 0x3FFFFFFF; in FLEXCAN_Reset()
795 base->RXFGMASK = 0x3FFFFFFF; in FLEXCAN_Reset()
811 status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps) in FLEXCAN_SetBitRate() argument
816 if (FLEXCAN_CalculateImprovedTimingValues(base, bitRate_Bps, sourceClock_Hz, &timingCfg)) in FLEXCAN_SetBitRate()
818 FLEXCAN_SetTimingConfig(base, &timingCfg); in FLEXCAN_SetBitRate()
838 status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint3… in FLEXCAN_SetFDBitRate() argument
843 …if (FLEXCAN_FDCalculateImprovedTimingValues(base, bitRateN_Bps, bitRateD_Bps, sourceClock_Hz, &tim… in FLEXCAN_SetFDBitRate()
845 FLEXCAN_SetFDTimingConfig(base, &timingCfg); in FLEXCAN_SetFDBitRate()
878 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) in FLEXCAN_Init() argument
883 … (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); in FLEXCAN_Init()
902 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_Init()
923 instance = FLEXCAN_GetInstance(base); in FLEXCAN_Init()
940 RESET_ReleasePeripheralReset(s_flexcanResets[FLEXCAN_GetInstance(base)]); in FLEXCAN_Init()
945 if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) in FLEXCAN_Init()
949 FLEXCAN_Enable(base, false); in FLEXCAN_Init()
954 … base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : in FLEXCAN_Init()
955 (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); in FLEXCAN_Init()
960 FLEXCAN_Enable(base, true); in FLEXCAN_Init()
963 FLEXCAN_Reset(base); in FLEXCAN_Init()
967 base->CTRL2 |= CAN_CTRL2_ECRWRE_MASK; in FLEXCAN_Init()
968 base->MECR &= ~CAN_MECR_ECRWRDIS_MASK; in FLEXCAN_Init()
971 base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : in FLEXCAN_Init()
972 (base->MECR | CAN_MECR_ECCDIS_MASK); in FLEXCAN_Init()
975 …base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MAS… in FLEXCAN_Init()
976 … (base->MECR & ~CAN_MECR_NCEFAFRZ_MASK); in FLEXCAN_Init()
978 base->CTRL2 &= ~CAN_CTRL2_ECRWRE_MASK; in FLEXCAN_Init()
982 ctrl1Temp = base->CTRL1; in FLEXCAN_Init()
985 mcrTemp = base->MCR; in FLEXCAN_Init()
1025 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) in FLEXCAN_Init()
1033 base->CTRL1 = ctrl1Temp; in FLEXCAN_Init()
1036 base->MCR = mcrTemp; in FLEXCAN_Init()
1049 FLEXCAN_SetTimingConfig(base, &timingCfg); in FLEXCAN_Init()
1083 …CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSi… in FLEXCAN_FDInit() argument
1109 FLEXCAN_Init(base, pConfig, sourceClock_Hz); in FLEXCAN_FDInit()
1122 FLEXCAN_SetFDTimingConfig(base, &timingCfg); in FLEXCAN_FDInit()
1125 fdctrl = base->FDCTRL; in FLEXCAN_FDInit()
1150 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_FDInit()
1152 base->MCR |= CAN_MCR_FDEN_MASK; in FLEXCAN_FDInit()
1155 base->CTRL1 &= ~CAN_CTRL1_SMP_MASK; in FLEXCAN_FDInit()
1165 base->ETDC = in FLEXCAN_FDInit()
1173 … base->ETDC = CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | in FLEXCAN_FDInit()
1197 base->FDCTRL = fdctrl; in FLEXCAN_FDInit()
1200 base->CTRL2 |= CAN_CTRL2_ISOCANFDEN_MASK; in FLEXCAN_FDInit()
1203 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_FDInit()
1215 void FLEXCAN_Deinit(CAN_Type *base) in FLEXCAN_Deinit() argument
1221 FLEXCAN_Reset(base); in FLEXCAN_Deinit()
1224 FLEXCAN_Enable(base, false); in FLEXCAN_Deinit()
1227 instance = FLEXCAN_GetInstance(base); in FLEXCAN_Deinit()
1332 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig) in FLEXCAN_SetPNConfig() argument
1339 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetPNConfig()
1346 base->CTRL1_PN = pnctrl; in FLEXCAN_SetPNConfig()
1347 base->CTRL2_PN = CAN_CTRL2_PN_MATCHTO(pConfig->timeoutValue); in FLEXCAN_SetPNConfig()
1348 base->FLT_ID1 = pConfig->idLower; in FLEXCAN_SetPNConfig()
1349 base->FLT_ID2_IDMASK = pConfig->idUpper; in FLEXCAN_SetPNConfig()
1350 …base->FLT_DLC = CAN_FLT_DLC_FLT_DLC_LO(pConfig->lengthLower) | CAN_FLT_DLC_FLT_DLC_HI(pConf… in FLEXCAN_SetPNConfig()
1351 base->PL1_LO = pConfig->lowerWord0; in FLEXCAN_SetPNConfig()
1352 base->PL1_HI = pConfig->lowerWord1; in FLEXCAN_SetPNConfig()
1353 base->PL2_PLMASK_LO = pConfig->upperWord0; in FLEXCAN_SetPNConfig()
1354 base->PL2_PLMASK_HI = pConfig->upperWord1; in FLEXCAN_SetPNConfig()
1356 …FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutInt… in FLEXCAN_SetPNConfig()
1359 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetPNConfig()
1375 status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) in FLEXCAN_ReadPNWakeUpMB() argument
1385 if (CAN_WU_MTC_MCOUNTER(mbIdx) < (base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK)) in FLEXCAN_ReadPNWakeUpMB()
1388 cs_temp = base->WMB[mbIdx].CS; in FLEXCAN_ReadPNWakeUpMB()
1391 pRxFrame->id = base->WMB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); in FLEXCAN_ReadPNWakeUpMB()
1409 pRxFrame->dataWord0 = base->WMB[mbIdx].D03; in FLEXCAN_ReadPNWakeUpMB()
1410 pRxFrame->dataWord1 = base->WMB[mbIdx].D47; in FLEXCAN_ReadPNWakeUpMB()
1437 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) in FLEXCAN_SetTimingConfig() argument
1443 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetTimingConfig()
1446 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_SetTimingConfig()
1450 base->CTRL2 |= CAN_CTRL2_BTE_MASK; in FLEXCAN_SetTimingConfig()
1453 … base->EPRS = (base->EPRS & (~CAN_EPRS_ENPRESDIV_MASK)) | CAN_EPRS_ENPRESDIV(pConfig->preDivider); in FLEXCAN_SetTimingConfig()
1454 base->ENCBT = CAN_ENCBT_NRJW(pConfig->rJumpwidth) | in FLEXCAN_SetTimingConfig()
1464 …base->CBT = CAN_CBT_BTF_MASK | CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJump… in FLEXCAN_SetTimingConfig()
1471 …(base->CBT & (CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MAS… in FLEXCAN_SetTimingConfig()
1478 …base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PS… in FLEXCAN_SetTimingConfig()
1482 … base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | in FLEXCAN_SetTimingConfig()
1488 …base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PS… in FLEXCAN_SetTimingConfig()
1492 base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | in FLEXCAN_SetTimingConfig()
1498 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetTimingConfig()
1516 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) in FLEXCAN_SetFDTimingConfig() argument
1522 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetFDTimingConfig()
1526 base->CTRL2 |= CAN_CTRL2_BTE_MASK; in FLEXCAN_SetFDTimingConfig()
1528 …base->EPRS = (base->EPRS & (~CAN_EPRS_EDPRESDIV_MASK)) | CAN_EPRS_EDPRESDIV(pConfig->fpreDivider); in FLEXCAN_SetFDTimingConfig()
1529 base->EDCBT = CAN_EDCBT_DRJW(pConfig->frJumpwidth) | CAN_EDCBT_DTSEG2(pConfig->fphaseSeg2) | in FLEXCAN_SetFDTimingConfig()
1533 base->CBT |= CAN_CBT_BTF_MASK; in FLEXCAN_SetFDTimingConfig()
1540 … base->FDCBT = (CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | in FLEXCAN_SetFDTimingConfig()
1546 (base->FDCBT & (CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | in FLEXCAN_SetFDTimingConfig()
1550 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetFDTimingConfig()
1563 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) in FLEXCAN_SetRxMbGlobalMask() argument
1566 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetRxMbGlobalMask()
1569 base->RXMGMASK = mask; in FLEXCAN_SetRxMbGlobalMask()
1570 base->RX14MASK = mask; in FLEXCAN_SetRxMbGlobalMask()
1571 base->RX15MASK = mask; in FLEXCAN_SetRxMbGlobalMask()
1574 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetRxMbGlobalMask()
1585 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) in FLEXCAN_SetRxFifoGlobalMask() argument
1588 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetRxFifoGlobalMask()
1591 base->RXFGMASK = mask; in FLEXCAN_SetRxFifoGlobalMask()
1594 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetRxFifoGlobalMask()
1611 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) in FLEXCAN_SetRxIndividualMask() argument
1613 assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_SetRxIndividualMask()
1616 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetRxIndividualMask()
1619 base->RXIMR[maskIdx] = mask; in FLEXCAN_SetRxIndividualMask()
1622 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetRxIndividualMask()
1637 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) in FLEXCAN_SetTxMbConfig() argument
1640 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_SetTxMbConfig()
1642 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_SetTxMbConfig()
1648 base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_SetTxMbConfig()
1652 base->MB[mbIdx].CS = 0; in FLEXCAN_SetTxMbConfig()
1656 base->MB[mbIdx].ID = 0x0; in FLEXCAN_SetTxMbConfig()
1657 base->MB[mbIdx].WORD0 = 0x0; in FLEXCAN_SetTxMbConfig()
1658 base->MB[mbIdx].WORD1 = 0x0; in FLEXCAN_SetTxMbConfig()
1671 static void FLEXCAN_GetSegments(CAN_Type *base, in FLEXCAN_GetSegments() argument
1680 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_GetSegments()
1725 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_GetSegments()
1766 if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_GetSegments()
1795 bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, in FLEXCAN_CalculateImprovedTimingValues() argument
1809 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) in FLEXCAN_CalculateImprovedTimingValues()
1858 FLEXCAN_GetSegments(base, bitRate, tqNum, &configTemp); in FLEXCAN_CalculateImprovedTimingValues()
1889 static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) in FLEXCAN_GetFDMailboxOffset() argument
1892 uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; in FLEXCAN_GetFDMailboxOffset()
2134 bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, in FLEXCAN_FDCalculateImprovedTimingValues() argument
2236 void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) in FLEXCAN_SetFDTxMbConfig() argument
2239 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_SetFDTxMbConfig()
2241 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_SetFDTxMbConfig()
2247 dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; in FLEXCAN_SetFDTxMbConfig()
2248 volatile uint32_t *mbAddr = &(base->MB[0].CS); in FLEXCAN_SetFDTxMbConfig()
2249 uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_SetFDTxMbConfig()
2252 uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); in FLEXCAN_SetFDTxMbConfig()
2301 void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig… in FLEXCAN_SetRxMbConfig() argument
2304 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_SetRxMbConfig()
2307 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_SetRxMbConfig()
2313 base->MB[mbIdx].CS = 0; in FLEXCAN_SetRxMbConfig()
2316 base->MB[mbIdx].ID = 0x0; in FLEXCAN_SetRxMbConfig()
2317 base->MB[mbIdx].WORD0 = 0x0; in FLEXCAN_SetRxMbConfig()
2318 base->MB[mbIdx].WORD1 = 0x0; in FLEXCAN_SetRxMbConfig()
2323 base->MB[mbIdx].ID = pRxMbConfig->id; in FLEXCAN_SetRxMbConfig()
2339 base->MB[mbIdx].CS = cs_temp; in FLEXCAN_SetRxMbConfig()
2357 void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConf… in FLEXCAN_SetFDRxMbConfig() argument
2360 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_SetFDRxMbConfig()
2363 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_SetFDRxMbConfig()
2368 volatile uint32_t *mbAddr = &(base->MB[0].CS); in FLEXCAN_SetFDRxMbConfig()
2369 uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_SetFDRxMbConfig()
2371 uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; in FLEXCAN_SetFDRxMbConfig()
2423 void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool en… in FLEXCAN_SetRxFifoConfig() argument
2433 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetRxFifoConfig()
2440 assert((base->ERFCR & CAN_ERFCR_ERFEN_MASK) == 0U); in FLEXCAN_SetRxFifoConfig()
2444 setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT); in FLEXCAN_SetRxFifoConfig()
2445 setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? in FLEXCAN_SetRxFifoConfig()
2447 (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); in FLEXCAN_SetRxFifoConfig()
2457 base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); in FLEXCAN_SetRxFifoConfig()
2470 mbAddr = &(base->MB[i].CS); in FLEXCAN_SetRxFifoConfig()
2490 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); in FLEXCAN_SetRxFifoConfig()
2493 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); in FLEXCAN_SetRxFifoConfig()
2496 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); in FLEXCAN_SetRxFifoConfig()
2500 base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); in FLEXCAN_SetRxFifoConfig()
2509 …base->CTRL2 = (pRxFifoConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP… in FLEXCAN_SetRxFifoConfig()
2510 … (base->CTRL2 | CAN_CTRL2_MRP_MASK); in FLEXCAN_SetRxFifoConfig()
2513 base->MCR |= CAN_MCR_RFEN_MASK; in FLEXCAN_SetRxFifoConfig()
2517 rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); in FLEXCAN_SetRxFifoConfig()
2522 base->MCR &= ~CAN_MCR_RFEN_MASK; in FLEXCAN_SetRxFifoConfig()
2528 FLEXCAN_SetRxMbConfig(base, i, NULL, false); in FLEXCAN_SetRxFifoConfig()
2533 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetRxFifoConfig()
2551 void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConf… in FLEXCAN_SetEnhancedRxFifoConfig() argument
2557 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_SetEnhancedRxFifoConfig()
2571 assert((base->MCR & CAN_MCR_RFEN_MASK) == 0U); in FLEXCAN_SetEnhancedRxFifoConfig()
2574 …base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_E… in FLEXCAN_SetEnhancedRxFifoConfig()
2577 …base->ERFCR = CAN_ERFCR_DMALW(pConfig->dmaPerReadLength) | CAN_ERFCR_NEXIF(pConfig->extendIdFilter… in FLEXCAN_SetEnhancedRxFifoConfig()
2582 …base->ERFFEL[i] = (i < ((uint32_t)pConfig->idFilterPairNum * 2U)) ? pConfig->idFilterTable[i] : 0x… in FLEXCAN_SetEnhancedRxFifoConfig()
2586 …base->CTRL2 = (pConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK)… in FLEXCAN_SetEnhancedRxFifoConfig()
2587 … (base->CTRL2 | CAN_CTRL2_MRP_MASK); in FLEXCAN_SetEnhancedRxFifoConfig()
2589 base->ERFCR |= CAN_ERFCR_ERFEN_MASK; in FLEXCAN_SetEnhancedRxFifoConfig()
2594 base->ERFCR = 0U; in FLEXCAN_SetEnhancedRxFifoConfig()
2596 …base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_E… in FLEXCAN_SetEnhancedRxFifoConfig()
2601 base->ERFFEL[i] = 0xFFFFFFFFU; in FLEXCAN_SetEnhancedRxFifoConfig()
2606 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_SetEnhancedRxFifoConfig()
2619 void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) in FLEXCAN_EnableRxFifoDMA() argument
2624 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_EnableRxFifoDMA()
2627 base->MCR |= CAN_MCR_DMA_MASK; in FLEXCAN_EnableRxFifoDMA()
2630 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_EnableRxFifoDMA()
2635 FLEXCAN_EnterFreezeMode(base); in FLEXCAN_EnableRxFifoDMA()
2638 base->MCR &= ~CAN_MCR_DMA_MASK; in FLEXCAN_EnableRxFifoDMA()
2641 FLEXCAN_ExitFreezeMode(base); in FLEXCAN_EnableRxFifoDMA()
2655 void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *error… in FLEXCAN_GetMemoryErrorReportStatus() argument
2659 base->MECR |= CAN_MECR_RERRDIS_MASK; in FLEXCAN_GetMemoryErrorReportStatus()
2661 errorStatus->accessAddress = (uint16_t)(base->RERRAR & CAN_RERRAR_ERRADDR_MASK); in FLEXCAN_GetMemoryErrorReportStatus()
2662 errorStatus->errorData = base->RERRDR; in FLEXCAN_GetMemoryErrorReportStatus()
2664 …(base->RERRAR & CAN_RERRAR_NCE_MASK) == 0U ? kFLEXCAN_CorrectableError : kFLEXCAN_NonCorrectableEr… in FLEXCAN_GetMemoryErrorReportStatus()
2666 temp = (base->RERRAR & CAN_RERRAR_SAID_MASK) >> CAN_RERRAR_SAID_SHIFT; in FLEXCAN_GetMemoryErrorReportStatus()
2683 temp = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_SYND0_MASK << (i * 8U))) >> (i * 8U); in FLEXCAN_GetMemoryErrorReportStatus()
2684 …errorStatus->byteStatus[i].byteIsRead = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_BE0_MASK << (i *… in FLEXCAN_GetMemoryErrorReportStatus()
2712 base->MECR &= CAN_MECR_RERRDIS_MASK; in FLEXCAN_GetMemoryErrorReportStatus()
2727 static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) in FLEXCAN_ERRATA_6032() argument
2734 dbg_temp = (uint32_t)(base->DBG1); in FLEXCAN_ERRATA_6032()
2741 while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) in FLEXCAN_ERRATA_6032()
2751 while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) in FLEXCAN_ERRATA_6032()
2762 if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK)) in FLEXCAN_ERRATA_6032()
2792 status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame) in FLEXCAN_WriteTxMb() argument
2795 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_WriteTxMb()
2799 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_WriteTxMb()
2806 if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) in FLEXCAN_WriteTxMb()
2809 FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); in FLEXCAN_WriteTxMb()
2812 …base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_WriteTxMb()
2815 base->MB[mbIdx].ID = pTxFrame->id; in FLEXCAN_WriteTxMb()
2832 base->MB[mbIdx].WORD0 = pTxFrame->dataWord0; in FLEXCAN_WriteTxMb()
2833 base->MB[mbIdx].WORD1 = pTxFrame->dataWord1; in FLEXCAN_WriteTxMb()
2836 base->MB[mbIdx].CS = cs_temp; in FLEXCAN_WriteTxMb()
2840 base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_WriteTxMb()
2841 base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); in FLEXCAN_WriteTxMb()
2869 status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame) in FLEXCAN_WriteFDTxMb() argument
2872 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_WriteFDTxMb()
2875 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_WriteFDTxMb()
2883 uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; in FLEXCAN_WriteFDTxMb()
2886 uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); in FLEXCAN_WriteFDTxMb()
2888 volatile uint32_t *mbAddr = &(base->MB[0].CS); in FLEXCAN_WriteFDTxMb()
2889 uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_WriteFDTxMb()
2896 FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); in FLEXCAN_WriteFDTxMb()
2964 status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) in FLEXCAN_ReadRxMb() argument
2967 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_ReadRxMb()
2970 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_ReadRxMb()
2978 cs_temp = base->MB[mbIdx].CS; in FLEXCAN_ReadRxMb()
2986 pRxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); in FLEXCAN_ReadRxMb()
3003 pRxFrame->dataWord0 = base->MB[mbIdx].WORD0; in FLEXCAN_ReadRxMb()
3004 pRxFrame->dataWord1 = base->MB[mbIdx].WORD1; in FLEXCAN_ReadRxMb()
3007 (void)base->TIMER; in FLEXCAN_ReadRxMb()
3021 (void)base->TIMER; in FLEXCAN_ReadRxMb()
3045 status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) in FLEXCAN_ReadFDRxMb() argument
3048 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_ReadFDRxMb()
3051 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_ReadFDRxMb()
3060 dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; in FLEXCAN_ReadFDRxMb()
3062 volatile uint32_t *mbAddr = &(base->MB[0].CS); in FLEXCAN_ReadFDRxMb()
3063 uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_ReadFDRxMb()
3112 (void)base->TIMER; in FLEXCAN_ReadFDRxMb()
3126 (void)base->TIMER; in FLEXCAN_ReadFDRxMb()
3145 status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame) in FLEXCAN_ReadRxFifo() argument
3154 if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) in FLEXCAN_ReadRxFifo()
3157 cs_temp = base->MB[0].CS; in FLEXCAN_ReadRxFifo()
3161 pRxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); in FLEXCAN_ReadRxFifo()
3178 pRxFrame->dataWord0 = base->MB[0].WORD0; in FLEXCAN_ReadRxFifo()
3179 pRxFrame->dataWord1 = base->MB[0].WORD1; in FLEXCAN_ReadRxFifo()
3182 pRxFrame->idhit = (uint16_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); in FLEXCAN_ReadRxFifo()
3185 (void)base->TIMER; in FLEXCAN_ReadRxFifo()
3208 status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) in FLEXCAN_ReadEnhancedRxFifo() argument
3217 if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) in FLEXCAN_ReadEnhancedRxFifo()
3220 … idHitOff = (DLC_LENGTH_DECODE(((flexcan_fd_frame_t *)E_RX_FIFO(base))->length) + 3U) / 4U + 3U; in FLEXCAN_ReadEnhancedRxFifo()
3223 … (void)memcpy((void *)pRxFrame, (void *)(uint32_t *)E_RX_FIFO(base), sizeof(uint32_t) * idHitOff); in FLEXCAN_ReadEnhancedRxFifo()
3232 base->ERFSR = CAN_ERFSR_ERFDA_MASK; in FLEXCAN_ReadEnhancedRxFifo()
3255 status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame) in FLEXCAN_TransferSendBlocking() argument
3260 …if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame… in FLEXCAN_TransferSendBlocking()
3266 while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) in FLEXCAN_TransferSendBlocking()
3269 FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferSendBlocking()
3273 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferSendBlocking()
3276 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferSendBlocking()
3279 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferSendBlocking()
3282 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferSendBlocking()
3284 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) in FLEXCAN_TransferSendBlocking()
3287 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferSendBlocking()
3291 …pTxFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAM… in FLEXCAN_TransferSendBlocking()
3315 status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) in FLEXCAN_TransferReceiveBlocking() argument
3321 while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) in FLEXCAN_TransferReceiveBlocking()
3324 FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferReceiveBlocking()
3328 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferReceiveBlocking()
3331 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferReceiveBlocking()
3334 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferReceiveBlocking()
3337 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferReceiveBlocking()
3339 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) in FLEXCAN_TransferReceiveBlocking()
3342 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferReceiveBlocking()
3346 return FLEXCAN_ReadRxMb(base, mbIdx, pRxFrame); in FLEXCAN_TransferReceiveBlocking()
3361 status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame) in FLEXCAN_TransferFDSendBlocking() argument
3366 …if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTx… in FLEXCAN_TransferFDSendBlocking()
3372 while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) in FLEXCAN_TransferFDSendBlocking()
3375 FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferFDSendBlocking()
3379 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferFDSendBlocking()
3382 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDSendBlocking()
3385 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferFDSendBlocking()
3388 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDSendBlocking()
3390 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) in FLEXCAN_TransferFDSendBlocking()
3393 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferFDSendBlocking()
3396 volatile uint32_t *mbAddr = &(base->MB[0].CS); in FLEXCAN_TransferFDSendBlocking()
3397 uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_TransferFDSendBlocking()
3422 status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFr… in FLEXCAN_TransferFDReceiveBlocking() argument
3428 while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) in FLEXCAN_TransferFDReceiveBlocking()
3431 FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferFDReceiveBlocking()
3435 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferFDReceiveBlocking()
3438 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDReceiveBlocking()
3441 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) in FLEXCAN_TransferFDReceiveBlocking()
3444 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDReceiveBlocking()
3446 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) in FLEXCAN_TransferFDReceiveBlocking()
3449 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferFDReceiveBlocking()
3453 return FLEXCAN_ReadFDRxMb(base, mbIdx, pRxFrame); in FLEXCAN_TransferFDReceiveBlocking()
3467 status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame) in FLEXCAN_TransferReceiveFifoBlocking() argument
3472 while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)) in FLEXCAN_TransferReceiveFifoBlocking()
3477 rxFifoStatus = FLEXCAN_ReadRxFifo(base, pRxFrame); in FLEXCAN_TransferReceiveFifoBlocking()
3480 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); in FLEXCAN_TransferReceiveFifoBlocking()
3496 status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) in FLEXCAN_TransferReceiveEnhancedFifoBlocking() argument
3501 while (0U == (FLEXCAN_GetStatusFlags(base) & (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)) in FLEXCAN_TransferReceiveEnhancedFifoBlocking()
3506 rxFifoStatus = FLEXCAN_ReadEnhancedRxFifo(base, pRxFrame); in FLEXCAN_TransferReceiveEnhancedFifoBlocking()
3524 void FLEXCAN_TransferCreateHandle(CAN_Type *base, in FLEXCAN_TransferCreateHandle() argument
3537 instance = (uint8_t)FLEXCAN_GetInstance(base); in FLEXCAN_TransferCreateHandle()
3555 … base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | in FLEXCAN_TransferCreateHandle()
3580 … base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | in FLEXCAN_TransferCreateHandle()
3625 status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_trans… in FLEXCAN_TransferSendNonBlocking() argument
3630 assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferSendNonBlocking()
3632 assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); in FLEXCAN_TransferSendNonBlocking()
3651 … FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) in FLEXCAN_TransferSendNonBlocking()
3657 FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); in FLEXCAN_TransferSendNonBlocking()
3661 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferSendNonBlocking()
3664 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferSendNonBlocking()
3666 FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferSendNonBlocking()
3696 status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_tr… in FLEXCAN_TransferReceiveNonBlocking() argument
3703 assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferReceiveNonBlocking()
3705 assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); in FLEXCAN_TransferReceiveNonBlocking()
3720 FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); in FLEXCAN_TransferReceiveNonBlocking()
3724 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferReceiveNonBlocking()
3727 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferReceiveNonBlocking()
3729 FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferReceiveNonBlocking()
3756 status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_tra… in FLEXCAN_TransferFDSendNonBlocking() argument
3761 assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferFDSendNonBlocking()
3763 assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); in FLEXCAN_TransferFDSendNonBlocking()
3782 …FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) in FLEXCAN_TransferFDSendNonBlocking()
3788 FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); in FLEXCAN_TransferFDSendNonBlocking()
3792 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDSendNonBlocking()
3795 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDSendNonBlocking()
3797 FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDSendNonBlocking()
3828 status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_… in FLEXCAN_TransferFDReceiveNonBlocking() argument
3833 assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferFDReceiveNonBlocking()
3835 assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); in FLEXCAN_TransferFDReceiveNonBlocking()
3852 FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); in FLEXCAN_TransferFDReceiveNonBlocking()
3856 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDReceiveNonBlocking()
3859 FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDReceiveNonBlocking()
3861 FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); in FLEXCAN_TransferFDReceiveNonBlocking()
3887 status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, in FLEXCAN_TransferReceiveFifoNonBlocking() argument
3915 FLEXCAN_EnableMbInterrupts(base, irqMask); in FLEXCAN_TransferReceiveFifoNonBlocking()
3937 status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *coun… in FLEXCAN_TransferGetReceiveFifoCount() argument
3968 status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, in FLEXCAN_TransferReceiveEnhancedFifoNonBlocking() argument
3977 uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; in FLEXCAN_TransferReceiveEnhancedFifoNonBlocking()
4002 FLEXCAN_EnableInterrupts(base, irqMask); in FLEXCAN_TransferReceiveEnhancedFifoNonBlocking()
4024 void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) in FLEXCAN_TransferAbortSend() argument
4030 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferAbortSend()
4032 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_TransferAbortSend()
4038 FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferAbortSend()
4042 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferAbortSend()
4045 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferAbortSend()
4047 FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferAbortSend()
4051 …timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME… in FLEXCAN_TransferAbortSend()
4055 FLEXCAN_SetTxMbConfig(base, mbIdx, true); in FLEXCAN_TransferAbortSend()
4070 void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) in FLEXCAN_TransferFDAbortSend() argument
4078 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferFDAbortSend()
4080 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_TransferFDAbortSend()
4087 FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferFDAbortSend()
4091 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDAbortSend()
4094 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDAbortSend()
4096 FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferFDAbortSend()
4100 mbAddr = &(base->MB[0].CS); in FLEXCAN_TransferFDAbortSend()
4101 offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); in FLEXCAN_TransferFDAbortSend()
4106 FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); in FLEXCAN_TransferFDAbortSend()
4120 void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) in FLEXCAN_TransferFDAbortReceive() argument
4124 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferFDAbortReceive()
4126 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_TransferFDAbortReceive()
4133 FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferFDAbortReceive()
4137 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDAbortReceive()
4140 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferFDAbortReceive()
4142 FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferFDAbortReceive()
4160 void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) in FLEXCAN_TransferAbortReceive() argument
4164 assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); in FLEXCAN_TransferAbortReceive()
4166 assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); in FLEXCAN_TransferAbortReceive()
4173 FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); in FLEXCAN_TransferAbortReceive()
4177 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferAbortReceive()
4180 FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); in FLEXCAN_TransferAbortReceive()
4182 FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); in FLEXCAN_TransferAbortReceive()
4198 void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) in FLEXCAN_TransferAbortReceiveFifo() argument
4204 if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) in FLEXCAN_TransferAbortReceiveFifo()
4207 …FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFif… in FLEXCAN_TransferAbortReceiveFifo()
4229 void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle) in FLEXCAN_TransferAbortReceiveEnhancedFifo() argument
4235 if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) in FLEXCAN_TransferAbortReceiveEnhancedFifo()
4238 FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | in FLEXCAN_TransferAbortReceiveEnhancedFifo()
4286 static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) in FLEXCAN_CheckUnhandleInterruptEvents() argument
4292 if (0U == (FLEXCAN_GetStatusFlags(base) & in FLEXCAN_CheckUnhandleInterruptEvents()
4301 tempmask = (uint64_t)base->IMASK1; in FLEXCAN_CheckUnhandleInterruptEvents()
4302 tempflag = (uint64_t)base->IFLAG1; in FLEXCAN_CheckUnhandleInterruptEvents()
4304 tempmask |= ((uint64_t)base->IMASK2) << 32; in FLEXCAN_CheckUnhandleInterruptEvents()
4305 tempflag |= ((uint64_t)base->IFLAG2) << 32; in FLEXCAN_CheckUnhandleInterruptEvents()
4309 if (0U != (base->IMASK3 & base->IFLAG3)) in FLEXCAN_CheckUnhandleInterruptEvents()
4315 if (0U != (base->IMASK4 & base->IFLAG4)) in FLEXCAN_CheckUnhandleInterruptEvents()
4322 else if (0U != (FLEXCAN_GetStatusFlags(base) & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG)) in FLEXCAN_CheckUnhandleInterruptEvents()
4325 tempmask = (uint64_t)base->ERFIER; in FLEXCAN_CheckUnhandleInterruptEvents()
4326 tempflag = (uint64_t)base->ERFSR; in FLEXCAN_CheckUnhandleInterruptEvents()
4348 static status_t FLEXCAN_SubHandlerForLegacyRxFIFO(CAN_Type *base, flexcan_handle_t *handle, uint32_… in FLEXCAN_SubHandlerForLegacyRxFIFO() argument
4360 …if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)… in FLEXCAN_SubHandlerForLegacyRxFIFO()
4364 status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); in FLEXCAN_SubHandlerForLegacyRxFIFO()
4376 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); in FLEXCAN_SubHandlerForLegacyRxFIFO()
4390 FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); in FLEXCAN_SubHandlerForLegacyRxFIFO()
4406 status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); in FLEXCAN_SubHandlerForLegacyRxFIFO()
4430 FLEXCAN_TransferAbortReceiveFifo(base, handle); in FLEXCAN_SubHandlerForLegacyRxFIFO()
4457 static status_t FLEXCAN_SubHandlerForMB(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) in FLEXCAN_SubHandlerForMB() argument
4467 if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) in FLEXCAN_SubHandlerForMB()
4469 status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); in FLEXCAN_SubHandlerForMB()
4484 status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); in FLEXCAN_SubHandlerForMB()
4497 if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) in FLEXCAN_SubHandlerForMB()
4499 FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4504 FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4512 if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) in FLEXCAN_SubHandlerForMB()
4514 FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4519 FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4527 if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) in FLEXCAN_SubHandlerForMB()
4529 FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4534 FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); in FLEXCAN_SubHandlerForMB()
4561 static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint3… in FLEXCAN_SubHandlerForDataTransfered() argument
4567 uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; in FLEXCAN_SubHandlerForDataTransfered()
4569 intflag[2] = base->IMASK3 & base->IFLAG3; in FLEXCAN_SubHandlerForDataTransfered()
4572 intflag[3] = base->IMASK4 & base->IFLAG4; in FLEXCAN_SubHandlerForDataTransfered()
4575 uint32_t intflag = base->IMASK1 & base->IFLAG1; in FLEXCAN_SubHandlerForDataTransfered()
4596 …for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); res… in FLEXCAN_SubHandlerForDataTransfered()
4606 if (result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) in FLEXCAN_SubHandlerForDataTransfered()
4610 ((base->MCR & CAN_MCR_RFEN_MASK) != 0U)) in FLEXCAN_SubHandlerForDataTransfered()
4612 status = FLEXCAN_SubHandlerForLegacyRxFIFO(base, handle, result); in FLEXCAN_SubHandlerForDataTransfered()
4628 status = FLEXCAN_SubHandlerForMB(base, handle, result); in FLEXCAN_SubHandlerForDataTransfered()
4635 FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (result - 64U)); in FLEXCAN_SubHandlerForDataTransfered()
4639 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); in FLEXCAN_SubHandlerForDataTransfered()
4642 FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); in FLEXCAN_SubHandlerForDataTransfered()
4644 FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << result); in FLEXCAN_SubHandlerForDataTransfered()
4663 static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64… in FLEXCAN_SubHandlerForEhancedRxFifo() argument
4665 uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; in FLEXCAN_SubHandlerForEhancedRxFifo()
4671 (0u != (base->ERFIER & CAN_ERFIER_ERFUFWIE_MASK))) in FLEXCAN_SubHandlerForEhancedRxFifo()
4674 FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag); in FLEXCAN_SubHandlerForEhancedRxFifo()
4677 (0u != (base->ERFIER & CAN_ERFIER_ERFOVFIE_MASK))) in FLEXCAN_SubHandlerForEhancedRxFifo()
4680 FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag); in FLEXCAN_SubHandlerForEhancedRxFifo()
4683 (0u != (base->ERFIER & CAN_ERFIER_ERFWMIIE_MASK))) in FLEXCAN_SubHandlerForEhancedRxFifo()
4690 status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); in FLEXCAN_SubHandlerForEhancedRxFifo()
4697 base->ERFSR = CAN_ERFSR_ERFWMI_MASK; in FLEXCAN_SubHandlerForEhancedRxFifo()
4707 FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); in FLEXCAN_SubHandlerForEhancedRxFifo()
4713 FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable); in FLEXCAN_SubHandlerForEhancedRxFifo()
4714 FLEXCAN_EnableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); in FLEXCAN_SubHandlerForEhancedRxFifo()
4728 status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); in FLEXCAN_SubHandlerForEhancedRxFifo()
4743 FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); in FLEXCAN_SubHandlerForEhancedRxFifo()
4764 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) in FLEXCAN_TransferHandleIRQ() argument
4781 result = FLEXCAN_GetStatusFlags(base); in FLEXCAN_TransferHandleIRQ()
4788 FLEXCAN_ClearStatusFlags(base, FLEXCAN_ERROR_AND_STATUS_INIT_FLAG); in FLEXCAN_TransferHandleIRQ()
4794 FLEXCAN_ClearStatusFlags(base, FLEXCAN_WAKE_UP_FLAG); in FLEXCAN_TransferHandleIRQ()
4798 …= (FLEXCAN_EFIFO_STATUS_UNMASK(result & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG) & base->ERFIER)) in FLEXCAN_TransferHandleIRQ()
4800 status = FLEXCAN_SubHandlerForEhancedRxFifo(base, handle, result); in FLEXCAN_TransferHandleIRQ()
4806 status = FLEXCAN_SubHandlerForDataTransfered(base, handle, &mbNum); in FLEXCAN_TransferHandleIRQ()
4813 handle->callback(base, handle, status, result, handle->userData); in FLEXCAN_TransferHandleIRQ()
4815 } while (FLEXCAN_CheckUnhandleInterruptEvents(base)); in FLEXCAN_TransferHandleIRQ()