93     uint32_t reg_value = 0;  in FLEXBUS_Init()  local
110     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;  in FLEXBUS_Init()
112     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;  in FLEXBUS_Init()
114     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;  in FLEXBUS_Init()
116     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;  in FLEXBUS_Init()
118     reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;  in FLEXBUS_Init()
120     base->CSPMCR = reg_value;  in FLEXBUS_Init()
123     reg_value = config->chipBaseAddress;  in FLEXBUS_Init()
125     base->CS[chip].CSAR = reg_value;  in FLEXBUS_Init()
128     reg_value = 0x1U << FB_CSMR_V_SHIFT;  in FLEXBUS_Init()
130     reg_value |= ((uint32_t)config->writeProtect) << FB_CSMR_WP_SHIFT;  in FLEXBUS_Init()
132     reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;  in FLEXBUS_Init()
134     base->CS[chip].CSMR = reg_value;  in FLEXBUS_Init()
137     reg_value = ((uint32_t)config->burstWrite) << FB_CSCR_BSTW_SHIFT;  in FLEXBUS_Init()
139     reg_value |= ((uint32_t)config->burstRead) << FB_CSCR_BSTR_SHIFT;  in FLEXBUS_Init()
141     reg_value |= ((uint32_t)config->byteEnableMode) << FB_CSCR_BEM_SHIFT;  in FLEXBUS_Init()
143     reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;  in FLEXBUS_Init()
145     reg_value |= ((uint32_t)config->autoAcknowledge) << FB_CSCR_AA_SHIFT;  in FLEXBUS_Init()
147     reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;  in FLEXBUS_Init()
149     reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT;  in FLEXBUS_Init()
151     reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT;  in FLEXBUS_Init()
153     reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT;  in FLEXBUS_Init()
155     reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;  in FLEXBUS_Init()
157     reg_value |= ((uint32_t)config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;  in FLEXBUS_Init()
161         reg_value |= FB_CSCR_SWSEN_MASK;  in FLEXBUS_Init()
162         reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWS_SHIFT;  in FLEXBUS_Init()
165     base->CS[chip].CSCR = reg_value;  in FLEXBUS_Init()
168     reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;  in FLEXBUS_Init()
170     reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;  in FLEXBUS_Init()
172     reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;  in FLEXBUS_Init()
174     reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;  in FLEXBUS_Init()
176     reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;  in FLEXBUS_Init()
178     base->CSPMCR = reg_value;  in FLEXBUS_Init()