764     dpu_unit_t unit;  member
842         .unit   = kDPU_Store9,
846         .unit   = kDPU_FetchWarp9,
850         .unit   = kDPU_FetchDecode9,
854         .unit   = kDPU_BlitBlend9,
858         .unit   = kDPU_Rop9,
862         .unit   = kDPU_Hscaler9,
866         .unit   = kDPU_Vscaler9,
870         .unit   = kDPU_Hscaler4,
874         .unit   = kDPU_Vscaler4,
878         .unit   = kDPU_Hscaler5,
882         .unit   = kDPU_Vscaler5,
886         .unit   = kDPU_ExtDst0,
890         .unit   = kDPU_ExtDst4,
894         .unit   = kDPU_ExtDst1,
898         .unit   = kDPU_ExtDst5,
902         .unit   = kDPU_FetchWarp2,
906         .unit   = kDPU_FetchDecode0,
910         .unit   = kDPU_FetchDecode1,
914         .unit   = kDPU_LayerBlend0,
918         .unit   = kDPU_LayerBlend1,
922         .unit   = kDPU_LayerBlend2,
926         .unit   = kDPU_LayerBlend3,
951 static uint32_t DPU_GetDynamicRegOffset(dpu_unit_t unit);
977 static DPU_SUBLAYER_CONTROL_Type *DPU_GetSubLayer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t su…
1065 static uint32_t DPU_GetDynamicRegOffset(dpu_unit_t unit)  in DPU_GetDynamicRegOffset()  argument
1072         if (s_dpuUnitDynamicRegOffsetTable[i].unit == unit)  in DPU_GetDynamicRegOffset()
1082 static DPU_SUBLAYER_CONTROL_Type *DPU_GetSubLayer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t su…  in DPU_GetSubLayer()  argument
1088     if (0U == ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrSubLayer)))  in DPU_GetSubLayer()
1093     if ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit))  in DPU_GetSubLayer()
1102     return (DPU_SUBLAYER_CONTROL_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit) + offset +  in DPU_GetSubLayer()
1470 status_t DPU_EnableShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)  in DPU_EnableShadowLoad()  argument
1476     if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrNoShdow)))  in DPU_EnableShadowLoad()
1482         staticRegOffset = DPU_GET_UNIT_OFFSET(unit) + DPU_STATIC_CONTROL_OFFSET;  in DPU_EnableShadowLoad()
1505 void DPU_InitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_InitPipeline()  argument
1507     assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));  in DPU_InitPipeline()
1509 … DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitPipeline()
1523 void DPU_DeinitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_DeinitPipeline()  argument
1525     assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));  in DPU_DeinitPipeline()
1527 … DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_DeinitPipeline()
1541 void DPU_TriggerPipelineShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_TriggerPipelineShadowLoad()  argument
1543     assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));  in DPU_TriggerPipelineShadowLoad()
1545 … DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_TriggerPipelineShadowLoad()
1562 void DPU_TriggerPipelineCompleteInterrupt(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_TriggerPipelineCompleteInterrupt()  argument
1564     assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));  in DPU_TriggerPipelineCompleteInterrupt()
1566 … DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_TriggerPipelineCompleteInterrupt()
1586 void DPU_SetUnitSrc(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_SetUnitSrc()  argument
1588     assert(0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrHasSrc)));  in DPU_SetUnitSrc()
1591     uint32_t offset = DPU_GetDynamicRegOffset(unit);  in DPU_SetUnitSrc()
1609 status_t DPU_SetColorPaletteIndexWidth(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t indexWidth)  in DPU_SetColorPaletteIndexWidth()  argument
1613     uint32_t type = DPU_GET_UNIT_TYPE(unit);  in DPU_SetColorPaletteIndexWidth()
1620     offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);  in DPU_SetColorPaletteIndexWidth()
1655 …IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t startIndex, const uint32_t *palette, uint32_t coun…  in DPU_UpdateColorPalette()  argument
1658     assert(((uint32_t)kDPU_FetchLayer == DPU_GET_UNIT_TYPE(unit)) ||  in DPU_UpdateColorPalette()
1659            ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit)));  in DPU_UpdateColorPalette()
1670     offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);  in DPU_UpdateColorPalette()
1689 void DPU_EnableColorPalette(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)  in DPU_EnableColorPalette()  argument
1691     assert(((uint32_t)kDPU_FetchLayer == DPU_GET_UNIT_TYPE(unit)) ||  in DPU_EnableColorPalette()
1692            ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit)));  in DPU_EnableColorPalette()
1694     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_EnableColorPalette()
1749 void DPU_InitFetchUnit(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_fetch_unit_config_t *config)  in DPU_InitFetchUnit()  argument
1752     assert(0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrIsFetch)));  in DPU_InitFetchUnit()
1761     offset = DPU_GET_UNIT_OFFSET(unit);  in DPU_InitFetchUnit()
1762     type   = DPU_GET_UNIT_TYPE(unit);  in DPU_InitFetchUnit()
1795     if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrSubLayer)))  in DPU_InitFetchUnit()
1806     if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrHasSrc)))  in DPU_InitFetchUnit()
1808         DPU_SetUnitSrc(base, unit, config->srcReg);  in DPU_InitFetchUnit()
1898 status_t DPU_InitFetchUnitWarp(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_warp_config_t *conf…  in DPU_InitFetchUnitWarp()  argument
1905     if ((uint32_t)kDPU_FetchWarp != DPU_GET_UNIT_TYPE(unit))  in DPU_InitFetchUnitWarp()
1910     fetchWarp = (DPU_FETCHWARP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitFetchUnitWarp()
1919     DPU_SetUnitSrc(base, unit, config->srcReg);  in DPU_InitFetchUnitWarp()
1991 status_t DPU_InitWarpCoordinates(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_coordinates_confi…  in DPU_InitWarpCoordinates()  argument
2004     fetchEco = (DPU_FETCHECO_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitWarpCoordinates()
2075                                          dpu_unit_t unit,  in DPU_SetFetchUnitSrcBufferConfig()  argument
2089     control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_SetFetchUnitSrcBufferConfig()
2109 void DPU_SetFetchUnitSrcBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_…  in DPU_SetFetchUnitSrcBufferAddr()  argument
2111     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_SetFetchUnitSrcBufferAddr()
2124 void DPU_SetFetchUnitFrameSize(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t height, uint16_t wid…  in DPU_SetFetchUnitFrameSize()  argument
2130     offset = DPU_GET_UNIT_OFFSET(unit);  in DPU_SetFetchUnitFrameSize()
2131     type   = DPU_GET_UNIT_TYPE(unit);  in DPU_SetFetchUnitFrameSize()
2165 void DPU_SetFetchUnitOffset(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint16_t offse…  in DPU_SetFetchUnitOffset()  argument
2167     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_SetFetchUnitOffset()
2180 void DPU_EnableFetchUnitSrcBuffer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool ena…  in DPU_EnableFetchUnitSrcBuffer()  argument
2182     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_EnableFetchUnitSrcBuffer()
2229                                       dpu_unit_t unit,  in DPU_SetFetchUnitClipWindowConfig()  argument
2235     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_SetFetchUnitClipWindowConfig()
2249 void DPU_EnableFetchUnitClipWindow(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool en…  in DPU_EnableFetchUnitClipWindow()  argument
2251     DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);  in DPU_EnableFetchUnitClipWindow()
2276                                dpu_unit_t unit,  in DPU_SetFetchUnitClipColor()  argument
2285     offset = DPU_GET_UNIT_OFFSET(unit);  in DPU_SetFetchUnitClipColor()
2286     type   = DPU_GET_UNIT_TYPE(unit);  in DPU_SetFetchUnitClipColor()
2342 void DPU_InitExtDst(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_InitExtDst()  argument
2346     assert((uint32_t)kDPU_ExtDst == DPU_GET_UNIT_TYPE(unit));  in DPU_InitExtDst()
2348     extDst = (DPU_EXTDST_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitExtDst()
2354     DPU_SetUnitSrc(base, unit, srcReg);  in DPU_InitExtDst()
2375 void DPU_InitStore(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_InitStore()  argument
2379     assert((uint32_t)kDPU_Store == DPU_GET_UNIT_TYPE(unit));  in DPU_InitStore()
2381     store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitStore()
2394     DPU_SetUnitSrc(base, unit, srcReg);  in DPU_InitStore()
2406 status_t DPU_SetStoreDstBufferConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_dst_buffer_co…  in DPU_SetStoreDstBufferConfig()  argument
2416     DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetStoreDstBufferConfig()
2466 void DPU_SetStoreDstBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t baseAddr)  in DPU_SetStoreDstBufferAddr()  argument
2468     DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetStoreDstBufferAddr()
2485 void DPU_SetStoreOffset(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t offsetX, uint16_t offsetY)  in DPU_SetStoreOffset()  argument
2487     DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetStoreOffset()
2505 void DPU_StartStore(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_StartStore()  argument
2507     DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_StartStore()
2585 void DPU_InitLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_InitLayerBlend()  argument
2589     assert((uint32_t)kDPU_LayerBlend == DPU_GET_UNIT_TYPE(unit));  in DPU_InitLayerBlend()
2591     layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitLayerBlend()
2613     DPU_SetUnitSrc(base, unit, srcReg);  in DPU_InitLayerBlend()
2623 void DPU_SetLayerBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_layer_blend_config_t …  in DPU_SetLayerBlendConfig()  argument
2629     layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetLayerBlendConfig()
2654 void DPU_EnableLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)  in DPU_EnableLayerBlend()  argument
2656 …AYERBLEND_Type *layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_EnableLayerBlend()
2689 void DPU_InitRop(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_InitRop()  argument
2691     assert((uint32_t)kDPU_Rop == DPU_GET_UNIT_TYPE(unit));  in DPU_InitRop()
2693     DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitRop()
2697     DPU_SetUnitSrc(base, unit, srcReg);  in DPU_InitRop()
2735 void DPU_SetRopConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_rop_config_t *config)  in DPU_SetRopConfig()  argument
2739     DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetRopConfig()
2755 void DPU_EnableRop(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)  in DPU_EnableRop()  argument
2757     DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_EnableRop()
2788 void DPU_InitBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)  in DPU_InitBlitBlend()  argument
2790     assert((uint32_t)kDPU_BlitBlend == DPU_GET_UNIT_TYPE(unit));  in DPU_InitBlitBlend()
2792 …U_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitBlitBlend()
2796     DPU_SetUnitSrc(base, unit, srcReg);  in DPU_InitBlitBlend()
2857 void DPU_SetBlitBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_blit_blend_config_t *c…  in DPU_SetBlitBlendConfig()  argument
2861 …U_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetBlitBlendConfig()
2891 void DPU_EnableBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)  in DPU_EnableBlitBlend()  argument
2893 …U_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_EnableBlitBlend()
2911 void DPU_InitConstFrame(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_InitConstFrame()  argument
2913     assert((uint32_t)kDPU_ConstFrame == DPU_GET_UNIT_TYPE(unit));  in DPU_InitConstFrame()
2915 …ONSTFRAME_Type *constFrame = (DPU_CONSTFRAME_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_InitConstFrame()
2951 void DPU_SetConstFrameConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_const_frame_config_t …  in DPU_SetConstFrameConfig()  argument
2955 …ONSTFRAME_Type *constFrame = (DPU_CONSTFRAME_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));  in DPU_SetConstFrameConfig()
2967 void DPU_InitScaler(IRIS_MVPL_Type *base, dpu_unit_t unit)  in DPU_InitScaler()  argument
2969     assert(((uint32_t)kDPU_VScaler == DPU_GET_UNIT_TYPE(unit)) ||  in DPU_InitScaler()
2970            (((uint32_t)kDPU_HScaler == DPU_GET_UNIT_TYPE(unit))));  in DPU_InitScaler()
2972     (void)DPU_EnableShadowLoad(base, unit, true);  in DPU_InitScaler()
3021 void DPU_SetScalerConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_scaler_config_t *config)  in DPU_SetScalerConfig()  argument
3028     uint32_t offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);  in DPU_SetScalerConfig()
3065     if ((uint32_t)kDPU_VScaler == DPU_GET_UNIT_TYPE(unit))  in DPU_SetScalerConfig()
3074     DPU_SetUnitSrc(base, unit, config->srcReg);  in DPU_SetScalerConfig()