Lines Matching refs:CONTROL
74 __IO uint32_t CONTROL; member
99 __IO uint32_t CONTROL; member
133 __IO uint32_t CONTROL; member
156 __IO uint32_t CONTROL; member
178 __IO uint32_t CONTROL; member
205 __IO uint32_t CONTROL; member
261 __IO uint32_t CONTROL; member
269 __IO uint32_t CONTROL; member
286 __IO uint32_t CONTROL; member
341 __IO uint32_t CONTROL; member
362 __IO uint32_t CONTROL; member
405 __IO uint32_t CONTROL; member
418 __IO uint32_t CONTROL; member
430 __IO uint32_t CONTROL; member
560 #define DPU_FETCHECO_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHECO_Type *)0)->CONTROL)
561 …efine DPU_FETCHDECODE_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHDECODER_Type *)0)->CONTROL)
562 #define DPU_FETCHLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHLAYER_Type *)0)->CONTROL)
563 #define DPU_FETCHWARP_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->CONTROL)
1625 reg = ((DPU_FETCHLAYER_Type *)offset)->CONTROL; in DPU_SetColorPaletteIndexWidth()
1627 ((DPU_FETCHLAYER_Type *)offset)->CONTROL = reg; in DPU_SetColorPaletteIndexWidth()
1631 reg = ((DPU_FETCHDECODER_Type *)offset)->CONTROL; in DPU_SetColorPaletteIndexWidth()
1633 ((DPU_FETCHDECODER_Type *)offset)->CONTROL = reg; in DPU_SetColorPaletteIndexWidth()
1942 …reg = fetchWarp->CONTROL & ~(DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK | DPU_FETCH_CONTROL_RASTE… in DPU_InitFetchUnitWarp()
1944 fetchWarp->CONTROL = reg | DPU_FETCH_CONTROL_INPUTSELECT(kDPU_FetchCtrlInputSelCoordinate) | in DPU_InitFetchUnitWarp()
2024 …reg = fetchEco->CONTROL & ~(DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK | DPU_FETCH_CONTROL_RASTER… in DPU_InitWarpCoordinates()
2026 fetchEco->CONTROL = in DPU_InitWarpCoordinates()
2639 layerBlend->CONTROL = ((layerBlend->CONTROL & ~(DPU_LAYERBLEND_CONTROL_AlphaMaskEnable_MASK | in DPU_SetLayerBlendConfig()
2660 layerBlend->CONTROL |= DPU_LAYERBLEND_CONTROL_MODE_MASK; in DPU_EnableLayerBlend()
2664 layerBlend->CONTROL &= ~DPU_LAYERBLEND_CONTROL_MODE_MASK; in DPU_EnableLayerBlend()
2743 rop->CONTROL = (rop->CONTROL & DPU_ROP_CONTROL_Mode_MASK) | config->controlFlags; in DPU_SetRopConfig()
2761 rop->CONTROL |= DPU_ROP_CONTROL_Mode_MASK; in DPU_EnableRop()
2765 rop->CONTROL &= ~DPU_ROP_CONTROL_Mode_MASK; in DPU_EnableRop()
2897 blitBlend->CONTROL = DPU_BLITBLEND_CONTROL_Mode_MASK; in DPU_EnableBlitBlend()
2901 blitBlend->CONTROL = 0U; in DPU_EnableBlitBlend()
3067 ((DPU_VSCALER_Type *)offset)->CONTROL = control; in DPU_SetScalerConfig()
3071 ((DPU_HSCALER_Type *)offset)->CONTROL = control; in DPU_SetScalerConfig()