201     uint32_t period, pulsePeriod = 0;  in CTIMER_SetupPwm()  local
236         pulsePeriod = period + 1U;  in CTIMER_SetupPwm()
240         pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;  in CTIMER_SetupPwm()
247     base->MR[matchChannel] = pulsePeriod;  in CTIMER_SetupPwm()
284                                uint32_t pulsePeriod,  in CTIMER_SetupPwmPeriod()  argument
289     assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU)));  in CTIMER_SetupPwmPeriod()
324     base->MR[matchChannel] = pulsePeriod;  in CTIMER_SetupPwmPeriod()
352     uint32_t pulsePeriod = 0, period;  in CTIMER_UpdatePwmDutycycle()  local
360         pulsePeriod = period + 1U;  in CTIMER_UpdatePwmDutycycle()
364         pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U;  in CTIMER_UpdatePwmDutycycle()
368     base->MR[matchChannel] = pulsePeriod;  in CTIMER_UpdatePwmDutycycle()