61     uint32_t regData = 0U;  in AFE_Init()  local
67 …regData = base->CKR & ~(AFE_CKR_CLS_MASK | AFE_CKR_DIV_MASK); /* Clear old clock select, divider v…  in AFE_Init()
68     regData |= AFE_CKR_CLS(config->clockSource) | AFE_CKR_DIV(config->clockDivider);  in AFE_Init()
69     base->CKR = regData;  in AFE_Init()
72 …regData = base->CR & ~(AFE_CR_STRTUP_CNT_MASK | AFE_CR_RESULT_FORMAT_MASK | AFE_CR_RST_B_MASK | AF…  in AFE_Init()
74 …regData |= AFE_CR_STRTUP_CNT((uint8_t)config->startupCount) | AFE_CR_RESULT_FORMAT(config->resultF…  in AFE_Init()
77     base->CR = regData;  in AFE_Init()
144     uint32_t regData = 0U;  in AFE_SetChannelConfig()  local
146     regData = base->CFR[channel];  in AFE_SetChannelConfig()
148     regData |= AFE_CFR_DEC_EN_MASK;  in AFE_SetChannelConfig()
152         regData &= ~(AFE_CFR_DEC_CLK_EDGE_SEL_MASK | AFE_CFR_DEC_CLK_INP_SEL_MASK);  in AFE_SetChannelConfig()
153 …regData |= (AFE_CFR_BYP_MODE_MASK | AFE_CFR_DEC_CLK_EDGE_SEL((((uint32_t)config->channelMode) >> 1…  in AFE_SetChannelConfig()
158         regData |= AFE_CFR_SD_MOD_EN_MASK;  in AFE_SetChannelConfig()
161             regData &= ~AFE_CFR_PGA_EN_MASK; /* PGA is disabled. */  in AFE_SetChannelConfig()
166             regData &= ~AFE_CFR_PGA_GAIN_SEL_MASK;  in AFE_SetChannelConfig()
167             regData |= (AFE_CFR_PGA_EN_MASK | AFE_CFR_PGA_GAIN_SEL(config->pgaGainSelect));  in AFE_SetChannelConfig()
171     regData &= ~(AFE_CFR_DEC_OSR_MASK | AFE_CFR_HW_TRG_MASK | AFE_CFR_CC_MASK);  in AFE_SetChannelConfig()
173     regData |= AFE_CFR_DEC_OSR((uint32_t)config->decimatorOversampleRatio) |  in AFE_SetChannelConfig()
176     base->CFR[channel] = regData;  in AFE_SetChannelConfig()
261     uint32_t regData = mask & ((uint32_t)kAFE_Channel0DMAEnable | (uint32_t)kAFE_Channel1DMAEnable |  in AFE_EnableChannelDMA()  local
266         base->DI |= regData;  in AFE_EnableChannelDMA()
270         base->DI &= ~regData;  in AFE_EnableChannelDMA()