147 #define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~…  argument
328 #define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))  argument
476 #define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))  argument
665 #define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))  argument
712 #define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))  argument
754 #define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))  argument
931 #define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))  argument
1090 #define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))  argument
1142 #define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))  argument
1192 #define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))  argument
1248 #define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))  argument
1290 #define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))  argument
1332 #define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))  argument
1374 #define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))  argument
1416 #define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))  argument
1458 #define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))  argument
1500 #define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))  argument
1558 #define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))  argument
1600 #define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))  argument
1642 #define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))  argument
1684 #define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))  argument
1726 #define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))  argument
1768 #define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))  argument
1810 #define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))  argument
1928 #define BLE_RF_REGS_RMW_BLE_AFC(base, mask, value) (BLE_RF_REGS_WR_BLE_AFC(base, (BLE_RF_REGS_RD_BL…  argument
1987 #define BLE_RF_REGS_RMW_BLE_BSM(base, mask, value) (BLE_RF_REGS_WR_BLE_BSM(base, (BLE_RF_REGS_RD_BL…  argument
2050 #define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))  argument
2126 #define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))  argument
2324 #define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))  argument
2345 #define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))  argument
2483 #define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (valu…  argument
2561 #define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (valu…  argument
2689 #define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))  argument
2713 #define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))  argument
2737 #define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))  argument
2761 #define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))  argument
2784 #define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))  argument
2873 #define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))  argument
3052 #define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))  argument
3076 #define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))  argument
3100 #define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))  argument
3124 #define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))  argument
3147 #define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))  argument
3208 #define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))  argument
3269 #define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) …  argument
3290 #define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) …  argument
3338 #define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))  argument
3399 #define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))  argument
3550 #define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))  argument
3631 #define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))  argument
3705 #define DCDC_RMW_REG0(base, mask, value) (DCDC_WR_REG0(base, (DCDC_RD_REG0(base) & ~(mask)) | (valu…  argument
4015 #define DCDC_RMW_REG1(base, mask, value) (DCDC_WR_REG1(base, (DCDC_RD_REG1(base) & ~(mask)) | (valu…  argument
4138 #define DCDC_RMW_REG2(base, mask, value) (DCDC_WR_REG2(base, (DCDC_RD_REG2(base) & ~(mask)) | (valu…  argument
4266 #define DCDC_RMW_REG3(base, mask, value) (DCDC_WR_REG3(base, (DCDC_RD_REG3(base) & ~(mask)) | (valu…  argument
4496 #define DCDC_RMW_REG4(base, mask, value) (DCDC_WR_REG4(base, (DCDC_RD_REG4(base) & ~(mask)) | (valu…  argument
4553 #define DCDC_RMW_REG6(base, mask, value) (DCDC_WR_REG6(base, (DCDC_RD_REG6(base) & ~(mask)) | (valu…  argument
4649 #define DCDC_RMW_REG7(base, mask, value) (DCDC_WR_REG7(base, (DCDC_RD_REG7(base) & ~(mask)) | (valu…  argument
4747 #define DMA_RMW_SAR(base, index, mask, value) (DMA_WR_SAR(base, index, (DMA_RD_SAR(base, index) & ~…  argument
4775 #define DMA_RMW_DAR(base, index, mask, value) (DMA_WR_DAR(base, index, (DMA_RD_DAR(base, index) & ~…  argument
4808 #define DMA_RMW_DSR_BCR(base, index, mask, value) (DMA_WR_DSR_BCR(base, index, (DMA_RD_DSR_BCR(base…  argument
4960 #define DMA_RMW_DSR(base, index, mask, value) (DMA_WR_DSR(base, index, (DMA_RD_DSR(base, index) & ~…  argument
4981 #define DMA_RMW_DCR(base, index, mask, value) (DMA_WR_DCR(base, index, (DMA_RD_DCR(base, index) & ~…  argument
5418 #define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(b…  argument
5525 #define FGPIO_RMW_PDOR(base, mask, value) (FGPIO_WR_PDOR(base, (FGPIO_RD_PDOR(base) & ~(mask)) | (v…  argument
5548 #define FGPIO_RMW_PSOR(base, mask, value) (FGPIO_WR_PSOR(base, (FGPIO_RD_PSOR(base) & ~(mask)) | (v…  argument
5568 #define FGPIO_RMW_PCOR(base, mask, value) (FGPIO_WR_PCOR(base, (FGPIO_RD_PCOR(base) & ~(mask)) | (v…  argument
5586 #define FGPIO_RMW_PTOR(base, mask, value) (FGPIO_WR_PTOR(base, (FGPIO_RD_PTOR(base) & ~(mask)) | (v…  argument
5622 #define FGPIO_RMW_PDDR(base, mask, value) (FGPIO_WR_PDDR(base, (FGPIO_RD_PDDR(base) & ~(mask)) | (v…  argument
5699 #define FTFA_RMW_FSTAT(base, mask, value) (FTFA_WR_FSTAT(base, (FTFA_RD_FSTAT(base) & ~(mask)) | (v…  argument
5838 #define FTFA_RMW_FCNFG(base, mask, value) (FTFA_WR_FCNFG(base, (FTFA_RD_FCNFG(base) & ~(mask)) | (v…  argument
6082 #define FTFA_RMW_FCCOB3(base, mask, value) (FTFA_WR_FCCOB3(base, (FTFA_RD_FCCOB3(base) & ~(mask)) |…  argument
6107 #define FTFA_RMW_FCCOB2(base, mask, value) (FTFA_WR_FCCOB2(base, (FTFA_RD_FCCOB2(base) & ~(mask)) |…  argument
6132 #define FTFA_RMW_FCCOB1(base, mask, value) (FTFA_WR_FCCOB1(base, (FTFA_RD_FCCOB1(base) & ~(mask)) |…  argument
6157 #define FTFA_RMW_FCCOB0(base, mask, value) (FTFA_WR_FCCOB0(base, (FTFA_RD_FCCOB0(base) & ~(mask)) |…  argument
6182 #define FTFA_RMW_FCCOB7(base, mask, value) (FTFA_WR_FCCOB7(base, (FTFA_RD_FCCOB7(base) & ~(mask)) |…  argument
6207 #define FTFA_RMW_FCCOB6(base, mask, value) (FTFA_WR_FCCOB6(base, (FTFA_RD_FCCOB6(base) & ~(mask)) |…  argument
6232 #define FTFA_RMW_FCCOB5(base, mask, value) (FTFA_WR_FCCOB5(base, (FTFA_RD_FCCOB5(base) & ~(mask)) |…  argument
6257 #define FTFA_RMW_FCCOB4(base, mask, value) (FTFA_WR_FCCOB4(base, (FTFA_RD_FCCOB4(base) & ~(mask)) |…  argument
6282 #define FTFA_RMW_FCCOBB(base, mask, value) (FTFA_WR_FCCOBB(base, (FTFA_RD_FCCOBB(base) & ~(mask)) |…  argument
6307 #define FTFA_RMW_FCCOBA(base, mask, value) (FTFA_WR_FCCOBA(base, (FTFA_RD_FCCOBA(base) & ~(mask)) |…  argument
6332 #define FTFA_RMW_FCCOB9(base, mask, value) (FTFA_WR_FCCOB9(base, (FTFA_RD_FCCOB9(base) & ~(mask)) |…  argument
6357 #define FTFA_RMW_FCCOB8(base, mask, value) (FTFA_WR_FCCOB8(base, (FTFA_RD_FCCOB8(base) & ~(mask)) |…  argument
6402 #define FTFA_RMW_FPROT3(base, mask, value) (FTFA_WR_FPROT3(base, (FTFA_RD_FPROT3(base) & ~(mask)) |…  argument
6447 #define FTFA_RMW_FPROT2(base, mask, value) (FTFA_WR_FPROT2(base, (FTFA_RD_FPROT2(base) & ~(mask)) |…  argument
6492 #define FTFA_RMW_FPROT1(base, mask, value) (FTFA_WR_FPROT1(base, (FTFA_RD_FPROT1(base) & ~(mask)) |…  argument
6537 #define FTFA_RMW_FPROT0(base, mask, value) (FTFA_WR_FPROT0(base, (FTFA_RD_FPROT0(base) & ~(mask)) |…  argument
7088 #define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (valu…  argument
7111 #define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (valu…  argument
7131 #define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (valu…  argument
7149 #define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (valu…  argument
7189 #define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (valu…  argument
7237 #define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))  argument
7279 #define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))  argument
7359 #define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))  argument
7551 #define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))  argument
7747 #define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))  argument
7768 #define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))  argument
7913 #define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))  argument
8068 #define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))  argument
8119 #define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))  argument
8302 #define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))  argument
8343 #define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))  argument
8364 #define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))  argument
8385 #define I2C_RMW_S2(base, mask, value) (I2C_WR_S2(base, (I2C_RD_S2(base) & ~(mask)) | (value)))  argument
8477 #define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))  argument
8594 #define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))  argument
8711 #define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))  argument
8828 #define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))  argument
8945 #define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))  argument
9134 #define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))  argument
9331 #define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))  argument
9694 #define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (v…  argument
9788 #define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (v…  argument
9889 #define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (valu…  argument
10061 #define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (valu…  argument
10183 #define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (valu…  argument
10227 #define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (valu…  argument
10282 #define LPUART_RMW_BAUD(base, mask, value) (LPUART_WR_BAUD(base, (LPUART_RD_BAUD(base) & ~(mask)) |…  argument
10568 #define LPUART_RMW_STAT(base, mask, value) (LPUART_WR_STAT(base, (LPUART_RD_STAT(base) & ~(mask)) |…  argument
11011 #define LPUART_RMW_CTRL(base, mask, value) (LPUART_WR_CTRL(base, (LPUART_RD_CTRL(base) & ~(mask)) |…  argument
11603 #define LPUART_RMW_DATA(base, mask, value) (LPUART_WR_DATA(base, (LPUART_RD_DATA(base) & ~(mask)) |…  argument
11868 #define LPUART_RMW_MATCH(base, mask, value) (LPUART_WR_MATCH(base, (LPUART_RD_MATCH(base) & ~(mask)…  argument
11933 #define LPUART_RMW_MODIR(base, mask, value) (LPUART_WR_MODIR(base, (LPUART_RD_MODIR(base) & ~(mask)…  argument
12158 #define LTC_RMW_MD(base, mask, value) (LTC_WR_MD(base, (LTC_RD_MD(base) & ~(mask)) | (value)))  argument
12302 #define LTC_RMW_KS(base, mask, value) (LTC_WR_KS(base, (LTC_RD_KS(base) & ~(mask)) | (value)))  argument
12334 #define LTC_RMW_DS(base, mask, value) (LTC_WR_DS(base, (LTC_RD_DS(base) & ~(mask)) | (value)))  argument
12382 #define LTC_RMW_ICVS(base, mask, value) (LTC_WR_ICVS(base, (LTC_RD_ICVS(base) & ~(mask)) | (value)))  argument
12482 #define LTC_RMW_CTL(base, mask, value) (LTC_WR_CTL(base, (LTC_RD_CTL(base) & ~(mask)) | (value)))  argument
12876 #define LTC_RMW_STA(base, mask, value) (LTC_WR_STA(base, (LTC_RD_STA(base) & ~(mask)) | (value)))  argument
13038 #define LTC_RMW_AADSZ(base, mask, value) (LTC_WR_AADSZ(base, (LTC_RD_AADSZ(base) & ~(mask)) | (valu…  argument
13102 #define LTC_RMW_CTX(base, index, mask, value) (LTC_WR_CTX(base, index, (LTC_RD_CTX(base, index) & ~…  argument
13131 #define LTC_RMW_KEY(base, index, mask, value) (LTC_WR_KEY(base, index, (LTC_RD_KEY(base, index) & ~…  argument
13384 #define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))  argument
13531 #define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))  argument
13703 #define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))  argument
13726 #define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))  argument
13864 #define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))  argument
14005 #define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))  argument
14167 #define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (valu…  argument
14188 #define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (valu…  argument
14209 #define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))  argument
14253 #define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))  argument
14451 #define MCM_RMW_PLACR(base, mask, value) (MCM_WR_PLACR(base, (MCM_RD_PLACR(base) & ~(mask)) | (valu…  argument
14629 #define MCM_RMW_CPO(base, mask, value) (MCM_WR_CPO(base, (MCM_RD_CPO(base) & ~(mask)) | (value)))  argument
14755 #define MTB_RMW_POSITION(base, mask, value) (MTB_WR_POSITION(base, (MTB_RD_POSITION(base) & ~(mask)…  argument
14837 #define MTB_RMW_MASTER(base, mask, value) (MTB_WR_MASTER(base, (MTB_RD_MASTER(base) & ~(mask)) | (v…  argument
15012 #define MTB_RMW_FLOW(base, mask, value) (MTB_WR_FLOW(base, (MTB_RD_FLOW(base) & ~(mask)) | (value)))  argument
15463 #define MTBDWT_RMW_COMP(base, index, mask, value) (MTBDWT_WR_COMP(base, index, (MTBDWT_RD_COMP(base…  argument
15488 #define MTBDWT_RMW_MASK(base, index, mask, value) (MTBDWT_WR_MASK(base, index, (MTBDWT_RD_MASK(base…  argument
15540 #define MTBDWT_RMW_FCT(base, index, mask, value) (MTBDWT_WR_FCT(base, index, (MTBDWT_RD_FCT(base, i…  argument
15678 #define MTBDWT_RMW_TBCTRL(base, mask, value) (MTBDWT_WR_TBCTRL(base, (MTBDWT_RD_TBCTRL(base) & ~(ma…  argument
16239 #define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))  argument
16349 #define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, inde…  argument
16391 #define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, inde…  argument
16479 #define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) …  argument
16551 #define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (v…  argument
16672 #define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (v…  argument
16776 #define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (valu…  argument
16908 #define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) …  argument
17136 #define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (v…  argument
17190 #define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (v…  argument
17247 #define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (valu…  argument
17510 #define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))  argument
17580 #define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))  argument
17926 #define RSIM_RMW_CONTROL(base, mask, value) (RSIM_WR_CONTROL(base, (RSIM_RD_CONTROL(base) & ~(mask)…  argument
18298 #define RSIM_RMW_ACTIVE_DELAY(base, mask, value) (RSIM_WR_ACTIVE_DELAY(base, (RSIM_RD_ACTIVE_DELAY(…  argument
18422 #define RSIM_RMW_ANA_TEST(base, mask, value) (RSIM_WR_ANA_TEST(base, (RSIM_RD_ANA_TEST(base) & ~(ma…  argument
18499 #define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))  argument
18520 #define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))  argument
18564 #define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))  argument
18585 #define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))  argument
18681 #define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))  argument
18908 #define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))  argument
19004 #define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))  argument
19106 #define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))  argument
19255 #define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (valu…  argument
19329 #define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (valu…  argument
19421 #define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (valu…  argument
19549 #define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (valu…  argument
19631 #define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (valu…  argument
19874 #define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (valu…  argument
19983 #define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (valu…  argument
20229 #define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (valu…  argument
20484 #define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (valu…  argument
20531 #define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) |…  argument
20621 #define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (valu…  argument
20830 #define SIM_RMW_COPC(base, mask, value) (SIM_WR_COPC(base, (SIM_RD_COPC(base) & ~(mask)) | (value)))  argument
21039 #define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (v…  argument
21131 #define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (v…  argument
21236 #define SMC_RMW_STOPCTRL(base, mask, value) (SMC_WR_STOPCTRL(base, (SMC_RD_STOPCTRL(base) & ~(mask)…  argument
21388 #define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))  argument
21713 #define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))  argument
21760 #define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_S…  argument
21858 #define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) …  argument
22184 #define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))  argument
22415 #define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))  argument
22607 #define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (valu…  argument
22762 #define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) …  argument
23118 #define TPM_RMW_SC(base, mask, value) (TPM_WR_SC(base, (TPM_RD_SC(base) & ~(mask)) | (value)))  argument
23281 #define TPM_RMW_CNT(base, mask, value) (TPM_WR_CNT(base, (TPM_RD_CNT(base) & ~(mask)) | (value)))  argument
23330 #define TPM_RMW_MOD(base, mask, value) (TPM_WR_MOD(base, (TPM_RD_MOD(base) & ~(mask)) | (value)))  argument
23385 #define TPM_RMW_CnSC(base, index, mask, value) (TPM_WR_CnSC(base, index, (TPM_RD_CnSC(base, index) …  argument
23547 #define TPM_RMW_CnV(base, index, mask, value) (TPM_WR_CnV(base, index, (TPM_RD_CnV(base, index) & ~…  argument
23599 #define TPM_RMW_STATUS(base, mask, value) (TPM_WR_STATUS(base, (TPM_RD_STATUS(base) & ~(mask)) | (v…  argument
23723 #define TPM_RMW_COMBINE(base, mask, value) (TPM_WR_COMBINE(base, (TPM_RD_COMBINE(base) & ~(mask)) |…  argument
23838 #define TPM_RMW_FILTER(base, mask, value) (TPM_WR_FILTER(base, (TPM_RD_FILTER(base) & ~(mask)) | (v…  argument
23933 #define TPM_RMW_QDCTRL(base, mask, value) (TPM_WR_QDCTRL(base, (TPM_RD_QDCTRL(base) & ~(mask)) | (v…  argument
24035 #define TPM_RMW_CONF(base, mask, value) (TPM_WR_CONF(base, (TPM_RD_CONF(base) & ~(mask)) | (value)))  argument
24280 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (valu…  argument
24528 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) |…  argument
24595 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) |…  argument
24646 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) |…  argument
24744 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (v…  argument
24811 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (v…  argument
24906 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) |…  argument
24956 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) |…  argument
25091 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu…  argument
25163 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v…  argument
25289 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (v…  argument
25468 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (v…  argument
25594 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (v…  argument
25667 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (v…  argument
25793 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) |…  argument
26587 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)…  argument
26680 #define TRNG_RMW_INT_CTRL(base, mask, value) (TRNG_WR_INT_CTRL(base, (TRNG_RD_INT_CTRL(base) & ~(ma…  argument
26786 #define TRNG_RMW_INT_MASK(base, mask, value) (TRNG_WR_INT_MASK(base, (TRNG_RD_INT_MASK(base) & ~(ma…  argument
26881 #define TRNG_RMW_INT_STATUS(base, mask, value) (TRNG_WR_INT_STATUS(base, (TRNG_RD_INT_STATUS(base) …  argument
27122 #define TSI_RMW_GENCS(base, mask, value) (TSI_WR_GENCS(base, (TSI_RD_GENCS(base) & ~(mask)) | (valu…  argument
27499 #define TSI_RMW_DATA(base, mask, value) (TSI_WR_DATA(base, (TSI_RD_DATA(base) & ~(mask)) | (value)))  argument
27612 #define TSI_RMW_TSHD(base, mask, value) (TSI_WR_TSHD(base, (TSI_RD_TSHD(base) & ~(mask)) | (value)))  argument
27842 #define XCVR_RMW_RX_DIG_CTRL(base, mask, value) (XCVR_WR_RX_DIG_CTRL(base, (XCVR_RD_RX_DIG_CTRL(bas…  argument
28070 #define XCVR_RMW_AGC_CTRL_0(base, mask, value) (XCVR_WR_AGC_CTRL_0(base, (XCVR_RD_AGC_CTRL_0(base) …  argument
28258 #define XCVR_RMW_AGC_CTRL_1(base, mask, value) (XCVR_WR_AGC_CTRL_1(base, (XCVR_RD_AGC_CTRL_1(base) …  argument
28409 #define XCVR_RMW_AGC_CTRL_2(base, mask, value) (XCVR_WR_AGC_CTRL_2(base, (XCVR_RD_AGC_CTRL_2(base) …  argument
28594 #define XCVR_RMW_AGC_CTRL_3(base, mask, value) (XCVR_WR_AGC_CTRL_3(base, (XCVR_RD_AGC_CTRL_3(base) …  argument
28795 #define XCVR_RMW_RSSI_CTRL_0(base, mask, value) (XCVR_WR_RSSI_CTRL_0(base, (XCVR_RD_RSSI_CTRL_0(bas…  argument
28938 #define XCVR_RMW_RSSI_CTRL_1(base, mask, value) (XCVR_WR_RSSI_CTRL_1(base, (XCVR_RD_RSSI_CTRL_1(bas…  argument
29034 #define XCVR_RMW_DCOC_CTRL_0(base, mask, value) (XCVR_WR_DCOC_CTRL_0(base, (XCVR_RD_DCOC_CTRL_0(bas…  argument
29224 #define XCVR_RMW_DCOC_CTRL_1(base, mask, value) (XCVR_WR_DCOC_CTRL_1(base, (XCVR_RD_DCOC_CTRL_1(bas…  argument
29328 #define XCVR_RMW_DCOC_CTRL_2(base, mask, value) (XCVR_WR_DCOC_CTRL_2(base, (XCVR_RD_DCOC_CTRL_2(bas…  argument
29371 #define XCVR_RMW_DCOC_CTRL_3(base, mask, value) (XCVR_WR_DCOC_CTRL_3(base, (XCVR_RD_DCOC_CTRL_3(bas…  argument
29456 #define XCVR_RMW_DCOC_CTRL_4(base, mask, value) (XCVR_WR_DCOC_CTRL_4(base, (XCVR_RD_DCOC_CTRL_4(bas…  argument
29513 #define XCVR_RMW_DCOC_CAL_GAIN(base, mask, value) (XCVR_WR_DCOC_CAL_GAIN(base, (XCVR_RD_DCOC_CAL_GA…  argument
29754 #define XCVR_RMW_DCOC_CAL_RCP(base, mask, value) (XCVR_WR_DCOC_CAL_RCP(base, (XCVR_RD_DCOC_CAL_RCP(…  argument
29814 #define XCVR_RMW_IQMC_CTRL(base, mask, value) (XCVR_WR_IQMC_CTRL(base, (XCVR_RD_IQMC_CTRL(base) & ~…  argument
29869 #define XCVR_RMW_IQMC_CAL(base, mask, value) (XCVR_WR_IQMC_CAL(base, (XCVR_RD_IQMC_CAL(base) & ~(ma…  argument
29924 #define XCVR_RMW_TCA_AGC_VAL_3_0(base, mask, value) (XCVR_WR_TCA_AGC_VAL_3_0(base, (XCVR_RD_TCA_AGC…  argument
30009 #define XCVR_RMW_TCA_AGC_VAL_7_4(base, mask, value) (XCVR_WR_TCA_AGC_VAL_7_4(base, (XCVR_RD_TCA_AGC…  argument
30094 #define XCVR_RMW_TCA_AGC_VAL_8(base, mask, value) (XCVR_WR_TCA_AGC_VAL_8(base, (XCVR_RD_TCA_AGC_VAL…  argument
30134 #define XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_7_0(base, (XCVR_…  argument
30279 #define XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_10_8(base, (XCV…  argument
30349 #define XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_2_0(base, (XCVR_RD…  argument
30421 #define XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_5_3(base, (XCVR_RD…  argument
30494 #define XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_8_6(base, (XCVR_RD…  argument
30567 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0(base…  argument
30656 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4(base…  argument
30745 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8(ba…  argument
30818 #define XCVR_RMW_AGC_GAIN_TBL_03_00(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_03_00(base, (XCVR_RD_A…  argument
30963 #define XCVR_RMW_AGC_GAIN_TBL_07_04(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_07_04(base, (XCVR_RD_A…  argument
31108 #define XCVR_RMW_AGC_GAIN_TBL_11_08(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_11_08(base, (XCVR_RD_A…  argument
31253 #define XCVR_RMW_AGC_GAIN_TBL_15_12(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_15_12(base, (XCVR_RD_A…  argument
31398 #define XCVR_RMW_AGC_GAIN_TBL_19_16(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_19_16(base, (XCVR_RD_A…  argument
31543 #define XCVR_RMW_AGC_GAIN_TBL_23_20(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_23_20(base, (XCVR_RD_A…  argument
31688 #define XCVR_RMW_AGC_GAIN_TBL_26_24(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_26_24(base, (XCVR_RD_A…  argument
31803 #define XCVR_RMW_DCOC_OFFSET_(base, index, mask, value) (XCVR_WR_DCOC_OFFSET_(base, index, (XCVR_RD…  argument
31896 #define XCVR_RMW_DCOC_TZA_STEP_(base, index, mask, value) (XCVR_WR_DCOC_TZA_STEP_(base, index, (XCV…  argument
32097 #define XCVR_RMW_DCOC_CAL_IIR(base, mask, value) (XCVR_WR_DCOC_CAL_IIR(base, (XCVR_RD_DCOC_CAL_IIR(…  argument
32232 #define XCVR_RMW_RX_CHF_COEF(base, index, mask, value) (XCVR_WR_RX_CHF_COEF(base, index, (XCVR_RD_R…  argument
32272 #define XCVR_RMW_TX_DIG_CTRL(base, mask, value) (XCVR_WR_TX_DIG_CTRL(base, (XCVR_RD_TX_DIG_CTRL(bas…  argument
32515 #define XCVR_RMW_TX_DATA_PAD_PAT(base, mask, value) (XCVR_WR_TX_DATA_PAD_PAT(base, (XCVR_RD_TX_DATA…  argument
32602 #define XCVR_RMW_TX_GFSK_MOD_CTRL(base, mask, value) (XCVR_WR_TX_GFSK_MOD_CTRL(base, (XCVR_RD_TX_GF…  argument
32737 #define XCVR_RMW_TX_GFSK_COEFF2(base, mask, value) (XCVR_WR_TX_GFSK_COEFF2(base, (XCVR_RD_TX_GFSK_C…  argument
32763 #define XCVR_RMW_TX_GFSK_COEFF1(base, mask, value) (XCVR_WR_TX_GFSK_COEFF1(base, (XCVR_RD_TX_GFSK_C…  argument
32784 #define XCVR_RMW_TX_FSK_MOD_SCALE(base, mask, value) (XCVR_WR_TX_FSK_MOD_SCALE(base, (XCVR_RD_TX_FS…  argument
32855 #define XCVR_RMW_TX_DFT_MOD_PAT(base, mask, value) (XCVR_WR_TX_DFT_MOD_PAT(base, (XCVR_RD_TX_DFT_MO…  argument
32881 #define XCVR_RMW_TX_DFT_TONE_0_1(base, mask, value) (XCVR_WR_TX_DFT_TONE_0_1(base, (XCVR_RD_TX_DFT_…  argument
32949 #define XCVR_RMW_TX_DFT_TONE_2_3(base, mask, value) (XCVR_WR_TX_DFT_TONE_2_3(base, (XCVR_RD_TX_DFT_…  argument
33012 #define XCVR_RMW_PLL_MOD_OVRD(base, mask, value) (XCVR_WR_PLL_MOD_OVRD(base, (XCVR_RD_PLL_MOD_OVRD(…  argument
33134 #define XCVR_RMW_PLL_CHAN_MAP(base, mask, value) (XCVR_WR_PLL_CHAN_MAP(base, (XCVR_RD_PLL_CHAN_MAP(…  argument
33261 #define XCVR_RMW_PLL_LOCK_DETECT(base, mask, value) (XCVR_WR_PLL_LOCK_DETECT(base, (XCVR_RD_PLL_LOC…  argument
33480 #define XCVR_RMW_PLL_HP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_HP_MOD_CTRL(base, (XCVR_RD_PLL_HP_…  argument
33668 #define XCVR_RMW_PLL_HPM_CAL_CTRL(base, mask, value) (XCVR_WR_PLL_HPM_CAL_CTRL(base, (XCVR_RD_PLL_H…  argument
33776 #define XCVR_RMW_PLL_LD_HPM_CAL1(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL1(base, (XCVR_RD_PLL_LD_…  argument
33880 #define XCVR_RMW_PLL_LD_HPM_CAL2(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL2(base, (XCVR_RD_PLL_LD_…  argument
33949 #define XCVR_RMW_PLL_HPM_SDM_FRACTION(base, mask, value) (XCVR_WR_PLL_HPM_SDM_FRACTION(base, (XCVR_…  argument
34007 #define XCVR_RMW_PLL_LP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_LP_MOD_CTRL(base, (XCVR_RD_PLL_LP_…  argument
34222 #define XCVR_RMW_PLL_LP_SDM_CTRL1(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL1(base, (XCVR_RD_PLL_L…  argument
34295 #define XCVR_RMW_PLL_LP_SDM_CTRL2(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL2(base, (XCVR_RD_PLL_L…  argument
34338 #define XCVR_RMW_PLL_LP_SDM_CTRL3(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL3(base, (XCVR_RD_PLL_L…  argument
34450 #define XCVR_RMW_PLL_DELAY_MATCH(base, mask, value) (XCVR_WR_PLL_DELAY_MATCH(base, (XCVR_RD_PLL_DEL…  argument
34526 #define XCVR_RMW_PLL_CTUNE_CTRL(base, mask, value) (XCVR_WR_PLL_CTUNE_CTRL(base, (XCVR_RD_PLL_CTUNE…  argument
34846 #define XCVR_RMW_CTRL(base, mask, value) (XCVR_WR_CTRL(base, (XCVR_RD_CTRL(base) & ~(mask)) | (valu…  argument
35088 #define XCVR_RMW_OVERWRITE_VER(base, mask, value) (XCVR_WR_OVERWRITE_VER(base, (XCVR_RD_OVERWRITE_V…  argument
35135 #define XCVR_RMW_DMA_CTRL(base, mask, value) (XCVR_WR_DMA_CTRL(base, (XCVR_RD_DMA_CTRL(base) & ~(ma…  argument
35265 #define XCVR_RMW_DTEST_CTRL(base, mask, value) (XCVR_WR_DTEST_CTRL(base, (XCVR_RD_DTEST_CTRL(base) …  argument
35489 #define XCVR_RMW_PB_CTRL(base, mask, value) (XCVR_WR_PB_CTRL(base, (XCVR_RD_PB_CTRL(base) & ~(mask)…  argument
35534 #define XCVR_RMW_TSM_CTRL(base, mask, value) (XCVR_WR_TSM_CTRL(base, (XCVR_RD_TSM_CTRL(base) & ~(ma…  argument
35745 #define XCVR_RMW_END_OF_SEQ(base, mask, value) (XCVR_WR_END_OF_SEQ(base, (XCVR_RD_END_OF_SEQ(base) …  argument
35844 #define XCVR_RMW_TSM_OVRD0(base, mask, value) (XCVR_WR_TSM_OVRD0(base, (XCVR_RD_TSM_OVRD0(base) & ~…  argument
36420 #define XCVR_RMW_TSM_OVRD1(base, mask, value) (XCVR_WR_TSM_OVRD1(base, (XCVR_RD_TSM_OVRD1(base) & ~…  argument
36984 #define XCVR_RMW_TSM_OVRD2(base, mask, value) (XCVR_WR_TSM_OVRD2(base, (XCVR_RD_TSM_OVRD2(base) & ~…  argument
37547 #define XCVR_RMW_TSM_OVRD3(base, mask, value) (XCVR_WR_TSM_OVRD3(base, (XCVR_RD_TSM_OVRD3(base) & ~…  argument
37777 #define XCVR_RMW_PA_POWER(base, mask, value) (XCVR_WR_PA_POWER(base, (XCVR_RD_PA_POWER(base) & ~(ma…  argument
37817 #define XCVR_RMW_PA_BIAS_TBL0(base, mask, value) (XCVR_WR_PA_BIAS_TBL0(base, (XCVR_RD_PA_BIAS_TBL0(…  argument
37920 #define XCVR_RMW_PA_BIAS_TBL1(base, mask, value) (XCVR_WR_PA_BIAS_TBL1(base, (XCVR_RD_PA_BIAS_TBL1(…  argument
38021 #define XCVR_RMW_RECYCLE_COUNT(base, mask, value) (XCVR_WR_RECYCLE_COUNT(base, (XCVR_RD_RECYCLE_COU…  argument
38102 #define XCVR_RMW_TSM_TIMING00(base, mask, value) (XCVR_WR_TSM_TIMING00(base, (XCVR_RD_TSM_TIMING00(…  argument
38195 #define XCVR_RMW_TSM_TIMING01(base, mask, value) (XCVR_WR_TSM_TIMING01(base, (XCVR_RD_TSM_TIMING01(…  argument
38288 #define XCVR_RMW_TSM_TIMING02(base, mask, value) (XCVR_WR_TSM_TIMING02(base, (XCVR_RD_TSM_TIMING02(…  argument
38381 #define XCVR_RMW_TSM_TIMING03(base, mask, value) (XCVR_WR_TSM_TIMING03(base, (XCVR_RD_TSM_TIMING03(…  argument
38474 #define XCVR_RMW_TSM_TIMING04(base, mask, value) (XCVR_WR_TSM_TIMING04(base, (XCVR_RD_TSM_TIMING04(…  argument
38535 #define XCVR_RMW_TSM_TIMING05(base, mask, value) (XCVR_WR_TSM_TIMING05(base, (XCVR_RD_TSM_TIMING05(…  argument
38628 #define XCVR_RMW_TSM_TIMING06(base, mask, value) (XCVR_WR_TSM_TIMING06(base, (XCVR_RD_TSM_TIMING06(…  argument
38689 #define XCVR_RMW_TSM_TIMING07(base, mask, value) (XCVR_WR_TSM_TIMING07(base, (XCVR_RD_TSM_TIMING07(…  argument
38786 #define XCVR_RMW_TSM_TIMING08(base, mask, value) (XCVR_WR_TSM_TIMING08(base, (XCVR_RD_TSM_TIMING08(…  argument
38883 #define XCVR_RMW_TSM_TIMING09(base, mask, value) (XCVR_WR_TSM_TIMING09(base, (XCVR_RD_TSM_TIMING09(…  argument
38976 #define XCVR_RMW_TSM_TIMING10(base, mask, value) (XCVR_WR_TSM_TIMING10(base, (XCVR_RD_TSM_TIMING10(…  argument
39037 #define XCVR_RMW_TSM_TIMING11(base, mask, value) (XCVR_WR_TSM_TIMING11(base, (XCVR_RD_TSM_TIMING11(…  argument
39098 #define XCVR_RMW_TSM_TIMING12(base, mask, value) (XCVR_WR_TSM_TIMING12(base, (XCVR_RD_TSM_TIMING12(…  argument
39159 #define XCVR_RMW_TSM_TIMING13(base, mask, value) (XCVR_WR_TSM_TIMING13(base, (XCVR_RD_TSM_TIMING13(…  argument
39252 #define XCVR_RMW_TSM_TIMING14(base, mask, value) (XCVR_WR_TSM_TIMING14(base, (XCVR_RD_TSM_TIMING14(…  argument
39315 #define XCVR_RMW_TSM_TIMING15(base, mask, value) (XCVR_WR_TSM_TIMING15(base, (XCVR_RD_TSM_TIMING15(…  argument
39378 #define XCVR_RMW_TSM_TIMING16(base, mask, value) (XCVR_WR_TSM_TIMING16(base, (XCVR_RD_TSM_TIMING16(…  argument
39475 #define XCVR_RMW_TSM_TIMING17(base, mask, value) (XCVR_WR_TSM_TIMING17(base, (XCVR_RD_TSM_TIMING17(…  argument
39568 #define XCVR_RMW_TSM_TIMING18(base, mask, value) (XCVR_WR_TSM_TIMING18(base, (XCVR_RD_TSM_TIMING18(…  argument
39629 #define XCVR_RMW_TSM_TIMING19(base, mask, value) (XCVR_WR_TSM_TIMING19(base, (XCVR_RD_TSM_TIMING19(…  argument
39690 #define XCVR_RMW_TSM_TIMING20(base, mask, value) (XCVR_WR_TSM_TIMING20(base, (XCVR_RD_TSM_TIMING20(…  argument
39751 #define XCVR_RMW_TSM_TIMING21(base, mask, value) (XCVR_WR_TSM_TIMING21(base, (XCVR_RD_TSM_TIMING21(…  argument
39812 #define XCVR_RMW_TSM_TIMING22(base, mask, value) (XCVR_WR_TSM_TIMING22(base, (XCVR_RD_TSM_TIMING22(…  argument
39873 #define XCVR_RMW_TSM_TIMING23(base, mask, value) (XCVR_WR_TSM_TIMING23(base, (XCVR_RD_TSM_TIMING23(…  argument
39934 #define XCVR_RMW_TSM_TIMING24(base, mask, value) (XCVR_WR_TSM_TIMING24(base, (XCVR_RD_TSM_TIMING24(…  argument
39995 #define XCVR_RMW_TSM_TIMING25(base, mask, value) (XCVR_WR_TSM_TIMING25(base, (XCVR_RD_TSM_TIMING25(…  argument
40056 #define XCVR_RMW_TSM_TIMING26(base, mask, value) (XCVR_WR_TSM_TIMING26(base, (XCVR_RD_TSM_TIMING26(…  argument
40149 #define XCVR_RMW_TSM_TIMING27(base, mask, value) (XCVR_WR_TSM_TIMING27(base, (XCVR_RD_TSM_TIMING27(…  argument
40210 #define XCVR_RMW_TSM_TIMING28(base, mask, value) (XCVR_WR_TSM_TIMING28(base, (XCVR_RD_TSM_TIMING28(…  argument
40271 #define XCVR_RMW_TSM_TIMING29(base, mask, value) (XCVR_WR_TSM_TIMING29(base, (XCVR_RD_TSM_TIMING29(…  argument
40332 #define XCVR_RMW_TSM_TIMING30(base, mask, value) (XCVR_WR_TSM_TIMING30(base, (XCVR_RD_TSM_TIMING30(…  argument
40425 #define XCVR_RMW_TSM_TIMING31(base, mask, value) (XCVR_WR_TSM_TIMING31(base, (XCVR_RD_TSM_TIMING31(…  argument
40486 #define XCVR_RMW_TSM_TIMING32(base, mask, value) (XCVR_WR_TSM_TIMING32(base, (XCVR_RD_TSM_TIMING32(…  argument
40547 #define XCVR_RMW_TSM_TIMING33(base, mask, value) (XCVR_WR_TSM_TIMING33(base, (XCVR_RD_TSM_TIMING33(…  argument
40608 #define XCVR_RMW_TSM_TIMING34(base, mask, value) (XCVR_WR_TSM_TIMING34(base, (XCVR_RD_TSM_TIMING34(…  argument
40701 #define XCVR_RMW_TSM_TIMING35(base, mask, value) (XCVR_WR_TSM_TIMING35(base, (XCVR_RD_TSM_TIMING35(…  argument
40794 #define XCVR_RMW_TSM_TIMING36(base, mask, value) (XCVR_WR_TSM_TIMING36(base, (XCVR_RD_TSM_TIMING36(…  argument
40887 #define XCVR_RMW_TSM_TIMING37(base, mask, value) (XCVR_WR_TSM_TIMING37(base, (XCVR_RD_TSM_TIMING37(…  argument
40980 #define XCVR_RMW_TSM_TIMING38(base, mask, value) (XCVR_WR_TSM_TIMING38(base, (XCVR_RD_TSM_TIMING38(…  argument
41073 #define XCVR_RMW_TSM_TIMING39(base, mask, value) (XCVR_WR_TSM_TIMING39(base, (XCVR_RD_TSM_TIMING39(…  argument
41166 #define XCVR_RMW_TSM_TIMING40(base, mask, value) (XCVR_WR_TSM_TIMING40(base, (XCVR_RD_TSM_TIMING40(…  argument
41259 #define XCVR_RMW_TSM_TIMING41(base, mask, value) (XCVR_WR_TSM_TIMING41(base, (XCVR_RD_TSM_TIMING41(…  argument
41352 #define XCVR_RMW_TSM_TIMING42(base, mask, value) (XCVR_WR_TSM_TIMING42(base, (XCVR_RD_TSM_TIMING42(…  argument
41445 #define XCVR_RMW_TSM_TIMING43(base, mask, value) (XCVR_WR_TSM_TIMING43(base, (XCVR_RD_TSM_TIMING43(…  argument
41534 #define XCVR_RMW_CORR_CTRL(base, mask, value) (XCVR_WR_CORR_CTRL(base, (XCVR_RD_CORR_CTRL(base) & ~…  argument
41631 #define XCVR_RMW_PN_TYPE(base, mask, value) (XCVR_WR_PN_TYPE(base, (XCVR_RD_PN_TYPE(base) & ~(mask)…  argument
41688 #define XCVR_RMW_PN_CODE(base, mask, value) (XCVR_WR_PN_CODE(base, (XCVR_RD_PN_CODE(base) & ~(mask)…  argument
41743 #define XCVR_RMW_SYNC_CTRL(base, mask, value) (XCVR_WR_SYNC_CTRL(base, (XCVR_RD_SYNC_CTRL(base) & ~…  argument
41803 #define XCVR_RMW_SNF_THR(base, mask, value) (XCVR_WR_SNF_THR(base, (XCVR_RD_SNF_THR(base) & ~(mask)…  argument
41845 #define XCVR_RMW_FAD_THR(base, mask, value) (XCVR_WR_FAD_THR(base, (XCVR_RD_FAD_THR(base) & ~(mask)…  argument
41885 #define XCVR_RMW_ZBDEM_AFC(base, mask, value) (XCVR_WR_ZBDEM_AFC(base, (XCVR_RD_ZBDEM_AFC(base) & ~…  argument
41953 #define XCVR_RMW_LPPS_CTRL(base, mask, value) (XCVR_WR_LPPS_CTRL(base, (XCVR_RD_LPPS_CTRL(base) & ~…  argument
42130 #define XCVR_RMW_ADC_CTRL(base, mask, value) (XCVR_WR_ADC_CTRL(base, (XCVR_RD_ADC_CTRL(base) & ~(ma…  argument
42238 #define XCVR_RMW_ADC_TUNE(base, mask, value) (XCVR_WR_ADC_TUNE(base, (XCVR_RD_ADC_TUNE(base) & ~(ma…  argument
42327 #define XCVR_RMW_ADC_ADJ(base, mask, value) (XCVR_WR_ADC_ADJ(base, (XCVR_RD_ADC_ADJ(base) & ~(mask)…  argument
42446 #define XCVR_RMW_ADC_REGS(base, mask, value) (XCVR_WR_ADC_REGS(base, (XCVR_RD_ADC_REGS(base) & ~(ma…  argument
42584 #define XCVR_RMW_ADC_TRIMS(base, mask, value) (XCVR_WR_ADC_TRIMS(base, (XCVR_RD_ADC_TRIMS(base) & ~…  argument
42659 #define XCVR_RMW_ADC_TEST_CTRL(base, mask, value) (XCVR_WR_ADC_TEST_CTRL(base, (XCVR_RD_ADC_TEST_CT…  argument
42779 #define XCVR_RMW_BBF_CTRL(base, mask, value) (XCVR_WR_BBF_CTRL(base, (XCVR_RD_BBF_CTRL(base) & ~(ma…  argument
42940 #define XCVR_RMW_RX_ANA_CTRL(base, mask, value) (XCVR_WR_RX_ANA_CTRL(base, (XCVR_RD_RX_ANA_CTRL(bas…  argument
43020 #define XCVR_RMW_XTAL_CTRL(base, mask, value) (XCVR_WR_XTAL_CTRL(base, (XCVR_RD_XTAL_CTRL(base) & ~…  argument
43190 #define XCVR_RMW_XTAL_CTRL2(base, mask, value) (XCVR_WR_XTAL_CTRL2(base, (XCVR_RD_XTAL_CTRL2(base) …  argument
43394 #define XCVR_RMW_BGAP_CTRL(base, mask, value) (XCVR_WR_BGAP_CTRL(base, (XCVR_RD_BGAP_CTRL(base) & ~…  argument
43482 #define XCVR_RMW_PLL_CTRL(base, mask, value) (XCVR_WR_PLL_CTRL(base, (XCVR_RD_PLL_CTRL(base) & ~(ma…  argument
43626 #define XCVR_RMW_PLL_CTRL2(base, mask, value) (XCVR_WR_PLL_CTRL2(base, (XCVR_RD_PLL_CTRL2(base) & ~…  argument
43719 #define XCVR_RMW_PLL_TEST_CTRL(base, mask, value) (XCVR_WR_PLL_TEST_CTRL(base, (XCVR_RD_PLL_TEST_CT…  argument
43841 #define XCVR_RMW_QGEN_CTRL(base, mask, value) (XCVR_WR_QGEN_CTRL(base, (XCVR_RD_QGEN_CTRL(base) & ~…  argument
43920 #define XCVR_RMW_TCA_CTRL(base, mask, value) (XCVR_WR_TCA_CTRL(base, (XCVR_RD_TCA_CTRL(base) & ~(ma…  argument
44029 #define XCVR_RMW_TZA_CTRL(base, mask, value) (XCVR_WR_TZA_CTRL(base, (XCVR_RD_TZA_CTRL(base) & ~(ma…  argument
44132 #define XCVR_RMW_TX_ANA_CTRL(base, mask, value) (XCVR_WR_TX_ANA_CTRL(base, (XCVR_RD_TX_ANA_CTRL(bas…  argument
44173 #define XCVR_RMW_ANA_SPARE(base, mask, value) (XCVR_WR_ANA_SPARE(base, (XCVR_RD_ANA_SPARE(base) & ~…  argument
44323 #define ZLL_RMW_IRQSTS(base, mask, value) (ZLL_WR_IRQSTS(base, (ZLL_RD_IRQSTS(base) & ~(mask)) | (v…  argument
44721 #define ZLL_RMW_PHY_CTRL(base, mask, value) (ZLL_WR_PHY_CTRL(base, (ZLL_RD_PHY_CTRL(base) & ~(mask)…  argument
45307 #define ZLL_RMW_T1CMP(base, mask, value) (ZLL_WR_T1CMP(base, (ZLL_RD_T1CMP(base) & ~(mask)) | (valu…  argument
45348 #define ZLL_RMW_T2CMP(base, mask, value) (ZLL_WR_T2CMP(base, (ZLL_RD_T2CMP(base) & ~(mask)) | (valu…  argument
45389 #define ZLL_RMW_T2PRIMECMP(base, mask, value) (ZLL_WR_T2PRIMECMP(base, (ZLL_RD_T2PRIMECMP(base) & ~…  argument
45430 #define ZLL_RMW_T3CMP(base, mask, value) (ZLL_WR_T3CMP(base, (ZLL_RD_T3CMP(base) & ~(mask)) | (valu…  argument
45471 #define ZLL_RMW_T4CMP(base, mask, value) (ZLL_WR_T4CMP(base, (ZLL_RD_T4CMP(base) & ~(mask)) | (valu…  argument
45511 #define ZLL_RMW_PA_PWR(base, mask, value) (ZLL_WR_PA_PWR(base, (ZLL_RD_PA_PWR(base) & ~(mask)) | (v…  argument
45553 #define ZLL_RMW_CHANNEL_NUM0(base, mask, value) (ZLL_WR_CHANNEL_NUM0(base, (ZLL_RD_CHANNEL_NUM0(bas…  argument
45646 #define ZLL_RMW_MACSHORTADDRS0(base, mask, value) (ZLL_WR_MACSHORTADDRS0(base, (ZLL_RD_MACSHORTADDR…  argument
45713 #define ZLL_RMW_MACLONGADDRS0_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_LSB(base, (ZLL_RD_MACLON…  argument
45738 #define ZLL_RMW_MACLONGADDRS0_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_MSB(base, (ZLL_RD_MACLON…  argument
45759 #define ZLL_RMW_RX_FRAME_FILTER(base, mask, value) (ZLL_WR_RX_FRAME_FILTER(base, (ZLL_RD_RX_FRAME_F…  argument
45913 #define ZLL_RMW_CCA_LQI_CTRL(base, mask, value) (ZLL_WR_CCA_LQI_CTRL(base, (ZLL_RD_CCA_LQI_CTRL(bas…  argument
45989 #define ZLL_RMW_CCA2_CTRL(base, mask, value) (ZLL_WR_CCA2_CTRL(base, (ZLL_RD_CCA2_CTRL(base) & ~(ma…  argument
46066 #define ZLL_RMW_FAD_CTRL(base, mask, value) (ZLL_WR_FAD_CTRL(base, (ZLL_RD_FAD_CTRL(base) & ~(mask)…  argument
46232 #define ZLL_RMW_SNF_CTRL(base, mask, value) (ZLL_WR_SNF_CTRL(base, (ZLL_RD_SNF_CTRL(base) & ~(mask)…  argument
46275 #define ZLL_RMW_BSM_CTRL(base, mask, value) (ZLL_WR_BSM_CTRL(base, (ZLL_RD_BSM_CTRL(base) & ~(mask)…  argument
46317 #define ZLL_RMW_MACSHORTADDRS1(base, mask, value) (ZLL_WR_MACSHORTADDRS1(base, (ZLL_RD_MACSHORTADDR…  argument
46384 #define ZLL_RMW_MACLONGADDRS1_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_LSB(base, (ZLL_RD_MACLON…  argument
46409 #define ZLL_RMW_MACLONGADDRS1_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_MSB(base, (ZLL_RD_MACLON…  argument
46430 #define ZLL_RMW_DUAL_PAN_CTRL(base, mask, value) (ZLL_WR_DUAL_PAN_CTRL(base, (ZLL_RD_DUAL_PAN_CTRL(…  argument
46666 #define ZLL_RMW_CHANNEL_NUM1(base, mask, value) (ZLL_WR_CHANNEL_NUM1(base, (ZLL_RD_CHANNEL_NUM1(bas…  argument
46706 #define ZLL_RMW_SAM_CTRL(base, mask, value) (ZLL_WR_SAM_CTRL(base, (ZLL_RD_SAM_CTRL(base) & ~(mask)…  argument
46840 #define ZLL_RMW_SAM_TABLE(base, mask, value) (ZLL_WR_SAM_TABLE(base, (ZLL_RD_SAM_TABLE(base) & ~(ma…  argument
47169 #define ZLL_RMW_SEQ_CTRL_STS(base, mask, value) (ZLL_WR_SEQ_CTRL_STS(base, (ZLL_RD_SEQ_CTRL_STS(bas…  argument
47461 #define ZLL_RMW_ACKDELAY(base, mask, value) (ZLL_WR_ACKDELAY(base, (ZLL_RD_ACKDELAY(base) & ~(mask)…  argument
47527 #define ZLL_RMW_FILTERFAIL_CODE(base, mask, value) (ZLL_WR_FILTERFAIL_CODE(base, (ZLL_RD_FILTERFAIL…  argument
47598 #define ZLL_RMW_RX_WTR_MARK(base, mask, value) (ZLL_WR_RX_WTR_MARK(base, (ZLL_RD_RX_WTR_MARK(base) …  argument
47645 #define ZLL_RMW_SLOT_PRELOAD(base, mask, value) (ZLL_WR_SLOT_PRELOAD(base, (ZLL_RD_SLOT_PRELOAD(bas…  argument
47853 #define ZLL_RMW_TMR_PRESCALE(base, mask, value) (ZLL_WR_TMR_PRESCALE(base, (ZLL_RD_TMR_PRESCALE(bas…  argument
47918 #define ZLL_RMW_LENIENCY_LSB(base, mask, value) (ZLL_WR_LENIENCY_LSB(base, (ZLL_RD_LENIENCY_LSB(bas…  argument
47953 #define ZLL_RMW_LENIENCY_MSB(base, mask, value) (ZLL_WR_LENIENCY_MSB(base, (ZLL_RD_LENIENCY_MSB(bas…  argument
48041 #define ZLL_RMW_PKT_BUFFER(base, index, mask, value) (ZLL_WR_PKT_BUFFER(base, index, (ZLL_RD_PKT_BU…  argument