145 #define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))  argument
146 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))  argument
147 #define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~…  argument
148 #define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))  argument
149 #define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value))))  argument
150 #define ADC_TOG_SC1(base, index, value) (BME_XOR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))  argument
238 #define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADC…  argument
239 #define ADC_BRD_SC1_ADCH(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_ADCH_SHIFT, AD…  argument
242 #define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_AD…  argument
243 #define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
259 #define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIF…  argument
260 #define ADC_BRD_SC1_DIFF(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT, AD…  argument
263 #define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DI…  argument
264 #define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
279 #define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIE…  argument
280 #define ADC_BRD_SC1_AIEN(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT, AD…  argument
283 #define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AI…  argument
284 #define ADC_BWR_SC1_AIEN(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
306 #define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COC…  argument
307 #define ADC_BRD_SC1_COCO(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT, AD…  argument
625 #define ADC_RD_R(base, index)    (ADC_R_REG(base, index))  argument
637 #define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)  argument
638 #define ADC_BRD_R_D(base, index) (BME_UBFX32(&ADC_R_REG(base, index), ADC_R_D_SHIFT, ADC_R_D_WIDTH))  argument
3267 #define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))  argument
3268 #define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))  argument
3269 #define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) …  argument
3270 #define DAC_SET_DATL(base, index, value) (BME_OR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))  argument
3271 #define DAC_CLR_DATL(base, index, value) (BME_AND8(&DAC_DATL_REG(base, index), (uint8_t)(~(value))))  argument
3272 #define DAC_TOG_DATL(base, index, value) (BME_XOR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))  argument
3288 #define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))  argument
3289 #define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))  argument
3290 #define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) …  argument
3291 #define DAC_SET_DATH(base, index, value) (BME_OR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))  argument
3292 #define DAC_CLR_DATH(base, index, value) (BME_AND8(&DAC_DATH_REG(base, index), (uint8_t)(~(value))))  argument
3293 #define DAC_TOG_DATH(base, index, value) (BME_XOR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))  argument
3309 #define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DA…  argument
3310 #define DAC_BRD_DATH_DATA1(base, index) (BME_UBFX8(&DAC_DATH_REG(base, index), DAC_DATH_DATA1_SHIFT…  argument
3313 #define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_D…  argument
3314 #define DAC_BWR_DATH_DATA1(base, index, value) (BME_BFI8(&DAC_DATH_REG(base, index), ((uint8_t)(val…  argument
4745 #define DMA_RD_SAR(base, index)  (DMA_SAR_REG(base, index))  argument
4746 #define DMA_WR_SAR(base, index, value) (DMA_SAR_REG(base, index) = (value))  argument
4747 #define DMA_RMW_SAR(base, index, mask, value) (DMA_WR_SAR(base, index, (DMA_RD_SAR(base, index) & ~…  argument
4748 #define DMA_SET_SAR(base, index, value) (BME_OR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))  argument
4749 #define DMA_CLR_SAR(base, index, value) (BME_AND32(&DMA_SAR_REG(base, index), (uint32_t)(~(value))))  argument
4750 #define DMA_TOG_SAR(base, index, value) (BME_XOR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))  argument
4773 #define DMA_RD_DAR(base, index)  (DMA_DAR_REG(base, index))  argument
4774 #define DMA_WR_DAR(base, index, value) (DMA_DAR_REG(base, index) = (value))  argument
4775 #define DMA_RMW_DAR(base, index, mask, value) (DMA_WR_DAR(base, index, (DMA_RD_DAR(base, index) & ~…  argument
4776 #define DMA_SET_DAR(base, index, value) (BME_OR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))  argument
4777 #define DMA_CLR_DAR(base, index, value) (BME_AND32(&DMA_DAR_REG(base, index), (uint32_t)(~(value))))  argument
4778 #define DMA_TOG_DAR(base, index, value) (BME_XOR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))  argument
4806 #define DMA_RD_DSR_BCR(base, index) (DMA_DSR_BCR_REG(base, index))  argument
4807 #define DMA_WR_DSR_BCR(base, index, value) (DMA_DSR_BCR_REG(base, index) = (value))  argument
4808 #define DMA_RMW_DSR_BCR(base, index, mask, value) (DMA_WR_DSR_BCR(base, index, (DMA_RD_DSR_BCR(base…  argument
4809 #define DMA_SET_DSR_BCR(base, index, value) (BME_OR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(val…  argument
4810 #define DMA_CLR_DSR_BCR(base, index, value) (BME_AND32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(~(…  argument
4811 #define DMA_TOG_DSR_BCR(base, index, value) (BME_XOR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(va…  argument
4830 #define DMA_RD_DSR_BCR_BCR(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BCR_MASK) >> D…  argument
4831 #define DMA_BRD_DSR_BCR_BCR(base, index) (DMA_RD_DSR_BCR_BCR(base, index))  argument
4834 #define DMA_WR_DSR_BCR_BCR(base, index, value) (DMA_RMW_DSR_BCR(base, index, (DMA_DSR_BCR_BCR_MASK …  argument
4835 #define DMA_BWR_DSR_BCR_BCR(base, index, value) (DMA_WR_DSR_BCR_BCR(base, index, value))  argument
4855 #define DMA_RD_DSR_BCR_DONE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_DONE_MASK) >>…  argument
4856 #define DMA_BRD_DSR_BCR_DONE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_DO…  argument
4859 #define DMA_WR_DSR_BCR_DONE(base, index, value) (DMA_RMW_DSR_BCR(base, index, DMA_DSR_BCR_DONE_MASK…  argument
4860 #define DMA_BWR_DSR_BCR_DONE(base, index, value) (BME_BFI32(&DMA_DSR_BCR_REG(base, index), ((uint32…  argument
4874 #define DMA_RD_DSR_BCR_BSY(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BSY_MASK) >> D…  argument
4875 #define DMA_BRD_DSR_BCR_BSY(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BSY…  argument
4889 #define DMA_RD_DSR_BCR_REQ(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_REQ_MASK) >> D…  argument
4890 #define DMA_BRD_DSR_BCR_REQ(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_REQ…  argument
4905 #define DMA_RD_DSR_BCR_BED(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BED_MASK) >> D…  argument
4906 #define DMA_BRD_DSR_BCR_BED(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BED…  argument
4921 #define DMA_RD_DSR_BCR_BES(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BES_MASK) >> D…  argument
4922 #define DMA_BRD_DSR_BCR_BES(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BES…  argument
4941 #define DMA_RD_DSR_BCR_CE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_CE_MASK) >> DMA…  argument
4942 #define DMA_BRD_DSR_BCR_CE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_CE_S…  argument
4958 #define DMA_RD_DSR(base, index)  (DMA_DSR_REG(base, index))  argument
4959 #define DMA_WR_DSR(base, index, value) (DMA_DSR_REG(base, index) = (value))  argument
4960 #define DMA_RMW_DSR(base, index, mask, value) (DMA_WR_DSR(base, index, (DMA_RD_DSR(base, index) & ~…  argument
4961 #define DMA_SET_DSR(base, index, value) (BME_OR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))  argument
4962 #define DMA_CLR_DSR(base, index, value) (BME_AND8(&DMA_DSR_REG(base, index), (uint8_t)(~(value))))  argument
4963 #define DMA_TOG_DSR(base, index, value) (BME_XOR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))  argument
4979 #define DMA_RD_DCR(base, index)  (DMA_DCR_REG(base, index))  argument
4980 #define DMA_WR_DCR(base, index, value) (DMA_DCR_REG(base, index) = (value))  argument
4981 #define DMA_RMW_DCR(base, index, mask, value) (DMA_WR_DCR(base, index, (DMA_RD_DCR(base, index) & ~…  argument
4982 #define DMA_SET_DCR(base, index, value) (BME_OR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))  argument
4983 #define DMA_CLR_DCR(base, index, value) (BME_AND32(&DMA_DCR_REG(base, index), (uint32_t)(~(value))))  argument
4984 #define DMA_TOG_DCR(base, index, value) (BME_XOR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))  argument
5005 #define DMA_RD_DCR_LCH2(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH2_MASK) >> DMA_DCR_LCH…  argument
5006 #define DMA_BRD_DCR_LCH2(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH2_SHIFT, DM…  argument
5009 #define DMA_WR_DCR_LCH2(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH2_MASK, DMA_DCR_LC…  argument
5010 #define DMA_BWR_DCR_LCH2(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5027 #define DMA_RD_DCR_LCH1(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH1_MASK) >> DMA_DCR_LCH…  argument
5028 #define DMA_BRD_DCR_LCH1(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH1_SHIFT, DM…  argument
5031 #define DMA_WR_DCR_LCH1(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH1_MASK, DMA_DCR_LC…  argument
5032 #define DMA_BWR_DCR_LCH1(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5059 #define DMA_RD_DCR_LINKCC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LINKCC_MASK) >> DMA_DCR…  argument
5060 #define DMA_BRD_DCR_LINKCC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LINKCC_SHIFT…  argument
5063 #define DMA_WR_DCR_LINKCC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LINKCC_MASK, DMA_DC…  argument
5064 #define DMA_BWR_DCR_LINKCC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…  argument
5079 #define DMA_RD_DCR_D_REQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_D_REQ_MASK) >> DMA_DCR_D…  argument
5080 #define DMA_BRD_DCR_D_REQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_D_REQ_SHIFT, …  argument
5083 #define DMA_WR_DCR_D_REQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_D_REQ_MASK, DMA_DCR_…  argument
5084 #define DMA_BWR_DCR_D_REQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5119 #define DMA_RD_DCR_DMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DMOD_MASK) >> DMA_DCR_DMO…  argument
5120 #define DMA_BRD_DCR_DMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DMOD_SHIFT, DM…  argument
5123 #define DMA_WR_DCR_DMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DMOD_MASK, DMA_DCR_DM…  argument
5124 #define DMA_BWR_DCR_DMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5176 #define DMA_RD_DCR_SMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SMOD_MASK) >> DMA_DCR_SMO…  argument
5177 #define DMA_BRD_DCR_SMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SMOD_SHIFT, DM…  argument
5180 #define DMA_WR_DCR_SMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SMOD_MASK, DMA_DCR_SM…  argument
5181 #define DMA_BWR_DCR_SMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5195 #define DMA_WR_DCR_START(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_START_MASK, DMA_DCR_…  argument
5196 #define DMA_BWR_DCR_START(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5213 #define DMA_RD_DCR_DSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DSIZE_MASK) >> DMA_DCR_D…  argument
5214 #define DMA_BRD_DCR_DSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DSIZE_SHIFT, …  argument
5217 #define DMA_WR_DCR_DSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DSIZE_MASK, DMA_DCR_…  argument
5218 #define DMA_BWR_DCR_DSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5233 #define DMA_RD_DCR_DINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DINC_MASK) >> DMA_DCR_DIN…  argument
5234 #define DMA_BRD_DCR_DINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DINC_SHIFT, DM…  argument
5237 #define DMA_WR_DCR_DINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DINC_MASK, DMA_DCR_DI…  argument
5238 #define DMA_BWR_DCR_DINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5255 #define DMA_RD_DCR_SSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SSIZE_MASK) >> DMA_DCR_S…  argument
5256 #define DMA_BRD_DCR_SSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SSIZE_SHIFT, …  argument
5259 #define DMA_WR_DCR_SSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SSIZE_MASK, DMA_DCR_…  argument
5260 #define DMA_BWR_DCR_SSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5274 #define DMA_RD_DCR_SINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SINC_MASK) >> DMA_DCR_SIN…  argument
5275 #define DMA_BRD_DCR_SINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SINC_SHIFT, DM…  argument
5278 #define DMA_WR_DCR_SINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SINC_MASK, DMA_DCR_SI…  argument
5279 #define DMA_BWR_DCR_SINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5294 #define DMA_RD_DCR_EADREQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EADREQ_MASK) >> DMA_DCR…  argument
5295 #define DMA_BRD_DCR_EADREQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EADREQ_SHIFT…  argument
5298 #define DMA_WR_DCR_EADREQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EADREQ_MASK, DMA_DC…  argument
5299 #define DMA_BWR_DCR_EADREQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…  argument
5318 #define DMA_RD_DCR_AA(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_AA_MASK) >> DMA_DCR_AA_SHIF…  argument
5319 #define DMA_BRD_DCR_AA(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_AA_SHIFT, DMA_DC…  argument
5322 #define DMA_WR_DCR_AA(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_AA_MASK, DMA_DCR_AA(val…  argument
5323 #define DMA_BWR_DCR_AA(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…  argument
5336 #define DMA_RD_DCR_CS(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_CS_MASK) >> DMA_DCR_CS_SHIF…  argument
5337 #define DMA_BRD_DCR_CS(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_CS_SHIFT, DMA_DC…  argument
5340 #define DMA_WR_DCR_CS(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_CS_MASK, DMA_DCR_CS(val…  argument
5341 #define DMA_BWR_DCR_CS(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…  argument
5356 #define DMA_RD_DCR_ERQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_ERQ_MASK) >> DMA_DCR_ERQ_S…  argument
5357 #define DMA_BRD_DCR_ERQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_ERQ_SHIFT, DMA_…  argument
5360 #define DMA_WR_DCR_ERQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_ERQ_MASK, DMA_DCR_ERQ(…  argument
5361 #define DMA_BWR_DCR_ERQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value…  argument
5376 #define DMA_RD_DCR_EINT(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EINT_MASK) >> DMA_DCR_EIN…  argument
5377 #define DMA_BRD_DCR_EINT(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EINT_SHIFT, DM…  argument
5380 #define DMA_WR_DCR_EINT(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EINT_MASK, DMA_DCR_EI…  argument
5381 #define DMA_BWR_DCR_EINT(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5416 #define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))  argument
5417 #define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))  argument
5418 #define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(b…  argument
5419 #define DMAMUX_SET_CHCFG(base, index, value) (BME_OR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(val…  argument
5420 #define DMAMUX_CLR_CHCFG(base, index, value) (BME_AND8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(~(…  argument
5421 #define DMAMUX_TOG_CHCFG(base, index, value) (BME_XOR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(va…  argument
5437 #define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_M…  argument
5438 #define DMAMUX_BRD_CHCFG_SOURCE(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCF…  argument
5441 #define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOUR…  argument
5442 #define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uin…  argument
5459 #define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK)…  argument
5460 #define DMAMUX_BRD_CHCFG_TRIG(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_…  argument
5463 #define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_M…  argument
5464 #define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8…  argument
5480 #define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK)…  argument
5481 #define DMAMUX_BRD_CHCFG_ENBL(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_…  argument
5484 #define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_M…  argument
5485 #define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8…  argument
13100 #define LTC_RD_CTX(base, index)  (LTC_CTX_REG(base, index))  argument
13101 #define LTC_WR_CTX(base, index, value) (LTC_CTX_REG(base, index) = (value))  argument
13102 #define LTC_RMW_CTX(base, index, mask, value) (LTC_WR_CTX(base, index, (LTC_RD_CTX(base, index) & ~…  argument
13103 #define LTC_SET_CTX(base, index, value) (BME_OR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))  argument
13104 #define LTC_CLR_CTX(base, index, value) (BME_AND32(&LTC_CTX_REG(base, index), (uint32_t)(~(value))))  argument
13105 #define LTC_TOG_CTX(base, index, value) (BME_XOR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))  argument
13129 #define LTC_RD_KEY(base, index)  (LTC_KEY_REG(base, index))  argument
13130 #define LTC_WR_KEY(base, index, value) (LTC_KEY_REG(base, index) = (value))  argument
13131 #define LTC_RMW_KEY(base, index, mask, value) (LTC_WR_KEY(base, index, (LTC_RD_KEY(base, index) & ~…  argument
13132 #define LTC_SET_KEY(base, index, value) (BME_OR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))  argument
13133 #define LTC_CLR_KEY(base, index, value) (BME_AND32(&LTC_KEY_REG(base, index), (uint32_t)(~(value))))  argument
13134 #define LTC_TOG_KEY(base, index, value) (BME_XOR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))  argument
15343 #define MTB_RD_PERIPHID(base, index) (MTB_PERIPHID_REG(base, index))  argument
15362 #define MTB_RD_COMPID(base, index) (MTB_COMPID_REG(base, index))  argument
15461 #define MTBDWT_RD_COMP(base, index) (MTBDWT_COMP_REG(base, index))  argument
15462 #define MTBDWT_WR_COMP(base, index, value) (MTBDWT_COMP_REG(base, index) = (value))  argument
15463 #define MTBDWT_RMW_COMP(base, index, mask, value) (MTBDWT_WR_COMP(base, index, (MTBDWT_RD_COMP(base…  argument
15464 #define MTBDWT_SET_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15465 #define MTBDWT_CLR_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15466 #define MTBDWT_TOG_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15486 #define MTBDWT_RD_MASK(base, index) (MTBDWT_MASK_REG(base, index))  argument
15487 #define MTBDWT_WR_MASK(base, index, value) (MTBDWT_MASK_REG(base, index) = (value))  argument
15488 #define MTBDWT_RMW_MASK(base, index, mask, value) (MTBDWT_WR_MASK(base, index, (MTBDWT_RD_MASK(base…  argument
15489 #define MTBDWT_SET_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15490 #define MTBDWT_CLR_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15491 #define MTBDWT_TOG_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15515 #define MTBDWT_RD_MASK_MASK(base, index) ((MTBDWT_MASK_REG(base, index) & MTBDWT_MASK_MASK_MASK) >>…  argument
15516 #define MTBDWT_BRD_MASK_MASK(base, index) (MTBDWT_RD_MASK_MASK(base, index))  argument
15519 #define MTBDWT_WR_MASK_MASK(base, index, value) (MTBDWT_RMW_MASK(base, index, MTBDWT_MASK_MASK_MASK…  argument
15520 #define MTBDWT_BWR_MASK_MASK(base, index, value) (MTBDWT_WR_MASK_MASK(base, index, value))  argument
15538 #define MTBDWT_RD_FCT(base, index) (MTBDWT_FCT_REG(base, index))  argument
15539 #define MTBDWT_WR_FCT(base, index, value) (MTBDWT_FCT_REG(base, index) = (value))  argument
15540 #define MTBDWT_RMW_FCT(base, index, mask, value) (MTBDWT_WR_FCT(base, index, (MTBDWT_RD_FCT(base, i…  argument
15541 #define MTBDWT_SET_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) |…  argument
15542 #define MTBDWT_CLR_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) &…  argument
15543 #define MTBDWT_TOG_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) ^…  argument
15567 #define MTBDWT_RD_FCT_FUNCTION(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_FUNCTION_MAS…  argument
15568 #define MTBDWT_BRD_FCT_FUNCTION(base, index) (MTBDWT_RD_FCT_FUNCTION(base, index))  argument
15571 #define MTBDWT_WR_FCT_FUNCTION(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_FUNCTION…  argument
15572 #define MTBDWT_BWR_FCT_FUNCTION(base, index, value) (MTBDWT_WR_FCT_FUNCTION(base, index, value))  argument
15588 #define MTBDWT_RD_FCT_DATAVMATCH(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVMATCH…  argument
15589 #define MTBDWT_BRD_FCT_DATAVMATCH(base, index) (MTBDWT_RD_FCT_DATAVMATCH(base, index))  argument
15592 #define MTBDWT_WR_FCT_DATAVMATCH(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVM…  argument
15593 #define MTBDWT_BWR_FCT_DATAVMATCH(base, index, value) (MTBDWT_WR_FCT_DATAVMATCH(base, index, value))  argument
15611 #define MTBDWT_RD_FCT_DATAVSIZE(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVSIZE_M…  argument
15612 #define MTBDWT_BRD_FCT_DATAVSIZE(base, index) (MTBDWT_RD_FCT_DATAVSIZE(base, index))  argument
15615 #define MTBDWT_WR_FCT_DATAVSIZE(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVSI…  argument
15616 #define MTBDWT_BWR_FCT_DATAVSIZE(base, index, value) (MTBDWT_WR_FCT_DATAVSIZE(base, index, value))  argument
15630 #define MTBDWT_RD_FCT_DATAVADDR0(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVADDR0…  argument
15631 #define MTBDWT_BRD_FCT_DATAVADDR0(base, index) (MTBDWT_RD_FCT_DATAVADDR0(base, index))  argument
15634 #define MTBDWT_WR_FCT_DATAVADDR0(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVA…  argument
15635 #define MTBDWT_BWR_FCT_DATAVADDR0(base, index, value) (MTBDWT_WR_FCT_DATAVADDR0(base, index, value))  argument
15651 #define MTBDWT_RD_FCT_MATCHED(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_MATCHED_MASK)…  argument
15652 #define MTBDWT_BRD_FCT_MATCHED(base, index) (MTBDWT_RD_FCT_MATCHED(base, index))  argument
15799 #define MTBDWT_RD_PERIPHID(base, index) (MTBDWT_PERIPHID_REG(base, index))  argument
15818 #define MTBDWT_RD_COMPID(base, index) (MTBDWT_COMPID_REG(base, index))  argument
16347 #define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))  argument
16348 #define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))  argument
16349 #define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, inde…  argument
16350 #define PIT_SET_LDVAL(base, index, value) (BME_OR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))  argument
16351 #define PIT_CLR_LDVAL(base, index, value) (BME_AND32(&PIT_LDVAL_REG(base, index), (uint32_t)(~(valu…  argument
16352 #define PIT_TOG_LDVAL(base, index, value) (BME_XOR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)…  argument
16370 #define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))  argument
16389 #define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))  argument
16390 #define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))  argument
16391 #define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, inde…  argument
16392 #define PIT_SET_TCTRL(base, index, value) (BME_OR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))  argument
16393 #define PIT_CLR_TCTRL(base, index, value) (BME_AND32(&PIT_TCTRL_REG(base, index), (uint32_t)(~(valu…  argument
16394 #define PIT_TOG_TCTRL(base, index, value) (BME_XOR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)…  argument
16412 #define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCT…  argument
16413 #define PIT_BRD_TCTRL_TEN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT…  argument
16416 #define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TC…  argument
16417 #define PIT_BWR_TCTRL_TEN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16433 #define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCT…  argument
16434 #define PIT_BRD_TCTRL_TIE(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT…  argument
16437 #define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TC…  argument
16438 #define PIT_BWR_TCTRL_TIE(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16454 #define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCT…  argument
16455 #define PIT_BRD_TCTRL_CHN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT…  argument
16458 #define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TC…  argument
16459 #define PIT_BWR_TCTRL_CHN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16477 #define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))  argument
16478 #define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))  argument
16479 #define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) …  argument
16480 #define PIT_SET_TFLG(base, index, value) (BME_OR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))  argument
16481 #define PIT_CLR_TFLG(base, index, value) (BME_AND32(&PIT_TFLG_REG(base, index), (uint32_t)(~(value)…  argument
16482 #define PIT_TOG_TFLG(base, index, value) (BME_XOR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))  argument
16502 #define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_T…  argument
16503 #define PIT_BRD_TFLG_TIF(base, index) (BME_UBFX32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT, P…  argument
16506 #define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_…  argument
16507 #define PIT_BWR_TFLG_TIF(base, index, value) (BME_BFI32(&PIT_TFLG_REG(base, index), ((uint32_t)(val…  argument
16906 #define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))  argument
16907 #define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))  argument
16908 #define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) …  argument
16909 #define PORT_SET_PCR(base, index, value) (BME_OR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))  argument
16910 #define PORT_CLR_PCR(base, index, value) (BME_AND32(&PORT_PCR_REG(base, index), (uint32_t)(~(value)…  argument
16911 #define PORT_TOG_PCR(base, index, value) (BME_XOR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))  argument
16932 #define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_…  argument
16933 #define PORT_BRD_PCR_PS(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT, POR…  argument
16936 #define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_…  argument
16937 #define PORT_BWR_PCR_PS(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…  argument
16956 #define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_…  argument
16957 #define PORT_BRD_PCR_PE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT, POR…  argument
16960 #define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_…  argument
16961 #define PORT_BWR_PCR_PE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…  argument
16978 #define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_S…  argument
16979 #define PORT_BRD_PCR_SRE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT, P…  argument
16982 #define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PC…  argument
16983 #define PORT_BWR_PCR_SRE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17001 #define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_P…  argument
17002 #define PORT_BRD_PCR_PFE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT, P…  argument
17005 #define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PC…  argument
17006 #define PORT_BWR_PCR_PFE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17023 #define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_D…  argument
17024 #define PORT_BRD_PCR_DSE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT, P…  argument
17027 #define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PC…  argument
17028 #define PORT_BWR_PCR_DSE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17051 #define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_M…  argument
17052 #define PORT_BRD_PCR_MUX(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_MUX_SHIFT, P…  argument
17055 #define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PC…  argument
17056 #define PORT_BWR_PCR_MUX(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17086 #define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR…  argument
17087 #define PORT_BRD_PCR_IRQC(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_IRQC_SHIFT,…  argument
17090 #define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_…  argument
17091 #define PORT_BWR_PCR_IRQC(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(va…  argument
17111 #define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_I…  argument
17112 #define PORT_BRD_PCR_ISF(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT, P…  argument
17115 #define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_…  argument
17116 #define PORT_BWR_PCR_ISF(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17680 #define ROM_RD_ENTRY(base, index) (ROM_ENTRY_REG(base, index))  argument
17889 #define ROM_RD_COMPID(base, index) (ROM_COMPID_REG(base, index))  argument
19881 #define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC4_REG(base) + (((uint…  argument
19882 #define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))  argument
19883 #define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_B…  argument
19884 #define SIM_BRD_SCGC_BIT(base, index)        (BME_UBFX32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SC…  argument
19885 #define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG…  argument
19886 #define SIM_BWR_SCGC_BIT(base, index, value) (BME_BFI32(&SIM_SCGC_BIT_REG((base), (index)), ((uint3…  argument
21758 #define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))  argument
21759 #define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))  argument
21760 #define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_S…  argument
21761 #define SPI_SET_CTAR_SLAVE(base, index, value) (BME_OR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_…  argument
21762 #define SPI_CLR_CTAR_SLAVE(base, index, value) (BME_AND32(&SPI_CTAR_SLAVE_REG(base, index), (uint32…  argument
21763 #define SPI_TOG_CTAR_SLAVE(base, index, value) (BME_XOR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32…  argument
21787 #define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA…  argument
21788 #define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21791 #define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21792 #define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21808 #define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL…  argument
21809 #define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21812 #define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21813 #define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21824 #define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ…  argument
21825 #define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21828 #define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21829 #define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21856 #define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))  argument
21857 #define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))  argument
21858 #define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) …  argument
21859 #define SPI_SET_CTAR(base, index, value) (BME_OR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))  argument
21860 #define SPI_CLR_CTAR(base, index, value) (BME_AND32(&SPI_CTAR_REG(base, index), (uint32_t)(~(value)…  argument
21861 #define SPI_TOG_CTAR(base, index, value) (BME_XOR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))  argument
21881 #define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_…  argument
21882 #define SPI_BRD_CTAR_BR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_BR_SHIFT, SPI…  argument
21885 #define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR…  argument
21886 #define SPI_BWR_CTAR_BR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…  argument
21903 #define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_…  argument
21904 #define SPI_BRD_CTAR_DT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DT_SHIFT, SPI…  argument
21907 #define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT…  argument
21908 #define SPI_BWR_CTAR_DT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…  argument
21923 #define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_A…  argument
21924 #define SPI_BRD_CTAR_ASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_ASC_SHIFT, S…  argument
21927 #define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_…  argument
21928 #define SPI_BWR_CTAR_ASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
21946 #define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CT…  argument
21947 #define SPI_BRD_CTAR_CSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CSSCK_SHIF…  argument
21950 #define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_C…  argument
21951 #define SPI_BWR_CTAR_CSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…  argument
21970 #define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_P…  argument
21971 #define SPI_BRD_CTAR_PBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PBR_SHIFT, S…  argument
21974 #define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_…  argument
21975 #define SPI_BWR_CTAR_PBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
21995 #define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_P…  argument
21996 #define SPI_BRD_CTAR_PDT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PDT_SHIFT, S…  argument
21999 #define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_…  argument
22000 #define SPI_BWR_CTAR_PDT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
22018 #define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR…  argument
22019 #define SPI_BRD_CTAR_PASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PASC_SHIFT,…  argument
22022 #define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTA…  argument
22023 #define SPI_BWR_CTAR_PASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22041 #define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_…  argument
22042 #define SPI_BRD_CTAR_PCSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PCSSCK_SH…  argument
22045 #define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI…  argument
22046 #define SPI_BWR_CTAR_PCSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(…  argument
22060 #define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CT…  argument
22061 #define SPI_BRD_CTAR_LSBFE(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIF…  argument
22064 #define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_C…  argument
22065 #define SPI_BWR_CTAR_LSBFE(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…  argument
22085 #define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR…  argument
22086 #define SPI_BRD_CTAR_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT,…  argument
22089 #define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTA…  argument
22090 #define SPI_BWR_CTAR_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22111 #define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR…  argument
22112 #define SPI_BRD_CTAR_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT,…  argument
22115 #define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTA…  argument
22116 #define SPI_BWR_CTAR_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22127 #define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR…  argument
22128 #define SPI_BRD_CTAR_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_FMSZ_SHIFT,…  argument
22131 #define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTA…  argument
22132 #define SPI_BWR_CTAR_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22155 #define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_D…  argument
22156 #define SPI_BRD_CTAR_DBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT, S…  argument
22159 #define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_…  argument
22160 #define SPI_BWR_CTAR_DBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
23383 #define TPM_RD_CnSC(base, index) (TPM_CnSC_REG(base, index))  argument
23384 #define TPM_WR_CnSC(base, index, value) (TPM_CnSC_REG(base, index) = (value))  argument
23385 #define TPM_RMW_CnSC(base, index, mask, value) (TPM_WR_CnSC(base, index, (TPM_RD_CnSC(base, index) …  argument
23386 #define TPM_SET_CnSC(base, index, value) (BME_OR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))  argument
23387 #define TPM_CLR_CnSC(base, index, value) (BME_AND32(&TPM_CnSC_REG(base, index), (uint32_t)(~(value)…  argument
23388 #define TPM_TOG_CnSC(base, index, value) (BME_XOR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))  argument
23406 #define TPM_RD_CnSC_DMA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_DMA_MASK) >> TPM_CnSC_D…  argument
23407 #define TPM_BRD_CnSC_DMA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_DMA_SHIFT, T…  argument
23410 #define TPM_WR_CnSC_DMA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_DMA_MASK | TPM_CnS…  argument
23411 #define TPM_BWR_CnSC_DMA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23423 #define TPM_RD_CnSC_ELSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSA_MASK) >> TPM_CnSC…  argument
23424 #define TPM_BRD_CnSC_ELSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSA_SHIFT,…  argument
23427 #define TPM_WR_CnSC_ELSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSA_MASK | TPM_C…  argument
23428 #define TPM_BWR_CnSC_ELSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23440 #define TPM_RD_CnSC_ELSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSB_MASK) >> TPM_CnSC…  argument
23441 #define TPM_BRD_CnSC_ELSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSB_SHIFT,…  argument
23444 #define TPM_WR_CnSC_ELSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSB_MASK | TPM_C…  argument
23445 #define TPM_BWR_CnSC_ELSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23457 #define TPM_RD_CnSC_MSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSA_MASK) >> TPM_CnSC_M…  argument
23458 #define TPM_BRD_CnSC_MSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSA_SHIFT, T…  argument
23461 #define TPM_WR_CnSC_MSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSA_MASK | TPM_CnS…  argument
23462 #define TPM_BWR_CnSC_MSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23474 #define TPM_RD_CnSC_MSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSB_MASK) >> TPM_CnSC_M…  argument
23475 #define TPM_BRD_CnSC_MSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSB_SHIFT, T…  argument
23478 #define TPM_WR_CnSC_MSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSB_MASK | TPM_CnS…  argument
23479 #define TPM_BWR_CnSC_MSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23493 #define TPM_RD_CnSC_CHIE(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHIE_MASK) >> TPM_CnSC…  argument
23494 #define TPM_BRD_CnSC_CHIE(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHIE_SHIFT,…  argument
23497 #define TPM_WR_CnSC_CHIE(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_CHIE_MASK | TPM_C…  argument
23498 #define TPM_BWR_CnSC_CHIE(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23517 #define TPM_RD_CnSC_CHF(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHF_MASK) >> TPM_CnSC_C…  argument
23518 #define TPM_BRD_CnSC_CHF(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHF_SHIFT, T…  argument
23521 #define TPM_WR_CnSC_CHF(base, index, value) (TPM_RMW_CnSC(base, index, TPM_CnSC_CHF_MASK, TPM_CnSC_…  argument
23522 #define TPM_BWR_CnSC_CHF(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23545 #define TPM_RD_CnV(base, index)  (TPM_CnV_REG(base, index))  argument
23546 #define TPM_WR_CnV(base, index, value) (TPM_CnV_REG(base, index) = (value))  argument
23547 #define TPM_RMW_CnV(base, index, mask, value) (TPM_WR_CnV(base, index, (TPM_RD_CnV(base, index) & ~…  argument
23548 #define TPM_SET_CnV(base, index, value) (BME_OR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))  argument
23549 #define TPM_CLR_CnV(base, index, value) (BME_AND32(&TPM_CnV_REG(base, index), (uint32_t)(~(value))))  argument
23550 #define TPM_TOG_CnV(base, index, value) (BME_XOR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))  argument
23565 #define TPM_RD_CnV_VAL(base, index) ((TPM_CnV_REG(base, index) & TPM_CnV_VAL_MASK) >> TPM_CnV_VAL_S…  argument
23566 #define TPM_BRD_CnV_VAL(base, index) (BME_UBFX32(&TPM_CnV_REG(base, index), TPM_CnV_VAL_SHIFT, TPM_…  argument
23569 #define TPM_WR_CnV_VAL(base, index, value) (TPM_RMW_CnV(base, index, TPM_CnV_VAL_MASK, TPM_CnV_VAL(…  argument
23570 #define TPM_BWR_CnV_VAL(base, index, value) (BME_BFI32(&TPM_CnV_REG(base, index), ((uint32_t)(value…  argument
26154 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))  argument
31801 #define XCVR_RD_DCOC_OFFSET_(base, index) (XCVR_DCOC_OFFSET__REG(base, index))  argument
31802 #define XCVR_WR_DCOC_OFFSET_(base, index, value) (XCVR_DCOC_OFFSET__REG(base, index) = (value))  argument
31803 #define XCVR_RMW_DCOC_OFFSET_(base, index, mask, value) (XCVR_WR_DCOC_OFFSET_(base, index, (XCVR_RD…  argument
31804 #define XCVR_SET_DCOC_OFFSET_(base, index, value) (BME_OR32(&XCVR_DCOC_OFFSET__REG(base, index), (u…  argument
31805 #define XCVR_CLR_DCOC_OFFSET_(base, index, value) (BME_AND32(&XCVR_DCOC_OFFSET__REG(base, index), (…  argument
31806 #define XCVR_TOG_DCOC_OFFSET_(base, index, value) (BME_XOR32(&XCVR_DCOC_OFFSET__REG(base, index), (…  argument
31822 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31823 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31826 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31827 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31839 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31840 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31843 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31844 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31856 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31857 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31860 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31861 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31873 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31874 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31877 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31878 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31894 #define XCVR_RD_DCOC_TZA_STEP_(base, index) (XCVR_DCOC_TZA_STEP__REG(base, index))  argument
31895 #define XCVR_WR_DCOC_TZA_STEP_(base, index, value) (XCVR_DCOC_TZA_STEP__REG(base, index) = (value))  argument
31896 #define XCVR_RMW_DCOC_TZA_STEP_(base, index, mask, value) (XCVR_WR_DCOC_TZA_STEP_(base, index, (XCV…  argument
31897 #define XCVR_SET_DCOC_TZA_STEP_(base, index, value) (BME_OR32(&XCVR_DCOC_TZA_STEP__REG(base, index)…  argument
31898 #define XCVR_CLR_DCOC_TZA_STEP_(base, index, value) (BME_AND32(&XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31899 #define XCVR_TOG_DCOC_TZA_STEP_(base, index, value) (BME_XOR32(&XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31916 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31917 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__REG…  argument
31920 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base,…  argument
31921 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_STE…  argument
31936 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, inde…  argument
31937 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__RE…  argument
31940 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base…  argument
31941 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_ST…  argument
32182 #define XCVR_RD_DCOC_CAL(base, index) (XCVR_DCOC_CAL_REG(base, index))  argument
32198 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_I(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_C…  argument
32199 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_I(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …  argument
32211 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_C…  argument
32212 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …  argument
32230 #define XCVR_RD_RX_CHF_COEF(base, index) (XCVR_RX_CHF_COEF_REG(base, index))  argument
32231 #define XCVR_WR_RX_CHF_COEF(base, index, value) (XCVR_RX_CHF_COEF_REG(base, index) = (value))  argument
32232 #define XCVR_RMW_RX_CHF_COEF(base, index, mask, value) (XCVR_WR_RX_CHF_COEF(base, index, (XCVR_RD_R…  argument
32233 #define XCVR_SET_RX_CHF_COEF(base, index, value) (BME_OR32(&XCVR_RX_CHF_COEF_REG(base, index), (uin…  argument
32234 #define XCVR_CLR_RX_CHF_COEF(base, index, value) (BME_AND32(&XCVR_RX_CHF_COEF_REG(base, index), (ui…  argument
32235 #define XCVR_TOG_RX_CHF_COEF(base, index, value) (BME_XOR32(&XCVR_RX_CHF_COEF_REG(base, index), (ui…  argument
32249 #define XCVR_RD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) ((XCVR_RX_CHF_COEF_REG(base, index) & XCVR_R…  argument
32250 #define XCVR_BRD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) (BME_UBFX32(&XCVR_RX_CHF_COEF_REG(base, ind…  argument
32253 #define XCVR_WR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (XCVR_RMW_RX_CHF_COEF(base, index, XC…  argument
32254 #define XCVR_BWR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (BME_BFI32(&XCVR_RX_CHF_COEF_REG(bas…  argument
48039 #define ZLL_RD_PKT_BUFFER(base, index) (ZLL_PKT_BUFFER_REG(base, index))  argument
48040 #define ZLL_WR_PKT_BUFFER(base, index, value) (ZLL_PKT_BUFFER_REG(base, index) = (value))  argument
48041 #define ZLL_RMW_PKT_BUFFER(base, index, mask, value) (ZLL_WR_PKT_BUFFER(base, index, (ZLL_RD_PKT_BU…  argument
48042 #define ZLL_SET_PKT_BUFFER(base, index, value) (BME_OR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_…  argument
48043 #define ZLL_CLR_PKT_BUFFER(base, index, value) (BME_AND32(&ZLL_PKT_BUFFER_REG(base, index), (uint32…  argument
48044 #define ZLL_TOG_PKT_BUFFER(base, index, value) (BME_XOR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32…  argument