145 #define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))  argument
146 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))  argument
147 #define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~…  argument
148 #define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))  argument
149 #define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value))))  argument
150 #define ADC_TOG_SC1(base, index, value) (BME_XOR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))  argument
238 #define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADC…  argument
239 #define ADC_BRD_SC1_ADCH(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_ADCH_SHIFT, AD…  argument
242 #define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_AD…  argument
243 #define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
259 #define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIF…  argument
260 #define ADC_BRD_SC1_DIFF(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT, AD…  argument
263 #define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DI…  argument
264 #define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
279 #define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIE…  argument
280 #define ADC_BRD_SC1_AIEN(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT, AD…  argument
283 #define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AI…  argument
284 #define ADC_BWR_SC1_AIEN(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(valu…  argument
306 #define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COC…  argument
307 #define ADC_BRD_SC1_COCO(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT, AD…  argument
326 #define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))  argument
327 #define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))  argument
328 #define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))  argument
329 #define ADC_SET_CFG1(base, value) (BME_OR32(&ADC_CFG1_REG(base), (uint32_t)(value)))  argument
330 #define ADC_CLR_CFG1(base, value) (BME_AND32(&ADC_CFG1_REG(base), (uint32_t)(~(value))))  argument
331 #define ADC_TOG_CFG1(base, value) (BME_XOR32(&ADC_CFG1_REG(base), (uint32_t)(value)))  argument
357 #define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SH…  argument
358 #define ADC_BRD_CFG1_ADICLK(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_…  argument
361 #define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(v…  argument
362 #define ADC_BWR_CFG1_ADICLK(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_…  argument
382 #define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)  argument
383 #define ADC_BRD_CFG1_MODE(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE…  argument
386 #define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))  argument
387 #define ADC_BWR_CFG1_MODE(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CF…  argument
407 #define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SH…  argument
408 #define ADC_BRD_CFG1_ADLSMP(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_…  argument
411 #define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(v…  argument
412 #define ADC_BWR_CFG1_ADLSMP(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_…  argument
428 #define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)  argument
429 #define ADC_BRD_CFG1_ADIV(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV…  argument
432 #define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))  argument
433 #define ADC_BWR_CFG1_ADIV(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CF…  argument
449 #define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)  argument
450 #define ADC_BRD_CFG1_ADLPC(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_AD…  argument
453 #define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(valu…  argument
454 #define ADC_BWR_CFG1_ADLPC(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_C…  argument
474 #define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))  argument
475 #define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))  argument
476 #define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))  argument
477 #define ADC_SET_CFG2(base, value) (BME_OR32(&ADC_CFG2_REG(base), (uint32_t)(value)))  argument
478 #define ADC_CLR_CFG2(base, value) (BME_AND32(&ADC_CFG2_REG(base), (uint32_t)(~(value))))  argument
479 #define ADC_TOG_CFG2(base, value) (BME_XOR32(&ADC_CFG2_REG(base), (uint32_t)(value)))  argument
504 #define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SH…  argument
505 #define ADC_BRD_CFG2_ADLSTS(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_…  argument
508 #define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(v…  argument
509 #define ADC_BWR_CFG2_ADLSTS(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_…  argument
526 #define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)  argument
527 #define ADC_BRD_CFG2_ADHSC(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_AD…  argument
530 #define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(valu…  argument
531 #define ADC_BWR_CFG2_ADHSC(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_C…  argument
553 #define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN…  argument
554 #define ADC_BRD_CFG2_ADACKEN(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG…  argument
557 #define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKE…  argument
558 #define ADC_BWR_CFG2_ADACKEN(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC…  argument
572 #define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SH…  argument
573 #define ADC_BRD_CFG2_MUXSEL(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_…  argument
576 #define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(v…  argument
577 #define ADC_BWR_CFG2_MUXSEL(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_…  argument
625 #define ADC_RD_R(base, index)    (ADC_R_REG(base, index))  argument
637 #define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)  argument
638 #define ADC_BRD_R_D(base, index) (BME_UBFX32(&ADC_R_REG(base, index), ADC_R_D_SHIFT, ADC_R_D_WIDTH))  argument
663 #define ADC_RD_CV1(base)         (ADC_CV1_REG(base))  argument
664 #define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))  argument
665 #define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))  argument
666 #define ADC_SET_CV1(base, value) (BME_OR32(&ADC_CV1_REG(base), (uint32_t)(value)))  argument
667 #define ADC_CLR_CV1(base, value) (BME_AND32(&ADC_CV1_REG(base), (uint32_t)(~(value))))  argument
668 #define ADC_TOG_CV1(base, value) (BME_XOR32(&ADC_CV1_REG(base), (uint32_t)(value)))  argument
680 #define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)  argument
681 #define ADC_BRD_CV1_CV(base) (BME_UBFX32(&ADC_CV1_REG(base), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))  argument
684 #define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))  argument
685 #define ADC_BWR_CV1_CV(base, value) (BME_BFI32(&ADC_CV1_REG(base), ((uint32_t)(value) << ADC_CV1_CV…  argument
710 #define ADC_RD_CV2(base)         (ADC_CV2_REG(base))  argument
711 #define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))  argument
712 #define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))  argument
713 #define ADC_SET_CV2(base, value) (BME_OR32(&ADC_CV2_REG(base), (uint32_t)(value)))  argument
714 #define ADC_CLR_CV2(base, value) (BME_AND32(&ADC_CV2_REG(base), (uint32_t)(~(value))))  argument
715 #define ADC_TOG_CV2(base, value) (BME_XOR32(&ADC_CV2_REG(base), (uint32_t)(value)))  argument
727 #define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)  argument
728 #define ADC_BRD_CV2_CV(base) (BME_UBFX32(&ADC_CV2_REG(base), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))  argument
731 #define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))  argument
732 #define ADC_BWR_CV2_CV(base, value) (BME_BFI32(&ADC_CV2_REG(base), ((uint32_t)(value) << ADC_CV2_CV…  argument
752 #define ADC_RD_SC2(base)         (ADC_SC2_REG(base))  argument
753 #define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))  argument
754 #define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))  argument
755 #define ADC_SET_SC2(base, value) (BME_OR32(&ADC_SC2_REG(base), (uint32_t)(value)))  argument
756 #define ADC_CLR_SC2(base, value) (BME_AND32(&ADC_SC2_REG(base), (uint32_t)(~(value))))  argument
757 #define ADC_TOG_SC2(base, value) (BME_XOR32(&ADC_SC2_REG(base), (uint32_t)(value)))  argument
782 #define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)  argument
783 #define ADC_BRD_SC2_REFSEL(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFS…  argument
786 #define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value…  argument
787 #define ADC_BWR_SC2_REFSEL(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC…  argument
800 #define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)  argument
801 #define ADC_BRD_SC2_DMAEN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_…  argument
804 #define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))  argument
805 #define ADC_BWR_SC2_DMAEN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…  argument
822 #define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)  argument
823 #define ADC_BRD_SC2_ACREN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_…  argument
826 #define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))  argument
827 #define ADC_BWR_SC2_ACREN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…  argument
846 #define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)  argument
847 #define ADC_BRD_SC2_ACFGT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_…  argument
850 #define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))  argument
851 #define ADC_BWR_SC2_ACFGT(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…  argument
865 #define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)  argument
866 #define ADC_BRD_SC2_ACFE(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WID…  argument
869 #define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))  argument
870 #define ADC_BWR_SC2_ACFE(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_…  argument
888 #define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)  argument
889 #define ADC_BRD_SC2_ADTRG(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_…  argument
892 #define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))  argument
893 #define ADC_BWR_SC2_ADTRG(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2…  argument
909 #define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)  argument
910 #define ADC_BRD_SC2_ADACT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT, ADC_SC2_ADACT_…  argument
929 #define ADC_RD_SC3(base)         (ADC_SC3_REG(base))  argument
930 #define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))  argument
931 #define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))  argument
932 #define ADC_SET_SC3(base, value) (BME_OR32(&ADC_SC3_REG(base), (uint32_t)(value)))  argument
933 #define ADC_CLR_SC3(base, value) (BME_AND32(&ADC_SC3_REG(base), (uint32_t)(~(value))))  argument
934 #define ADC_TOG_SC3(base, value) (BME_XOR32(&ADC_SC3_REG(base), (uint32_t)(value)))  argument
955 #define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)  argument
956 #define ADC_BRD_SC3_AVGS(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WID…  argument
959 #define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), AD…  argument
960 #define ADC_BWR_SC3_AVGS(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…  argument
974 #define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)  argument
975 #define ADC_BRD_SC3_AVGE(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WID…  argument
978 #define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), AD…  argument
979 #define ADC_BWR_SC3_AVGE(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…  argument
995 #define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)  argument
996 #define ADC_BRD_SC3_ADCO(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WID…  argument
999 #define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), AD…  argument
1000 #define ADC_BWR_SC3_ADCO(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…  argument
1016 #define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)  argument
1017 #define ADC_BRD_SC3_CALF(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WID…  argument
1020 #define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))  argument
1021 #define ADC_BWR_SC3_CALF(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_…  argument
1036 #define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)  argument
1037 #define ADC_BRD_SC3_CAL(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))  argument
1040 #define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_…  argument
1041 #define ADC_BWR_SC3_CAL(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_C…  argument
1088 #define ADC_RD_OFS(base)         (ADC_OFS_REG(base))  argument
1089 #define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))  argument
1090 #define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))  argument
1091 #define ADC_SET_OFS(base, value) (BME_OR32(&ADC_OFS_REG(base), (uint32_t)(value)))  argument
1092 #define ADC_CLR_OFS(base, value) (BME_AND32(&ADC_OFS_REG(base), (uint32_t)(~(value))))  argument
1093 #define ADC_TOG_OFS(base, value) (BME_XOR32(&ADC_OFS_REG(base), (uint32_t)(value)))  argument
1105 #define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)  argument
1106 #define ADC_BRD_OFS_OFS(base) (BME_UBFX32(&ADC_OFS_REG(base), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))  argument
1109 #define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))  argument
1110 #define ADC_BWR_OFS_OFS(base, value) (BME_BFI32(&ADC_OFS_REG(base), ((uint32_t)(value) << ADC_OFS_O…  argument
1140 #define ADC_RD_PG(base)          (ADC_PG_REG(base))  argument
1141 #define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))  argument
1142 #define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))  argument
1143 #define ADC_SET_PG(base, value)  (BME_OR32(&ADC_PG_REG(base), (uint32_t)(value)))  argument
1144 #define ADC_CLR_PG(base, value)  (BME_AND32(&ADC_PG_REG(base), (uint32_t)(~(value))))  argument
1145 #define ADC_TOG_PG(base, value)  (BME_XOR32(&ADC_PG_REG(base), (uint32_t)(value)))  argument
1157 #define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)  argument
1158 #define ADC_BRD_PG_PG(base)  (BME_UBFX32(&ADC_PG_REG(base), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))  argument
1161 #define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))  argument
1162 #define ADC_BWR_PG_PG(base, value) (BME_BFI32(&ADC_PG_REG(base), ((uint32_t)(value) << ADC_PG_PG_SH…  argument
1190 #define ADC_RD_MG(base)          (ADC_MG_REG(base))  argument
1191 #define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))  argument
1192 #define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))  argument
1193 #define ADC_SET_MG(base, value)  (BME_OR32(&ADC_MG_REG(base), (uint32_t)(value)))  argument
1194 #define ADC_CLR_MG(base, value)  (BME_AND32(&ADC_MG_REG(base), (uint32_t)(~(value))))  argument
1195 #define ADC_TOG_MG(base, value)  (BME_XOR32(&ADC_MG_REG(base), (uint32_t)(value)))  argument
1207 #define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)  argument
1208 #define ADC_BRD_MG_MG(base)  (BME_UBFX32(&ADC_MG_REG(base), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))  argument
1211 #define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))  argument
1212 #define ADC_BWR_MG_MG(base, value) (BME_BFI32(&ADC_MG_REG(base), ((uint32_t)(value) << ADC_MG_MG_SH…  argument
1246 #define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))  argument
1247 #define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))  argument
1248 #define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))  argument
1249 #define ADC_SET_CLPD(base, value) (BME_OR32(&ADC_CLPD_REG(base), (uint32_t)(value)))  argument
1250 #define ADC_CLR_CLPD(base, value) (BME_AND32(&ADC_CLPD_REG(base), (uint32_t)(~(value))))  argument
1251 #define ADC_TOG_CLPD(base, value) (BME_XOR32(&ADC_CLPD_REG(base), (uint32_t)(value)))  argument
1265 #define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)  argument
1266 #define ADC_BRD_CLPD_CLPD(base) (BME_UBFX32(&ADC_CLPD_REG(base), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD…  argument
1269 #define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))  argument
1270 #define ADC_BWR_CLPD_CLPD(base, value) (BME_BFI32(&ADC_CLPD_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1288 #define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))  argument
1289 #define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))  argument
1290 #define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))  argument
1291 #define ADC_SET_CLPS(base, value) (BME_OR32(&ADC_CLPS_REG(base), (uint32_t)(value)))  argument
1292 #define ADC_CLR_CLPS(base, value) (BME_AND32(&ADC_CLPS_REG(base), (uint32_t)(~(value))))  argument
1293 #define ADC_TOG_CLPS(base, value) (BME_XOR32(&ADC_CLPS_REG(base), (uint32_t)(value)))  argument
1307 #define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)  argument
1308 #define ADC_BRD_CLPS_CLPS(base) (BME_UBFX32(&ADC_CLPS_REG(base), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS…  argument
1311 #define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))  argument
1312 #define ADC_BWR_CLPS_CLPS(base, value) (BME_BFI32(&ADC_CLPS_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1330 #define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))  argument
1331 #define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))  argument
1332 #define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))  argument
1333 #define ADC_SET_CLP4(base, value) (BME_OR32(&ADC_CLP4_REG(base), (uint32_t)(value)))  argument
1334 #define ADC_CLR_CLP4(base, value) (BME_AND32(&ADC_CLP4_REG(base), (uint32_t)(~(value))))  argument
1335 #define ADC_TOG_CLP4(base, value) (BME_XOR32(&ADC_CLP4_REG(base), (uint32_t)(value)))  argument
1349 #define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)  argument
1350 #define ADC_BRD_CLP4_CLP4(base) (BME_UBFX32(&ADC_CLP4_REG(base), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4…  argument
1353 #define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))  argument
1354 #define ADC_BWR_CLP4_CLP4(base, value) (BME_BFI32(&ADC_CLP4_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1372 #define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))  argument
1373 #define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))  argument
1374 #define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))  argument
1375 #define ADC_SET_CLP3(base, value) (BME_OR32(&ADC_CLP3_REG(base), (uint32_t)(value)))  argument
1376 #define ADC_CLR_CLP3(base, value) (BME_AND32(&ADC_CLP3_REG(base), (uint32_t)(~(value))))  argument
1377 #define ADC_TOG_CLP3(base, value) (BME_XOR32(&ADC_CLP3_REG(base), (uint32_t)(value)))  argument
1391 #define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)  argument
1392 #define ADC_BRD_CLP3_CLP3(base) (BME_UBFX32(&ADC_CLP3_REG(base), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3…  argument
1395 #define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))  argument
1396 #define ADC_BWR_CLP3_CLP3(base, value) (BME_BFI32(&ADC_CLP3_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1414 #define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))  argument
1415 #define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))  argument
1416 #define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))  argument
1417 #define ADC_SET_CLP2(base, value) (BME_OR32(&ADC_CLP2_REG(base), (uint32_t)(value)))  argument
1418 #define ADC_CLR_CLP2(base, value) (BME_AND32(&ADC_CLP2_REG(base), (uint32_t)(~(value))))  argument
1419 #define ADC_TOG_CLP2(base, value) (BME_XOR32(&ADC_CLP2_REG(base), (uint32_t)(value)))  argument
1433 #define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)  argument
1434 #define ADC_BRD_CLP2_CLP2(base) (BME_UBFX32(&ADC_CLP2_REG(base), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2…  argument
1437 #define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))  argument
1438 #define ADC_BWR_CLP2_CLP2(base, value) (BME_BFI32(&ADC_CLP2_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1456 #define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))  argument
1457 #define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))  argument
1458 #define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))  argument
1459 #define ADC_SET_CLP1(base, value) (BME_OR32(&ADC_CLP1_REG(base), (uint32_t)(value)))  argument
1460 #define ADC_CLR_CLP1(base, value) (BME_AND32(&ADC_CLP1_REG(base), (uint32_t)(~(value))))  argument
1461 #define ADC_TOG_CLP1(base, value) (BME_XOR32(&ADC_CLP1_REG(base), (uint32_t)(value)))  argument
1475 #define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)  argument
1476 #define ADC_BRD_CLP1_CLP1(base) (BME_UBFX32(&ADC_CLP1_REG(base), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1…  argument
1479 #define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))  argument
1480 #define ADC_BWR_CLP1_CLP1(base, value) (BME_BFI32(&ADC_CLP1_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1498 #define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))  argument
1499 #define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))  argument
1500 #define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))  argument
1501 #define ADC_SET_CLP0(base, value) (BME_OR32(&ADC_CLP0_REG(base), (uint32_t)(value)))  argument
1502 #define ADC_CLR_CLP0(base, value) (BME_AND32(&ADC_CLP0_REG(base), (uint32_t)(~(value))))  argument
1503 #define ADC_TOG_CLP0(base, value) (BME_XOR32(&ADC_CLP0_REG(base), (uint32_t)(value)))  argument
1517 #define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)  argument
1518 #define ADC_BRD_CLP0_CLP0(base) (BME_UBFX32(&ADC_CLP0_REG(base), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0…  argument
1521 #define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))  argument
1522 #define ADC_BWR_CLP0_CLP0(base, value) (BME_BFI32(&ADC_CLP0_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1556 #define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))  argument
1557 #define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))  argument
1558 #define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))  argument
1559 #define ADC_SET_CLMD(base, value) (BME_OR32(&ADC_CLMD_REG(base), (uint32_t)(value)))  argument
1560 #define ADC_CLR_CLMD(base, value) (BME_AND32(&ADC_CLMD_REG(base), (uint32_t)(~(value))))  argument
1561 #define ADC_TOG_CLMD(base, value) (BME_XOR32(&ADC_CLMD_REG(base), (uint32_t)(value)))  argument
1575 #define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)  argument
1576 #define ADC_BRD_CLMD_CLMD(base) (BME_UBFX32(&ADC_CLMD_REG(base), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD…  argument
1579 #define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))  argument
1580 #define ADC_BWR_CLMD_CLMD(base, value) (BME_BFI32(&ADC_CLMD_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1598 #define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))  argument
1599 #define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))  argument
1600 #define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))  argument
1601 #define ADC_SET_CLMS(base, value) (BME_OR32(&ADC_CLMS_REG(base), (uint32_t)(value)))  argument
1602 #define ADC_CLR_CLMS(base, value) (BME_AND32(&ADC_CLMS_REG(base), (uint32_t)(~(value))))  argument
1603 #define ADC_TOG_CLMS(base, value) (BME_XOR32(&ADC_CLMS_REG(base), (uint32_t)(value)))  argument
1617 #define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)  argument
1618 #define ADC_BRD_CLMS_CLMS(base) (BME_UBFX32(&ADC_CLMS_REG(base), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS…  argument
1621 #define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))  argument
1622 #define ADC_BWR_CLMS_CLMS(base, value) (BME_BFI32(&ADC_CLMS_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1640 #define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))  argument
1641 #define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))  argument
1642 #define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))  argument
1643 #define ADC_SET_CLM4(base, value) (BME_OR32(&ADC_CLM4_REG(base), (uint32_t)(value)))  argument
1644 #define ADC_CLR_CLM4(base, value) (BME_AND32(&ADC_CLM4_REG(base), (uint32_t)(~(value))))  argument
1645 #define ADC_TOG_CLM4(base, value) (BME_XOR32(&ADC_CLM4_REG(base), (uint32_t)(value)))  argument
1659 #define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)  argument
1660 #define ADC_BRD_CLM4_CLM4(base) (BME_UBFX32(&ADC_CLM4_REG(base), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4…  argument
1663 #define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))  argument
1664 #define ADC_BWR_CLM4_CLM4(base, value) (BME_BFI32(&ADC_CLM4_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1682 #define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))  argument
1683 #define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))  argument
1684 #define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))  argument
1685 #define ADC_SET_CLM3(base, value) (BME_OR32(&ADC_CLM3_REG(base), (uint32_t)(value)))  argument
1686 #define ADC_CLR_CLM3(base, value) (BME_AND32(&ADC_CLM3_REG(base), (uint32_t)(~(value))))  argument
1687 #define ADC_TOG_CLM3(base, value) (BME_XOR32(&ADC_CLM3_REG(base), (uint32_t)(value)))  argument
1701 #define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)  argument
1702 #define ADC_BRD_CLM3_CLM3(base) (BME_UBFX32(&ADC_CLM3_REG(base), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3…  argument
1705 #define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))  argument
1706 #define ADC_BWR_CLM3_CLM3(base, value) (BME_BFI32(&ADC_CLM3_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1724 #define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))  argument
1725 #define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))  argument
1726 #define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))  argument
1727 #define ADC_SET_CLM2(base, value) (BME_OR32(&ADC_CLM2_REG(base), (uint32_t)(value)))  argument
1728 #define ADC_CLR_CLM2(base, value) (BME_AND32(&ADC_CLM2_REG(base), (uint32_t)(~(value))))  argument
1729 #define ADC_TOG_CLM2(base, value) (BME_XOR32(&ADC_CLM2_REG(base), (uint32_t)(value)))  argument
1743 #define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)  argument
1744 #define ADC_BRD_CLM2_CLM2(base) (BME_UBFX32(&ADC_CLM2_REG(base), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2…  argument
1747 #define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))  argument
1748 #define ADC_BWR_CLM2_CLM2(base, value) (BME_BFI32(&ADC_CLM2_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1766 #define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))  argument
1767 #define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))  argument
1768 #define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))  argument
1769 #define ADC_SET_CLM1(base, value) (BME_OR32(&ADC_CLM1_REG(base), (uint32_t)(value)))  argument
1770 #define ADC_CLR_CLM1(base, value) (BME_AND32(&ADC_CLM1_REG(base), (uint32_t)(~(value))))  argument
1771 #define ADC_TOG_CLM1(base, value) (BME_XOR32(&ADC_CLM1_REG(base), (uint32_t)(value)))  argument
1785 #define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)  argument
1786 #define ADC_BRD_CLM1_CLM1(base) (BME_UBFX32(&ADC_CLM1_REG(base), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1…  argument
1789 #define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))  argument
1790 #define ADC_BWR_CLM1_CLM1(base, value) (BME_BFI32(&ADC_CLM1_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1808 #define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))  argument
1809 #define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))  argument
1810 #define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))  argument
1811 #define ADC_SET_CLM0(base, value) (BME_OR32(&ADC_CLM0_REG(base), (uint32_t)(value)))  argument
1812 #define ADC_CLR_CLM0(base, value) (BME_AND32(&ADC_CLM0_REG(base), (uint32_t)(~(value))))  argument
1813 #define ADC_TOG_CLM0(base, value) (BME_XOR32(&ADC_CLM0_REG(base), (uint32_t)(value)))  argument
1827 #define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)  argument
1828 #define ADC_BRD_CLM0_CLM0(base) (BME_UBFX32(&ADC_CLM0_REG(base), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0…  argument
1831 #define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))  argument
1832 #define ADC_BWR_CLM0_CLM0(base, value) (BME_BFI32(&ADC_CLM0_REG(base), ((uint32_t)(value) << ADC_CL…  argument
1863 #define BLE_RF_REGS_RD_BLE_PART_ID(base) (BLE_RF_REGS_BLE_PART_ID_REG(base))  argument
1879 #define BLE_RF_REGS_RD_DSM_STATUS(base) (BLE_RF_REGS_DSM_STATUS_REG(base))  argument
1895 #define BLE_RF_REGS_RD_DSM_STATUS_ORF_SYSCLK_REQ(base) ((BLE_RF_REGS_DSM_STATUS_REG(base) & BLE_RF_…  argument
1896 #define BLE_RF_REGS_BRD_DSM_STATUS_ORF_SYSCLK_REQ(base) (BME_UBFX16(&BLE_RF_REGS_DSM_STATUS_REG(bas…  argument
1909 #define BLE_RF_REGS_RD_DSM_STATUS_RIF_LL_ACTIVE(base) ((BLE_RF_REGS_DSM_STATUS_REG(base) & BLE_RF_R…  argument
1910 #define BLE_RF_REGS_BRD_DSM_STATUS_RIF_LL_ACTIVE(base) (BME_UBFX16(&BLE_RF_REGS_DSM_STATUS_REG(base…  argument
1926 #define BLE_RF_REGS_RD_BLE_AFC(base) (BLE_RF_REGS_BLE_AFC_REG(base))  argument
1927 #define BLE_RF_REGS_WR_BLE_AFC(base, value) (BLE_RF_REGS_BLE_AFC_REG(base) = (value))  argument
1928 #define BLE_RF_REGS_RMW_BLE_AFC(base, mask, value) (BLE_RF_REGS_WR_BLE_AFC(base, (BLE_RF_REGS_RD_BL…  argument
1929 #define BLE_RF_REGS_SET_BLE_AFC(base, value) (BME_OR16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(v…  argument
1930 #define BLE_RF_REGS_CLR_BLE_AFC(base, value) (BME_AND16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(…  argument
1931 #define BLE_RF_REGS_TOG_BLE_AFC(base, value) (BME_XOR16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(…  argument
1950 #define BLE_RF_REGS_RD_BLE_AFC_BLE_AFC(base) ((BLE_RF_REGS_BLE_AFC_REG(base) & BLE_RF_REGS_BLE_AFC_…  argument
1951 #define BLE_RF_REGS_BRD_BLE_AFC_BLE_AFC(base) (BME_UBFX16(&BLE_RF_REGS_BLE_AFC_REG(base), BLE_RF_RE…  argument
1964 #define BLE_RF_REGS_RD_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base) ((BLE_RF_REGS_BLE_AFC_REG(base) & BL…  argument
1965 #define BLE_RF_REGS_BRD_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base) (BME_UBFX16(&BLE_RF_REGS_BLE_AFC_RE…  argument
1968 #define BLE_RF_REGS_WR_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base, value) (BLE_RF_REGS_RMW_BLE_AFC(base…  argument
1969 #define BLE_RF_REGS_BWR_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base, value) (BME_BFI16(&BLE_RF_REGS_BLE_…  argument
1985 #define BLE_RF_REGS_RD_BLE_BSM(base) (BLE_RF_REGS_BLE_BSM_REG(base))  argument
1986 #define BLE_RF_REGS_WR_BLE_BSM(base, value) (BLE_RF_REGS_BLE_BSM_REG(base) = (value))  argument
1987 #define BLE_RF_REGS_RMW_BLE_BSM(base, mask, value) (BLE_RF_REGS_WR_BLE_BSM(base, (BLE_RF_REGS_RD_BL…  argument
1988 #define BLE_RF_REGS_SET_BLE_BSM(base, value) (BME_OR16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(v…  argument
1989 #define BLE_RF_REGS_CLR_BLE_BSM(base, value) (BME_AND16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(…  argument
1990 #define BLE_RF_REGS_TOG_BLE_BSM(base, value) (BME_XOR16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(…  argument
2010 #define BLE_RF_REGS_RD_BLE_BSM_BSM_EN_BLE(base) ((BLE_RF_REGS_BLE_BSM_REG(base) & BLE_RF_REGS_BLE_B…  argument
2011 #define BLE_RF_REGS_BRD_BLE_BSM_BSM_EN_BLE(base) (BME_UBFX16(&BLE_RF_REGS_BLE_BSM_REG(base), BLE_RF…  argument
2014 #define BLE_RF_REGS_WR_BLE_BSM_BSM_EN_BLE(base, value) (BLE_RF_REGS_RMW_BLE_BSM(base, BLE_RF_REGS_B…  argument
2015 #define BLE_RF_REGS_BWR_BLE_BSM_BSM_EN_BLE(base, value) (BME_BFI16(&BLE_RF_REGS_BLE_BSM_REG(base), …  argument
2048 #define CMP_RD_CR0(base)         (CMP_CR0_REG(base))  argument
2049 #define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))  argument
2050 #define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))  argument
2051 #define CMP_SET_CR0(base, value) (BME_OR8(&CMP_CR0_REG(base), (uint8_t)(value)))  argument
2052 #define CMP_CLR_CR0(base, value) (BME_AND8(&CMP_CR0_REG(base), (uint8_t)(~(value))))  argument
2053 #define CMP_TOG_CR0(base, value) (BME_XOR8(&CMP_CR0_REG(base), (uint8_t)(value)))  argument
2075 #define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHI…  argument
2076 #define CMP_BRD_CR0_HYSTCTR(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_HYSTCTR_SHIFT, CMP_CR0_HYS…  argument
2079 #define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(va…  argument
2080 #define CMP_BWR_CR0_HYSTCTR(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_CR0…  argument
2103 #define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTE…  argument
2104 #define CMP_BRD_CR0_FILTER_CNT(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_FILTER_CNT_SHIFT, CMP_C…  argument
2107 #define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILT…  argument
2108 #define CMP_BWR_CR0_FILTER_CNT(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_…  argument
2124 #define CMP_RD_CR1(base)         (CMP_CR1_REG(base))  argument
2125 #define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))  argument
2126 #define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))  argument
2127 #define CMP_SET_CR1(base, value) (BME_OR8(&CMP_CR1_REG(base), (uint8_t)(value)))  argument
2128 #define CMP_CLR_CR1(base, value) (BME_AND8(&CMP_CR1_REG(base), (uint8_t)(~(value))))  argument
2129 #define CMP_TOG_CR1(base, value) (BME_XOR8(&CMP_CR1_REG(base), (uint8_t)(value)))  argument
2150 #define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)  argument
2151 #define CMP_BRD_CR1_EN(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT, CMP_CR1_EN_WIDTH))  argument
2154 #define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))  argument
2155 #define CMP_BWR_CR1_EN(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_EN_S…  argument
2177 #define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)  argument
2178 #define CMP_BRD_CR1_OPE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT, CMP_CR1_OPE_WIDTH))  argument
2181 #define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))  argument
2182 #define CMP_BWR_CR1_OPE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_OPE…  argument
2194 #define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)  argument
2195 #define CMP_BRD_CR1_COS(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT, CMP_CR1_COS_WIDTH))  argument
2198 #define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))  argument
2199 #define CMP_BWR_CR1_COS(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_COS…  argument
2215 #define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)  argument
2216 #define CMP_BRD_CR1_INV(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT, CMP_CR1_INV_WIDTH))  argument
2219 #define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))  argument
2220 #define CMP_BWR_CR1_INV(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_INV…  argument
2236 #define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)  argument
2237 #define CMP_BRD_CR1_PMODE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT, CMP_CR1_PMODE_W…  argument
2240 #define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))  argument
2241 #define CMP_BWR_CR1_PMODE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_P…  argument
2261 #define CMP_RD_CR1_TRIGM(base) ((CMP_CR1_REG(base) & CMP_CR1_TRIGM_MASK) >> CMP_CR1_TRIGM_SHIFT)  argument
2262 #define CMP_BRD_CR1_TRIGM(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_TRIGM_SHIFT, CMP_CR1_TRIGM_W…  argument
2265 #define CMP_WR_CR1_TRIGM(base, value) (CMP_RMW_CR1(base, CMP_CR1_TRIGM_MASK, CMP_CR1_TRIGM(value)))  argument
2266 #define CMP_BWR_CR1_TRIGM(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_T…  argument
2281 #define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)  argument
2282 #define CMP_BRD_CR1_WE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT, CMP_CR1_WE_WIDTH))  argument
2285 #define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))  argument
2286 #define CMP_BWR_CR1_WE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_WE_S…  argument
2301 #define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)  argument
2302 #define CMP_BRD_CR1_SE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT, CMP_CR1_SE_WIDTH))  argument
2305 #define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))  argument
2306 #define CMP_BWR_CR1_SE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_SE_S…  argument
2322 #define CMP_RD_FPR(base)         (CMP_FPR_REG(base))  argument
2323 #define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))  argument
2324 #define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))  argument
2325 #define CMP_SET_FPR(base, value) (BME_OR8(&CMP_FPR_REG(base), (uint8_t)(value)))  argument
2326 #define CMP_CLR_FPR(base, value) (BME_AND8(&CMP_FPR_REG(base), (uint8_t)(~(value))))  argument
2327 #define CMP_TOG_FPR(base, value) (BME_XOR8(&CMP_FPR_REG(base), (uint8_t)(value)))  argument
2343 #define CMP_RD_SCR(base)         (CMP_SCR_REG(base))  argument
2344 #define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))  argument
2345 #define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))  argument
2346 #define CMP_SET_SCR(base, value) (BME_OR8(&CMP_SCR_REG(base), (uint8_t)(value)))  argument
2347 #define CMP_CLR_SCR(base, value) (BME_AND8(&CMP_SCR_REG(base), (uint8_t)(~(value))))  argument
2348 #define CMP_TOG_SCR(base, value) (BME_XOR8(&CMP_SCR_REG(base), (uint8_t)(value)))  argument
2364 #define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)  argument
2365 #define CMP_BRD_SCR_COUT(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT, CMP_SCR_COUT_WIDT…  argument
2380 #define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)  argument
2381 #define CMP_BRD_SCR_CFF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT, CMP_SCR_CFF_WIDTH))  argument
2384 #define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_S…  argument
2385 #define CMP_BWR_SCR_CFF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFF…  argument
2400 #define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)  argument
2401 #define CMP_BRD_SCR_CFR(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT, CMP_SCR_CFR_WIDTH))  argument
2404 #define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_S…  argument
2405 #define CMP_BWR_SCR_CFR(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFR…  argument
2420 #define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)  argument
2421 #define CMP_BRD_SCR_IEF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT, CMP_SCR_IEF_WIDTH))  argument
2424 #define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_S…  argument
2425 #define CMP_BWR_SCR_IEF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IEF…  argument
2440 #define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)  argument
2441 #define CMP_BRD_SCR_IER(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT, CMP_SCR_IER_WIDTH))  argument
2444 #define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_S…  argument
2445 #define CMP_BWR_SCR_IER(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IER…  argument
2460 #define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)  argument
2461 #define CMP_BRD_SCR_DMAEN(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT, CMP_SCR_DMAEN_W…  argument
2464 #define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | C…  argument
2465 #define CMP_BWR_SCR_DMAEN(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_D…  argument
2481 #define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))  argument
2482 #define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))  argument
2483 #define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (valu…  argument
2484 #define CMP_SET_DACCR(base, value) (BME_OR8(&CMP_DACCR_REG(base), (uint8_t)(value)))  argument
2485 #define CMP_CLR_DACCR(base, value) (BME_AND8(&CMP_DACCR_REG(base), (uint8_t)(~(value))))  argument
2486 #define CMP_TOG_DACCR(base, value) (BME_XOR8(&CMP_DACCR_REG(base), (uint8_t)(value)))  argument
2501 #define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_S…  argument
2502 #define CMP_BRD_DACCR_VOSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VOSEL_SHIFT, CMP_DACCR…  argument
2505 #define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(…  argument
2506 #define CMP_BWR_DACCR_VOSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_D…  argument
2518 #define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_S…  argument
2519 #define CMP_BRD_DACCR_VRSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT, CMP_DACCR…  argument
2522 #define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(…  argument
2523 #define CMP_BWR_DACCR_VRSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_D…  argument
2538 #define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_S…  argument
2539 #define CMP_BRD_DACCR_DACEN(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT, CMP_DACCR…  argument
2542 #define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(…  argument
2543 #define CMP_BWR_DACCR_DACEN(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_D…  argument
2559 #define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))  argument
2560 #define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))  argument
2561 #define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (valu…  argument
2562 #define CMP_SET_MUXCR(base, value) (BME_OR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))  argument
2563 #define CMP_CLR_MUXCR(base, value) (BME_AND8(&CMP_MUXCR_REG(base), (uint8_t)(~(value))))  argument
2564 #define CMP_TOG_MUXCR(base, value) (BME_XOR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))  argument
2591 #define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIF…  argument
2592 #define CMP_BRD_MUXCR_MSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_MSEL_SHIFT, CMP_MUXCR_M…  argument
2595 #define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(val…  argument
2596 #define CMP_BWR_MUXCR_MSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MU…  argument
2619 #define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIF…  argument
2620 #define CMP_BRD_MUXCR_PSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSEL_SHIFT, CMP_MUXCR_P…  argument
2623 #define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(val…  argument
2624 #define CMP_BWR_MUXCR_PSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MU…  argument
2640 #define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIF…  argument
2641 #define CMP_BRD_MUXCR_PSTM(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT, CMP_MUXCR_P…  argument
2644 #define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(val…  argument
2645 #define CMP_BWR_MUXCR_PSTM(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MU…  argument
2687 #define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))  argument
2688 #define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))  argument
2689 #define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))  argument
2690 #define CMT_SET_CGH1(base, value) (BME_OR8(&CMT_CGH1_REG(base), (uint8_t)(value)))  argument
2691 #define CMT_CLR_CGH1(base, value) (BME_AND8(&CMT_CGH1_REG(base), (uint8_t)(~(value))))  argument
2692 #define CMT_TOG_CGH1(base, value) (BME_XOR8(&CMT_CGH1_REG(base), (uint8_t)(value)))  argument
2711 #define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))  argument
2712 #define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))  argument
2713 #define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))  argument
2714 #define CMT_SET_CGL1(base, value) (BME_OR8(&CMT_CGL1_REG(base), (uint8_t)(value)))  argument
2715 #define CMT_CLR_CGL1(base, value) (BME_AND8(&CMT_CGL1_REG(base), (uint8_t)(~(value))))  argument
2716 #define CMT_TOG_CGL1(base, value) (BME_XOR8(&CMT_CGL1_REG(base), (uint8_t)(value)))  argument
2735 #define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))  argument
2736 #define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))  argument
2737 #define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))  argument
2738 #define CMT_SET_CGH2(base, value) (BME_OR8(&CMT_CGH2_REG(base), (uint8_t)(value)))  argument
2739 #define CMT_CLR_CGH2(base, value) (BME_AND8(&CMT_CGH2_REG(base), (uint8_t)(~(value))))  argument
2740 #define CMT_TOG_CGH2(base, value) (BME_XOR8(&CMT_CGH2_REG(base), (uint8_t)(value)))  argument
2759 #define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))  argument
2760 #define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))  argument
2761 #define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))  argument
2762 #define CMT_SET_CGL2(base, value) (BME_OR8(&CMT_CGL2_REG(base), (uint8_t)(value)))  argument
2763 #define CMT_CLR_CGL2(base, value) (BME_AND8(&CMT_CGL2_REG(base), (uint8_t)(~(value))))  argument
2764 #define CMT_TOG_CGL2(base, value) (BME_XOR8(&CMT_CGL2_REG(base), (uint8_t)(value)))  argument
2782 #define CMT_RD_OC(base)          (CMT_OC_REG(base))  argument
2783 #define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))  argument
2784 #define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))  argument
2785 #define CMT_SET_OC(base, value)  (BME_OR8(&CMT_OC_REG(base), (uint8_t)(value)))  argument
2786 #define CMT_CLR_OC(base, value)  (BME_AND8(&CMT_OC_REG(base), (uint8_t)(~(value))))  argument
2787 #define CMT_TOG_OC(base, value)  (BME_XOR8(&CMT_OC_REG(base), (uint8_t)(value)))  argument
2810 #define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)  argument
2811 #define CMT_BRD_OC_IROPEN(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT, CMT_OC_IROPEN_WI…  argument
2814 #define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))  argument
2815 #define CMT_BWR_OC_IROPEN(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_IRO…  argument
2829 #define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)  argument
2830 #define CMT_BRD_OC_CMTPOL(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT, CMT_OC_CMTPOL_WI…  argument
2833 #define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))  argument
2834 #define CMT_BWR_OC_CMTPOL(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_CMT…  argument
2845 #define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)  argument
2846 #define CMT_BRD_OC_IROL(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT, CMT_OC_IROL_WIDTH))  argument
2849 #define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))  argument
2850 #define CMT_BWR_OC_IROL(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_IROL_…  argument
2871 #define CMT_RD_MSC(base)         (CMT_MSC_REG(base))  argument
2872 #define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))  argument
2873 #define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))  argument
2874 #define CMT_SET_MSC(base, value) (BME_OR8(&CMT_MSC_REG(base), (uint8_t)(value)))  argument
2875 #define CMT_CLR_MSC(base, value) (BME_AND8(&CMT_MSC_REG(base), (uint8_t)(~(value))))  argument
2876 #define CMT_TOG_MSC(base, value) (BME_XOR8(&CMT_MSC_REG(base), (uint8_t)(value)))  argument
2900 #define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)  argument
2901 #define CMT_BRD_MSC_MCGEN(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT, CMT_MSC_MCGEN_W…  argument
2904 #define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))  argument
2905 #define CMT_BWR_MSC_MCGEN(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_M…  argument
2919 #define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)  argument
2920 #define CMT_BRD_MSC_EOCIE(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT, CMT_MSC_EOCIE_W…  argument
2923 #define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))  argument
2924 #define CMT_BWR_MSC_EOCIE(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_E…  argument
2938 #define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)  argument
2939 #define CMT_BRD_MSC_FSK(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT, CMT_MSC_FSK_WIDTH))  argument
2942 #define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))  argument
2943 #define CMT_BWR_MSC_FSK(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_FSK…  argument
2962 #define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)  argument
2963 #define CMT_BRD_MSC_BASE(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT, CMT_MSC_BASE_WIDT…  argument
2966 #define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))  argument
2967 #define CMT_BWR_MSC_BASE(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_BA…  argument
2981 #define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)  argument
2982 #define CMT_BRD_MSC_EXSPC(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT, CMT_MSC_EXSPC_W…  argument
2985 #define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))  argument
2986 #define CMT_BWR_MSC_EXSPC(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_E…  argument
3004 #define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)  argument
3005 #define CMT_BRD_MSC_CMTDIV(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_CMTDIV_SHIFT, CMT_MSC_CMTDI…  argument
3008 #define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value…  argument
3009 #define CMT_BWR_MSC_CMTDIV(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_…  argument
3030 #define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)  argument
3031 #define CMT_BRD_MSC_EOCF(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT, CMT_MSC_EOCF_WIDT…  argument
3050 #define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))  argument
3051 #define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))  argument
3052 #define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))  argument
3053 #define CMT_SET_CMD1(base, value) (BME_OR8(&CMT_CMD1_REG(base), (uint8_t)(value)))  argument
3054 #define CMT_CLR_CMD1(base, value) (BME_AND8(&CMT_CMD1_REG(base), (uint8_t)(~(value))))  argument
3055 #define CMT_TOG_CMD1(base, value) (BME_XOR8(&CMT_CMD1_REG(base), (uint8_t)(value)))  argument
3074 #define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))  argument
3075 #define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))  argument
3076 #define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))  argument
3077 #define CMT_SET_CMD2(base, value) (BME_OR8(&CMT_CMD2_REG(base), (uint8_t)(value)))  argument
3078 #define CMT_CLR_CMD2(base, value) (BME_AND8(&CMT_CMD2_REG(base), (uint8_t)(~(value))))  argument
3079 #define CMT_TOG_CMD2(base, value) (BME_XOR8(&CMT_CMD2_REG(base), (uint8_t)(value)))  argument
3098 #define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))  argument
3099 #define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))  argument
3100 #define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))  argument
3101 #define CMT_SET_CMD3(base, value) (BME_OR8(&CMT_CMD3_REG(base), (uint8_t)(value)))  argument
3102 #define CMT_CLR_CMD3(base, value) (BME_AND8(&CMT_CMD3_REG(base), (uint8_t)(~(value))))  argument
3103 #define CMT_TOG_CMD3(base, value) (BME_XOR8(&CMT_CMD3_REG(base), (uint8_t)(value)))  argument
3122 #define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))  argument
3123 #define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))  argument
3124 #define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))  argument
3125 #define CMT_SET_CMD4(base, value) (BME_OR8(&CMT_CMD4_REG(base), (uint8_t)(value)))  argument
3126 #define CMT_CLR_CMD4(base, value) (BME_AND8(&CMT_CMD4_REG(base), (uint8_t)(~(value))))  argument
3127 #define CMT_TOG_CMD4(base, value) (BME_XOR8(&CMT_CMD4_REG(base), (uint8_t)(value)))  argument
3145 #define CMT_RD_PPS(base)         (CMT_PPS_REG(base))  argument
3146 #define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))  argument
3147 #define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))  argument
3148 #define CMT_SET_PPS(base, value) (BME_OR8(&CMT_PPS_REG(base), (uint8_t)(value)))  argument
3149 #define CMT_CLR_PPS(base, value) (BME_AND8(&CMT_PPS_REG(base), (uint8_t)(~(value))))  argument
3150 #define CMT_TOG_PPS(base, value) (BME_XOR8(&CMT_PPS_REG(base), (uint8_t)(value)))  argument
3183 #define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)  argument
3184 #define CMT_BRD_PPS_PPSDIV(base) (BME_UBFX8(&CMT_PPS_REG(base), CMT_PPS_PPSDIV_SHIFT, CMT_PPS_PPSDI…  argument
3187 #define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value…  argument
3188 #define CMT_BWR_PPS_PPSDIV(base, value) (BME_BFI8(&CMT_PPS_REG(base), ((uint8_t)(value) << CMT_PPS_…  argument
3206 #define CMT_RD_DMA(base)         (CMT_DMA_REG(base))  argument
3207 #define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))  argument
3208 #define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))  argument
3209 #define CMT_SET_DMA(base, value) (BME_OR8(&CMT_DMA_REG(base), (uint8_t)(value)))  argument
3210 #define CMT_CLR_DMA(base, value) (BME_AND8(&CMT_DMA_REG(base), (uint8_t)(~(value))))  argument
3211 #define CMT_TOG_DMA(base, value) (BME_XOR8(&CMT_DMA_REG(base), (uint8_t)(value)))  argument
3229 #define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)  argument
3230 #define CMT_BRD_DMA_DMA(base) (BME_UBFX8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT, CMT_DMA_DMA_WIDTH))  argument
3233 #define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))  argument
3234 #define CMT_BWR_DMA_DMA(base, value) (BME_BFI8(&CMT_DMA_REG(base), ((uint8_t)(value) << CMT_DMA_DMA…  argument
3267 #define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))  argument
3268 #define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))  argument
3269 #define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) …  argument
3270 #define DAC_SET_DATL(base, index, value) (BME_OR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))  argument
3271 #define DAC_CLR_DATL(base, index, value) (BME_AND8(&DAC_DATL_REG(base, index), (uint8_t)(~(value))))  argument
3272 #define DAC_TOG_DATL(base, index, value) (BME_XOR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))  argument
3288 #define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))  argument
3289 #define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))  argument
3290 #define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) …  argument
3291 #define DAC_SET_DATH(base, index, value) (BME_OR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))  argument
3292 #define DAC_CLR_DATH(base, index, value) (BME_AND8(&DAC_DATH_REG(base, index), (uint8_t)(~(value))))  argument
3293 #define DAC_TOG_DATH(base, index, value) (BME_XOR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))  argument
3309 #define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DA…  argument
3310 #define DAC_BRD_DATH_DATA1(base, index) (BME_UBFX8(&DAC_DATH_REG(base, index), DAC_DATH_DATA1_SHIFT…  argument
3313 #define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_D…  argument
3314 #define DAC_BWR_DATH_DATA1(base, index, value) (BME_BFI8(&DAC_DATH_REG(base, index), ((uint8_t)(val…  argument
3336 #define DAC_RD_SR(base)          (DAC_SR_REG(base))  argument
3337 #define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))  argument
3338 #define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))  argument
3339 #define DAC_SET_SR(base, value)  (BME_OR8(&DAC_SR_REG(base), (uint8_t)(value)))  argument
3340 #define DAC_CLR_SR(base, value)  (BME_AND8(&DAC_SR_REG(base), (uint8_t)(~(value))))  argument
3341 #define DAC_TOG_SR(base, value)  (BME_XOR8(&DAC_SR_REG(base), (uint8_t)(value)))  argument
3357 #define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_S…  argument
3358 #define DAC_BRD_SR_DACBFRPBF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT, DAC_SR_DAC…  argument
3361 #define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(…  argument
3362 #define DAC_BWR_SR_DACBFRPBF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_…  argument
3374 #define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_S…  argument
3375 #define DAC_BRD_SR_DACBFRPTF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT, DAC_SR_DAC…  argument
3378 #define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(…  argument
3379 #define DAC_BWR_SR_DACBFRPTF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_…  argument
3397 #define DAC_RD_C0(base)          (DAC_C0_REG(base))  argument
3398 #define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))  argument
3399 #define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))  argument
3400 #define DAC_SET_C0(base, value)  (BME_OR8(&DAC_C0_REG(base), (uint8_t)(value)))  argument
3401 #define DAC_CLR_C0(base, value)  (BME_AND8(&DAC_C0_REG(base), (uint8_t)(~(value))))  argument
3402 #define DAC_TOG_C0(base, value)  (BME_XOR8(&DAC_C0_REG(base), (uint8_t)(value)))  argument
3418 #define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIF…  argument
3419 #define DAC_BRD_C0_DACBBIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT, DAC_C0_DACBB…  argument
3422 #define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(val…  argument
3423 #define DAC_BWR_C0_DACBBIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_D…  argument
3435 #define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIF…  argument
3436 #define DAC_BRD_C0_DACBTIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT, DAC_C0_DACBT…  argument
3439 #define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(val…  argument
3440 #define DAC_BWR_C0_DACBTIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_D…  argument
3455 #define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)  argument
3456 #define DAC_BRD_C0_LPEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT, DAC_C0_LPEN_WIDTH))  argument
3459 #define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))  argument
3460 #define DAC_BWR_C0_LPEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_LPEN_…  argument
3476 #define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(val…  argument
3477 #define DAC_BWR_C0_DACSWTRG(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_D…  argument
3489 #define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_S…  argument
3490 #define DAC_BRD_C0_DACTRGSEL(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT, DAC_C0_DAC…  argument
3493 #define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(…  argument
3494 #define DAC_BWR_C0_DACTRGSEL(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_…  argument
3506 #define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)  argument
3507 #define DAC_BRD_C0_DACRFS(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT, DAC_C0_DACRFS_WI…  argument
3510 #define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))  argument
3511 #define DAC_BWR_C0_DACRFS(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DAC…  argument
3525 #define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)  argument
3526 #define DAC_BRD_C0_DACEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT, DAC_C0_DACEN_WIDTH…  argument
3529 #define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))  argument
3530 #define DAC_BWR_C0_DACEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACE…  argument
3548 #define DAC_RD_C1(base)          (DAC_C1_REG(base))  argument
3549 #define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))  argument
3550 #define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))  argument
3551 #define DAC_SET_C1(base, value)  (BME_OR8(&DAC_C1_REG(base), (uint8_t)(value)))  argument
3552 #define DAC_CLR_C1(base, value)  (BME_AND8(&DAC_C1_REG(base), (uint8_t)(~(value))))  argument
3553 #define DAC_TOG_C1(base, value)  (BME_XOR8(&DAC_C1_REG(base), (uint8_t)(value)))  argument
3572 #define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)  argument
3573 #define DAC_BRD_C1_DACBFEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT, DAC_C1_DACBFEN…  argument
3576 #define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)…  argument
3577 #define DAC_BWR_C1_DACBFEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DA…  argument
3589 #define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)  argument
3590 #define DAC_BRD_C1_DACBFMD(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFMD_SHIFT, DAC_C1_DACBFMD…  argument
3593 #define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)…  argument
3594 #define DAC_BWR_C1_DACBFMD(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DA…  argument
3608 #define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)  argument
3609 #define DAC_BRD_C1_DMAEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT, DAC_C1_DMAEN_WIDTH…  argument
3612 #define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))  argument
3613 #define DAC_BWR_C1_DMAEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DMAE…  argument
3629 #define DAC_RD_C2(base)          (DAC_C2_REG(base))  argument
3630 #define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))  argument
3631 #define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))  argument
3632 #define DAC_SET_C2(base, value)  (BME_OR8(&DAC_C2_REG(base), (uint8_t)(value)))  argument
3633 #define DAC_CLR_C2(base, value)  (BME_AND8(&DAC_C2_REG(base), (uint8_t)(~(value))))  argument
3634 #define DAC_TOG_C2(base, value)  (BME_XOR8(&DAC_C2_REG(base), (uint8_t)(value)))  argument
3649 #define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)  argument
3650 #define DAC_BRD_C2_DACBFUP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFUP_SHIFT, DAC_C2_DACBFUP…  argument
3653 #define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)…  argument
3654 #define DAC_BWR_C2_DACBFUP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DA…  argument
3664 #define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)  argument
3665 #define DAC_BRD_C2_DACBFRP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFRP_SHIFT, DAC_C2_DACBFRP…  argument
3668 #define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)…  argument
3669 #define DAC_BWR_C2_DACBFRP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DA…  argument
3703 #define DCDC_RD_REG0(base)       (DCDC_REG0_REG(base))  argument
3704 #define DCDC_WR_REG0(base, value) (DCDC_REG0_REG(base) = (value))  argument
3705 #define DCDC_RMW_REG0(base, mask, value) (DCDC_WR_REG0(base, (DCDC_RD_REG0(base) & ~(mask)) | (valu…  argument
3706 #define DCDC_SET_REG0(base, value) (BME_OR32(&DCDC_REG0_REG(base), (uint32_t)(value)))  argument
3707 #define DCDC_CLR_REG0(base, value) (BME_AND32(&DCDC_REG0_REG(base), (uint32_t)(~(value))))  argument
3708 #define DCDC_TOG_REG0(base, value) (BME_XOR32(&DCDC_REG0_REG(base), (uint32_t)(value)))  argument
3722 #define DCDC_RD_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_DISA…  argument
3723 #define DCDC_BRD_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG…  argument
3726 #define DCDC_WR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_…  argument
3727 #define DCDC_BWR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((…  argument
3737 #define DCDC_RD_REG0_DCDC_SEL_CLK(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_SEL_CLK_MASK) >> DCD…  argument
3738 #define DCDC_BRD_REG0_DCDC_SEL_CLK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_SEL_CLK_S…  argument
3741 #define DCDC_WR_REG0_DCDC_SEL_CLK(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_SEL_CLK_MASK, DC…  argument
3742 #define DCDC_BWR_REG0_DCDC_SEL_CLK(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value)…  argument
3753 #define DCDC_RD_REG0_DCDC_PWD_OSC_INT(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK…  argument
3754 #define DCDC_BRD_REG0_DCDC_PWD_OSC_INT(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_PWD_O…  argument
3757 #define DCDC_WR_REG0_DCDC_PWD_OSC_INT(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_PWD_OSC_INT_…  argument
3758 #define DCDC_BWR_REG0_DCDC_PWD_OSC_INT(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(va…  argument
3769 #define DCDC_RD_REG0_DCDC_LP_DF_CMP_ENABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_DF_CMP_E…  argument
3770 #define DCDC_BRD_REG0_DCDC_LP_DF_CMP_ENABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_…  argument
3773 #define DCDC_WR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_DF_C…  argument
3774 #define DCDC_BWR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_…  argument
3785 #define DCDC_RD_REG0_DCDC_VBAT_DIV_CTRL(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_…  argument
3786 #define DCDC_BRD_REG0_DCDC_VBAT_DIV_CTRL(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_VBA…  argument
3789 #define DCDC_WR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_VBAT_DIV_C…  argument
3790 #define DCDC_BWR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(…  argument
3807 #define DCDC_RD_REG0_DCDC_LP_STATE_HYS_L(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_STATE_HYS_…  argument
3808 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_L(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP…  argument
3811 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_L(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_…  argument
3812 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_L(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…  argument
3829 #define DCDC_RD_REG0_DCDC_LP_STATE_HYS_H(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_STATE_HYS_…  argument
3830 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_H(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP…  argument
3833 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_H(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_…  argument
3834 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_H(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…  argument
3844 #define DCDC_RD_REG0_HYST_LP_COMP_ADJ(base) ((DCDC_REG0_REG(base) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK…  argument
3845 #define DCDC_BRD_REG0_HYST_LP_COMP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP_CO…  argument
3848 #define DCDC_WR_REG0_HYST_LP_COMP_ADJ(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_COMP_ADJ_…  argument
3849 #define DCDC_BWR_REG0_HYST_LP_COMP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(va…  argument
3859 #define DCDC_RD_REG0_HYST_LP_CMP_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_HYST_LP_CMP_DISABL…  argument
3860 #define DCDC_BRD_REG0_HYST_LP_CMP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP…  argument
3863 #define DCDC_WR_REG0_HYST_LP_CMP_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_CMP_DI…  argument
3864 #define DCDC_BWR_REG0_HYST_LP_CMP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…  argument
3874 #define DCDC_RD_REG0_OFFSET_RSNS_LP_ADJ(base) ((DCDC_REG0_REG(base) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_…  argument
3875 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFSET_R…  argument
3878 #define DCDC_WR_REG0_OFFSET_RSNS_LP_ADJ(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_OFFSET_RSNS_LP_…  argument
3879 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(…  argument
3889 #define DCDC_RD_REG0_OFFSET_RSNS_LP_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_OFFSET_RSNS_LP_…  argument
3890 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFS…  argument
3893 #define DCDC_WR_REG0_OFFSET_RSNS_LP_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_OFFSET_RSNS…  argument
3894 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32…  argument
3904 #define DCDC_RD_REG0_DCDC_LESS_I(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LESS_I_MASK) >> DCDC_…  argument
3905 #define DCDC_BRD_REG0_DCDC_LESS_I(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LESS_I_SHI…  argument
3908 #define DCDC_WR_REG0_DCDC_LESS_I(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LESS_I_MASK, DCDC…  argument
3909 #define DCDC_BWR_REG0_DCDC_LESS_I(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) …  argument
3919 #define DCDC_RD_REG0_PWD_CMP_OFFSET(base) ((DCDC_REG0_REG(base) & DCDC_REG0_PWD_CMP_OFFSET_MASK) >>…  argument
3920 #define DCDC_BRD_REG0_PWD_CMP_OFFSET(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PWD_CMP_OFFS…  argument
3923 #define DCDC_WR_REG0_PWD_CMP_OFFSET(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_PWD_CMP_OFFSET_MASK…  argument
3924 #define DCDC_BWR_REG0_PWD_CMP_OFFSET(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(valu…  argument
3934 #define DCDC_RD_REG0_DCDC_XTALOK_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_XTALOK_DISABL…  argument
3935 #define DCDC_BRD_REG0_DCDC_XTALOK_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_XT…  argument
3938 #define DCDC_WR_REG0_DCDC_XTALOK_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_XTALOK_DI…  argument
3939 #define DCDC_BWR_REG0_DCDC_XTALOK_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…  argument
3949 #define DCDC_RD_REG0_PSWITCH_STATUS(base) ((DCDC_REG0_REG(base) & DCDC_REG0_PSWITCH_STATUS_MASK) >>…  argument
3950 #define DCDC_BRD_REG0_PSWITCH_STATUS(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PSWITCH_STAT…  argument
3961 #define DCDC_RD_REG0_VLPS_CONFIG_DCDC_HP(base) ((DCDC_REG0_REG(base) & DCDC_REG0_VLPS_CONFIG_DCDC_H…  argument
3962 #define DCDC_BRD_REG0_VLPS_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VLPS_CO…  argument
3965 #define DCDC_WR_REG0_VLPS_CONFIG_DCDC_HP(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_VLPS_CONFIG_DC…  argument
3966 #define DCDC_BWR_REG0_VLPS_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)…  argument
3978 #define DCDC_RD_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base) ((DCDC_REG0_REG(base) & DCDC_REG0_VLPR_VLPW_CON…  argument
3979 #define DCDC_BRD_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VL…  argument
3982 #define DCDC_WR_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_VLPR_VLPW…  argument
3983 #define DCDC_BWR_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint…  argument
3996 #define DCDC_RD_REG0_DCDC_STS_DC_OK(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_STS_DC_OK_MASK) >>…  argument
3997 #define DCDC_BRD_REG0_DCDC_STS_DC_OK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_STS_DC_…  argument
4013 #define DCDC_RD_REG1(base)       (DCDC_REG1_REG(base))  argument
4014 #define DCDC_WR_REG1(base, value) (DCDC_REG1_REG(base) = (value))  argument
4015 #define DCDC_RMW_REG1(base, mask, value) (DCDC_WR_REG1(base, (DCDC_RD_REG1(base) & ~(mask)) | (valu…  argument
4016 #define DCDC_SET_REG1(base, value) (BME_OR32(&DCDC_REG1_REG(base), (uint32_t)(value)))  argument
4017 #define DCDC_CLR_REG1(base, value) (BME_AND32(&DCDC_REG1_REG(base), (uint32_t)(~(value))))  argument
4018 #define DCDC_TOG_REG1(base, value) (BME_XOR32(&DCDC_REG1_REG(base), (uint32_t)(value)))  argument
4034 #define DCDC_RD_REG1_POSLIMIT_BUCK_IN(base) ((DCDC_REG1_REG(base) & DCDC_REG1_POSLIMIT_BUCK_IN_MASK…  argument
4035 #define DCDC_BRD_REG1_POSLIMIT_BUCK_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_B…  argument
4038 #define DCDC_WR_REG1_POSLIMIT_BUCK_IN(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_POSLIMIT_BUCK_IN_…  argument
4039 #define DCDC_BWR_REG1_POSLIMIT_BUCK_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(va…  argument
4051 #define DCDC_RD_REG1_POSLIMIT_BOOST_IN(base) ((DCDC_REG1_REG(base) & DCDC_REG1_POSLIMIT_BOOST_IN_MA…  argument
4052 #define DCDC_BRD_REG1_POSLIMIT_BOOST_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_…  argument
4055 #define DCDC_WR_REG1_POSLIMIT_BOOST_IN(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_POSLIMIT_BOOST_I…  argument
4056 #define DCDC_BWR_REG1_POSLIMIT_BOOST_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(v…  argument
4067 #define DCDC_RD_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPC…  argument
4068 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1…  argument
4071 #define DCDC_WR_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_L…  argument
4072 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((u…  argument
4083 #define DCDC_RD_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPC…  argument
4084 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1…  argument
4087 #define DCDC_WR_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_L…  argument
4088 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((u…  argument
4099 #define DCDC_RD_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL…  argument
4100 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DC…  argument
4103 #define DCDC_WR_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOP…  argument
4104 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint…  argument
4115 #define DCDC_RD_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL…  argument
4116 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DC…  argument
4119 #define DCDC_WR_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOP…  argument
4120 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint…  argument
4136 #define DCDC_RD_REG2(base)       (DCDC_REG2_REG(base))  argument
4137 #define DCDC_WR_REG2(base, value) (DCDC_REG2_REG(base) = (value))  argument
4138 #define DCDC_RMW_REG2(base, mask, value) (DCDC_WR_REG2(base, (DCDC_RD_REG2(base) & ~(mask)) | (valu…  argument
4139 #define DCDC_SET_REG2(base, value) (BME_OR32(&DCDC_REG2_REG(base), (uint32_t)(value)))  argument
4140 #define DCDC_CLR_REG2(base, value) (BME_AND32(&DCDC_REG2_REG(base), (uint32_t)(~(value))))  argument
4141 #define DCDC_TOG_REG2(base, value) (BME_XOR32(&DCDC_REG2_REG(base), (uint32_t)(value)))  argument
4157 #define DCDC_RD_REG2_DCDC_LOOPCTRL_DC_C(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_DC_C_…  argument
4158 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_C(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOO…  argument
4161 #define DCDC_WR_REG2_DCDC_LOOPCTRL_DC_C(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_D…  argument
4162 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_C(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(…  argument
4176 #define DCDC_RD_REG2_DCDC_LOOPCTRL_DC_FF(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_DC_F…  argument
4177 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_FF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LO…  argument
4180 #define DCDC_WR_REG2_DCDC_LOOPCTRL_DC_FF(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_…  argument
4181 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_FF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)…  argument
4192 #define DCDC_RD_REG2_DCDC_LOOPCTRL_HYST_SIGN(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_…  argument
4193 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_HYST_SIGN(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCD…  argument
4196 #define DCDC_WR_REG2_DCDC_LOOPCTRL_HYST_SIGN(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPC…  argument
4197 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_HYST_SIGN(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint3…  argument
4209 #define DCDC_RD_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL…  argument
4210 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DC…  argument
4213 #define DCDC_WR_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOP…  argument
4214 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint…  argument
4226 #define DCDC_RD_REG2_DCDC_BATTMONITOR_EN_BATADJ(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_BATTMO…  argument
4227 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_EN_BATADJ(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_…  argument
4230 #define DCDC_WR_REG2_DCDC_BATTMONITOR_EN_BATADJ(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_BA…  argument
4231 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_EN_BATADJ(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((ui…  argument
4243 #define DCDC_RD_REG2_DCDC_BATTMONITOR_BATT_VAL(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_BATTMON…  argument
4244 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_BATT_VAL(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_D…  argument
4247 #define DCDC_WR_REG2_DCDC_BATTMONITOR_BATT_VAL(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_BAT…  argument
4248 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_BATT_VAL(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uin…  argument
4264 #define DCDC_RD_REG3(base)       (DCDC_REG3_REG(base))  argument
4265 #define DCDC_WR_REG3(base, value) (DCDC_REG3_REG(base) = (value))  argument
4266 #define DCDC_RMW_REG3(base, mask, value) (DCDC_WR_REG3(base, (DCDC_RD_REG3(base) & ~(mask)) | (valu…  argument
4267 #define DCDC_SET_REG3(base, value) (BME_OR32(&DCDC_REG3_REG(base), (uint32_t)(value)))  argument
4268 #define DCDC_CLR_REG3(base, value) (BME_AND32(&DCDC_REG3_REG(base), (uint32_t)(~(value))))  argument
4269 #define DCDC_TOG_REG3(base, value) (BME_XOR32(&DCDC_REG3_REG(base), (uint32_t)(value)))  argument
4292 #define DCDC_RD_REG3_DCDC_VDD1P8CTRL_TRG(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P8CTRL_TR…  argument
4293 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_TRG(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VD…  argument
4296 #define DCDC_WR_REG3_DCDC_VDD1P8CTRL_TRG(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P8CTR…  argument
4297 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_TRG(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)…  argument
4312 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45…  argument
4313 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_D…  argument
4316 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD…  argument
4317 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uin…  argument
4337 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P4…  argument
4338 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_…  argument
4341 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VD…  argument
4342 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((ui…  argument
4353 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_ADJTN(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45CTR…  argument
4354 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_ADJTN(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC…  argument
4357 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_ADJTN(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P4…  argument
4358 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_ADJTN(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32…  argument
4368 #define DCDC_RD_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPW…  argument
4369 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3…  argument
4372 #define DCDC_WR_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_M…  argument
4373 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((u…  argument
4383 #define DCDC_RD_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINP…  argument
4384 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG…  argument
4387 #define DCDC_WR_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_…  argument
4388 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((…  argument
4398 #define DCDC_RD_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR…  argument
4399 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_…  argument
4402 #define DCDC_WR_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MI…  argument
4403 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((ui…  argument
4413 #define DCDC_RD_REG3_DCDC_MINPWR_DC_HALFCLK(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DC_…  argument
4414 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC…  argument
4417 #define DCDC_WR_REG3_DCDC_MINPWR_DC_HALFCLK(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR…  argument
4418 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32…  argument
4428 #define DCDC_RD_REG3_DCDC_MINPWR_DOUBLE_FETS(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DO…  argument
4429 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCD…  argument
4432 #define DCDC_WR_REG3_DCDC_MINPWR_DOUBLE_FETS(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPW…  argument
4433 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint3…  argument
4443 #define DCDC_RD_REG3_DCDC_MINPWR_HALF_FETS(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_HALF…  argument
4444 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_…  argument
4447 #define DCDC_WR_REG3_DCDC_MINPWR_HALF_FETS(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_…  argument
4448 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_…  argument
4458 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD…  argument
4459 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_RE…  argument
4462 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC…  argument
4463 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), (…  argument
4473 #define DCDC_RD_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1…  argument
4474 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG…  argument
4477 #define DCDC_WR_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_…  argument
4478 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((…  argument
4494 #define DCDC_RD_REG4(base)       (DCDC_REG4_REG(base))  argument
4495 #define DCDC_WR_REG4(base, value) (DCDC_REG4_REG(base) = (value))  argument
4496 #define DCDC_RMW_REG4(base, mask, value) (DCDC_WR_REG4(base, (DCDC_RD_REG4(base) & ~(mask)) | (valu…  argument
4497 #define DCDC_SET_REG4(base, value) (BME_OR32(&DCDC_REG4_REG(base), (uint32_t)(value)))  argument
4498 #define DCDC_CLR_REG4(base, value) (BME_AND32(&DCDC_REG4_REG(base), (uint32_t)(~(value))))  argument
4499 #define DCDC_TOG_REG4(base, value) (BME_XOR32(&DCDC_REG4_REG(base), (uint32_t)(value)))  argument
4511 #define DCDC_RD_REG4_DCDC_SW_SHUTDOWN(base) ((DCDC_REG4_REG(base) & DCDC_REG4_DCDC_SW_SHUTDOWN_MASK…  argument
4512 #define DCDC_BRD_REG4_DCDC_SW_SHUTDOWN(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_DCDC_SW_SH…  argument
4515 #define DCDC_WR_REG4_DCDC_SW_SHUTDOWN(base, value) (DCDC_RMW_REG4(base, DCDC_REG4_DCDC_SW_SHUTDOWN_…  argument
4516 #define DCDC_BWR_REG4_DCDC_SW_SHUTDOWN(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(va…  argument
4530 #define DCDC_RD_REG4_UNLOCK(base) ((DCDC_REG4_REG(base) & DCDC_REG4_UNLOCK_MASK) >> DCDC_REG4_UNLOC…  argument
4531 #define DCDC_BRD_REG4_UNLOCK(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_UNLOCK_SHIFT, DCDC_R…  argument
4534 #define DCDC_WR_REG4_UNLOCK(base, value) (DCDC_RMW_REG4(base, DCDC_REG4_UNLOCK_MASK, DCDC_REG4_UNLO…  argument
4535 #define DCDC_BWR_REG4_UNLOCK(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(value) << DC…  argument
4551 #define DCDC_RD_REG6(base)       (DCDC_REG6_REG(base))  argument
4552 #define DCDC_WR_REG6(base, value) (DCDC_REG6_REG(base) = (value))  argument
4553 #define DCDC_RMW_REG6(base, mask, value) (DCDC_WR_REG6(base, (DCDC_RD_REG6(base) & ~(mask)) | (valu…  argument
4554 #define DCDC_SET_REG6(base, value) (BME_OR32(&DCDC_REG6_REG(base), (uint32_t)(value)))  argument
4555 #define DCDC_CLR_REG6(base, value) (BME_AND32(&DCDC_REG6_REG(base), (uint32_t)(~(value))))  argument
4556 #define DCDC_TOG_REG6(base, value) (BME_XOR32(&DCDC_REG6_REG(base), (uint32_t)(value)))  argument
4570 #define DCDC_RD_REG6_PSWITCH_INT_RISE_EN(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_RISE_E…  argument
4571 #define DCDC_BRD_REG6_PSWITCH_INT_RISE_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH…  argument
4574 #define DCDC_WR_REG6_PSWITCH_INT_RISE_EN(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_RI…  argument
4575 #define DCDC_BWR_REG6_PSWITCH_INT_RISE_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)…  argument
4585 #define DCDC_RD_REG6_PSWITCH_INT_FALL_EN(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_FALL_E…  argument
4586 #define DCDC_BRD_REG6_PSWITCH_INT_FALL_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH…  argument
4589 #define DCDC_WR_REG6_PSWITCH_INT_FALL_EN(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_FA…  argument
4590 #define DCDC_BWR_REG6_PSWITCH_INT_FALL_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)…  argument
4600 #define DCDC_RD_REG6_PSWITCH_INT_CLEAR(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_CLEAR_MA…  argument
4601 #define DCDC_BRD_REG6_PSWITCH_INT_CLEAR(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_I…  argument
4604 #define DCDC_WR_REG6_PSWITCH_INT_CLEAR(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_CLEA…  argument
4605 #define DCDC_BWR_REG6_PSWITCH_INT_CLEAR(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(v…  argument
4615 #define DCDC_RD_REG6_PSWITCH_INT_MUTE(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_MUTE_MASK…  argument
4616 #define DCDC_BRD_REG6_PSWITCH_INT_MUTE(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_IN…  argument
4619 #define DCDC_WR_REG6_PSWITCH_INT_MUTE(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_MUTE_…  argument
4620 #define DCDC_BWR_REG6_PSWITCH_INT_MUTE(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(va…  argument
4630 #define DCDC_RD_REG6_PSWITCH_INT_STS(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_STS_MASK) …  argument
4631 #define DCDC_BRD_REG6_PSWITCH_INT_STS(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT…  argument
4647 #define DCDC_RD_REG7(base)       (DCDC_REG7_REG(base))  argument
4648 #define DCDC_WR_REG7(base, value) (DCDC_REG7_REG(base) = (value))  argument
4649 #define DCDC_RMW_REG7(base, mask, value) (DCDC_WR_REG7(base, (DCDC_RD_REG7(base) & ~(mask)) | (valu…  argument
4650 #define DCDC_SET_REG7(base, value) (BME_OR32(&DCDC_REG7_REG(base), (uint32_t)(value)))  argument
4651 #define DCDC_CLR_REG7(base, value) (BME_AND32(&DCDC_REG7_REG(base), (uint32_t)(~(value))))  argument
4652 #define DCDC_TOG_REG7(base, value) (BME_XOR32(&DCDC_REG7_REG(base), (uint32_t)(value)))  argument
4670 #define DCDC_RD_REG7_INTEGRATOR_VALUE(base) ((DCDC_REG7_REG(base) & DCDC_REG7_INTEGRATOR_VALUE_MASK…  argument
4671 #define DCDC_BRD_REG7_INTEGRATOR_VALUE(base) (DCDC_RD_REG7_INTEGRATOR_VALUE(base))  argument
4674 #define DCDC_WR_REG7_INTEGRATOR_VALUE(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_INTEGRATOR_VALUE_…  argument
4675 #define DCDC_BWR_REG7_INTEGRATOR_VALUE(base, value) (DCDC_WR_REG7_INTEGRATOR_VALUE(base, value))  argument
4685 #define DCDC_RD_REG7_INTEGRATOR_VALUE_SEL(base) ((DCDC_REG7_REG(base) & DCDC_REG7_INTEGRATOR_VALUE_…  argument
4686 #define DCDC_BRD_REG7_INTEGRATOR_VALUE_SEL(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_INTEGR…  argument
4689 #define DCDC_WR_REG7_INTEGRATOR_VALUE_SEL(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_INTEGRATOR_VA…  argument
4690 #define DCDC_BWR_REG7_INTEGRATOR_VALUE_SEL(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t…  argument
4701 #define DCDC_RD_REG7_PULSE_RUN_SPEEDUP(base) ((DCDC_REG7_REG(base) & DCDC_REG7_PULSE_RUN_SPEEDUP_MA…  argument
4702 #define DCDC_BRD_REG7_PULSE_RUN_SPEEDUP(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_PULSE_RUN…  argument
4705 #define DCDC_WR_REG7_PULSE_RUN_SPEEDUP(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_PULSE_RUN_SPEEDU…  argument
4706 #define DCDC_BWR_REG7_PULSE_RUN_SPEEDUP(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t)(v…  argument
4745 #define DMA_RD_SAR(base, index)  (DMA_SAR_REG(base, index))  argument
4746 #define DMA_WR_SAR(base, index, value) (DMA_SAR_REG(base, index) = (value))  argument
4747 #define DMA_RMW_SAR(base, index, mask, value) (DMA_WR_SAR(base, index, (DMA_RD_SAR(base, index) & ~…  argument
4748 #define DMA_SET_SAR(base, index, value) (BME_OR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))  argument
4749 #define DMA_CLR_SAR(base, index, value) (BME_AND32(&DMA_SAR_REG(base, index), (uint32_t)(~(value))))  argument
4750 #define DMA_TOG_SAR(base, index, value) (BME_XOR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))  argument
4773 #define DMA_RD_DAR(base, index)  (DMA_DAR_REG(base, index))  argument
4774 #define DMA_WR_DAR(base, index, value) (DMA_DAR_REG(base, index) = (value))  argument
4775 #define DMA_RMW_DAR(base, index, mask, value) (DMA_WR_DAR(base, index, (DMA_RD_DAR(base, index) & ~…  argument
4776 #define DMA_SET_DAR(base, index, value) (BME_OR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))  argument
4777 #define DMA_CLR_DAR(base, index, value) (BME_AND32(&DMA_DAR_REG(base, index), (uint32_t)(~(value))))  argument
4778 #define DMA_TOG_DAR(base, index, value) (BME_XOR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))  argument
4806 #define DMA_RD_DSR_BCR(base, index) (DMA_DSR_BCR_REG(base, index))  argument
4807 #define DMA_WR_DSR_BCR(base, index, value) (DMA_DSR_BCR_REG(base, index) = (value))  argument
4808 #define DMA_RMW_DSR_BCR(base, index, mask, value) (DMA_WR_DSR_BCR(base, index, (DMA_RD_DSR_BCR(base…  argument
4809 #define DMA_SET_DSR_BCR(base, index, value) (BME_OR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(val…  argument
4810 #define DMA_CLR_DSR_BCR(base, index, value) (BME_AND32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(~(…  argument
4811 #define DMA_TOG_DSR_BCR(base, index, value) (BME_XOR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(va…  argument
4830 #define DMA_RD_DSR_BCR_BCR(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BCR_MASK) >> D…  argument
4831 #define DMA_BRD_DSR_BCR_BCR(base, index) (DMA_RD_DSR_BCR_BCR(base, index))  argument
4834 #define DMA_WR_DSR_BCR_BCR(base, index, value) (DMA_RMW_DSR_BCR(base, index, (DMA_DSR_BCR_BCR_MASK …  argument
4835 #define DMA_BWR_DSR_BCR_BCR(base, index, value) (DMA_WR_DSR_BCR_BCR(base, index, value))  argument
4855 #define DMA_RD_DSR_BCR_DONE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_DONE_MASK) >>…  argument
4856 #define DMA_BRD_DSR_BCR_DONE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_DO…  argument
4859 #define DMA_WR_DSR_BCR_DONE(base, index, value) (DMA_RMW_DSR_BCR(base, index, DMA_DSR_BCR_DONE_MASK…  argument
4860 #define DMA_BWR_DSR_BCR_DONE(base, index, value) (BME_BFI32(&DMA_DSR_BCR_REG(base, index), ((uint32…  argument
4874 #define DMA_RD_DSR_BCR_BSY(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BSY_MASK) >> D…  argument
4875 #define DMA_BRD_DSR_BCR_BSY(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BSY…  argument
4889 #define DMA_RD_DSR_BCR_REQ(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_REQ_MASK) >> D…  argument
4890 #define DMA_BRD_DSR_BCR_REQ(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_REQ…  argument
4905 #define DMA_RD_DSR_BCR_BED(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BED_MASK) >> D…  argument
4906 #define DMA_BRD_DSR_BCR_BED(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BED…  argument
4921 #define DMA_RD_DSR_BCR_BES(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BES_MASK) >> D…  argument
4922 #define DMA_BRD_DSR_BCR_BES(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BES…  argument
4941 #define DMA_RD_DSR_BCR_CE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_CE_MASK) >> DMA…  argument
4942 #define DMA_BRD_DSR_BCR_CE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_CE_S…  argument
4958 #define DMA_RD_DSR(base, index)  (DMA_DSR_REG(base, index))  argument
4959 #define DMA_WR_DSR(base, index, value) (DMA_DSR_REG(base, index) = (value))  argument
4960 #define DMA_RMW_DSR(base, index, mask, value) (DMA_WR_DSR(base, index, (DMA_RD_DSR(base, index) & ~…  argument
4961 #define DMA_SET_DSR(base, index, value) (BME_OR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))  argument
4962 #define DMA_CLR_DSR(base, index, value) (BME_AND8(&DMA_DSR_REG(base, index), (uint8_t)(~(value))))  argument
4963 #define DMA_TOG_DSR(base, index, value) (BME_XOR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))  argument
4979 #define DMA_RD_DCR(base, index)  (DMA_DCR_REG(base, index))  argument
4980 #define DMA_WR_DCR(base, index, value) (DMA_DCR_REG(base, index) = (value))  argument
4981 #define DMA_RMW_DCR(base, index, mask, value) (DMA_WR_DCR(base, index, (DMA_RD_DCR(base, index) & ~…  argument
4982 #define DMA_SET_DCR(base, index, value) (BME_OR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))  argument
4983 #define DMA_CLR_DCR(base, index, value) (BME_AND32(&DMA_DCR_REG(base, index), (uint32_t)(~(value))))  argument
4984 #define DMA_TOG_DCR(base, index, value) (BME_XOR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))  argument
5005 #define DMA_RD_DCR_LCH2(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH2_MASK) >> DMA_DCR_LCH…  argument
5006 #define DMA_BRD_DCR_LCH2(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH2_SHIFT, DM…  argument
5009 #define DMA_WR_DCR_LCH2(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH2_MASK, DMA_DCR_LC…  argument
5010 #define DMA_BWR_DCR_LCH2(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5027 #define DMA_RD_DCR_LCH1(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH1_MASK) >> DMA_DCR_LCH…  argument
5028 #define DMA_BRD_DCR_LCH1(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH1_SHIFT, DM…  argument
5031 #define DMA_WR_DCR_LCH1(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH1_MASK, DMA_DCR_LC…  argument
5032 #define DMA_BWR_DCR_LCH1(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5059 #define DMA_RD_DCR_LINKCC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LINKCC_MASK) >> DMA_DCR…  argument
5060 #define DMA_BRD_DCR_LINKCC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LINKCC_SHIFT…  argument
5063 #define DMA_WR_DCR_LINKCC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LINKCC_MASK, DMA_DC…  argument
5064 #define DMA_BWR_DCR_LINKCC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…  argument
5079 #define DMA_RD_DCR_D_REQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_D_REQ_MASK) >> DMA_DCR_D…  argument
5080 #define DMA_BRD_DCR_D_REQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_D_REQ_SHIFT, …  argument
5083 #define DMA_WR_DCR_D_REQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_D_REQ_MASK, DMA_DCR_…  argument
5084 #define DMA_BWR_DCR_D_REQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5119 #define DMA_RD_DCR_DMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DMOD_MASK) >> DMA_DCR_DMO…  argument
5120 #define DMA_BRD_DCR_DMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DMOD_SHIFT, DM…  argument
5123 #define DMA_WR_DCR_DMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DMOD_MASK, DMA_DCR_DM…  argument
5124 #define DMA_BWR_DCR_DMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5176 #define DMA_RD_DCR_SMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SMOD_MASK) >> DMA_DCR_SMO…  argument
5177 #define DMA_BRD_DCR_SMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SMOD_SHIFT, DM…  argument
5180 #define DMA_WR_DCR_SMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SMOD_MASK, DMA_DCR_SM…  argument
5181 #define DMA_BWR_DCR_SMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5195 #define DMA_WR_DCR_START(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_START_MASK, DMA_DCR_…  argument
5196 #define DMA_BWR_DCR_START(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5213 #define DMA_RD_DCR_DSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DSIZE_MASK) >> DMA_DCR_D…  argument
5214 #define DMA_BRD_DCR_DSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DSIZE_SHIFT, …  argument
5217 #define DMA_WR_DCR_DSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DSIZE_MASK, DMA_DCR_…  argument
5218 #define DMA_BWR_DCR_DSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5233 #define DMA_RD_DCR_DINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DINC_MASK) >> DMA_DCR_DIN…  argument
5234 #define DMA_BRD_DCR_DINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DINC_SHIFT, DM…  argument
5237 #define DMA_WR_DCR_DINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DINC_MASK, DMA_DCR_DI…  argument
5238 #define DMA_BWR_DCR_DINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5255 #define DMA_RD_DCR_SSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SSIZE_MASK) >> DMA_DCR_S…  argument
5256 #define DMA_BRD_DCR_SSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SSIZE_SHIFT, …  argument
5259 #define DMA_WR_DCR_SSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SSIZE_MASK, DMA_DCR_…  argument
5260 #define DMA_BWR_DCR_SSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(val…  argument
5274 #define DMA_RD_DCR_SINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SINC_MASK) >> DMA_DCR_SIN…  argument
5275 #define DMA_BRD_DCR_SINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SINC_SHIFT, DM…  argument
5278 #define DMA_WR_DCR_SINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SINC_MASK, DMA_DCR_SI…  argument
5279 #define DMA_BWR_DCR_SINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5294 #define DMA_RD_DCR_EADREQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EADREQ_MASK) >> DMA_DCR…  argument
5295 #define DMA_BRD_DCR_EADREQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EADREQ_SHIFT…  argument
5298 #define DMA_WR_DCR_EADREQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EADREQ_MASK, DMA_DC…  argument
5299 #define DMA_BWR_DCR_EADREQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(va…  argument
5318 #define DMA_RD_DCR_AA(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_AA_MASK) >> DMA_DCR_AA_SHIF…  argument
5319 #define DMA_BRD_DCR_AA(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_AA_SHIFT, DMA_DC…  argument
5322 #define DMA_WR_DCR_AA(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_AA_MASK, DMA_DCR_AA(val…  argument
5323 #define DMA_BWR_DCR_AA(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…  argument
5336 #define DMA_RD_DCR_CS(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_CS_MASK) >> DMA_DCR_CS_SHIF…  argument
5337 #define DMA_BRD_DCR_CS(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_CS_SHIFT, DMA_DC…  argument
5340 #define DMA_WR_DCR_CS(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_CS_MASK, DMA_DCR_CS(val…  argument
5341 #define DMA_BWR_DCR_CS(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value)…  argument
5356 #define DMA_RD_DCR_ERQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_ERQ_MASK) >> DMA_DCR_ERQ_S…  argument
5357 #define DMA_BRD_DCR_ERQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_ERQ_SHIFT, DMA_…  argument
5360 #define DMA_WR_DCR_ERQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_ERQ_MASK, DMA_DCR_ERQ(…  argument
5361 #define DMA_BWR_DCR_ERQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value…  argument
5376 #define DMA_RD_DCR_EINT(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EINT_MASK) >> DMA_DCR_EIN…  argument
5377 #define DMA_BRD_DCR_EINT(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EINT_SHIFT, DM…  argument
5380 #define DMA_WR_DCR_EINT(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EINT_MASK, DMA_DCR_EI…  argument
5381 #define DMA_BWR_DCR_EINT(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(valu…  argument
5416 #define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))  argument
5417 #define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))  argument
5418 #define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(b…  argument
5419 #define DMAMUX_SET_CHCFG(base, index, value) (BME_OR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(val…  argument
5420 #define DMAMUX_CLR_CHCFG(base, index, value) (BME_AND8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(~(…  argument
5421 #define DMAMUX_TOG_CHCFG(base, index, value) (BME_XOR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(va…  argument
5437 #define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_M…  argument
5438 #define DMAMUX_BRD_CHCFG_SOURCE(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCF…  argument
5441 #define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOUR…  argument
5442 #define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uin…  argument
5459 #define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK)…  argument
5460 #define DMAMUX_BRD_CHCFG_TRIG(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_…  argument
5463 #define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_M…  argument
5464 #define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8…  argument
5480 #define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK)…  argument
5481 #define DMAMUX_BRD_CHCFG_ENBL(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_…  argument
5484 #define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_M…  argument
5485 #define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8…  argument
5523 #define FGPIO_RD_PDOR(base)      (FGPIO_PDOR_REG(base))  argument
5524 #define FGPIO_WR_PDOR(base, value) (FGPIO_PDOR_REG(base) = (value))  argument
5525 #define FGPIO_RMW_PDOR(base, mask, value) (FGPIO_WR_PDOR(base, (FGPIO_RD_PDOR(base) & ~(mask)) | (v…  argument
5526 #define FGPIO_SET_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) |  (value)))  argument
5527 #define FGPIO_CLR_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) & ~(value)))  argument
5528 #define FGPIO_TOG_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) ^  (value)))  argument
5546 #define FGPIO_RD_PSOR(base)      (FGPIO_PSOR_REG(base))  argument
5547 #define FGPIO_WR_PSOR(base, value) (FGPIO_PSOR_REG(base) = (value))  argument
5548 #define FGPIO_RMW_PSOR(base, mask, value) (FGPIO_WR_PSOR(base, (FGPIO_RD_PSOR(base) & ~(mask)) | (v…  argument
5566 #define FGPIO_RD_PCOR(base)      (FGPIO_PCOR_REG(base))  argument
5567 #define FGPIO_WR_PCOR(base, value) (FGPIO_PCOR_REG(base) = (value))  argument
5568 #define FGPIO_RMW_PCOR(base, mask, value) (FGPIO_WR_PCOR(base, (FGPIO_RD_PCOR(base) & ~(mask)) | (v…  argument
5584 #define FGPIO_RD_PTOR(base)      (FGPIO_PTOR_REG(base))  argument
5585 #define FGPIO_WR_PTOR(base, value) (FGPIO_PTOR_REG(base) = (value))  argument
5586 #define FGPIO_RMW_PTOR(base, mask, value) (FGPIO_WR_PTOR(base, (FGPIO_RD_PTOR(base) & ~(mask)) | (v…  argument
5602 #define FGPIO_RD_PDIR(base)      (FGPIO_PDIR_REG(base))  argument
5620 #define FGPIO_RD_PDDR(base)      (FGPIO_PDDR_REG(base))  argument
5621 #define FGPIO_WR_PDDR(base, value) (FGPIO_PDDR_REG(base) = (value))  argument
5622 #define FGPIO_RMW_PDDR(base, mask, value) (FGPIO_WR_PDDR(base, (FGPIO_RD_PDDR(base) & ~(mask)) | (v…  argument
5623 #define FGPIO_SET_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) |  (value)))  argument
5624 #define FGPIO_CLR_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) & ~(value)))  argument
5625 #define FGPIO_TOG_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) ^  (value)))  argument
5697 #define FTFA_RD_FSTAT(base)      (FTFA_FSTAT_REG(base))  argument
5698 #define FTFA_WR_FSTAT(base, value) (FTFA_FSTAT_REG(base) = (value))  argument
5699 #define FTFA_RMW_FSTAT(base, mask, value) (FTFA_WR_FSTAT(base, (FTFA_RD_FSTAT(base) & ~(mask)) | (v…  argument
5700 #define FTFA_SET_FSTAT(base, value) (BME_OR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))  argument
5701 #define FTFA_CLR_FSTAT(base, value) (BME_AND8(&FTFA_FSTAT_REG(base), (uint8_t)(~(value))))  argument
5702 #define FTFA_TOG_FSTAT(base, value) (BME_XOR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))  argument
5722 #define FTFA_RD_FSTAT_MGSTAT0(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_MGSTAT0_MASK) >> FTFA_FSTAT…  argument
5723 #define FTFA_BRD_FSTAT_MGSTAT0(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_MGSTAT0_SHIFT, FT…  argument
5741 #define FTFA_RD_FSTAT_FPVIOL(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_FPVIOL_MASK) >> FTFA_FSTAT_F…  argument
5742 #define FTFA_BRD_FSTAT_FPVIOL(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_FPVIOL_SHIFT, FTFA…  argument
5745 #define FTFA_WR_FSTAT_FPVIOL(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTA…  argument
5746 #define FTFA_BWR_FSTAT_FPVIOL(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FT…  argument
5764 #define FTFA_RD_FSTAT_ACCERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_ACCERR_MASK) >> FTFA_FSTAT_A…  argument
5765 #define FTFA_BRD_FSTAT_ACCERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_ACCERR_SHIFT, FTFA…  argument
5768 #define FTFA_WR_FSTAT_ACCERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_ACCERR_MASK | FTFA_FSTA…  argument
5769 #define FTFA_BWR_FSTAT_ACCERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FT…  argument
5787 #define FTFA_RD_FSTAT_RDCOLERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_RDCOLERR_MASK) >> FTFA_FST…  argument
5788 #define FTFA_BRD_FSTAT_RDCOLERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_RDCOLERR_SHIFT, …  argument
5791 #define FTFA_WR_FSTAT_RDCOLERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_RDCOLERR_MASK | FTFA_…  argument
5792 #define FTFA_BWR_FSTAT_RDCOLERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << …  argument
5811 #define FTFA_RD_FSTAT_CCIF(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_CCIF_MASK) >> FTFA_FSTAT_CCIF_…  argument
5812 #define FTFA_BRD_FSTAT_CCIF(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_CCIF_SHIFT, FTFA_FST…  argument
5815 #define FTFA_WR_FSTAT_CCIF(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_CCIF_MASK | FTFA_FSTAT_FP…  argument
5816 #define FTFA_BWR_FSTAT_CCIF(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA…  argument
5836 #define FTFA_RD_FCNFG(base)      (FTFA_FCNFG_REG(base))  argument
5837 #define FTFA_WR_FCNFG(base, value) (FTFA_FCNFG_REG(base) = (value))  argument
5838 #define FTFA_RMW_FCNFG(base, mask, value) (FTFA_WR_FCNFG(base, (FTFA_RD_FCNFG(base) & ~(mask)) | (v…  argument
5839 #define FTFA_SET_FCNFG(base, value) (BME_OR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))  argument
5840 #define FTFA_CLR_FCNFG(base, value) (BME_AND8(&FTFA_FCNFG_REG(base), (uint8_t)(~(value))))  argument
5841 #define FTFA_TOG_FCNFG(base, value) (BME_XOR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))  argument
5860 #define FTFA_RD_FCNFG_ERSSUSP(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSSUSP_MASK) >> FTFA_FCNFG…  argument
5861 #define FTFA_BRD_FCNFG_ERSSUSP(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSSUSP_SHIFT, FT…  argument
5864 #define FTFA_WR_FCNFG_ERSSUSP(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_ERSSUSP_MASK, FTFA_FCNF…  argument
5865 #define FTFA_BWR_FCNFG_ERSSUSP(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << F…  argument
5887 #define FTFA_RD_FCNFG_ERSAREQ(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSAREQ_MASK) >> FTFA_FCNFG…  argument
5888 #define FTFA_BRD_FCNFG_ERSAREQ(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSAREQ_SHIFT, FT…  argument
5904 #define FTFA_RD_FCNFG_RDCOLLIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_RDCOLLIE_MASK) >> FTFA_FCN…  argument
5905 #define FTFA_BRD_FCNFG_RDCOLLIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_RDCOLLIE_SHIFT, …  argument
5908 #define FTFA_WR_FCNFG_RDCOLLIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_RDCOLLIE_MASK, FTFA_FC…  argument
5909 #define FTFA_BWR_FCNFG_RDCOLLIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << …  argument
5924 #define FTFA_RD_FCNFG_CCIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_CCIE_MASK) >> FTFA_FCNFG_CCIE_…  argument
5925 #define FTFA_BRD_FCNFG_CCIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_CCIE_SHIFT, FTFA_FCN…  argument
5928 #define FTFA_WR_FCNFG_CCIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_CCIE_MASK, FTFA_FCNFG_CCIE…  argument
5929 #define FTFA_BWR_FCNFG_CCIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA…  argument
5951 #define FTFA_RD_FSEC(base)       (FTFA_FSEC_REG(base))  argument
5975 #define FTFA_RD_FSEC_SEC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_SEC_MASK) >> FTFA_FSEC_SEC_SHIFT)  argument
5976 #define FTFA_BRD_FSEC_SEC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_SEC_SHIFT, FTFA_FSEC_SEC…  argument
5999 #define FTFA_RD_FSEC_FSLACC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_FSLACC_MASK) >> FTFA_FSEC_FSLAC…  argument
6000 #define FTFA_BRD_FSEC_FSLACC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_FSLACC_SHIFT, FTFA_FS…  argument
6017 #define FTFA_RD_FSEC_MEEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_MEEN_MASK) >> FTFA_FSEC_MEEN_SHIF…  argument
6018 #define FTFA_BRD_FSEC_MEEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_MEEN_SHIFT, FTFA_FSEC_M…  argument
6035 #define FTFA_RD_FSEC_KEYEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_KEYEN_MASK) >> FTFA_FSEC_KEYEN_S…  argument
6036 #define FTFA_BRD_FSEC_KEYEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_KEYEN_SHIFT, FTFA_FSEC…  argument
6060 #define FTFA_RD_FOPT(base)       (FTFA_FOPT_REG(base))  argument
6080 #define FTFA_RD_FCCOB3(base)     (FTFA_FCCOB3_REG(base))  argument
6081 #define FTFA_WR_FCCOB3(base, value) (FTFA_FCCOB3_REG(base) = (value))  argument
6082 #define FTFA_RMW_FCCOB3(base, mask, value) (FTFA_WR_FCCOB3(base, (FTFA_RD_FCCOB3(base) & ~(mask)) |…  argument
6083 #define FTFA_SET_FCCOB3(base, value) (BME_OR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))  argument
6084 #define FTFA_CLR_FCCOB3(base, value) (BME_AND8(&FTFA_FCCOB3_REG(base), (uint8_t)(~(value))))  argument
6085 #define FTFA_TOG_FCCOB3(base, value) (BME_XOR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))  argument
6105 #define FTFA_RD_FCCOB2(base)     (FTFA_FCCOB2_REG(base))  argument
6106 #define FTFA_WR_FCCOB2(base, value) (FTFA_FCCOB2_REG(base) = (value))  argument
6107 #define FTFA_RMW_FCCOB2(base, mask, value) (FTFA_WR_FCCOB2(base, (FTFA_RD_FCCOB2(base) & ~(mask)) |…  argument
6108 #define FTFA_SET_FCCOB2(base, value) (BME_OR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))  argument
6109 #define FTFA_CLR_FCCOB2(base, value) (BME_AND8(&FTFA_FCCOB2_REG(base), (uint8_t)(~(value))))  argument
6110 #define FTFA_TOG_FCCOB2(base, value) (BME_XOR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))  argument
6130 #define FTFA_RD_FCCOB1(base)     (FTFA_FCCOB1_REG(base))  argument
6131 #define FTFA_WR_FCCOB1(base, value) (FTFA_FCCOB1_REG(base) = (value))  argument
6132 #define FTFA_RMW_FCCOB1(base, mask, value) (FTFA_WR_FCCOB1(base, (FTFA_RD_FCCOB1(base) & ~(mask)) |…  argument
6133 #define FTFA_SET_FCCOB1(base, value) (BME_OR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))  argument
6134 #define FTFA_CLR_FCCOB1(base, value) (BME_AND8(&FTFA_FCCOB1_REG(base), (uint8_t)(~(value))))  argument
6135 #define FTFA_TOG_FCCOB1(base, value) (BME_XOR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))  argument
6155 #define FTFA_RD_FCCOB0(base)     (FTFA_FCCOB0_REG(base))  argument
6156 #define FTFA_WR_FCCOB0(base, value) (FTFA_FCCOB0_REG(base) = (value))  argument
6157 #define FTFA_RMW_FCCOB0(base, mask, value) (FTFA_WR_FCCOB0(base, (FTFA_RD_FCCOB0(base) & ~(mask)) |…  argument
6158 #define FTFA_SET_FCCOB0(base, value) (BME_OR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))  argument
6159 #define FTFA_CLR_FCCOB0(base, value) (BME_AND8(&FTFA_FCCOB0_REG(base), (uint8_t)(~(value))))  argument
6160 #define FTFA_TOG_FCCOB0(base, value) (BME_XOR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))  argument
6180 #define FTFA_RD_FCCOB7(base)     (FTFA_FCCOB7_REG(base))  argument
6181 #define FTFA_WR_FCCOB7(base, value) (FTFA_FCCOB7_REG(base) = (value))  argument
6182 #define FTFA_RMW_FCCOB7(base, mask, value) (FTFA_WR_FCCOB7(base, (FTFA_RD_FCCOB7(base) & ~(mask)) |…  argument
6183 #define FTFA_SET_FCCOB7(base, value) (BME_OR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))  argument
6184 #define FTFA_CLR_FCCOB7(base, value) (BME_AND8(&FTFA_FCCOB7_REG(base), (uint8_t)(~(value))))  argument
6185 #define FTFA_TOG_FCCOB7(base, value) (BME_XOR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))  argument
6205 #define FTFA_RD_FCCOB6(base)     (FTFA_FCCOB6_REG(base))  argument
6206 #define FTFA_WR_FCCOB6(base, value) (FTFA_FCCOB6_REG(base) = (value))  argument
6207 #define FTFA_RMW_FCCOB6(base, mask, value) (FTFA_WR_FCCOB6(base, (FTFA_RD_FCCOB6(base) & ~(mask)) |…  argument
6208 #define FTFA_SET_FCCOB6(base, value) (BME_OR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))  argument
6209 #define FTFA_CLR_FCCOB6(base, value) (BME_AND8(&FTFA_FCCOB6_REG(base), (uint8_t)(~(value))))  argument
6210 #define FTFA_TOG_FCCOB6(base, value) (BME_XOR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))  argument
6230 #define FTFA_RD_FCCOB5(base)     (FTFA_FCCOB5_REG(base))  argument
6231 #define FTFA_WR_FCCOB5(base, value) (FTFA_FCCOB5_REG(base) = (value))  argument
6232 #define FTFA_RMW_FCCOB5(base, mask, value) (FTFA_WR_FCCOB5(base, (FTFA_RD_FCCOB5(base) & ~(mask)) |…  argument
6233 #define FTFA_SET_FCCOB5(base, value) (BME_OR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))  argument
6234 #define FTFA_CLR_FCCOB5(base, value) (BME_AND8(&FTFA_FCCOB5_REG(base), (uint8_t)(~(value))))  argument
6235 #define FTFA_TOG_FCCOB5(base, value) (BME_XOR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))  argument
6255 #define FTFA_RD_FCCOB4(base)     (FTFA_FCCOB4_REG(base))  argument
6256 #define FTFA_WR_FCCOB4(base, value) (FTFA_FCCOB4_REG(base) = (value))  argument
6257 #define FTFA_RMW_FCCOB4(base, mask, value) (FTFA_WR_FCCOB4(base, (FTFA_RD_FCCOB4(base) & ~(mask)) |…  argument
6258 #define FTFA_SET_FCCOB4(base, value) (BME_OR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))  argument
6259 #define FTFA_CLR_FCCOB4(base, value) (BME_AND8(&FTFA_FCCOB4_REG(base), (uint8_t)(~(value))))  argument
6260 #define FTFA_TOG_FCCOB4(base, value) (BME_XOR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))  argument
6280 #define FTFA_RD_FCCOBB(base)     (FTFA_FCCOBB_REG(base))  argument
6281 #define FTFA_WR_FCCOBB(base, value) (FTFA_FCCOBB_REG(base) = (value))  argument
6282 #define FTFA_RMW_FCCOBB(base, mask, value) (FTFA_WR_FCCOBB(base, (FTFA_RD_FCCOBB(base) & ~(mask)) |…  argument
6283 #define FTFA_SET_FCCOBB(base, value) (BME_OR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))  argument
6284 #define FTFA_CLR_FCCOBB(base, value) (BME_AND8(&FTFA_FCCOBB_REG(base), (uint8_t)(~(value))))  argument
6285 #define FTFA_TOG_FCCOBB(base, value) (BME_XOR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))  argument
6305 #define FTFA_RD_FCCOBA(base)     (FTFA_FCCOBA_REG(base))  argument
6306 #define FTFA_WR_FCCOBA(base, value) (FTFA_FCCOBA_REG(base) = (value))  argument
6307 #define FTFA_RMW_FCCOBA(base, mask, value) (FTFA_WR_FCCOBA(base, (FTFA_RD_FCCOBA(base) & ~(mask)) |…  argument
6308 #define FTFA_SET_FCCOBA(base, value) (BME_OR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))  argument
6309 #define FTFA_CLR_FCCOBA(base, value) (BME_AND8(&FTFA_FCCOBA_REG(base), (uint8_t)(~(value))))  argument
6310 #define FTFA_TOG_FCCOBA(base, value) (BME_XOR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))  argument
6330 #define FTFA_RD_FCCOB9(base)     (FTFA_FCCOB9_REG(base))  argument
6331 #define FTFA_WR_FCCOB9(base, value) (FTFA_FCCOB9_REG(base) = (value))  argument
6332 #define FTFA_RMW_FCCOB9(base, mask, value) (FTFA_WR_FCCOB9(base, (FTFA_RD_FCCOB9(base) & ~(mask)) |…  argument
6333 #define FTFA_SET_FCCOB9(base, value) (BME_OR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))  argument
6334 #define FTFA_CLR_FCCOB9(base, value) (BME_AND8(&FTFA_FCCOB9_REG(base), (uint8_t)(~(value))))  argument
6335 #define FTFA_TOG_FCCOB9(base, value) (BME_XOR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))  argument
6355 #define FTFA_RD_FCCOB8(base)     (FTFA_FCCOB8_REG(base))  argument
6356 #define FTFA_WR_FCCOB8(base, value) (FTFA_FCCOB8_REG(base) = (value))  argument
6357 #define FTFA_RMW_FCCOB8(base, mask, value) (FTFA_WR_FCCOB8(base, (FTFA_RD_FCCOB8(base) & ~(mask)) |…  argument
6358 #define FTFA_SET_FCCOB8(base, value) (BME_OR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))  argument
6359 #define FTFA_CLR_FCCOB8(base, value) (BME_AND8(&FTFA_FCCOB8_REG(base), (uint8_t)(~(value))))  argument
6360 #define FTFA_TOG_FCCOB8(base, value) (BME_XOR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))  argument
6400 #define FTFA_RD_FPROT3(base)     (FTFA_FPROT3_REG(base))  argument
6401 #define FTFA_WR_FPROT3(base, value) (FTFA_FPROT3_REG(base) = (value))  argument
6402 #define FTFA_RMW_FPROT3(base, mask, value) (FTFA_WR_FPROT3(base, (FTFA_RD_FPROT3(base) & ~(mask)) |…  argument
6403 #define FTFA_SET_FPROT3(base, value) (BME_OR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))  argument
6404 #define FTFA_CLR_FPROT3(base, value) (BME_AND8(&FTFA_FPROT3_REG(base), (uint8_t)(~(value))))  argument
6405 #define FTFA_TOG_FPROT3(base, value) (BME_XOR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))  argument
6445 #define FTFA_RD_FPROT2(base)     (FTFA_FPROT2_REG(base))  argument
6446 #define FTFA_WR_FPROT2(base, value) (FTFA_FPROT2_REG(base) = (value))  argument
6447 #define FTFA_RMW_FPROT2(base, mask, value) (FTFA_WR_FPROT2(base, (FTFA_RD_FPROT2(base) & ~(mask)) |…  argument
6448 #define FTFA_SET_FPROT2(base, value) (BME_OR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))  argument
6449 #define FTFA_CLR_FPROT2(base, value) (BME_AND8(&FTFA_FPROT2_REG(base), (uint8_t)(~(value))))  argument
6450 #define FTFA_TOG_FPROT2(base, value) (BME_XOR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))  argument
6490 #define FTFA_RD_FPROT1(base)     (FTFA_FPROT1_REG(base))  argument
6491 #define FTFA_WR_FPROT1(base, value) (FTFA_FPROT1_REG(base) = (value))  argument
6492 #define FTFA_RMW_FPROT1(base, mask, value) (FTFA_WR_FPROT1(base, (FTFA_RD_FPROT1(base) & ~(mask)) |…  argument
6493 #define FTFA_SET_FPROT1(base, value) (BME_OR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))  argument
6494 #define FTFA_CLR_FPROT1(base, value) (BME_AND8(&FTFA_FPROT1_REG(base), (uint8_t)(~(value))))  argument
6495 #define FTFA_TOG_FPROT1(base, value) (BME_XOR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))  argument
6535 #define FTFA_RD_FPROT0(base)     (FTFA_FPROT0_REG(base))  argument
6536 #define FTFA_WR_FPROT0(base, value) (FTFA_FPROT0_REG(base) = (value))  argument
6537 #define FTFA_RMW_FPROT0(base, mask, value) (FTFA_WR_FPROT0(base, (FTFA_RD_FPROT0(base) & ~(mask)) |…  argument
6538 #define FTFA_SET_FPROT0(base, value) (BME_OR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))  argument
6539 #define FTFA_CLR_FPROT0(base, value) (BME_AND8(&FTFA_FPROT0_REG(base), (uint8_t)(~(value))))  argument
6540 #define FTFA_TOG_FPROT0(base, value) (BME_XOR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))  argument
6569 #define FTFA_RD_XACCH3(base)     (FTFA_XACCH3_REG(base))  argument
6598 #define FTFA_RD_XACCH2(base)     (FTFA_XACCH2_REG(base))  argument
6627 #define FTFA_RD_XACCH1(base)     (FTFA_XACCH1_REG(base))  argument
6656 #define FTFA_RD_XACCH0(base)     (FTFA_XACCH0_REG(base))  argument
6685 #define FTFA_RD_XACCL3(base)     (FTFA_XACCL3_REG(base))  argument
6714 #define FTFA_RD_XACCL2(base)     (FTFA_XACCL2_REG(base))  argument
6743 #define FTFA_RD_XACCL1(base)     (FTFA_XACCL1_REG(base))  argument
6772 #define FTFA_RD_XACCL0(base)     (FTFA_XACCL0_REG(base))  argument
6801 #define FTFA_RD_SACCH3(base)     (FTFA_SACCH3_REG(base))  argument
6830 #define FTFA_RD_SACCH2(base)     (FTFA_SACCH2_REG(base))  argument
6859 #define FTFA_RD_SACCH1(base)     (FTFA_SACCH1_REG(base))  argument
6888 #define FTFA_RD_SACCH0(base)     (FTFA_SACCH0_REG(base))  argument
6917 #define FTFA_RD_SACCL3(base)     (FTFA_SACCL3_REG(base))  argument
6946 #define FTFA_RD_SACCL2(base)     (FTFA_SACCL2_REG(base))  argument
6975 #define FTFA_RD_SACCL1(base)     (FTFA_SACCL1_REG(base))  argument
7004 #define FTFA_RD_SACCL0(base)     (FTFA_SACCL0_REG(base))  argument
7025 #define FTFA_RD_FACSS(base)      (FTFA_FACSS_REG(base))  argument
7046 #define FTFA_RD_FACSN(base)      (FTFA_FACSN_REG(base))  argument
7086 #define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))  argument
7087 #define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))  argument
7088 #define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (valu…  argument
7089 #define GPIO_SET_PDOR(base, value) (BME_OR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))  argument
7090 #define GPIO_CLR_PDOR(base, value) (BME_AND32(&GPIO_PDOR_REG(base), (uint32_t)(~(value))))  argument
7091 #define GPIO_TOG_PDOR(base, value) (BME_XOR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))  argument
7109 #define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))  argument
7110 #define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))  argument
7111 #define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (valu…  argument
7129 #define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))  argument
7130 #define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))  argument
7131 #define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (valu…  argument
7147 #define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))  argument
7148 #define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))  argument
7149 #define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (valu…  argument
7169 #define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))  argument
7187 #define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))  argument
7188 #define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))  argument
7189 #define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (valu…  argument
7190 #define GPIO_SET_PDDR(base, value) (BME_OR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))  argument
7191 #define GPIO_CLR_PDDR(base, value) (BME_AND32(&GPIO_PDDR_REG(base), (uint32_t)(~(value))))  argument
7192 #define GPIO_TOG_PDDR(base, value) (BME_XOR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))  argument
7235 #define I2C_RD_A1(base)          (I2C_A1_REG(base))  argument
7236 #define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))  argument
7237 #define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))  argument
7238 #define I2C_SET_A1(base, value)  (BME_OR8(&I2C_A1_REG(base), (uint8_t)(value)))  argument
7239 #define I2C_CLR_A1(base, value)  (BME_AND8(&I2C_A1_REG(base), (uint8_t)(~(value))))  argument
7240 #define I2C_TOG_A1(base, value)  (BME_XOR8(&I2C_A1_REG(base), (uint8_t)(value)))  argument
7256 #define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)  argument
7257 #define I2C_BRD_A1_AD(base)  (BME_UBFX8(&I2C_A1_REG(base), I2C_A1_AD_SHIFT, I2C_A1_AD_WIDTH))  argument
7260 #define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))  argument
7261 #define I2C_BWR_A1_AD(base, value) (BME_BFI8(&I2C_A1_REG(base), ((uint8_t)(value) << I2C_A1_AD_SHIF…  argument
7277 #define I2C_RD_F(base)           (I2C_F_REG(base))  argument
7278 #define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))  argument
7279 #define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))  argument
7280 #define I2C_SET_F(base, value)   (BME_OR8(&I2C_F_REG(base), (uint8_t)(value)))  argument
7281 #define I2C_CLR_F(base, value)   (BME_AND8(&I2C_F_REG(base), (uint8_t)(~(value))))  argument
7282 #define I2C_TOG_F(base, value)   (BME_XOR8(&I2C_F_REG(base), (uint8_t)(value)))  argument
7314 #define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)  argument
7315 #define I2C_BRD_F_ICR(base)  (BME_UBFX8(&I2C_F_REG(base), I2C_F_ICR_SHIFT, I2C_F_ICR_WIDTH))  argument
7318 #define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))  argument
7319 #define I2C_BWR_F_ICR(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_ICR_SHIFT…  argument
7336 #define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)  argument
7337 #define I2C_BRD_F_MULT(base) (BME_UBFX8(&I2C_F_REG(base), I2C_F_MULT_SHIFT, I2C_F_MULT_WIDTH))  argument
7340 #define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))  argument
7341 #define I2C_BWR_F_MULT(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_MULT_SHI…  argument
7357 #define I2C_RD_C1(base)          (I2C_C1_REG(base))  argument
7358 #define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))  argument
7359 #define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))  argument
7360 #define I2C_SET_C1(base, value)  (BME_OR8(&I2C_C1_REG(base), (uint8_t)(value)))  argument
7361 #define I2C_CLR_C1(base, value)  (BME_AND8(&I2C_C1_REG(base), (uint8_t)(~(value))))  argument
7362 #define I2C_TOG_C1(base, value)  (BME_XOR8(&I2C_C1_REG(base), (uint8_t)(value)))  argument
7389 #define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)  argument
7390 #define I2C_BRD_C1_DMAEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT, I2C_C1_DMAEN_WIDTH…  argument
7393 #define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))  argument
7394 #define I2C_BWR_C1_DMAEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_DMAE…  argument
7410 #define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)  argument
7411 #define I2C_BRD_C1_WUEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT, I2C_C1_WUEN_WIDTH))  argument
7414 #define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))  argument
7415 #define I2C_BWR_C1_WUEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_WUEN_…  argument
7427 #define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))  argument
7428 #define I2C_BWR_C1_RSTA(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_RSTA_…  argument
7447 #define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)  argument
7448 #define I2C_BRD_C1_TXAK(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT, I2C_C1_TXAK_WIDTH))  argument
7451 #define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))  argument
7452 #define I2C_BWR_C1_TXAK(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TXAK_…  argument
7469 #define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)  argument
7470 #define I2C_BRD_C1_TX(base)  (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT, I2C_C1_TX_WIDTH))  argument
7473 #define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))  argument
7474 #define I2C_BWR_C1_TX(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TX_SHIF…  argument
7490 #define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)  argument
7491 #define I2C_BRD_C1_MST(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT, I2C_C1_MST_WIDTH))  argument
7494 #define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))  argument
7495 #define I2C_BWR_C1_MST(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_MST_SH…  argument
7509 #define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)  argument
7510 #define I2C_BRD_C1_IICIE(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT, I2C_C1_IICIE_WIDTH…  argument
7513 #define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))  argument
7514 #define I2C_BWR_C1_IICIE(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICI…  argument
7528 #define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)  argument
7529 #define I2C_BRD_C1_IICEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT, I2C_C1_IICEN_WIDTH…  argument
7532 #define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))  argument
7533 #define I2C_BWR_C1_IICEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICE…  argument
7549 #define I2C_RD_S(base)           (I2C_S_REG(base))  argument
7550 #define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))  argument
7551 #define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))  argument
7552 #define I2C_SET_S(base, value)   (BME_OR8(&I2C_S_REG(base), (uint8_t)(value)))  argument
7553 #define I2C_CLR_S(base, value)   (BME_AND8(&I2C_S_REG(base), (uint8_t)(~(value))))  argument
7554 #define I2C_TOG_S(base, value)   (BME_XOR8(&I2C_S_REG(base), (uint8_t)(value)))  argument
7571 #define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)  argument
7572 #define I2C_BRD_S_RXAK(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT, I2C_S_RXAK_WIDTH))  argument
7599 #define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)  argument
7600 #define I2C_BRD_S_IICIF(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT, I2C_S_IICIF_WIDTH))  argument
7603 #define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_II…  argument
7604 #define I2C_BWR_S_IICIF(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IICIF_S…  argument
7619 #define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)  argument
7620 #define I2C_BRD_S_SRW(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_SRW_SHIFT, I2C_S_SRW_WIDTH))  argument
7638 #define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)  argument
7639 #define I2C_BRD_S_RAM(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_RAM_SHIFT, I2C_S_RAM_WIDTH))  argument
7642 #define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_…  argument
7643 #define I2C_BWR_S_RAM(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_RAM_SHIFT…  argument
7658 #define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)  argument
7659 #define I2C_BRD_S_ARBL(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT, I2C_S_ARBL_WIDTH))  argument
7662 #define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARB…  argument
7663 #define I2C_BWR_S_ARBL(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_ARBL_SHI…  argument
7679 #define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)  argument
7680 #define I2C_BRD_S_BUSY(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT, I2C_S_BUSY_WIDTH))  argument
7703 #define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)  argument
7704 #define I2C_BRD_S_IAAS(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT, I2C_S_IAAS_WIDTH))  argument
7707 #define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARB…  argument
7708 #define I2C_BWR_S_IAAS(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IAAS_SHI…  argument
7728 #define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)  argument
7729 #define I2C_BRD_S_TCF(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_TCF_SHIFT, I2C_S_TCF_WIDTH))  argument
7745 #define I2C_RD_D(base)           (I2C_D_REG(base))  argument
7746 #define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))  argument
7747 #define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))  argument
7748 #define I2C_SET_D(base, value)   (BME_OR8(&I2C_D_REG(base), (uint8_t)(value)))  argument
7749 #define I2C_CLR_D(base, value)   (BME_AND8(&I2C_D_REG(base), (uint8_t)(~(value))))  argument
7750 #define I2C_TOG_D(base, value)   (BME_XOR8(&I2C_D_REG(base), (uint8_t)(value)))  argument
7766 #define I2C_RD_C2(base)          (I2C_C2_REG(base))  argument
7767 #define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))  argument
7768 #define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))  argument
7769 #define I2C_SET_C2(base, value)  (BME_OR8(&I2C_C2_REG(base), (uint8_t)(value)))  argument
7770 #define I2C_CLR_C2(base, value)  (BME_AND8(&I2C_C2_REG(base), (uint8_t)(~(value))))  argument
7771 #define I2C_TOG_C2(base, value)  (BME_XOR8(&I2C_C2_REG(base), (uint8_t)(value)))  argument
7786 #define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)  argument
7787 #define I2C_BRD_C2_AD(base)  (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_AD_SHIFT, I2C_C2_AD_WIDTH))  argument
7790 #define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))  argument
7791 #define I2C_BWR_C2_AD(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_AD_SHIF…  argument
7810 #define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)  argument
7811 #define I2C_BRD_C2_RMEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT, I2C_C2_RMEN_WIDTH))  argument
7814 #define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))  argument
7815 #define I2C_BWR_C2_RMEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_RMEN_…  argument
7833 #define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)  argument
7834 #define I2C_BRD_C2_SBRC(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT, I2C_C2_SBRC_WIDTH))  argument
7837 #define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))  argument
7838 #define I2C_BWR_C2_SBRC(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_SBRC_…  argument
7852 #define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)  argument
7853 #define I2C_BRD_C2_HDRS(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT, I2C_C2_HDRS_WIDTH))  argument
7856 #define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))  argument
7857 #define I2C_BWR_C2_HDRS(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_HDRS_…  argument
7871 #define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)  argument
7872 #define I2C_BRD_C2_ADEXT(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT, I2C_C2_ADEXT_WIDTH…  argument
7875 #define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))  argument
7876 #define I2C_BWR_C2_ADEXT(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_ADEX…  argument
7890 #define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)  argument
7891 #define I2C_BRD_C2_GCAEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT, I2C_C2_GCAEN_WIDTH…  argument
7894 #define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))  argument
7895 #define I2C_BWR_C2_GCAEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_GCAE…  argument
7911 #define I2C_RD_FLT(base)         (I2C_FLT_REG(base))  argument
7912 #define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))  argument
7913 #define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))  argument
7914 #define I2C_SET_FLT(base, value) (BME_OR8(&I2C_FLT_REG(base), (uint8_t)(value)))  argument
7915 #define I2C_CLR_FLT(base, value) (BME_AND8(&I2C_FLT_REG(base), (uint8_t)(~(value))))  argument
7916 #define I2C_TOG_FLT(base, value) (BME_XOR8(&I2C_FLT_REG(base), (uint8_t)(value)))  argument
7940 #define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)  argument
7941 #define I2C_BRD_FLT_FLT(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_FLT_SHIFT, I2C_FLT_FLT_WIDTH))  argument
7944 #define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2…  argument
7945 #define I2C_BWR_FLT_FLT(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_FLT…  argument
7960 #define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)  argument
7961 #define I2C_BRD_FLT_STARTF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT, I2C_FLT_START…  argument
7964 #define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK…  argument
7965 #define I2C_BWR_FLT_STARTF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_…  argument
7983 #define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)  argument
7984 #define I2C_BRD_FLT_SSIE(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT, I2C_FLT_SSIE_WIDT…  argument
7987 #define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | …  argument
7988 #define I2C_BWR_FLT_SSIE(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SS…  argument
8003 #define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)  argument
8004 #define I2C_BRD_FLT_STOPF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT, I2C_FLT_STOPF_W…  argument
8007 #define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK)…  argument
8008 #define I2C_BWR_FLT_STOPF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_S…  argument
8045 #define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)  argument
8046 #define I2C_BRD_FLT_SHEN(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT, I2C_FLT_SHEN_WIDT…  argument
8049 #define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | …  argument
8050 #define I2C_BWR_FLT_SHEN(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SH…  argument
8066 #define I2C_RD_RA(base)          (I2C_RA_REG(base))  argument
8067 #define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))  argument
8068 #define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))  argument
8069 #define I2C_SET_RA(base, value)  (BME_OR8(&I2C_RA_REG(base), (uint8_t)(value)))  argument
8070 #define I2C_CLR_RA(base, value)  (BME_AND8(&I2C_RA_REG(base), (uint8_t)(~(value))))  argument
8071 #define I2C_TOG_RA(base, value)  (BME_XOR8(&I2C_RA_REG(base), (uint8_t)(value)))  argument
8088 #define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)  argument
8089 #define I2C_BRD_RA_RAD(base) (BME_UBFX8(&I2C_RA_REG(base), I2C_RA_RAD_SHIFT, I2C_RA_RAD_WIDTH))  argument
8092 #define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))  argument
8093 #define I2C_BWR_RA_RAD(base, value) (BME_BFI8(&I2C_RA_REG(base), ((uint8_t)(value) << I2C_RA_RAD_SH…  argument
8117 #define I2C_RD_SMB(base)         (I2C_SMB_REG(base))  argument
8118 #define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))  argument
8119 #define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))  argument
8120 #define I2C_SET_SMB(base, value) (BME_OR8(&I2C_SMB_REG(base), (uint8_t)(value)))  argument
8121 #define I2C_CLR_SMB(base, value) (BME_AND8(&I2C_SMB_REG(base), (uint8_t)(~(value))))  argument
8122 #define I2C_TOG_SMB(base, value) (BME_XOR8(&I2C_SMB_REG(base), (uint8_t)(value)))  argument
8140 #define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHI…  argument
8141 #define I2C_BRD_SMB_SHTF2IE(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT, I2C_SMB_SHT…  argument
8144 #define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MA…  argument
8145 #define I2C_BWR_SMB_SHTF2IE(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB…  argument
8160 #define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)  argument
8161 #define I2C_BRD_SMB_SHTF2(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT, I2C_SMB_SHTF2_W…  argument
8164 #define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), …  argument
8165 #define I2C_BWR_SMB_SHTF2(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_S…  argument
8180 #define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)  argument
8181 #define I2C_BRD_SMB_SHTF1(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT, I2C_SMB_SHTF1_W…  argument
8198 #define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)  argument
8199 #define I2C_BRD_SMB_SLTF(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT, I2C_SMB_SLTF_WIDT…  argument
8202 #define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I…  argument
8203 #define I2C_BWR_SMB_SLTF(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SL…  argument
8217 #define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)  argument
8218 #define I2C_BRD_SMB_TCKSEL(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT, I2C_SMB_TCKSE…  argument
8221 #define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK…  argument
8222 #define I2C_BWR_SMB_TCKSEL(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_…  argument
8236 #define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHI…  argument
8237 #define I2C_BRD_SMB_SIICAEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT, I2C_SMB_SII…  argument
8240 #define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MA…  argument
8241 #define I2C_BWR_SMB_SIICAEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB…  argument
8258 #define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHI…  argument
8259 #define I2C_BRD_SMB_ALERTEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT, I2C_SMB_ALE…  argument
8262 #define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MA…  argument
8263 #define I2C_BWR_SMB_ALERTEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB…  argument
8279 #define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)  argument
8280 #define I2C_BRD_SMB_FACK(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT, I2C_SMB_FACK_WIDT…  argument
8283 #define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I…  argument
8284 #define I2C_BWR_SMB_FACK(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_FA…  argument
8300 #define I2C_RD_A2(base)          (I2C_A2_REG(base))  argument
8301 #define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))  argument
8302 #define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))  argument
8303 #define I2C_SET_A2(base, value)  (BME_OR8(&I2C_A2_REG(base), (uint8_t)(value)))  argument
8304 #define I2C_CLR_A2(base, value)  (BME_AND8(&I2C_A2_REG(base), (uint8_t)(~(value))))  argument
8305 #define I2C_TOG_A2(base, value)  (BME_XOR8(&I2C_A2_REG(base), (uint8_t)(value)))  argument
8320 #define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)  argument
8321 #define I2C_BRD_A2_SAD(base) (BME_UBFX8(&I2C_A2_REG(base), I2C_A2_SAD_SHIFT, I2C_A2_SAD_WIDTH))  argument
8324 #define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))  argument
8325 #define I2C_BWR_A2_SAD(base, value) (BME_BFI8(&I2C_A2_REG(base), ((uint8_t)(value) << I2C_A2_SAD_SH…  argument
8341 #define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))  argument
8342 #define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))  argument
8343 #define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))  argument
8344 #define I2C_SET_SLTH(base, value) (BME_OR8(&I2C_SLTH_REG(base), (uint8_t)(value)))  argument
8345 #define I2C_CLR_SLTH(base, value) (BME_AND8(&I2C_SLTH_REG(base), (uint8_t)(~(value))))  argument
8346 #define I2C_TOG_SLTH(base, value) (BME_XOR8(&I2C_SLTH_REG(base), (uint8_t)(value)))  argument
8362 #define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))  argument
8363 #define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))  argument
8364 #define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))  argument
8365 #define I2C_SET_SLTL(base, value) (BME_OR8(&I2C_SLTL_REG(base), (uint8_t)(value)))  argument
8366 #define I2C_CLR_SLTL(base, value) (BME_AND8(&I2C_SLTL_REG(base), (uint8_t)(~(value))))  argument
8367 #define I2C_TOG_SLTL(base, value) (BME_XOR8(&I2C_SLTL_REG(base), (uint8_t)(value)))  argument
8383 #define I2C_RD_S2(base)          (I2C_S2_REG(base))  argument
8384 #define I2C_WR_S2(base, value)   (I2C_S2_REG(base) = (value))  argument
8385 #define I2C_RMW_S2(base, mask, value) (I2C_WR_S2(base, (I2C_RD_S2(base) & ~(mask)) | (value)))  argument
8386 #define I2C_SET_S2(base, value)  (BME_OR8(&I2C_S2_REG(base), (uint8_t)(value)))  argument
8387 #define I2C_CLR_S2(base, value)  (BME_AND8(&I2C_S2_REG(base), (uint8_t)(~(value))))  argument
8388 #define I2C_TOG_S2(base, value)  (BME_XOR8(&I2C_S2_REG(base), (uint8_t)(value)))  argument
8409 #define I2C_RD_S2_EMPTY(base) ((I2C_S2_REG(base) & I2C_S2_EMPTY_MASK) >> I2C_S2_EMPTY_SHIFT)  argument
8410 #define I2C_BRD_S2_EMPTY(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_EMPTY_SHIFT, I2C_S2_EMPTY_WIDTH…  argument
8425 #define I2C_RD_S2_ERROR(base) ((I2C_S2_REG(base) & I2C_S2_ERROR_MASK) >> I2C_S2_ERROR_SHIFT)  argument
8426 #define I2C_BRD_S2_ERROR(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_ERROR_SHIFT, I2C_S2_ERROR_WIDTH…  argument
8429 #define I2C_WR_S2_ERROR(base, value) (I2C_RMW_S2(base, I2C_S2_ERROR_MASK, I2C_S2_ERROR(value)))  argument
8430 #define I2C_BWR_S2_ERROR(base, value) (BME_BFI8(&I2C_S2_REG(base), ((uint8_t)(value) << I2C_S2_ERRO…  argument
8475 #define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))  argument
8476 #define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))  argument
8477 #define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))  argument
8478 #define LLWU_SET_PE1(base, value) (BME_OR8(&LLWU_PE1_REG(base), (uint8_t)(value)))  argument
8479 #define LLWU_CLR_PE1(base, value) (BME_AND8(&LLWU_PE1_REG(base), (uint8_t)(~(value))))  argument
8480 #define LLWU_TOG_PE1(base, value) (BME_XOR8(&LLWU_PE1_REG(base), (uint8_t)(value)))  argument
8500 #define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)  argument
8501 #define LLWU_BRD_PE1_WUPE0(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE0_SHIFT, LLWU_PE1_WUP…  argument
8504 #define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(valu…  argument
8505 #define LLWU_BWR_PE1_WUPE0(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8521 #define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)  argument
8522 #define LLWU_BRD_PE1_WUPE1(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE1_SHIFT, LLWU_PE1_WUP…  argument
8525 #define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(valu…  argument
8526 #define LLWU_BWR_PE1_WUPE1(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8542 #define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)  argument
8543 #define LLWU_BRD_PE1_WUPE2(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE2_SHIFT, LLWU_PE1_WUP…  argument
8546 #define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(valu…  argument
8547 #define LLWU_BWR_PE1_WUPE2(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8563 #define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)  argument
8564 #define LLWU_BRD_PE1_WUPE3(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE3_SHIFT, LLWU_PE1_WUP…  argument
8567 #define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(valu…  argument
8568 #define LLWU_BWR_PE1_WUPE3(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8592 #define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))  argument
8593 #define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))  argument
8594 #define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))  argument
8595 #define LLWU_SET_PE2(base, value) (BME_OR8(&LLWU_PE2_REG(base), (uint8_t)(value)))  argument
8596 #define LLWU_CLR_PE2(base, value) (BME_AND8(&LLWU_PE2_REG(base), (uint8_t)(~(value))))  argument
8597 #define LLWU_TOG_PE2(base, value) (BME_XOR8(&LLWU_PE2_REG(base), (uint8_t)(value)))  argument
8617 #define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)  argument
8618 #define LLWU_BRD_PE2_WUPE4(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE4_SHIFT, LLWU_PE2_WUP…  argument
8621 #define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(valu…  argument
8622 #define LLWU_BWR_PE2_WUPE4(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8638 #define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)  argument
8639 #define LLWU_BRD_PE2_WUPE5(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE5_SHIFT, LLWU_PE2_WUP…  argument
8642 #define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(valu…  argument
8643 #define LLWU_BWR_PE2_WUPE5(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8659 #define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)  argument
8660 #define LLWU_BRD_PE2_WUPE6(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE6_SHIFT, LLWU_PE2_WUP…  argument
8663 #define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(valu…  argument
8664 #define LLWU_BWR_PE2_WUPE6(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8680 #define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)  argument
8681 #define LLWU_BRD_PE2_WUPE7(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE7_SHIFT, LLWU_PE2_WUP…  argument
8684 #define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(valu…  argument
8685 #define LLWU_BWR_PE2_WUPE7(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8709 #define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))  argument
8710 #define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))  argument
8711 #define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))  argument
8712 #define LLWU_SET_PE3(base, value) (BME_OR8(&LLWU_PE3_REG(base), (uint8_t)(value)))  argument
8713 #define LLWU_CLR_PE3(base, value) (BME_AND8(&LLWU_PE3_REG(base), (uint8_t)(~(value))))  argument
8714 #define LLWU_TOG_PE3(base, value) (BME_XOR8(&LLWU_PE3_REG(base), (uint8_t)(value)))  argument
8734 #define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)  argument
8735 #define LLWU_BRD_PE3_WUPE8(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE8_SHIFT, LLWU_PE3_WUP…  argument
8738 #define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(valu…  argument
8739 #define LLWU_BWR_PE3_WUPE8(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8755 #define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)  argument
8756 #define LLWU_BRD_PE3_WUPE9(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE9_SHIFT, LLWU_PE3_WUP…  argument
8759 #define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(valu…  argument
8760 #define LLWU_BWR_PE3_WUPE9(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE…  argument
8776 #define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SH…  argument
8777 #define LLWU_BRD_PE3_WUPE10(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE10_SHIFT, LLWU_PE3_W…  argument
8780 #define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(v…  argument
8781 #define LLWU_BWR_PE3_WUPE10(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8797 #define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SH…  argument
8798 #define LLWU_BRD_PE3_WUPE11(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE11_SHIFT, LLWU_PE3_W…  argument
8801 #define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(v…  argument
8802 #define LLWU_BWR_PE3_WUPE11(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8826 #define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))  argument
8827 #define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))  argument
8828 #define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))  argument
8829 #define LLWU_SET_PE4(base, value) (BME_OR8(&LLWU_PE4_REG(base), (uint8_t)(value)))  argument
8830 #define LLWU_CLR_PE4(base, value) (BME_AND8(&LLWU_PE4_REG(base), (uint8_t)(~(value))))  argument
8831 #define LLWU_TOG_PE4(base, value) (BME_XOR8(&LLWU_PE4_REG(base), (uint8_t)(value)))  argument
8851 #define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SH…  argument
8852 #define LLWU_BRD_PE4_WUPE12(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE12_SHIFT, LLWU_PE4_W…  argument
8855 #define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(v…  argument
8856 #define LLWU_BWR_PE4_WUPE12(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8872 #define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SH…  argument
8873 #define LLWU_BRD_PE4_WUPE13(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE13_SHIFT, LLWU_PE4_W…  argument
8876 #define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(v…  argument
8877 #define LLWU_BWR_PE4_WUPE13(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8893 #define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SH…  argument
8894 #define LLWU_BRD_PE4_WUPE14(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE14_SHIFT, LLWU_PE4_W…  argument
8897 #define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(v…  argument
8898 #define LLWU_BWR_PE4_WUPE14(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8914 #define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SH…  argument
8915 #define LLWU_BRD_PE4_WUPE15(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE15_SHIFT, LLWU_PE4_W…  argument
8918 #define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(v…  argument
8919 #define LLWU_BWR_PE4_WUPE15(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_P…  argument
8943 #define LLWU_RD_ME(base)         (LLWU_ME_REG(base))  argument
8944 #define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))  argument
8945 #define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))  argument
8946 #define LLWU_SET_ME(base, value) (BME_OR8(&LLWU_ME_REG(base), (uint8_t)(value)))  argument
8947 #define LLWU_CLR_ME(base, value) (BME_AND8(&LLWU_ME_REG(base), (uint8_t)(~(value))))  argument
8948 #define LLWU_TOG_ME(base, value) (BME_XOR8(&LLWU_ME_REG(base), (uint8_t)(value)))  argument
8966 #define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)  argument
8967 #define LLWU_BRD_ME_WUME0(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT, LLWU_ME_WUME0_W…  argument
8970 #define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))  argument
8971 #define LLWU_BWR_ME_WUME0(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
8985 #define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)  argument
8986 #define LLWU_BRD_ME_WUME1(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT, LLWU_ME_WUME1_W…  argument
8989 #define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))  argument
8990 #define LLWU_BWR_ME_WUME1(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9004 #define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)  argument
9005 #define LLWU_BRD_ME_WUME2(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT, LLWU_ME_WUME2_W…  argument
9008 #define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))  argument
9009 #define LLWU_BWR_ME_WUME2(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9023 #define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)  argument
9024 #define LLWU_BRD_ME_WUME3(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT, LLWU_ME_WUME3_W…  argument
9027 #define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))  argument
9028 #define LLWU_BWR_ME_WUME3(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9042 #define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)  argument
9043 #define LLWU_BRD_ME_WUME4(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT, LLWU_ME_WUME4_W…  argument
9046 #define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))  argument
9047 #define LLWU_BWR_ME_WUME4(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9061 #define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)  argument
9062 #define LLWU_BRD_ME_WUME5(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT, LLWU_ME_WUME5_W…  argument
9065 #define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))  argument
9066 #define LLWU_BWR_ME_WUME5(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9080 #define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)  argument
9081 #define LLWU_BRD_ME_WUME6(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT, LLWU_ME_WUME6_W…  argument
9084 #define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))  argument
9085 #define LLWU_BWR_ME_WUME6(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9099 #define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)  argument
9100 #define LLWU_BRD_ME_WUME7(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT, LLWU_ME_WUME7_W…  argument
9103 #define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))  argument
9104 #define LLWU_BWR_ME_WUME7(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_W…  argument
9132 #define LLWU_RD_F1(base)         (LLWU_F1_REG(base))  argument
9133 #define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))  argument
9134 #define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))  argument
9135 #define LLWU_SET_F1(base, value) (BME_OR8(&LLWU_F1_REG(base), (uint8_t)(value)))  argument
9136 #define LLWU_CLR_F1(base, value) (BME_AND8(&LLWU_F1_REG(base), (uint8_t)(~(value))))  argument
9137 #define LLWU_TOG_F1(base, value) (BME_XOR8(&LLWU_F1_REG(base), (uint8_t)(value)))  argument
9156 #define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)  argument
9157 #define LLWU_BRD_F1_WUF0(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT, LLWU_F1_WUF0_WIDT…  argument
9160 #define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LL…  argument
9161 #define LLWU_BWR_F1_WUF0(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9176 #define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)  argument
9177 #define LLWU_BRD_F1_WUF1(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT, LLWU_F1_WUF1_WIDT…  argument
9180 #define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9181 #define LLWU_BWR_F1_WUF1(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9196 #define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)  argument
9197 #define LLWU_BRD_F1_WUF2(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT, LLWU_F1_WUF2_WIDT…  argument
9200 #define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9201 #define LLWU_BWR_F1_WUF2(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9216 #define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)  argument
9217 #define LLWU_BRD_F1_WUF3(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT, LLWU_F1_WUF3_WIDT…  argument
9220 #define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9221 #define LLWU_BWR_F1_WUF3(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9236 #define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)  argument
9237 #define LLWU_BRD_F1_WUF4(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT, LLWU_F1_WUF4_WIDT…  argument
9240 #define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9241 #define LLWU_BWR_F1_WUF4(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9256 #define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)  argument
9257 #define LLWU_BRD_F1_WUF5(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT, LLWU_F1_WUF5_WIDT…  argument
9260 #define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9261 #define LLWU_BWR_F1_WUF5(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9276 #define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)  argument
9277 #define LLWU_BRD_F1_WUF6(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT, LLWU_F1_WUF6_WIDT…  argument
9280 #define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9281 #define LLWU_BWR_F1_WUF6(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9296 #define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)  argument
9297 #define LLWU_BRD_F1_WUF7(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT, LLWU_F1_WUF7_WIDT…  argument
9300 #define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LL…  argument
9301 #define LLWU_BWR_F1_WUF7(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WU…  argument
9329 #define LLWU_RD_F2(base)         (LLWU_F2_REG(base))  argument
9330 #define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))  argument
9331 #define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))  argument
9332 #define LLWU_SET_F2(base, value) (BME_OR8(&LLWU_F2_REG(base), (uint8_t)(value)))  argument
9333 #define LLWU_CLR_F2(base, value) (BME_AND8(&LLWU_F2_REG(base), (uint8_t)(~(value))))  argument
9334 #define LLWU_TOG_F2(base, value) (BME_XOR8(&LLWU_F2_REG(base), (uint8_t)(value)))  argument
9353 #define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)  argument
9354 #define LLWU_BRD_F2_WUF8(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT, LLWU_F2_WUF8_WIDT…  argument
9357 #define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LL…  argument
9358 #define LLWU_BWR_F2_WUF8(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WU…  argument
9373 #define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)  argument
9374 #define LLWU_BRD_F2_WUF9(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT, LLWU_F2_WUF9_WIDT…  argument
9377 #define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LL…  argument
9378 #define LLWU_BWR_F2_WUF9(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WU…  argument
9393 #define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)  argument
9394 #define LLWU_BRD_F2_WUF10(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT, LLWU_F2_WUF10_W…  argument
9397 #define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | …  argument
9398 #define LLWU_BWR_F2_WUF10(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9413 #define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)  argument
9414 #define LLWU_BRD_F2_WUF11(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT, LLWU_F2_WUF11_W…  argument
9417 #define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | …  argument
9418 #define LLWU_BWR_F2_WUF11(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9433 #define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)  argument
9434 #define LLWU_BRD_F2_WUF12(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT, LLWU_F2_WUF12_W…  argument
9437 #define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | …  argument
9438 #define LLWU_BWR_F2_WUF12(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9453 #define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)  argument
9454 #define LLWU_BRD_F2_WUF13(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT, LLWU_F2_WUF13_W…  argument
9457 #define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | …  argument
9458 #define LLWU_BWR_F2_WUF13(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9473 #define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)  argument
9474 #define LLWU_BRD_F2_WUF14(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT, LLWU_F2_WUF14_W…  argument
9477 #define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | …  argument
9478 #define LLWU_BWR_F2_WUF14(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9493 #define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)  argument
9494 #define LLWU_BRD_F2_WUF15(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT, LLWU_F2_WUF15_W…  argument
9497 #define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | …  argument
9498 #define LLWU_BWR_F2_WUF15(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_W…  argument
9528 #define LLWU_RD_F3(base)         (LLWU_F3_REG(base))  argument
9548 #define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)  argument
9549 #define LLWU_BRD_F3_MWUF0(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT, LLWU_F3_MWUF0_W…  argument
9565 #define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)  argument
9566 #define LLWU_BRD_F3_MWUF1(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT, LLWU_F3_MWUF1_W…  argument
9582 #define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)  argument
9583 #define LLWU_BRD_F3_MWUF2(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT, LLWU_F3_MWUF2_W…  argument
9599 #define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)  argument
9600 #define LLWU_BRD_F3_MWUF3(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT, LLWU_F3_MWUF3_W…  argument
9616 #define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)  argument
9617 #define LLWU_BRD_F3_MWUF4(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT, LLWU_F3_MWUF4_W…  argument
9633 #define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)  argument
9634 #define LLWU_BRD_F3_MWUF5(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT, LLWU_F3_MWUF5_W…  argument
9650 #define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)  argument
9651 #define LLWU_BRD_F3_MWUF6(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT, LLWU_F3_MWUF6_W…  argument
9667 #define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)  argument
9668 #define LLWU_BRD_F3_MWUF7(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT, LLWU_F3_MWUF7_W…  argument
9692 #define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))  argument
9693 #define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))  argument
9694 #define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (v…  argument
9695 #define LLWU_SET_FILT1(base, value) (BME_OR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))  argument
9696 #define LLWU_CLR_FILT1(base, value) (BME_AND8(&LLWU_FILT1_REG(base), (uint8_t)(~(value))))  argument
9697 #define LLWU_TOG_FILT1(base, value) (BME_XOR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))  argument
9715 #define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1…  argument
9716 #define LLWU_BRD_FILT1_FILTSEL(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTSEL_SHIFT, LL…  argument
9719 #define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FI…  argument
9720 #define LLWU_BWR_FILT1_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << L…  argument
9736 #define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FIL…  argument
9737 #define LLWU_BRD_FILT1_FILTE(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTE_SHIFT, LLWU_F…  argument
9740 #define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_…  argument
9741 #define LLWU_BWR_FILT1_FILTE(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLW…  argument
9757 #define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FIL…  argument
9758 #define LLWU_BRD_FILT1_FILTF(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT, LLWU_F…  argument
9761 #define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FI…  argument
9762 #define LLWU_BWR_FILT1_FILTF(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLW…  argument
9786 #define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))  argument
9787 #define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))  argument
9788 #define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (v…  argument
9789 #define LLWU_SET_FILT2(base, value) (BME_OR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))  argument
9790 #define LLWU_CLR_FILT2(base, value) (BME_AND8(&LLWU_FILT2_REG(base), (uint8_t)(~(value))))  argument
9791 #define LLWU_TOG_FILT2(base, value) (BME_XOR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))  argument
9809 #define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2…  argument
9810 #define LLWU_BRD_FILT2_FILTSEL(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTSEL_SHIFT, LL…  argument
9813 #define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FI…  argument
9814 #define LLWU_BWR_FILT2_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << L…  argument
9830 #define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FIL…  argument
9831 #define LLWU_BRD_FILT2_FILTE(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTE_SHIFT, LLWU_F…  argument
9834 #define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_…  argument
9835 #define LLWU_BWR_FILT2_FILTE(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLW…  argument
9851 #define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FIL…  argument
9852 #define LLWU_BRD_FILT2_FILTF(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT, LLWU_F…  argument
9855 #define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FI…  argument
9856 #define LLWU_BWR_FILT2_FILTF(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLW…  argument
9887 #define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))  argument
9888 #define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))  argument
9889 #define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (valu…  argument
9890 #define LPTMR_SET_CSR(base, value) (BME_OR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))  argument
9891 #define LPTMR_CLR_CSR(base, value) (BME_AND32(&LPTMR_CSR_REG(base), (uint32_t)(~(value))))  argument
9892 #define LPTMR_TOG_CSR(base, value) (BME_XOR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))  argument
9912 #define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)  argument
9913 #define LPTMR_BRD_CSR_TEN(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TE…  argument
9916 #define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK…  argument
9917 #define LPTMR_BWR_CSR_TEN(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
9932 #define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)  argument
9933 #define LPTMR_BRD_CSR_TMS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TM…  argument
9936 #define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK…  argument
9937 #define LPTMR_BWR_CSR_TMS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
9953 #define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)  argument
9954 #define LPTMR_BRD_CSR_TFC(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TF…  argument
9957 #define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK…  argument
9958 #define LPTMR_BWR_CSR_TFC(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
9975 #define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)  argument
9976 #define LPTMR_BRD_CSR_TPP(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TP…  argument
9979 #define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK…  argument
9980 #define LPTMR_BWR_CSR_TPP(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
9999 #define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)  argument
10000 #define LPTMR_BRD_CSR_TPS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TP…  argument
10003 #define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK…  argument
10004 #define LPTMR_BWR_CSR_TPS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
10018 #define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)  argument
10019 #define LPTMR_BRD_CSR_TIE(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TI…  argument
10022 #define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK…  argument
10023 #define LPTMR_BWR_CSR_TIE(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
10038 #define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)  argument
10039 #define LPTMR_BRD_CSR_TCF(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TC…  argument
10042 #define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)…  argument
10043 #define LPTMR_BWR_CSR_TCF(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
10059 #define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))  argument
10060 #define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))  argument
10061 #define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (valu…  argument
10062 #define LPTMR_SET_PSR(base, value) (BME_OR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))  argument
10063 #define LPTMR_CLR_PSR(base, value) (BME_AND32(&LPTMR_PSR_REG(base), (uint32_t)(~(value))))  argument
10064 #define LPTMR_TOG_PSR(base, value) (BME_XOR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))  argument
10087 #define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)  argument
10088 #define LPTMR_BRD_PSR_PCS(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PC…  argument
10091 #define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)…  argument
10092 #define LPTMR_BWR_PSR_PCS(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR…  argument
10109 #define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIF…  argument
10110 #define LPTMR_BRD_PSR_PBYP(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_…  argument
10113 #define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(val…  argument
10114 #define LPTMR_BWR_PSR_PBYP(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTM…  argument
10160 #define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_P…  argument
10161 #define LPTMR_BRD_PSR_PRESCALE(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PRESCALE_SHIFT, LP…  argument
10164 #define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_…  argument
10165 #define LPTMR_BWR_PSR_PRESCALE(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << …  argument
10181 #define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))  argument
10182 #define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))  argument
10183 #define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (valu…  argument
10184 #define LPTMR_SET_CMR(base, value) (BME_OR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))  argument
10185 #define LPTMR_CLR_CMR(base, value) (BME_AND32(&LPTMR_CMR_REG(base), (uint32_t)(~(value))))  argument
10186 #define LPTMR_TOG_CMR(base, value) (BME_XOR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))  argument
10204 #define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COM…  argument
10205 #define LPTMR_BRD_CMR_COMPARE(base) (BME_UBFX32(&LPTMR_CMR_REG(base), LPTMR_CMR_COMPARE_SHIFT, LPTM…  argument
10208 #define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_CO…  argument
10209 #define LPTMR_BWR_CMR_COMPARE(base, value) (BME_BFI32(&LPTMR_CMR_REG(base), ((uint32_t)(value) << L…  argument
10225 #define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))  argument
10226 #define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))  argument
10227 #define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (valu…  argument
10228 #define LPTMR_SET_CNR(base, value) (BME_OR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))  argument
10229 #define LPTMR_CLR_CNR(base, value) (BME_AND32(&LPTMR_CNR_REG(base), (uint32_t)(~(value))))  argument
10230 #define LPTMR_TOG_CNR(base, value) (BME_XOR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))  argument
10242 #define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COU…  argument
10243 #define LPTMR_BRD_CNR_COUNTER(base) (BME_UBFX32(&LPTMR_CNR_REG(base), LPTMR_CNR_COUNTER_SHIFT, LPTM…  argument
10246 #define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_CO…  argument
10247 #define LPTMR_BWR_CNR_COUNTER(base, value) (BME_BFI32(&LPTMR_CNR_REG(base), ((uint32_t)(value) << L…  argument
10280 #define LPUART_RD_BAUD(base)     (LPUART_BAUD_REG(base))  argument
10281 #define LPUART_WR_BAUD(base, value) (LPUART_BAUD_REG(base) = (value))  argument
10282 #define LPUART_RMW_BAUD(base, mask, value) (LPUART_WR_BAUD(base, (LPUART_RD_BAUD(base) & ~(mask)) |…  argument
10283 #define LPUART_SET_BAUD(base, value) (BME_OR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))  argument
10284 #define LPUART_CLR_BAUD(base, value) (BME_AND32(&LPUART_BAUD_REG(base), (uint32_t)(~(value))))  argument
10285 #define LPUART_TOG_BAUD(base, value) (BME_XOR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))  argument
10303 #define LPUART_RD_BAUD_SBR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBR_MASK) >> LPUART_BAUD_SBR…  argument
10304 #define LPUART_BRD_BAUD_SBR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBR_SHIFT, LPUART…  argument
10307 #define LPUART_WR_BAUD_SBR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBR_MASK, LPUART_BAUD_SB…  argument
10308 #define LPUART_BWR_BAUD_SBR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…  argument
10323 #define LPUART_RD_BAUD_SBNS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBNS_MASK) >> LPUART_BAUD_S…  argument
10324 #define LPUART_BRD_BAUD_SBNS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBNS_SHIFT, LPUA…  argument
10327 #define LPUART_WR_BAUD_SBNS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBNS_MASK, LPUART_BAUD_…  argument
10328 #define LPUART_BWR_BAUD_SBNS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << …  argument
10344 #define LPUART_RD_BAUD_RXEDGIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RXEDGIE_MASK) >> LPUART_…  argument
10345 #define LPUART_BRD_BAUD_RXEDGIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RXEDGIE_SHIFT…  argument
10348 #define LPUART_WR_BAUD_RXEDGIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RXEDGIE_MASK, LPUART…  argument
10349 #define LPUART_BWR_BAUD_RXEDGIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) …  argument
10364 #define LPUART_RD_BAUD_LBKDIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_LBKDIE_MASK) >> LPUART_BA…  argument
10365 #define LPUART_BRD_BAUD_LBKDIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_LBKDIE_SHIFT, …  argument
10368 #define LPUART_WR_BAUD_LBKDIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_LBKDIE_MASK, LPUART_B…  argument
10369 #define LPUART_BWR_BAUD_LBKDIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <…  argument
10385 #define LPUART_RD_BAUD_RESYNCDIS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RESYNCDIS_MASK) >> LPU…  argument
10386 #define LPUART_BRD_BAUD_RESYNCDIS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RESYNCDIS_S…  argument
10389 #define LPUART_WR_BAUD_RESYNCDIS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RESYNCDIS_MASK, LP…  argument
10390 #define LPUART_BWR_BAUD_RESYNCDIS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value…  argument
10410 #define LPUART_RD_BAUD_BOTHEDGE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_BOTHEDGE_MASK) >> LPUAR…  argument
10411 #define LPUART_BRD_BAUD_BOTHEDGE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_BOTHEDGE_SHI…  argument
10414 #define LPUART_WR_BAUD_BOTHEDGE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_BOTHEDGE_MASK, LPUA…  argument
10415 #define LPUART_BWR_BAUD_BOTHEDGE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value)…  argument
10431 #define LPUART_RD_BAUD_MATCFG(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MATCFG_MASK) >> LPUART_BA…  argument
10432 #define LPUART_BRD_BAUD_MATCFG(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MATCFG_SHIFT, …  argument
10435 #define LPUART_WR_BAUD_MATCFG(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MATCFG_MASK, LPUART_B…  argument
10436 #define LPUART_BWR_BAUD_MATCFG(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <…  argument
10451 #define LPUART_RD_BAUD_RDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RDMAE_MASK) >> LPUART_BAUD…  argument
10452 #define LPUART_BRD_BAUD_RDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RDMAE_SHIFT, LP…  argument
10455 #define LPUART_WR_BAUD_RDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RDMAE_MASK, LPUART_BAU…  argument
10456 #define LPUART_BWR_BAUD_RDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…  argument
10471 #define LPUART_RD_BAUD_TDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_TDMAE_MASK) >> LPUART_BAUD…  argument
10472 #define LPUART_BRD_BAUD_TDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_TDMAE_SHIFT, LP…  argument
10475 #define LPUART_WR_BAUD_TDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_TDMAE_MASK, LPUART_BAU…  argument
10476 #define LPUART_BWR_BAUD_TDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…  argument
10489 #define LPUART_RD_BAUD_OSR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_OSR_MASK) >> LPUART_BAUD_OSR…  argument
10490 #define LPUART_BRD_BAUD_OSR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_OSR_SHIFT, LPUART…  argument
10493 #define LPUART_WR_BAUD_OSR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_OSR_MASK, LPUART_BAUD_OS…  argument
10494 #define LPUART_BWR_BAUD_OSR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…  argument
10509 #define LPUART_RD_BAUD_M10(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_M10_MASK) >> LPUART_BAUD_M10…  argument
10510 #define LPUART_BRD_BAUD_M10(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_M10_SHIFT, LPUART…  argument
10513 #define LPUART_WR_BAUD_M10(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_M10_MASK, LPUART_BAUD_M1…  argument
10514 #define LPUART_BWR_BAUD_M10(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << L…  argument
10527 #define LPUART_RD_BAUD_MAEN2(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN2_MASK) >> LPUART_BAUD…  argument
10528 #define LPUART_BRD_BAUD_MAEN2(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN2_SHIFT, LP…  argument
10531 #define LPUART_WR_BAUD_MAEN2(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN2_MASK, LPUART_BAU…  argument
10532 #define LPUART_BWR_BAUD_MAEN2(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…  argument
10545 #define LPUART_RD_BAUD_MAEN1(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN1_MASK) >> LPUART_BAUD…  argument
10546 #define LPUART_BRD_BAUD_MAEN1(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN1_SHIFT, LP…  argument
10549 #define LPUART_WR_BAUD_MAEN1(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN1_MASK, LPUART_BAU…  argument
10550 #define LPUART_BWR_BAUD_MAEN1(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) <<…  argument
10566 #define LPUART_RD_STAT(base)     (LPUART_STAT_REG(base))  argument
10567 #define LPUART_WR_STAT(base, value) (LPUART_STAT_REG(base) = (value))  argument
10568 #define LPUART_RMW_STAT(base, mask, value) (LPUART_WR_STAT(base, (LPUART_RD_STAT(base) & ~(mask)) |…  argument
10569 #define LPUART_SET_STAT(base, value) (BME_OR32(&LPUART_STAT_REG(base), (uint32_t)(value)))  argument
10570 #define LPUART_CLR_STAT(base, value) (BME_AND32(&LPUART_STAT_REG(base), (uint32_t)(~(value))))  argument
10571 #define LPUART_TOG_STAT(base, value) (BME_XOR32(&LPUART_STAT_REG(base), (uint32_t)(value)))  argument
10590 #define LPUART_RD_STAT_MA2F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA2F_MASK) >> LPUART_STAT_M…  argument
10591 #define LPUART_BRD_STAT_MA2F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA2F_SHIFT, LPUA…  argument
10594 #define LPUART_WR_STAT_MA2F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA2F_MASK | LPUART_STA…  argument
10595 #define LPUART_BWR_STAT_MA2F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …  argument
10610 #define LPUART_RD_STAT_MA1F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA1F_MASK) >> LPUART_STAT_M…  argument
10611 #define LPUART_BRD_STAT_MA1F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA1F_SHIFT, LPUA…  argument
10614 #define LPUART_WR_STAT_MA1F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA1F_MASK | LPUART_STA…  argument
10615 #define LPUART_BWR_STAT_MA1F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …  argument
10632 #define LPUART_RD_STAT_PF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_PF_MASK) >> LPUART_STAT_PF_SH…  argument
10633 #define LPUART_BRD_STAT_PF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_PF_SHIFT, LPUART_S…  argument
10636 #define LPUART_WR_STAT_PF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_PF_MASK | LPUART_STAT_MA…  argument
10637 #define LPUART_BWR_STAT_PF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…  argument
10654 #define LPUART_RD_STAT_FE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_FE_MASK) >> LPUART_STAT_FE_SH…  argument
10655 #define LPUART_BRD_STAT_FE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_FE_SHIFT, LPUART_S…  argument
10658 #define LPUART_WR_STAT_FE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_FE_MASK | LPUART_STAT_MA…  argument
10659 #define LPUART_BWR_STAT_FE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…  argument
10678 #define LPUART_RD_STAT_NF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_NF_MASK) >> LPUART_STAT_NF_SH…  argument
10679 #define LPUART_BRD_STAT_NF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_NF_SHIFT, LPUART_S…  argument
10682 #define LPUART_WR_STAT_NF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_NF_MASK | LPUART_STAT_MA…  argument
10683 #define LPUART_BWR_STAT_NF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…  argument
10705 #define LPUART_RD_STAT_OR(base) ((LPUART_STAT_REG(base) & LPUART_STAT_OR_MASK) >> LPUART_STAT_OR_SH…  argument
10706 #define LPUART_BRD_STAT_OR(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_OR_SHIFT, LPUART_S…  argument
10709 #define LPUART_WR_STAT_OR(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_OR_MASK | LPUART_STAT_MA…  argument
10710 #define LPUART_BWR_STAT_OR(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LP…  argument
10736 #define LPUART_RD_STAT_IDLE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_IDLE_MASK) >> LPUART_STAT_I…  argument
10737 #define LPUART_BRD_STAT_IDLE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_IDLE_SHIFT, LPUA…  argument
10740 #define LPUART_WR_STAT_IDLE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_IDLE_MASK | LPUART_STA…  argument
10741 #define LPUART_BWR_STAT_IDLE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …  argument
10764 #define LPUART_RD_STAT_RDRF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_R…  argument
10765 #define LPUART_BRD_STAT_RDRF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RDRF_SHIFT, LPUA…  argument
10785 #define LPUART_RD_STAT_TC(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TC_MASK) >> LPUART_STAT_TC_SH…  argument
10786 #define LPUART_BRD_STAT_TC(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TC_SHIFT, LPUART_S…  argument
10808 #define LPUART_RD_STAT_TDRE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_T…  argument
10809 #define LPUART_BRD_STAT_TDRE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TDRE_SHIFT, LPUA…  argument
10824 #define LPUART_RD_STAT_RAF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RAF_MASK) >> LPUART_STAT_RAF…  argument
10825 #define LPUART_BRD_STAT_RAF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RAF_SHIFT, LPUART…  argument
10844 #define LPUART_RD_STAT_LBKDE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDE_MASK) >> LPUART_STAT…  argument
10845 #define LPUART_BRD_STAT_LBKDE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDE_SHIFT, LP…  argument
10848 #define LPUART_WR_STAT_LBKDE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDE_MASK | LPUART_S…  argument
10849 #define LPUART_BWR_STAT_LBKDE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…  argument
10869 #define LPUART_RD_STAT_BRK13(base) ((LPUART_STAT_REG(base) & LPUART_STAT_BRK13_MASK) >> LPUART_STAT…  argument
10870 #define LPUART_BRD_STAT_BRK13(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_BRK13_SHIFT, LP…  argument
10873 #define LPUART_WR_STAT_BRK13(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_BRK13_MASK | LPUART_S…  argument
10874 #define LPUART_BWR_STAT_BRK13(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…  argument
10895 #define LPUART_RD_STAT_RWUID(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RWUID_MASK) >> LPUART_STAT…  argument
10896 #define LPUART_BRD_STAT_RWUID(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RWUID_SHIFT, LP…  argument
10899 #define LPUART_WR_STAT_RWUID(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RWUID_MASK | LPUART_S…  argument
10900 #define LPUART_BWR_STAT_RWUID(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…  argument
10916 #define LPUART_RD_STAT_RXINV(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXINV_MASK) >> LPUART_STAT…  argument
10917 #define LPUART_BRD_STAT_RXINV(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXINV_SHIFT, LP…  argument
10920 #define LPUART_WR_STAT_RXINV(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXINV_MASK | LPUART_S…  argument
10921 #define LPUART_BWR_STAT_RXINV(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <<…  argument
10944 #define LPUART_RD_STAT_MSBF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MSBF_MASK) >> LPUART_STAT_M…  argument
10945 #define LPUART_BRD_STAT_MSBF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MSBF_SHIFT, LPUA…  argument
10948 #define LPUART_WR_STAT_MSBF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MSBF_MASK | LPUART_STA…  argument
10949 #define LPUART_BWR_STAT_MSBF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << …  argument
10964 #define LPUART_RD_STAT_RXEDGIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXEDGIF_MASK) >> LPUART_…  argument
10965 #define LPUART_BRD_STAT_RXEDGIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXEDGIF_SHIFT…  argument
10968 #define LPUART_WR_STAT_RXEDGIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXEDGIF_MASK | LPUA…  argument
10969 #define LPUART_BWR_STAT_RXEDGIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) …  argument
10984 #define LPUART_RD_STAT_LBKDIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDIF_MASK) >> LPUART_ST…  argument
10985 #define LPUART_BRD_STAT_LBKDIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDIF_SHIFT, …  argument
10988 #define LPUART_WR_STAT_LBKDIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDIF_MASK | LPUART…  argument
10989 #define LPUART_BWR_STAT_LBKDIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) <…  argument
11009 #define LPUART_RD_CTRL(base)     (LPUART_CTRL_REG(base))  argument
11010 #define LPUART_WR_CTRL(base, value) (LPUART_CTRL_REG(base) = (value))  argument
11011 #define LPUART_RMW_CTRL(base, mask, value) (LPUART_WR_CTRL(base, (LPUART_RD_CTRL(base) & ~(mask)) |…  argument
11012 #define LPUART_SET_CTRL(base, value) (BME_OR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))  argument
11013 #define LPUART_CLR_CTRL(base, value) (BME_AND32(&LPUART_CTRL_REG(base), (uint32_t)(~(value))))  argument
11014 #define LPUART_TOG_CTRL(base, value) (BME_XOR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))  argument
11035 #define LPUART_RD_CTRL_PT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PT_MASK) >> LPUART_CTRL_PT_SH…  argument
11036 #define LPUART_BRD_CTRL_PT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PT_SHIFT, LPUART_C…  argument
11039 #define LPUART_WR_CTRL_PT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PT_MASK, LPUART_CTRL_PT(v…  argument
11040 #define LPUART_BWR_CTRL_PT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…  argument
11055 #define LPUART_RD_CTRL_PE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PE_MASK) >> LPUART_CTRL_PE_SH…  argument
11056 #define LPUART_BRD_CTRL_PE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PE_SHIFT, LPUART_C…  argument
11059 #define LPUART_WR_CTRL_PE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PE_MASK, LPUART_CTRL_PE(v…  argument
11060 #define LPUART_BWR_CTRL_PE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…  argument
11081 #define LPUART_RD_CTRL_ILT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILT_MASK) >> LPUART_CTRL_ILT…  argument
11082 #define LPUART_BRD_CTRL_ILT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILT_SHIFT, LPUART…  argument
11085 #define LPUART_WR_CTRL_ILT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILT_MASK, LPUART_CTRL_IL…  argument
11086 #define LPUART_BWR_CTRL_ILT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…  argument
11102 #define LPUART_RD_CTRL_WAKE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_WAKE_MASK) >> LPUART_CTRL_W…  argument
11103 #define LPUART_BRD_CTRL_WAKE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_WAKE_SHIFT, LPUA…  argument
11106 #define LPUART_WR_CTRL_WAKE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_WAKE_MASK, LPUART_CTRL_…  argument
11107 #define LPUART_BWR_CTRL_WAKE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11119 #define LPUART_RD_CTRL_M(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_M_MASK) >> LPUART_CTRL_M_SHIFT)  argument
11120 #define LPUART_BRD_CTRL_M(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_M_SHIFT, LPUART_CTR…  argument
11123 #define LPUART_WR_CTRL_M(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_M_MASK, LPUART_CTRL_M(valu…  argument
11124 #define LPUART_BWR_CTRL_M(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPU…  argument
11142 #define LPUART_RD_CTRL_RSRC(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RSRC_MASK) >> LPUART_CTRL_R…  argument
11143 #define LPUART_BRD_CTRL_RSRC(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RSRC_SHIFT, LPUA…  argument
11146 #define LPUART_WR_CTRL_RSRC(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RSRC_MASK, LPUART_CTRL_…  argument
11147 #define LPUART_BWR_CTRL_RSRC(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11159 #define LPUART_RD_CTRL_DOZEEN(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_DOZEEN_MASK) >> LPUART_CT…  argument
11160 #define LPUART_BRD_CTRL_DOZEEN(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_DOZEEN_SHIFT, …  argument
11163 #define LPUART_WR_CTRL_DOZEEN(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_DOZEEN_MASK, LPUART_C…  argument
11164 #define LPUART_BWR_CTRL_DOZEEN(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <…  argument
11181 #define LPUART_RD_CTRL_LOOPS(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_LOOPS_MASK) >> LPUART_CTRL…  argument
11182 #define LPUART_BRD_CTRL_LOOPS(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_LOOPS_SHIFT, LP…  argument
11185 #define LPUART_WR_CTRL_LOOPS(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_LOOPS_MASK, LPUART_CTR…  argument
11186 #define LPUART_BWR_CTRL_LOOPS(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…  argument
11207 #define LPUART_RD_CTRL_IDLECFG(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_IDLECFG_MASK) >> LPUART_…  argument
11208 #define LPUART_BRD_CTRL_IDLECFG(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_IDLECFG_SHIFT…  argument
11211 #define LPUART_WR_CTRL_IDLECFG(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_IDLECFG_MASK, LPUART…  argument
11212 #define LPUART_BWR_CTRL_IDLECFG(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) …  argument
11224 #define LPUART_RD_CTRL_MA2IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA2IE_MASK) >> LPUART_CTRL…  argument
11225 #define LPUART_BRD_CTRL_MA2IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA2IE_SHIFT, LP…  argument
11228 #define LPUART_WR_CTRL_MA2IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA2IE_MASK, LPUART_CTR…  argument
11229 #define LPUART_BWR_CTRL_MA2IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…  argument
11241 #define LPUART_RD_CTRL_MA1IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA1IE_MASK) >> LPUART_CTRL…  argument
11242 #define LPUART_BRD_CTRL_MA1IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA1IE_SHIFT, LP…  argument
11245 #define LPUART_WR_CTRL_MA1IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA1IE_MASK, LPUART_CTR…  argument
11246 #define LPUART_BWR_CTRL_MA1IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…  argument
11265 #define LPUART_RD_CTRL_SBK(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_SBK_MASK) >> LPUART_CTRL_SBK…  argument
11266 #define LPUART_BRD_CTRL_SBK(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_SBK_SHIFT, LPUART…  argument
11269 #define LPUART_WR_CTRL_SBK(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_SBK_MASK, LPUART_CTRL_SB…  argument
11270 #define LPUART_BWR_CTRL_SBK(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…  argument
11292 #define LPUART_RD_CTRL_RWU(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RWU_MASK) >> LPUART_CTRL_RWU…  argument
11293 #define LPUART_BRD_CTRL_RWU(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RWU_SHIFT, LPUART…  argument
11296 #define LPUART_WR_CTRL_RWU(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RWU_MASK, LPUART_CTRL_RW…  argument
11297 #define LPUART_BWR_CTRL_RWU(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…  argument
11312 #define LPUART_RD_CTRL_RE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RE_MASK) >> LPUART_CTRL_RE_SH…  argument
11313 #define LPUART_BRD_CTRL_RE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RE_SHIFT, LPUART_C…  argument
11316 #define LPUART_WR_CTRL_RE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RE_MASK, LPUART_CTRL_RE(v…  argument
11317 #define LPUART_BWR_CTRL_RE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…  argument
11334 #define LPUART_RD_CTRL_TE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TE_MASK) >> LPUART_CTRL_TE_SH…  argument
11335 #define LPUART_BRD_CTRL_TE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TE_SHIFT, LPUART_C…  argument
11338 #define LPUART_WR_CTRL_TE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TE_MASK, LPUART_CTRL_TE(v…  argument
11339 #define LPUART_BWR_CTRL_TE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LP…  argument
11353 #define LPUART_RD_CTRL_ILIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILIE_MASK) >> LPUART_CTRL_I…  argument
11354 #define LPUART_BRD_CTRL_ILIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILIE_SHIFT, LPUA…  argument
11357 #define LPUART_WR_CTRL_ILIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILIE_MASK, LPUART_CTRL_…  argument
11358 #define LPUART_BWR_CTRL_ILIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11372 #define LPUART_RD_CTRL_RIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RIE_MASK) >> LPUART_CTRL_RIE…  argument
11373 #define LPUART_BRD_CTRL_RIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RIE_SHIFT, LPUART…  argument
11376 #define LPUART_WR_CTRL_RIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RIE_MASK, LPUART_CTRL_RI…  argument
11377 #define LPUART_BWR_CTRL_RIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…  argument
11392 #define LPUART_RD_CTRL_TCIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TCIE_MASK) >> LPUART_CTRL_T…  argument
11393 #define LPUART_BRD_CTRL_TCIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TCIE_SHIFT, LPUA…  argument
11396 #define LPUART_WR_CTRL_TCIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TCIE_MASK, LPUART_CTRL_…  argument
11397 #define LPUART_BWR_CTRL_TCIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11411 #define LPUART_RD_CTRL_TIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TIE_MASK) >> LPUART_CTRL_TIE…  argument
11412 #define LPUART_BRD_CTRL_TIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TIE_SHIFT, LPUART…  argument
11415 #define LPUART_WR_CTRL_TIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TIE_MASK, LPUART_CTRL_TI…  argument
11416 #define LPUART_BWR_CTRL_TIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << L…  argument
11431 #define LPUART_RD_CTRL_PEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PEIE_MASK) >> LPUART_CTRL_P…  argument
11432 #define LPUART_BRD_CTRL_PEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PEIE_SHIFT, LPUA…  argument
11435 #define LPUART_WR_CTRL_PEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PEIE_MASK, LPUART_CTRL_…  argument
11436 #define LPUART_BWR_CTRL_PEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11451 #define LPUART_RD_CTRL_FEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_FEIE_MASK) >> LPUART_CTRL_F…  argument
11452 #define LPUART_BRD_CTRL_FEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_FEIE_SHIFT, LPUA…  argument
11455 #define LPUART_WR_CTRL_FEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_FEIE_MASK, LPUART_CTRL_…  argument
11456 #define LPUART_BWR_CTRL_FEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11470 #define LPUART_RD_CTRL_NEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_NEIE_MASK) >> LPUART_CTRL_N…  argument
11471 #define LPUART_BRD_CTRL_NEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_NEIE_SHIFT, LPUA…  argument
11474 #define LPUART_WR_CTRL_NEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_NEIE_MASK, LPUART_CTRL_…  argument
11475 #define LPUART_BWR_CTRL_NEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11490 #define LPUART_RD_CTRL_ORIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ORIE_MASK) >> LPUART_CTRL_O…  argument
11491 #define LPUART_BRD_CTRL_ORIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ORIE_SHIFT, LPUA…  argument
11494 #define LPUART_WR_CTRL_ORIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ORIE_MASK, LPUART_CTRL_…  argument
11495 #define LPUART_BWR_CTRL_ORIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11511 #define LPUART_RD_CTRL_TXINV(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXINV_MASK) >> LPUART_CTRL…  argument
11512 #define LPUART_BRD_CTRL_TXINV(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXINV_SHIFT, LP…  argument
11515 #define LPUART_WR_CTRL_TXINV(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXINV_MASK, LPUART_CTR…  argument
11516 #define LPUART_BWR_CTRL_TXINV(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…  argument
11533 #define LPUART_RD_CTRL_TXDIR(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXDIR_MASK) >> LPUART_CTRL…  argument
11534 #define LPUART_BRD_CTRL_TXDIR(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXDIR_SHIFT, LP…  argument
11537 #define LPUART_WR_CTRL_TXDIR(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXDIR_MASK, LPUART_CTR…  argument
11538 #define LPUART_BWR_CTRL_TXDIR(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) <<…  argument
11554 #define LPUART_RD_CTRL_R9T8(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R9T8_MASK) >> LPUART_CTRL_R…  argument
11555 #define LPUART_BRD_CTRL_R9T8(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R9T8_SHIFT, LPUA…  argument
11558 #define LPUART_WR_CTRL_R9T8(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R9T8_MASK, LPUART_CTRL_…  argument
11559 #define LPUART_BWR_CTRL_R9T8(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11575 #define LPUART_RD_CTRL_R8T9(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R8T9_MASK) >> LPUART_CTRL_R…  argument
11576 #define LPUART_BRD_CTRL_R8T9(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R8T9_SHIFT, LPUA…  argument
11579 #define LPUART_WR_CTRL_R8T9(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R8T9_MASK, LPUART_CTRL_…  argument
11580 #define LPUART_BWR_CTRL_R8T9(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << …  argument
11601 #define LPUART_RD_DATA(base)     (LPUART_DATA_REG(base))  argument
11602 #define LPUART_WR_DATA(base, value) (LPUART_DATA_REG(base) = (value))  argument
11603 #define LPUART_RMW_DATA(base, mask, value) (LPUART_WR_DATA(base, (LPUART_RD_DATA(base) & ~(mask)) |…  argument
11604 #define LPUART_SET_DATA(base, value) (BME_OR32(&LPUART_DATA_REG(base), (uint32_t)(value)))  argument
11605 #define LPUART_CLR_DATA(base, value) (BME_AND32(&LPUART_DATA_REG(base), (uint32_t)(~(value))))  argument
11606 #define LPUART_TOG_DATA(base, value) (BME_XOR32(&LPUART_DATA_REG(base), (uint32_t)(value)))  argument
11620 #define LPUART_RD_DATA_R0T0(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R0T0_MASK) >> LPUART_DATA_R…  argument
11621 #define LPUART_BRD_DATA_R0T0(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R0T0_SHIFT, LPUA…  argument
11624 #define LPUART_WR_DATA_R0T0(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R0T0_MASK, LPUART_DATA_…  argument
11625 #define LPUART_BWR_DATA_R0T0(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11635 #define LPUART_RD_DATA_R1T1(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R1T1_MASK) >> LPUART_DATA_R…  argument
11636 #define LPUART_BRD_DATA_R1T1(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R1T1_SHIFT, LPUA…  argument
11639 #define LPUART_WR_DATA_R1T1(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R1T1_MASK, LPUART_DATA_…  argument
11640 #define LPUART_BWR_DATA_R1T1(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11650 #define LPUART_RD_DATA_R2T2(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R2T2_MASK) >> LPUART_DATA_R…  argument
11651 #define LPUART_BRD_DATA_R2T2(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R2T2_SHIFT, LPUA…  argument
11654 #define LPUART_WR_DATA_R2T2(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R2T2_MASK, LPUART_DATA_…  argument
11655 #define LPUART_BWR_DATA_R2T2(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11665 #define LPUART_RD_DATA_R3T3(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R3T3_MASK) >> LPUART_DATA_R…  argument
11666 #define LPUART_BRD_DATA_R3T3(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R3T3_SHIFT, LPUA…  argument
11669 #define LPUART_WR_DATA_R3T3(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R3T3_MASK, LPUART_DATA_…  argument
11670 #define LPUART_BWR_DATA_R3T3(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11680 #define LPUART_RD_DATA_R4T4(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R4T4_MASK) >> LPUART_DATA_R…  argument
11681 #define LPUART_BRD_DATA_R4T4(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R4T4_SHIFT, LPUA…  argument
11684 #define LPUART_WR_DATA_R4T4(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R4T4_MASK, LPUART_DATA_…  argument
11685 #define LPUART_BWR_DATA_R4T4(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11695 #define LPUART_RD_DATA_R5T5(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R5T5_MASK) >> LPUART_DATA_R…  argument
11696 #define LPUART_BRD_DATA_R5T5(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R5T5_SHIFT, LPUA…  argument
11699 #define LPUART_WR_DATA_R5T5(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R5T5_MASK, LPUART_DATA_…  argument
11700 #define LPUART_BWR_DATA_R5T5(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11710 #define LPUART_RD_DATA_R6T6(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R6T6_MASK) >> LPUART_DATA_R…  argument
11711 #define LPUART_BRD_DATA_R6T6(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R6T6_SHIFT, LPUA…  argument
11714 #define LPUART_WR_DATA_R6T6(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R6T6_MASK, LPUART_DATA_…  argument
11715 #define LPUART_BWR_DATA_R6T6(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11725 #define LPUART_RD_DATA_R7T7(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R7T7_MASK) >> LPUART_DATA_R…  argument
11726 #define LPUART_BRD_DATA_R7T7(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R7T7_SHIFT, LPUA…  argument
11729 #define LPUART_WR_DATA_R7T7(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R7T7_MASK, LPUART_DATA_…  argument
11730 #define LPUART_BWR_DATA_R7T7(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11740 #define LPUART_RD_DATA_R8T8(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R8T8_MASK) >> LPUART_DATA_R…  argument
11741 #define LPUART_BRD_DATA_R8T8(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R8T8_SHIFT, LPUA…  argument
11744 #define LPUART_WR_DATA_R8T8(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R8T8_MASK, LPUART_DATA_…  argument
11745 #define LPUART_BWR_DATA_R8T8(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11755 #define LPUART_RD_DATA_R9T9(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R9T9_MASK) >> LPUART_DATA_R…  argument
11756 #define LPUART_BRD_DATA_R9T9(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R9T9_SHIFT, LPUA…  argument
11759 #define LPUART_WR_DATA_R9T9(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R9T9_MASK, LPUART_DATA_…  argument
11760 #define LPUART_BWR_DATA_R9T9(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << …  argument
11776 #define LPUART_RD_DATA_IDLINE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_IDLINE_MASK) >> LPUART_DA…  argument
11777 #define LPUART_BRD_DATA_IDLINE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_IDLINE_SHIFT, …  argument
11792 #define LPUART_RD_DATA_RXEMPT(base) ((LPUART_DATA_REG(base) & LPUART_DATA_RXEMPT_MASK) >> LPUART_DA…  argument
11793 #define LPUART_BRD_DATA_RXEMPT(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_RXEMPT_SHIFT, …  argument
11813 #define LPUART_RD_DATA_FRETSC(base) ((LPUART_DATA_REG(base) & LPUART_DATA_FRETSC_MASK) >> LPUART_DA…  argument
11814 #define LPUART_BRD_DATA_FRETSC(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_FRETSC_SHIFT, …  argument
11817 #define LPUART_WR_DATA_FRETSC(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_FRETSC_MASK, LPUART_D…  argument
11818 #define LPUART_BWR_DATA_FRETSC(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) <…  argument
11833 #define LPUART_RD_DATA_PARITYE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_PARITYE_MASK) >> LPUART_…  argument
11834 #define LPUART_BRD_DATA_PARITYE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_PARITYE_SHIFT…  argument
11849 #define LPUART_RD_DATA_NOISY(base) ((LPUART_DATA_REG(base) & LPUART_DATA_NOISY_MASK) >> LPUART_DATA…  argument
11850 #define LPUART_BRD_DATA_NOISY(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_NOISY_SHIFT, LP…  argument
11866 #define LPUART_RD_MATCH(base)    (LPUART_MATCH_REG(base))  argument
11867 #define LPUART_WR_MATCH(base, value) (LPUART_MATCH_REG(base) = (value))  argument
11868 #define LPUART_RMW_MATCH(base, mask, value) (LPUART_WR_MATCH(base, (LPUART_RD_MATCH(base) & ~(mask)…  argument
11869 #define LPUART_SET_MATCH(base, value) (BME_OR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))  argument
11870 #define LPUART_CLR_MATCH(base, value) (BME_AND32(&LPUART_MATCH_REG(base), (uint32_t)(~(value))))  argument
11871 #define LPUART_TOG_MATCH(base, value) (BME_XOR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))  argument
11889 #define LPUART_RD_MATCH_MA1(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA1_MASK) >> LPUART_MATCH…  argument
11890 #define LPUART_BRD_MATCH_MA1(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA1_SHIFT, LPU…  argument
11893 #define LPUART_WR_MATCH_MA1(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA1_MASK, LPUART_MATC…  argument
11894 #define LPUART_BWR_MATCH_MA1(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) <<…  argument
11908 #define LPUART_RD_MATCH_MA2(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA2_MASK) >> LPUART_MATCH…  argument
11909 #define LPUART_BRD_MATCH_MA2(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA2_SHIFT, LPU…  argument
11912 #define LPUART_WR_MATCH_MA2(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA2_MASK, LPUART_MATC…  argument
11913 #define LPUART_BWR_MATCH_MA2(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) <<…  argument
11931 #define LPUART_RD_MODIR(base)    (LPUART_MODIR_REG(base))  argument
11932 #define LPUART_WR_MODIR(base, value) (LPUART_MODIR_REG(base) = (value))  argument
11933 #define LPUART_RMW_MODIR(base, mask, value) (LPUART_WR_MODIR(base, (LPUART_RD_MODIR(base) & ~(mask)…  argument
11934 #define LPUART_SET_MODIR(base, value) (BME_OR32(&LPUART_MODIR_REG(base), (uint32_t)(value)))  argument
11935 #define LPUART_CLR_MODIR(base, value) (BME_AND32(&LPUART_MODIR_REG(base), (uint32_t)(~(value))))  argument
11936 #define LPUART_TOG_MODIR(base, value) (BME_XOR32(&LPUART_MODIR_REG(base), (uint32_t)(value)))  argument
11959 #define LPUART_RD_MODIR_TXCTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSE_MASK) >> LPUART…  argument
11960 #define LPUART_BRD_MODIR_TXCTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSE_SHIF…  argument
11963 #define LPUART_WR_MODIR_TXCTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSE_MASK, LPUAR…  argument
11964 #define LPUART_BWR_MODIR_TXCTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…  argument
11981 #define LPUART_RD_MODIR_TXRTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXRTSE_MASK) >> LPUART…  argument
11982 #define LPUART_BRD_MODIR_TXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSE_SHIF…  argument
11985 #define LPUART_WR_MODIR_TXRTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXRTSE_MASK, LPUAR…  argument
11986 #define LPUART_BWR_MODIR_TXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…  argument
12002 #define LPUART_RD_MODIR_TXRTSPOL(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXRTSPOL_MASK) >> LP…  argument
12003 #define LPUART_BRD_MODIR_TXRTSPOL(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSPOL_…  argument
12006 #define LPUART_WR_MODIR_TXRTSPOL(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXRTSPOL_MASK, L…  argument
12007 #define LPUART_BWR_MODIR_TXRTSPOL(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(valu…  argument
12022 #define LPUART_RD_MODIR_RXRTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_RXRTSE_MASK) >> LPUART…  argument
12023 #define LPUART_BRD_MODIR_RXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_RXRTSE_SHIF…  argument
12026 #define LPUART_WR_MODIR_RXRTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_RXRTSE_MASK, LPUAR…  argument
12027 #define LPUART_BWR_MODIR_RXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…  argument
12042 #define LPUART_RD_MODIR_TXCTSC(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSC_MASK) >> LPUART…  argument
12043 #define LPUART_BRD_MODIR_TXCTSC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSC_SHIF…  argument
12046 #define LPUART_WR_MODIR_TXCTSC(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSC_MASK, LPUAR…  argument
12047 #define LPUART_BWR_MODIR_TXCTSC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value)…  argument
12061 #define LPUART_RD_MODIR_TXCTSSRC(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSSRC_MASK) >> LP…  argument
12062 #define LPUART_BRD_MODIR_TXCTSSRC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSSRC_…  argument
12065 #define LPUART_WR_MODIR_TXCTSSRC(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSSRC_MASK, L…  argument
12066 #define LPUART_BWR_MODIR_TXCTSSRC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(valu…  argument
12083 #define LPUART_RD_MODIR_TNP(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TNP_MASK) >> LPUART_MODIR…  argument
12084 #define LPUART_BRD_MODIR_TNP(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TNP_SHIFT, LPU…  argument
12087 #define LPUART_WR_MODIR_TNP(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TNP_MASK, LPUART_MODI…  argument
12088 #define LPUART_BWR_MODIR_TNP(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) <<…  argument
12102 #define LPUART_RD_MODIR_IREN(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_IREN_MASK) >> LPUART_MOD…  argument
12103 #define LPUART_BRD_MODIR_IREN(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_IREN_SHIFT, L…  argument
12106 #define LPUART_WR_MODIR_IREN(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_IREN_MASK, LPUART_MO…  argument
12107 #define LPUART_BWR_MODIR_IREN(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) <…  argument
12156 #define LTC_RD_MD(base)          (LTC_MD_REG(base))  argument
12157 #define LTC_WR_MD(base, value)   (LTC_MD_REG(base) = (value))  argument
12158 #define LTC_RMW_MD(base, mask, value) (LTC_WR_MD(base, (LTC_RD_MD(base) & ~(mask)) | (value)))  argument
12159 #define LTC_SET_MD(base, value)  (BME_OR32(&LTC_MD_REG(base), (uint32_t)(value)))  argument
12160 #define LTC_CLR_MD(base, value)  (BME_AND32(&LTC_MD_REG(base), (uint32_t)(~(value))))  argument
12161 #define LTC_TOG_MD(base, value)  (BME_XOR32(&LTC_MD_REG(base), (uint32_t)(value)))  argument
12181 #define LTC_RD_MD_ENC(base)  ((LTC_MD_REG(base) & LTC_MD_ENC_MASK) >> LTC_MD_ENC_SHIFT)  argument
12182 #define LTC_BRD_MD_ENC(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ENC_SHIFT, LTC_MD_ENC_WIDTH))  argument
12185 #define LTC_WR_MD_ENC(base, value) (LTC_RMW_MD(base, LTC_MD_ENC_MASK, LTC_MD_ENC(value)))  argument
12186 #define LTC_BWR_MD_ENC(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ENC_…  argument
12202 #define LTC_RD_MD_ICV_TEST(base) ((LTC_MD_REG(base) & LTC_MD_ICV_TEST_MASK) >> LTC_MD_ICV_TEST_SHIF…  argument
12203 #define LTC_BRD_MD_ICV_TEST(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ICV_TEST_SHIFT, LTC_MD_ICV_…  argument
12206 #define LTC_WR_MD_ICV_TEST(base, value) (LTC_RMW_MD(base, LTC_MD_ICV_TEST_MASK, LTC_MD_ICV_TEST(val…  argument
12207 #define LTC_BWR_MD_ICV_TEST(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD…  argument
12228 #define LTC_RD_MD_AS(base)   ((LTC_MD_REG(base) & LTC_MD_AS_MASK) >> LTC_MD_AS_SHIFT)  argument
12229 #define LTC_BRD_MD_AS(base)  (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AS_SHIFT, LTC_MD_AS_WIDTH))  argument
12232 #define LTC_WR_MD_AS(base, value) (LTC_RMW_MD(base, LTC_MD_AS_MASK, LTC_MD_AS(value)))  argument
12233 #define LTC_BWR_MD_AS(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AS_SH…  argument
12252 #define LTC_RD_MD_AAI(base)  ((LTC_MD_REG(base) & LTC_MD_AAI_MASK) >> LTC_MD_AAI_SHIFT)  argument
12253 #define LTC_BRD_MD_AAI(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AAI_SHIFT, LTC_MD_AAI_WIDTH))  argument
12256 #define LTC_WR_MD_AAI(base, value) (LTC_RMW_MD(base, LTC_MD_AAI_MASK, LTC_MD_AAI(value)))  argument
12257 #define LTC_BWR_MD_AAI(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AAI_…  argument
12271 #define LTC_RD_MD_ALG(base)  ((LTC_MD_REG(base) & LTC_MD_ALG_MASK) >> LTC_MD_ALG_SHIFT)  argument
12272 #define LTC_BRD_MD_ALG(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ALG_SHIFT, LTC_MD_ALG_WIDTH))  argument
12275 #define LTC_WR_MD_ALG(base, value) (LTC_RMW_MD(base, LTC_MD_ALG_MASK, LTC_MD_ALG(value)))  argument
12276 #define LTC_BWR_MD_ALG(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ALG_…  argument
12300 #define LTC_RD_KS(base)          (LTC_KS_REG(base))  argument
12301 #define LTC_WR_KS(base, value)   (LTC_KS_REG(base) = (value))  argument
12302 #define LTC_RMW_KS(base, mask, value) (LTC_WR_KS(base, (LTC_RD_KS(base) & ~(mask)) | (value)))  argument
12303 #define LTC_SET_KS(base, value)  (BME_OR32(&LTC_KS_REG(base), (uint32_t)(value)))  argument
12304 #define LTC_CLR_KS(base, value)  (BME_AND32(&LTC_KS_REG(base), (uint32_t)(~(value))))  argument
12305 #define LTC_TOG_KS(base, value)  (BME_XOR32(&LTC_KS_REG(base), (uint32_t)(value)))  argument
12332 #define LTC_RD_DS(base)          (LTC_DS_REG(base))  argument
12333 #define LTC_WR_DS(base, value)   (LTC_DS_REG(base) = (value))  argument
12334 #define LTC_RMW_DS(base, mask, value) (LTC_WR_DS(base, (LTC_RD_DS(base) & ~(mask)) | (value)))  argument
12335 #define LTC_SET_DS(base, value)  (BME_OR32(&LTC_DS_REG(base), (uint32_t)(value)))  argument
12336 #define LTC_CLR_DS(base, value)  (BME_AND32(&LTC_DS_REG(base), (uint32_t)(~(value))))  argument
12337 #define LTC_TOG_DS(base, value)  (BME_XOR32(&LTC_DS_REG(base), (uint32_t)(value)))  argument
12353 #define LTC_RD_DS_DS(base)   ((LTC_DS_REG(base) & LTC_DS_DS_MASK) >> LTC_DS_DS_SHIFT)  argument
12354 #define LTC_BRD_DS_DS(base)  (BME_UBFX32(&LTC_DS_REG(base), LTC_DS_DS_SHIFT, LTC_DS_DS_WIDTH))  argument
12357 #define LTC_WR_DS_DS(base, value) (LTC_RMW_DS(base, LTC_DS_DS_MASK, LTC_DS_DS(value)))  argument
12358 #define LTC_BWR_DS_DS(base, value) (BME_BFI32(&LTC_DS_REG(base), ((uint32_t)(value) << LTC_DS_DS_SH…  argument
12380 #define LTC_RD_ICVS(base)        (LTC_ICVS_REG(base))  argument
12381 #define LTC_WR_ICVS(base, value) (LTC_ICVS_REG(base) = (value))  argument
12382 #define LTC_RMW_ICVS(base, mask, value) (LTC_WR_ICVS(base, (LTC_RD_ICVS(base) & ~(mask)) | (value)))  argument
12383 #define LTC_SET_ICVS(base, value) (BME_OR32(&LTC_ICVS_REG(base), (uint32_t)(value)))  argument
12384 #define LTC_CLR_ICVS(base, value) (BME_AND32(&LTC_ICVS_REG(base), (uint32_t)(~(value))))  argument
12385 #define LTC_TOG_ICVS(base, value) (BME_XOR32(&LTC_ICVS_REG(base), (uint32_t)(value)))  argument
12399 #define LTC_RD_ICVS_ICVS(base) ((LTC_ICVS_REG(base) & LTC_ICVS_ICVS_MASK) >> LTC_ICVS_ICVS_SHIFT)  argument
12400 #define LTC_BRD_ICVS_ICVS(base) (BME_UBFX32(&LTC_ICVS_REG(base), LTC_ICVS_ICVS_SHIFT, LTC_ICVS_ICVS…  argument
12403 #define LTC_WR_ICVS_ICVS(base, value) (LTC_RMW_ICVS(base, LTC_ICVS_ICVS_MASK, LTC_ICVS_ICVS(value)))  argument
12404 #define LTC_BWR_ICVS_ICVS(base, value) (BME_BFI32(&LTC_ICVS_REG(base), ((uint32_t)(value) << LTC_IC…  argument
12423 #define LTC_WR_COM(base, value)  (LTC_COM_REG(base) = (value))  argument
12444 #define LTC_WR_COM_ALL(base, value) (LTC_WR_COM(base, LTC_COM_ALL(value)))  argument
12445 #define LTC_BWR_COM_ALL(base, value) (LTC_WR_COM_ALL(base, value))  argument
12461 #define LTC_WR_COM_AES(base, value) (LTC_WR_COM(base, LTC_COM_AES(value)))  argument
12462 #define LTC_BWR_COM_AES(base, value) (LTC_WR_COM_AES(base, value))  argument
12480 #define LTC_RD_CTL(base)         (LTC_CTL_REG(base))  argument
12481 #define LTC_WR_CTL(base, value)  (LTC_CTL_REG(base) = (value))  argument
12482 #define LTC_RMW_CTL(base, mask, value) (LTC_WR_CTL(base, (LTC_RD_CTL(base) & ~(mask)) | (value)))  argument
12483 #define LTC_SET_CTL(base, value) (BME_OR32(&LTC_CTL_REG(base), (uint32_t)(value)))  argument
12484 #define LTC_CLR_CTL(base, value) (BME_AND32(&LTC_CTL_REG(base), (uint32_t)(~(value))))  argument
12485 #define LTC_TOG_CTL(base, value) (BME_XOR32(&LTC_CTL_REG(base), (uint32_t)(value)))  argument
12505 #define LTC_RD_CTL_IM(base)  ((LTC_CTL_REG(base) & LTC_CTL_IM_MASK) >> LTC_CTL_IM_SHIFT)  argument
12506 #define LTC_BRD_CTL_IM(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IM_SHIFT, LTC_CTL_IM_WIDTH))  argument
12509 #define LTC_WR_CTL_IM(base, value) (LTC_RMW_CTL(base, LTC_CTL_IM_MASK, LTC_CTL_IM(value)))  argument
12510 #define LTC_BWR_CTL_IM(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IM…  argument
12526 #define LTC_RD_CTL_IFE(base) ((LTC_CTL_REG(base) & LTC_CTL_IFE_MASK) >> LTC_CTL_IFE_SHIFT)  argument
12527 #define LTC_BRD_CTL_IFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFE_SHIFT, LTC_CTL_IFE_WIDTH))  argument
12530 #define LTC_WR_CTL_IFE(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFE_MASK, LTC_CTL_IFE(value)))  argument
12531 #define LTC_BWR_CTL_IFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…  argument
12548 #define LTC_RD_CTL_IFR(base) ((LTC_CTL_REG(base) & LTC_CTL_IFR_MASK) >> LTC_CTL_IFR_SHIFT)  argument
12549 #define LTC_BRD_CTL_IFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFR_SHIFT, LTC_CTL_IFR_WIDTH))  argument
12552 #define LTC_WR_CTL_IFR(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFR_MASK, LTC_CTL_IFR(value)))  argument
12553 #define LTC_BWR_CTL_IFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…  argument
12569 #define LTC_RD_CTL_OFE(base) ((LTC_CTL_REG(base) & LTC_CTL_OFE_MASK) >> LTC_CTL_OFE_SHIFT)  argument
12570 #define LTC_BRD_CTL_OFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFE_SHIFT, LTC_CTL_OFE_WIDTH))  argument
12573 #define LTC_WR_CTL_OFE(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFE_MASK, LTC_CTL_OFE(value)))  argument
12574 #define LTC_BWR_CTL_OFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…  argument
12591 #define LTC_RD_CTL_OFR(base) ((LTC_CTL_REG(base) & LTC_CTL_OFR_MASK) >> LTC_CTL_OFR_SHIFT)  argument
12592 #define LTC_BRD_CTL_OFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFR_SHIFT, LTC_CTL_OFR_WIDTH))  argument
12595 #define LTC_WR_CTL_OFR(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFR_MASK, LTC_CTL_OFR(value)))  argument
12596 #define LTC_BWR_CTL_OFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…  argument
12612 #define LTC_RD_CTL_IFS(base) ((LTC_CTL_REG(base) & LTC_CTL_IFS_MASK) >> LTC_CTL_IFS_SHIFT)  argument
12613 #define LTC_BRD_CTL_IFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFS_SHIFT, LTC_CTL_IFS_WIDTH))  argument
12616 #define LTC_WR_CTL_IFS(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFS_MASK, LTC_CTL_IFS(value)))  argument
12617 #define LTC_BWR_CTL_IFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_I…  argument
12633 #define LTC_RD_CTL_OFS(base) ((LTC_CTL_REG(base) & LTC_CTL_OFS_MASK) >> LTC_CTL_OFS_SHIFT)  argument
12634 #define LTC_BRD_CTL_OFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFS_SHIFT, LTC_CTL_OFS_WIDTH))  argument
12637 #define LTC_WR_CTL_OFS(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFS_MASK, LTC_CTL_OFS(value)))  argument
12638 #define LTC_BWR_CTL_OFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_O…  argument
12655 #define LTC_RD_CTL_KIS(base) ((LTC_CTL_REG(base) & LTC_CTL_KIS_MASK) >> LTC_CTL_KIS_SHIFT)  argument
12656 #define LTC_BRD_CTL_KIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KIS_SHIFT, LTC_CTL_KIS_WIDTH))  argument
12659 #define LTC_WR_CTL_KIS(base, value) (LTC_RMW_CTL(base, LTC_CTL_KIS_MASK, LTC_CTL_KIS(value)))  argument
12660 #define LTC_BWR_CTL_KIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…  argument
12677 #define LTC_RD_CTL_KOS(base) ((LTC_CTL_REG(base) & LTC_CTL_KOS_MASK) >> LTC_CTL_KOS_SHIFT)  argument
12678 #define LTC_BRD_CTL_KOS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KOS_SHIFT, LTC_CTL_KOS_WIDTH))  argument
12681 #define LTC_WR_CTL_KOS(base, value) (LTC_RMW_CTL(base, LTC_CTL_KOS_MASK, LTC_CTL_KOS(value)))  argument
12682 #define LTC_BWR_CTL_KOS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…  argument
12699 #define LTC_RD_CTL_CIS(base) ((LTC_CTL_REG(base) & LTC_CTL_CIS_MASK) >> LTC_CTL_CIS_SHIFT)  argument
12700 #define LTC_BRD_CTL_CIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_CIS_SHIFT, LTC_CTL_CIS_WIDTH))  argument
12703 #define LTC_WR_CTL_CIS(base, value) (LTC_RMW_CTL(base, LTC_CTL_CIS_MASK, LTC_CTL_CIS(value)))  argument
12704 #define LTC_BWR_CTL_CIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_C…  argument
12721 #define LTC_RD_CTL_COS(base) ((LTC_CTL_REG(base) & LTC_CTL_COS_MASK) >> LTC_CTL_COS_SHIFT)  argument
12722 #define LTC_BRD_CTL_COS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_COS_SHIFT, LTC_CTL_COS_WIDTH))  argument
12725 #define LTC_WR_CTL_COS(base, value) (LTC_RMW_CTL(base, LTC_CTL_COS_MASK, LTC_CTL_COS(value)))  argument
12726 #define LTC_BWR_CTL_COS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_C…  argument
12744 #define LTC_RD_CTL_KAL(base) ((LTC_CTL_REG(base) & LTC_CTL_KAL_MASK) >> LTC_CTL_KAL_SHIFT)  argument
12745 #define LTC_BRD_CTL_KAL(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KAL_SHIFT, LTC_CTL_KAL_WIDTH))  argument
12748 #define LTC_WR_CTL_KAL(base, value) (LTC_RMW_CTL(base, LTC_CTL_KAL_MASK, LTC_CTL_KAL(value)))  argument
12749 #define LTC_BWR_CTL_KAL(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_K…  argument
12768 #define LTC_WR_CW(base, value)   (LTC_CW_REG(base) = (value))  argument
12783 #define LTC_WR_CW_CM(base, value) (LTC_WR_CW(base, LTC_CW_CM(value)))  argument
12784 #define LTC_BWR_CW_CM(base, value) (LTC_WR_CW_CM(base, value))  argument
12795 #define LTC_WR_CW_CDS(base, value) (LTC_WR_CW(base, LTC_CW_CDS(value)))  argument
12796 #define LTC_BWR_CW_CDS(base, value) (LTC_WR_CW_CDS(base, value))  argument
12807 #define LTC_WR_CW_CICV(base, value) (LTC_WR_CW(base, LTC_CW_CICV(value)))  argument
12808 #define LTC_BWR_CW_CICV(base, value) (LTC_WR_CW_CICV(base, value))  argument
12819 #define LTC_WR_CW_CCR(base, value) (LTC_WR_CW(base, LTC_CW_CCR(value)))  argument
12820 #define LTC_BWR_CW_CCR(base, value) (LTC_WR_CW_CCR(base, value))  argument
12831 #define LTC_WR_CW_CKR(base, value) (LTC_WR_CW(base, LTC_CW_CKR(value)))  argument
12832 #define LTC_BWR_CW_CKR(base, value) (LTC_WR_CW_CKR(base, value))  argument
12843 #define LTC_WR_CW_COF(base, value) (LTC_WR_CW(base, LTC_CW_COF(value)))  argument
12844 #define LTC_BWR_CW_COF(base, value) (LTC_WR_CW_COF(base, value))  argument
12854 #define LTC_WR_CW_CIF(base, value) (LTC_WR_CW(base, LTC_CW_CIF(value)))  argument
12855 #define LTC_BWR_CW_CIF(base, value) (LTC_WR_CW_CIF(base, value))  argument
12874 #define LTC_RD_STA(base)         (LTC_STA_REG(base))  argument
12875 #define LTC_WR_STA(base, value)  (LTC_STA_REG(base) = (value))  argument
12876 #define LTC_RMW_STA(base, mask, value) (LTC_WR_STA(base, (LTC_RD_STA(base) & ~(mask)) | (value)))  argument
12877 #define LTC_SET_STA(base, value) (BME_OR32(&LTC_STA_REG(base), (uint32_t)(value)))  argument
12878 #define LTC_CLR_STA(base, value) (BME_AND32(&LTC_STA_REG(base), (uint32_t)(~(value))))  argument
12879 #define LTC_TOG_STA(base, value) (BME_XOR32(&LTC_STA_REG(base), (uint32_t)(value)))  argument
12900 #define LTC_RD_STA_AB(base)  ((LTC_STA_REG(base) & LTC_STA_AB_MASK) >> LTC_STA_AB_SHIFT)  argument
12901 #define LTC_BRD_STA_AB(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_AB_SHIFT, LTC_STA_AB_WIDTH))  argument
12912 #define LTC_RD_STA_DI(base)  ((LTC_STA_REG(base) & LTC_STA_DI_MASK) >> LTC_STA_DI_SHIFT)  argument
12913 #define LTC_BRD_STA_DI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_DI_SHIFT, LTC_STA_DI_WIDTH))  argument
12916 #define LTC_WR_STA_DI(base, value) (LTC_RMW_STA(base, LTC_STA_DI_MASK, LTC_STA_DI(value)))  argument
12917 #define LTC_BWR_STA_DI(base, value) (BME_BFI32(&LTC_STA_REG(base), ((uint32_t)(value) << LTC_STA_DI…  argument
12934 #define LTC_RD_STA_EI(base)  ((LTC_STA_REG(base) & LTC_STA_EI_MASK) >> LTC_STA_EI_SHIFT)  argument
12935 #define LTC_BRD_STA_EI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_EI_SHIFT, LTC_STA_EI_WIDTH))  argument
12954 #define LTC_RD_ESTA(base)        (LTC_ESTA_REG(base))  argument
12990 #define LTC_RD_ESTA_ERRID1(base) ((LTC_ESTA_REG(base) & LTC_ESTA_ERRID1_MASK) >> LTC_ESTA_ERRID1_SH…  argument
12991 #define LTC_BRD_ESTA_ERRID1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_ERRID1_SHIFT, LTC_ESTA_…  argument
13008 #define LTC_RD_ESTA_CL1(base) ((LTC_ESTA_REG(base) & LTC_ESTA_CL1_MASK) >> LTC_ESTA_CL1_SHIFT)  argument
13009 #define LTC_BRD_ESTA_CL1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_CL1_SHIFT, LTC_ESTA_CL1_WI…  argument
13036 #define LTC_RD_AADSZ(base)       (LTC_AADSZ_REG(base))  argument
13037 #define LTC_WR_AADSZ(base, value) (LTC_AADSZ_REG(base) = (value))  argument
13038 #define LTC_RMW_AADSZ(base, mask, value) (LTC_WR_AADSZ(base, (LTC_RD_AADSZ(base) & ~(mask)) | (valu…  argument
13039 #define LTC_SET_AADSZ(base, value) (BME_OR32(&LTC_AADSZ_REG(base), (uint32_t)(value)))  argument
13040 #define LTC_CLR_AADSZ(base, value) (BME_AND32(&LTC_AADSZ_REG(base), (uint32_t)(~(value))))  argument
13041 #define LTC_TOG_AADSZ(base, value) (BME_XOR32(&LTC_AADSZ_REG(base), (uint32_t)(value)))  argument
13055 #define LTC_RD_AADSZ_AADSZ(base) ((LTC_AADSZ_REG(base) & LTC_AADSZ_AADSZ_MASK) >> LTC_AADSZ_AADSZ_S…  argument
13056 #define LTC_BRD_AADSZ_AADSZ(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AADSZ_SHIFT, LTC_AADS…  argument
13059 #define LTC_WR_AADSZ_AADSZ(base, value) (LTC_RMW_AADSZ(base, LTC_AADSZ_AADSZ_MASK, LTC_AADSZ_AADSZ(…  argument
13060 #define LTC_BWR_AADSZ_AADSZ(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC…  argument
13070 #define LTC_RD_AADSZ_AL(base) ((LTC_AADSZ_REG(base) & LTC_AADSZ_AL_MASK) >> LTC_AADSZ_AL_SHIFT)  argument
13071 #define LTC_BRD_AADSZ_AL(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AL_SHIFT, LTC_AADSZ_AL_W…  argument
13074 #define LTC_WR_AADSZ_AL(base, value) (LTC_RMW_AADSZ(base, LTC_AADSZ_AL_MASK, LTC_AADSZ_AL(value)))  argument
13075 #define LTC_BWR_AADSZ_AL(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC_AA…  argument
13100 #define LTC_RD_CTX(base, index)  (LTC_CTX_REG(base, index))  argument
13101 #define LTC_WR_CTX(base, index, value) (LTC_CTX_REG(base, index) = (value))  argument
13102 #define LTC_RMW_CTX(base, index, mask, value) (LTC_WR_CTX(base, index, (LTC_RD_CTX(base, index) & ~…  argument
13103 #define LTC_SET_CTX(base, index, value) (BME_OR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))  argument
13104 #define LTC_CLR_CTX(base, index, value) (BME_AND32(&LTC_CTX_REG(base, index), (uint32_t)(~(value))))  argument
13105 #define LTC_TOG_CTX(base, index, value) (BME_XOR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))  argument
13129 #define LTC_RD_KEY(base, index)  (LTC_KEY_REG(base, index))  argument
13130 #define LTC_WR_KEY(base, index, value) (LTC_KEY_REG(base, index) = (value))  argument
13131 #define LTC_RMW_KEY(base, index, mask, value) (LTC_WR_KEY(base, index, (LTC_RD_KEY(base, index) & ~…  argument
13132 #define LTC_SET_KEY(base, index, value) (BME_OR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))  argument
13133 #define LTC_CLR_KEY(base, index, value) (BME_AND32(&LTC_KEY_REG(base, index), (uint32_t)(~(value))))  argument
13134 #define LTC_TOG_KEY(base, index, value) (BME_XOR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))  argument
13152 #define LTC_RD_FIFOSTA(base)     (LTC_FIFOSTA_REG(base))  argument
13167 #define LTC_RD_FIFOSTA_IFL(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_IFL_MASK) >> LTC_FIFOSTA_IFL…  argument
13168 #define LTC_BRD_FIFOSTA_IFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFL_SHIFT, LTC_FI…  argument
13178 #define LTC_RD_FIFOSTA_IFF(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_IFF_MASK) >> LTC_FIFOSTA_IFF…  argument
13179 #define LTC_BRD_FIFOSTA_IFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFF_SHIFT, LTC_FI…  argument
13190 #define LTC_RD_FIFOSTA_OFL(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_OFL_MASK) >> LTC_FIFOSTA_OFL…  argument
13191 #define LTC_BRD_FIFOSTA_OFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFL_SHIFT, LTC_FI…  argument
13201 #define LTC_RD_FIFOSTA_OFF(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_OFF_MASK) >> LTC_FIFOSTA_OFF…  argument
13202 #define LTC_BRD_FIFOSTA_OFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFF_SHIFT, LTC_FI…  argument
13224 #define LTC_WR_IFIFO(base, value) (LTC_IFIFO_REG(base) = (value))  argument
13245 #define LTC_RD_OFIFO(base)       (LTC_OFIFO_REG(base))  argument
13263 #define LTC_RD_VID1(base)        (LTC_VID1_REG(base))  argument
13277 #define LTC_RD_VID1_MIN_REV(base) ((LTC_VID1_REG(base) & LTC_VID1_MIN_REV_MASK) >> LTC_VID1_MIN_REV…  argument
13278 #define LTC_BRD_VID1_MIN_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MIN_REV_SHIFT, LTC_VID…  argument
13288 #define LTC_RD_VID1_MAJ_REV(base) ((LTC_VID1_REG(base) & LTC_VID1_MAJ_REV_MASK) >> LTC_VID1_MAJ_REV…  argument
13289 #define LTC_BRD_VID1_MAJ_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MAJ_REV_SHIFT, LTC_VID…  argument
13297 #define LTC_RD_VID1_IP_ID(base) ((LTC_VID1_REG(base) & LTC_VID1_IP_ID_MASK) >> LTC_VID1_IP_ID_SHIFT)  argument
13298 #define LTC_BRD_VID1_IP_ID(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_IP_ID_SHIFT, LTC_VID1_IP…  argument
13317 #define LTC_RD_CHAVID(base)      (LTC_CHAVID_REG(base))  argument
13331 #define LTC_RD_CHAVID_AESREV(base) ((LTC_CHAVID_REG(base) & LTC_CHAVID_AESREV_MASK) >> LTC_CHAVID_A…  argument
13332 #define LTC_BRD_CHAVID_AESREV(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESREV_SHIFT, LTC…  argument
13342 #define LTC_RD_CHAVID_AESVID(base) ((LTC_CHAVID_REG(base) & LTC_CHAVID_AESVID_MASK) >> LTC_CHAVID_A…  argument
13343 #define LTC_BRD_CHAVID_AESVID(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESVID_SHIFT, LTC…  argument
13382 #define MCG_RD_C1(base)          (MCG_C1_REG(base))  argument
13383 #define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))  argument
13384 #define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))  argument
13385 #define MCG_SET_C1(base, value)  (BME_OR8(&MCG_C1_REG(base), (uint8_t)(value)))  argument
13386 #define MCG_CLR_C1(base, value)  (BME_AND8(&MCG_C1_REG(base), (uint8_t)(~(value))))  argument
13387 #define MCG_TOG_C1(base, value)  (BME_XOR8(&MCG_C1_REG(base), (uint8_t)(value)))  argument
13407 #define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIF…  argument
13408 #define MCG_BRD_C1_IREFSTEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT, MCG_C1_IREFS…  argument
13411 #define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(val…  argument
13412 #define MCG_BWR_C1_IREFSTEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_I…  argument
13426 #define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)  argument
13427 #define MCG_BRD_C1_IRCLKEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT, MCG_C1_IRCLKEN…  argument
13430 #define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)…  argument
13431 #define MCG_BWR_C1_IRCLKEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IR…  argument
13448 #define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)  argument
13449 #define MCG_BRD_C1_IREFS(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT, MCG_C1_IREFS_WIDTH…  argument
13452 #define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))  argument
13453 #define MCG_BWR_C1_IREFS(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IREF…  argument
13485 #define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)  argument
13486 #define MCG_BRD_C1_FRDIV(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_FRDIV_SHIFT, MCG_C1_FRDIV_WIDTH…  argument
13489 #define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))  argument
13490 #define MCG_BWR_C1_FRDIV(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_FRDI…  argument
13508 #define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)  argument
13509 #define MCG_BRD_C1_CLKS(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_CLKS_SHIFT, MCG_C1_CLKS_WIDTH))  argument
13512 #define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))  argument
13513 #define MCG_BWR_C1_CLKS(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_CLKS_…  argument
13529 #define MCG_RD_C2(base)          (MCG_C2_REG(base))  argument
13530 #define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))  argument
13531 #define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))  argument
13532 #define MCG_SET_C2(base, value)  (BME_OR8(&MCG_C2_REG(base), (uint8_t)(value)))  argument
13533 #define MCG_CLR_C2(base, value)  (BME_AND8(&MCG_C2_REG(base), (uint8_t)(~(value))))  argument
13534 #define MCG_TOG_C2(base, value)  (BME_XOR8(&MCG_C2_REG(base), (uint8_t)(value)))  argument
13554 #define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)  argument
13555 #define MCG_BRD_C2_IRCS(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT, MCG_C2_IRCS_WIDTH))  argument
13558 #define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))  argument
13559 #define MCG_BWR_C2_IRCS(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_IRCS_…  argument
13576 #define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)  argument
13577 #define MCG_BRD_C2_LP(base)  (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT, MCG_C2_LP_WIDTH))  argument
13580 #define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))  argument
13581 #define MCG_BWR_C2_LP(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_LP_SHIF…  argument
13596 #define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)  argument
13597 #define MCG_BRD_C2_EREFS(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT, MCG_C2_EREFS_WIDTH…  argument
13600 #define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))  argument
13601 #define MCG_BWR_C2_EREFS(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_EREF…  argument
13616 #define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)  argument
13617 #define MCG_BRD_C2_HGO(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT, MCG_C2_HGO_WIDTH))  argument
13620 #define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))  argument
13621 #define MCG_BWR_C2_HGO(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_HGO_SH…  argument
13639 #define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)  argument
13640 #define MCG_BRD_C2_RANGE(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_RANGE_SHIFT, MCG_C2_RANGE_WIDTH…  argument
13643 #define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))  argument
13644 #define MCG_BWR_C2_RANGE(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_RANG…  argument
13658 #define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)  argument
13659 #define MCG_BRD_C2_FCFTRIM(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT, MCG_C2_FCFTRIM…  argument
13662 #define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)…  argument
13663 #define MCG_BWR_C2_FCFTRIM(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_FC…  argument
13680 #define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)  argument
13681 #define MCG_BRD_C2_LOCRE0(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT, MCG_C2_LOCRE0_WI…  argument
13684 #define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))  argument
13685 #define MCG_BWR_C2_LOCRE0(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_LOC…  argument
13701 #define MCG_RD_C3(base)          (MCG_C3_REG(base))  argument
13702 #define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))  argument
13703 #define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))  argument
13704 #define MCG_SET_C3(base, value)  (BME_OR8(&MCG_C3_REG(base), (uint8_t)(value)))  argument
13705 #define MCG_CLR_C3(base, value)  (BME_AND8(&MCG_C3_REG(base), (uint8_t)(~(value))))  argument
13706 #define MCG_TOG_C3(base, value)  (BME_XOR8(&MCG_C3_REG(base), (uint8_t)(value)))  argument
13724 #define MCG_RD_C4(base)          (MCG_C4_REG(base))  argument
13725 #define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))  argument
13726 #define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))  argument
13727 #define MCG_SET_C4(base, value)  (BME_OR8(&MCG_C4_REG(base), (uint8_t)(value)))  argument
13728 #define MCG_CLR_C4(base, value)  (BME_AND8(&MCG_C4_REG(base), (uint8_t)(~(value))))  argument
13729 #define MCG_TOG_C4(base, value)  (BME_XOR8(&MCG_C4_REG(base), (uint8_t)(value)))  argument
13750 #define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)  argument
13751 #define MCG_BRD_C4_SCFTRIM(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT, MCG_C4_SCFTRIM…  argument
13754 #define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)…  argument
13755 #define MCG_BWR_C4_SCFTRIM(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_SC…  argument
13774 #define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)  argument
13775 #define MCG_BRD_C4_FCTRIM(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_FCTRIM_SHIFT, MCG_C4_FCTRIM_WI…  argument
13778 #define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))  argument
13779 #define MCG_BWR_C4_FCTRIM(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_FCT…  argument
13799 #define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIF…  argument
13800 #define MCG_BRD_C4_DRST_DRS(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_DRST_DRS_SHIFT, MCG_C4_DRST_…  argument
13803 #define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(val…  argument
13804 #define MCG_BWR_C4_DRST_DRS(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_D…  argument
13825 #define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)  argument
13826 #define MCG_BRD_C4_DMX32(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT, MCG_C4_DMX32_WIDTH…  argument
13829 #define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))  argument
13830 #define MCG_BWR_C4_DMX32(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_DMX3…  argument
13846 #define MCG_RD_C5(base)          (MCG_C5_REG(base))  argument
13862 #define MCG_RD_C6(base)          (MCG_C6_REG(base))  argument
13863 #define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))  argument
13864 #define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))  argument
13865 #define MCG_SET_C6(base, value)  (BME_OR8(&MCG_C6_REG(base), (uint8_t)(value)))  argument
13866 #define MCG_CLR_C6(base, value)  (BME_AND8(&MCG_C6_REG(base), (uint8_t)(~(value))))  argument
13867 #define MCG_TOG_C6(base, value)  (BME_XOR8(&MCG_C6_REG(base), (uint8_t)(value)))  argument
13892 #define MCG_RD_C6_CME(base)  ((MCG_C6_REG(base) & MCG_C6_CME_MASK) >> MCG_C6_CME_SHIFT)  argument
13893 #define MCG_BRD_C6_CME(base) (BME_UBFX8(&MCG_C6_REG(base), MCG_C6_CME_SHIFT, MCG_C6_CME_WIDTH))  argument
13896 #define MCG_WR_C6_CME(base, value) (MCG_RMW_C6(base, MCG_C6_CME_MASK, MCG_C6_CME(value)))  argument
13897 #define MCG_BWR_C6_CME(base, value) (BME_BFI8(&MCG_C6_REG(base), ((uint8_t)(value) << MCG_C6_CME_SH…  argument
13913 #define MCG_RD_S(base)           (MCG_S_REG(base))  argument
13936 #define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)  argument
13937 #define MCG_BRD_S_IRCST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT, MCG_S_IRCST_WIDTH))  argument
13950 #define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)  argument
13951 #define MCG_BRD_S_OSCINIT0(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT, MCG_S_OSCINIT0_…  argument
13969 #define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)  argument
13970 #define MCG_BRD_S_CLKST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_CLKST_SHIFT, MCG_S_CLKST_WIDTH))  argument
13986 #define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)  argument
13987 #define MCG_BRD_S_IREFST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT, MCG_S_IREFST_WIDTH))  argument
14003 #define MCG_RD_SC(base)          (MCG_SC_REG(base))  argument
14004 #define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))  argument
14005 #define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))  argument
14006 #define MCG_SET_SC(base, value)  (BME_OR8(&MCG_SC_REG(base), (uint8_t)(value)))  argument
14007 #define MCG_CLR_SC(base, value)  (BME_AND8(&MCG_SC_REG(base), (uint8_t)(~(value))))  argument
14008 #define MCG_TOG_SC(base, value)  (BME_XOR8(&MCG_SC_REG(base), (uint8_t)(value)))  argument
14028 #define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)  argument
14029 #define MCG_BRD_SC_LOCS0(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT, MCG_SC_LOCS0_WIDTH…  argument
14032 #define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, (MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_…  argument
14033 #define MCG_BWR_SC_LOCS0(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_LOCS…  argument
14055 #define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)  argument
14056 #define MCG_BRD_SC_FCRDIV(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_FCRDIV_SHIFT, MCG_SC_FCRDIV_WI…  argument
14059 #define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK | M…  argument
14060 #define MCG_BWR_SC_FCRDIV(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_FCR…  argument
14080 #define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIF…  argument
14081 #define MCG_BRD_SC_FLTPRSRV(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT, MCG_SC_FLTPR…  argument
14084 #define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK…  argument
14085 #define MCG_BWR_SC_FLTPRSRV(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_F…  argument
14102 #define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)  argument
14103 #define MCG_BRD_SC_ATMF(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT, MCG_SC_ATMF_WIDTH))  argument
14106 #define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_S…  argument
14107 #define MCG_BWR_SC_ATMF(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATMF_…  argument
14121 #define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)  argument
14122 #define MCG_BRD_SC_ATMS(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT, MCG_SC_ATMS_WIDTH))  argument
14125 #define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK | MCG_S…  argument
14126 #define MCG_BWR_SC_ATMS(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATMS_…  argument
14144 #define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)  argument
14145 #define MCG_BRD_SC_ATME(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT, MCG_SC_ATME_WIDTH))  argument
14148 #define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK | MCG_S…  argument
14149 #define MCG_BWR_SC_ATME(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATME_…  argument
14165 #define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))  argument
14166 #define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))  argument
14167 #define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (valu…  argument
14168 #define MCG_SET_ATCVH(base, value) (BME_OR8(&MCG_ATCVH_REG(base), (uint8_t)(value)))  argument
14169 #define MCG_CLR_ATCVH(base, value) (BME_AND8(&MCG_ATCVH_REG(base), (uint8_t)(~(value))))  argument
14170 #define MCG_TOG_ATCVH(base, value) (BME_XOR8(&MCG_ATCVH_REG(base), (uint8_t)(value)))  argument
14186 #define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))  argument
14187 #define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))  argument
14188 #define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (valu…  argument
14189 #define MCG_SET_ATCVL(base, value) (BME_OR8(&MCG_ATCVL_REG(base), (uint8_t)(value)))  argument
14190 #define MCG_CLR_ATCVL(base, value) (BME_AND8(&MCG_ATCVL_REG(base), (uint8_t)(~(value))))  argument
14191 #define MCG_TOG_ATCVL(base, value) (BME_XOR8(&MCG_ATCVL_REG(base), (uint8_t)(value)))  argument
14207 #define MCG_RD_C7(base)          (MCG_C7_REG(base))  argument
14208 #define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))  argument
14209 #define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))  argument
14210 #define MCG_SET_C7(base, value)  (BME_OR8(&MCG_C7_REG(base), (uint8_t)(value)))  argument
14211 #define MCG_CLR_C7(base, value)  (BME_AND8(&MCG_C7_REG(base), (uint8_t)(~(value))))  argument
14212 #define MCG_TOG_C7(base, value)  (BME_XOR8(&MCG_C7_REG(base), (uint8_t)(value)))  argument
14230 #define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)  argument
14231 #define MCG_BRD_C7_OSCSEL(base) (BME_UBFX8(&MCG_C7_REG(base), MCG_C7_OSCSEL_SHIFT, MCG_C7_OSCSEL_WI…  argument
14234 #define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))  argument
14235 #define MCG_BWR_C7_OSCSEL(base, value) (BME_BFI8(&MCG_C7_REG(base), ((uint8_t)(value) << MCG_C7_OSC…  argument
14251 #define MCG_RD_C8(base)          (MCG_C8_REG(base))  argument
14252 #define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))  argument
14253 #define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))  argument
14254 #define MCG_SET_C8(base, value)  (BME_OR8(&MCG_C8_REG(base), (uint8_t)(value)))  argument
14255 #define MCG_CLR_C8(base, value)  (BME_AND8(&MCG_C8_REG(base), (uint8_t)(~(value))))  argument
14256 #define MCG_TOG_C8(base, value)  (BME_XOR8(&MCG_C8_REG(base), (uint8_t)(value)))  argument
14275 #define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)  argument
14276 #define MCG_BRD_C8_LOCS1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT, MCG_C8_LOCS1_WIDTH…  argument
14279 #define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))  argument
14280 #define MCG_BWR_C8_LOCS1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_LOCS…  argument
14301 #define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)  argument
14302 #define MCG_BRD_C8_CME1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT, MCG_C8_CME1_WIDTH))  argument
14305 #define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C…  argument
14306 #define MCG_BWR_C8_CME1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_CME1_…  argument
14322 #define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)  argument
14323 #define MCG_BRD_C8_LOCRE1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT, MCG_C8_LOCRE1_WI…  argument
14326 #define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), M…  argument
14327 #define MCG_BWR_C8_LOCRE1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_LOC…  argument
14361 #define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))  argument
14377 #define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)  argument
14378 #define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))  argument
14397 #define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))  argument
14413 #define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)  argument
14414 #define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))  argument
14449 #define MCM_RD_PLACR(base)       (MCM_PLACR_REG(base))  argument
14450 #define MCM_WR_PLACR(base, value) (MCM_PLACR_REG(base) = (value))  argument
14451 #define MCM_RMW_PLACR(base, mask, value) (MCM_WR_PLACR(base, (MCM_RD_PLACR(base) & ~(mask)) | (valu…  argument
14452 #define MCM_SET_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) |  (value)))  argument
14453 #define MCM_CLR_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) & ~(value)))  argument
14454 #define MCM_TOG_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) ^  (value)))  argument
14470 #define MCM_RD_PLACR_ARB(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ARB_MASK) >> MCM_PLACR_ARB_SHIFT)  argument
14471 #define MCM_BRD_PLACR_ARB(base) (MCM_RD_PLACR_ARB(base))  argument
14474 #define MCM_WR_PLACR_ARB(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ARB_MASK, MCM_PLACR_ARB(value)…  argument
14475 #define MCM_BWR_PLACR_ARB(base, value) (MCM_WR_PLACR_ARB(base, value))  argument
14486 #define MCM_WR_PLACR_CFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC(val…  argument
14487 #define MCM_BWR_PLACR_CFCC(base, value) (MCM_WR_PLACR_CFCC(base, value))  argument
14501 #define MCM_RD_PLACR_DFCDA(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCDA_MASK) >> MCM_PLACR_DFCDA_S…  argument
14502 #define MCM_BRD_PLACR_DFCDA(base) (MCM_RD_PLACR_DFCDA(base))  argument
14505 #define MCM_WR_PLACR_DFCDA(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCDA_MASK, MCM_PLACR_DFCDA(…  argument
14506 #define MCM_BWR_PLACR_DFCDA(base, value) (MCM_WR_PLACR_DFCDA(base, value))  argument
14520 #define MCM_RD_PLACR_DFCIC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCIC_MASK) >> MCM_PLACR_DFCIC_S…  argument
14521 #define MCM_BRD_PLACR_DFCIC(base) (MCM_RD_PLACR_DFCIC(base))  argument
14524 #define MCM_WR_PLACR_DFCIC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCIC_MASK, MCM_PLACR_DFCIC(…  argument
14525 #define MCM_BWR_PLACR_DFCIC(base, value) (MCM_WR_PLACR_DFCIC(base, value))  argument
14539 #define MCM_RD_PLACR_DFCC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCC_MASK) >> MCM_PLACR_DFCC_SHIF…  argument
14540 #define MCM_BRD_PLACR_DFCC(base) (MCM_RD_PLACR_DFCC(base))  argument
14543 #define MCM_WR_PLACR_DFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCC_MASK, MCM_PLACR_DFCC(val…  argument
14544 #define MCM_BWR_PLACR_DFCC(base, value) (MCM_WR_PLACR_DFCC(base, value))  argument
14558 #define MCM_RD_PLACR_EFDS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_EFDS_MASK) >> MCM_PLACR_EFDS_SHIF…  argument
14559 #define MCM_BRD_PLACR_EFDS(base) (MCM_RD_PLACR_EFDS(base))  argument
14562 #define MCM_WR_PLACR_EFDS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS(val…  argument
14563 #define MCM_BWR_PLACR_EFDS(base, value) (MCM_WR_PLACR_EFDS(base, value))  argument
14577 #define MCM_RD_PLACR_DFCS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCS_MASK) >> MCM_PLACR_DFCS_SHIF…  argument
14578 #define MCM_BRD_PLACR_DFCS(base) (MCM_RD_PLACR_DFCS(base))  argument
14581 #define MCM_WR_PLACR_DFCS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS(val…  argument
14582 #define MCM_BWR_PLACR_DFCS(base, value) (MCM_WR_PLACR_DFCS(base, value))  argument
14604 #define MCM_RD_PLACR_ESFC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ESFC_MASK) >> MCM_PLACR_ESFC_SHIF…  argument
14605 #define MCM_BRD_PLACR_ESFC(base) (MCM_RD_PLACR_ESFC(base))  argument
14608 #define MCM_WR_PLACR_ESFC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ESFC_MASK, MCM_PLACR_ESFC(val…  argument
14609 #define MCM_BWR_PLACR_ESFC(base, value) (MCM_WR_PLACR_ESFC(base, value))  argument
14627 #define MCM_RD_CPO(base)         (MCM_CPO_REG(base))  argument
14628 #define MCM_WR_CPO(base, value)  (MCM_CPO_REG(base) = (value))  argument
14629 #define MCM_RMW_CPO(base, mask, value) (MCM_WR_CPO(base, (MCM_RD_CPO(base) & ~(mask)) | (value)))  argument
14630 #define MCM_SET_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) |  (value)))  argument
14631 #define MCM_CLR_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) & ~(value)))  argument
14632 #define MCM_TOG_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) ^  (value)))  argument
14650 #define MCM_RD_CPO_CPOREQ(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOREQ_MASK) >> MCM_CPO_CPOREQ_SHIFT)  argument
14651 #define MCM_BRD_CPO_CPOREQ(base) (MCM_RD_CPO_CPOREQ(base))  argument
14654 #define MCM_WR_CPO_CPOREQ(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOREQ_MASK, MCM_CPO_CPOREQ(value…  argument
14655 #define MCM_BWR_CPO_CPOREQ(base, value) (MCM_WR_CPO_CPOREQ(base, value))  argument
14669 #define MCM_RD_CPO_CPOACK(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOACK_MASK) >> MCM_CPO_CPOACK_SHIFT)  argument
14670 #define MCM_BRD_CPO_CPOACK(base) (MCM_RD_CPO_CPOACK(base))  argument
14683 #define MCM_RD_CPO_CPOWOI(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOWOI_MASK) >> MCM_CPO_CPOWOI_SHIFT)  argument
14684 #define MCM_BRD_CPO_CPOWOI(base) (MCM_RD_CPO_CPOWOI(base))  argument
14687 #define MCM_WR_CPO_CPOWOI(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOWOI_MASK, MCM_CPO_CPOWOI(value…  argument
14688 #define MCM_BWR_CPO_CPOWOI(base, value) (MCM_WR_CPO_CPOWOI(base, value))  argument
14753 #define MTB_RD_POSITION(base)    (MTB_POSITION_REG(base))  argument
14754 #define MTB_WR_POSITION(base, value) (MTB_POSITION_REG(base) = (value))  argument
14755 #define MTB_RMW_POSITION(base, mask, value) (MTB_WR_POSITION(base, (MTB_RD_POSITION(base) & ~(mask)…  argument
14756 #define MTB_SET_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) |  (value)))  argument
14757 #define MTB_CLR_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) & ~(value)))  argument
14758 #define MTB_TOG_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) ^  (value)))  argument
14775 #define MTB_RD_POSITION_WRAP(base) ((MTB_POSITION_REG(base) & MTB_POSITION_WRAP_MASK) >> MTB_POSITI…  argument
14776 #define MTB_BRD_POSITION_WRAP(base) (MTB_RD_POSITION_WRAP(base))  argument
14779 #define MTB_WR_POSITION_WRAP(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_WRAP_MASK, MTB_POSIT…  argument
14780 #define MTB_BWR_POSITION_WRAP(base, value) (MTB_WR_POSITION_WRAP(base, value))  argument
14804 #define MTB_RD_POSITION_POINTER(base) ((MTB_POSITION_REG(base) & MTB_POSITION_POINTER_MASK) >> MTB_…  argument
14805 #define MTB_BRD_POSITION_POINTER(base) (MTB_RD_POSITION_POINTER(base))  argument
14808 #define MTB_WR_POSITION_POINTER(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_POINTER_MASK, MTB…  argument
14809 #define MTB_BWR_POSITION_POINTER(base, value) (MTB_WR_POSITION_POINTER(base, value))  argument
14835 #define MTB_RD_MASTER(base)      (MTB_MASTER_REG(base))  argument
14836 #define MTB_WR_MASTER(base, value) (MTB_MASTER_REG(base) = (value))  argument
14837 #define MTB_RMW_MASTER(base, mask, value) (MTB_WR_MASTER(base, (MTB_RD_MASTER(base) & ~(mask)) | (v…  argument
14838 #define MTB_SET_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) |  (value)))  argument
14839 #define MTB_CLR_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) & ~(value)))  argument
14840 #define MTB_TOG_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) ^  (value)))  argument
14864 #define MTB_RD_MASTER_MASK(base) ((MTB_MASTER_REG(base) & MTB_MASTER_MASK_MASK) >> MTB_MASTER_MASK_…  argument
14865 #define MTB_BRD_MASTER_MASK(base) (MTB_RD_MASTER_MASK(base))  argument
14868 #define MTB_WR_MASTER_MASK(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_MASK_MASK, MTB_MASTER_MASK…  argument
14869 #define MTB_BWR_MASTER_MASK(base, value) (MTB_WR_MASTER_MASK(base, value))  argument
14880 #define MTB_RD_MASTER_TSTARTEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTARTEN_MASK) >> MTB_MAST…  argument
14881 #define MTB_BRD_MASTER_TSTARTEN(base) (MTB_RD_MASTER_TSTARTEN(base))  argument
14884 #define MTB_WR_MASTER_TSTARTEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTARTEN_MASK, MTB_MAS…  argument
14885 #define MTB_BWR_MASTER_TSTARTEN(base, value) (MTB_WR_MASTER_TSTARTEN(base, value))  argument
14897 #define MTB_RD_MASTER_TSTOPEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTOPEN_MASK) >> MTB_MASTER…  argument
14898 #define MTB_BRD_MASTER_TSTOPEN(base) (MTB_RD_MASTER_TSTOPEN(base))  argument
14901 #define MTB_WR_MASTER_TSTOPEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTOPEN_MASK, MTB_MASTE…  argument
14902 #define MTB_BWR_MASTER_TSTOPEN(base, value) (MTB_WR_MASTER_TSTOPEN(base, value))  argument
14917 #define MTB_RD_MASTER_SFRWPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_SFRWPRIV_MASK) >> MTB_MAST…  argument
14918 #define MTB_BRD_MASTER_SFRWPRIV(base) (MTB_RD_MASTER_SFRWPRIV(base))  argument
14921 #define MTB_WR_MASTER_SFRWPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_SFRWPRIV_MASK, MTB_MAS…  argument
14922 #define MTB_BWR_MASTER_SFRWPRIV(base, value) (MTB_WR_MASTER_SFRWPRIV(base, value))  argument
14935 #define MTB_RD_MASTER_RAMPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_RAMPRIV_MASK) >> MTB_MASTER…  argument
14936 #define MTB_BRD_MASTER_RAMPRIV(base) (MTB_RD_MASTER_RAMPRIV(base))  argument
14939 #define MTB_WR_MASTER_RAMPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_RAMPRIV_MASK, MTB_MASTE…  argument
14940 #define MTB_BWR_MASTER_RAMPRIV(base, value) (MTB_WR_MASTER_RAMPRIV(base, value))  argument
14953 #define MTB_RD_MASTER_HALTREQ(base) ((MTB_MASTER_REG(base) & MTB_MASTER_HALTREQ_MASK) >> MTB_MASTER…  argument
14954 #define MTB_BRD_MASTER_HALTREQ(base) (MTB_RD_MASTER_HALTREQ(base))  argument
14957 #define MTB_WR_MASTER_HALTREQ(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_HALTREQ_MASK, MTB_MASTE…  argument
14958 #define MTB_BWR_MASTER_HALTREQ(base, value) (MTB_WR_MASTER_HALTREQ(base, value))  argument
14977 #define MTB_RD_MASTER_EN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_EN_MASK) >> MTB_MASTER_EN_SHIFT)  argument
14978 #define MTB_BRD_MASTER_EN(base) (MTB_RD_MASTER_EN(base))  argument
14981 #define MTB_WR_MASTER_EN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_EN_MASK, MTB_MASTER_EN(value…  argument
14982 #define MTB_BWR_MASTER_EN(base, value) (MTB_WR_MASTER_EN(base, value))  argument
15010 #define MTB_RD_FLOW(base)        (MTB_FLOW_REG(base))  argument
15011 #define MTB_WR_FLOW(base, value) (MTB_FLOW_REG(base) = (value))  argument
15012 #define MTB_RMW_FLOW(base, mask, value) (MTB_WR_FLOW(base, (MTB_RD_FLOW(base) & ~(mask)) | (value)))  argument
15013 #define MTB_SET_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) |  (value)))  argument
15014 #define MTB_CLR_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) & ~(value)))  argument
15015 #define MTB_TOG_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) ^  (value)))  argument
15030 #define MTB_RD_FLOW_AUTOSTOP(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOSTOP_MASK) >> MTB_FLOW_AUTOS…  argument
15031 #define MTB_BRD_FLOW_AUTOSTOP(base) (MTB_RD_FLOW_AUTOSTOP(base))  argument
15034 #define MTB_WR_FLOW_AUTOSTOP(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOSTOP_MASK, MTB_FLOW_AUTO…  argument
15035 #define MTB_BWR_FLOW_AUTOSTOP(base, value) (MTB_WR_FLOW_AUTOSTOP(base, value))  argument
15048 #define MTB_RD_FLOW_AUTOHALT(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOHALT_MASK) >> MTB_FLOW_AUTOH…  argument
15049 #define MTB_BRD_FLOW_AUTOHALT(base) (MTB_RD_FLOW_AUTOHALT(base))  argument
15052 #define MTB_WR_FLOW_AUTOHALT(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOHALT_MASK, MTB_FLOW_AUTO…  argument
15053 #define MTB_BWR_FLOW_AUTOHALT(base, value) (MTB_WR_FLOW_AUTOHALT(base, value))  argument
15065 #define MTB_RD_FLOW_WATERMARK(base) ((MTB_FLOW_REG(base) & MTB_FLOW_WATERMARK_MASK) >> MTB_FLOW_WAT…  argument
15066 #define MTB_BRD_FLOW_WATERMARK(base) (MTB_RD_FLOW_WATERMARK(base))  argument
15069 #define MTB_WR_FLOW_WATERMARK(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_WATERMARK_MASK, MTB_FLOW_WA…  argument
15070 #define MTB_BWR_FLOW_WATERMARK(base, value) (MTB_WR_FLOW_WATERMARK(base, value))  argument
15092 #define MTB_RD_BASE(base)        (MTB_BASE_REG(base))  argument
15112 #define MTB_RD_MODECTRL(base)    (MTB_MODECTRL_REG(base))  argument
15132 #define MTB_RD_TAGSET(base)      (MTB_TAGSET_REG(base))  argument
15153 #define MTB_RD_TAGCLEAR(base)    (MTB_TAGCLEAR_REG(base))  argument
15173 #define MTB_RD_LOCKACCESS(base)  (MTB_LOCKACCESS_REG(base))  argument
15194 #define MTB_RD_LOCKSTAT(base)    (MTB_LOCKSTAT_REG(base))  argument
15219 #define MTB_RD_AUTHSTAT(base)    (MTB_AUTHSTAT_REG(base))  argument
15233 #define MTB_RD_AUTHSTAT_BIT0(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT0_MASK) >> MTB_AUTHST…  argument
15234 #define MTB_BRD_AUTHSTAT_BIT0(base) (MTB_RD_AUTHSTAT_BIT0(base))  argument
15244 #define MTB_RD_AUTHSTAT_BIT1(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT1_MASK) >> MTB_AUTHST…  argument
15245 #define MTB_BRD_AUTHSTAT_BIT1(base) (MTB_RD_AUTHSTAT_BIT1(base))  argument
15255 #define MTB_RD_AUTHSTAT_BIT2(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT2_MASK) >> MTB_AUTHST…  argument
15256 #define MTB_BRD_AUTHSTAT_BIT2(base) (MTB_RD_AUTHSTAT_BIT2(base))  argument
15266 #define MTB_RD_AUTHSTAT_BIT3(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT3_MASK) >> MTB_AUTHST…  argument
15267 #define MTB_BRD_AUTHSTAT_BIT3(base) (MTB_RD_AUTHSTAT_BIT3(base))  argument
15286 #define MTB_RD_DEVICEARCH(base)  (MTB_DEVICEARCH_REG(base))  argument
15305 #define MTB_RD_DEVICECFG(base)   (MTB_DEVICECFG_REG(base))  argument
15324 #define MTB_RD_DEVICETYPID(base) (MTB_DEVICETYPID_REG(base))  argument
15343 #define MTB_RD_PERIPHID(base, index) (MTB_PERIPHID_REG(base, index))  argument
15362 #define MTB_RD_COMPID(base, index) (MTB_COMPID_REG(base, index))  argument
15401 #define MTBDWT_RD_CTRL(base)     (MTBDWT_CTRL_REG(base))  argument
15431 #define MTBDWT_RD_CTRL_DWTCFGCTRL(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_DWTCFGCTRL_MASK) >> M…  argument
15432 #define MTBDWT_BRD_CTRL_DWTCFGCTRL(base) (MTBDWT_RD_CTRL_DWTCFGCTRL(base))  argument
15442 #define MTBDWT_RD_CTRL_NUMCMP(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_NUMCMP_MASK) >> MTBDWT_CT…  argument
15443 #define MTBDWT_BRD_CTRL_NUMCMP(base) (MTBDWT_RD_CTRL_NUMCMP(base))  argument
15461 #define MTBDWT_RD_COMP(base, index) (MTBDWT_COMP_REG(base, index))  argument
15462 #define MTBDWT_WR_COMP(base, index, value) (MTBDWT_COMP_REG(base, index) = (value))  argument
15463 #define MTBDWT_RMW_COMP(base, index, mask, value) (MTBDWT_WR_COMP(base, index, (MTBDWT_RD_COMP(base…  argument
15464 #define MTBDWT_SET_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15465 #define MTBDWT_CLR_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15466 #define MTBDWT_TOG_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index…  argument
15486 #define MTBDWT_RD_MASK(base, index) (MTBDWT_MASK_REG(base, index))  argument
15487 #define MTBDWT_WR_MASK(base, index, value) (MTBDWT_MASK_REG(base, index) = (value))  argument
15488 #define MTBDWT_RMW_MASK(base, index, mask, value) (MTBDWT_WR_MASK(base, index, (MTBDWT_RD_MASK(base…  argument
15489 #define MTBDWT_SET_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15490 #define MTBDWT_CLR_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15491 #define MTBDWT_TOG_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index…  argument
15515 #define MTBDWT_RD_MASK_MASK(base, index) ((MTBDWT_MASK_REG(base, index) & MTBDWT_MASK_MASK_MASK) >>…  argument
15516 #define MTBDWT_BRD_MASK_MASK(base, index) (MTBDWT_RD_MASK_MASK(base, index))  argument
15519 #define MTBDWT_WR_MASK_MASK(base, index, value) (MTBDWT_RMW_MASK(base, index, MTBDWT_MASK_MASK_MASK…  argument
15520 #define MTBDWT_BWR_MASK_MASK(base, index, value) (MTBDWT_WR_MASK_MASK(base, index, value))  argument
15538 #define MTBDWT_RD_FCT(base, index) (MTBDWT_FCT_REG(base, index))  argument
15539 #define MTBDWT_WR_FCT(base, index, value) (MTBDWT_FCT_REG(base, index) = (value))  argument
15540 #define MTBDWT_RMW_FCT(base, index, mask, value) (MTBDWT_WR_FCT(base, index, (MTBDWT_RD_FCT(base, i…  argument
15541 #define MTBDWT_SET_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) |…  argument
15542 #define MTBDWT_CLR_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) &…  argument
15543 #define MTBDWT_TOG_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) ^…  argument
15567 #define MTBDWT_RD_FCT_FUNCTION(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_FUNCTION_MAS…  argument
15568 #define MTBDWT_BRD_FCT_FUNCTION(base, index) (MTBDWT_RD_FCT_FUNCTION(base, index))  argument
15571 #define MTBDWT_WR_FCT_FUNCTION(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_FUNCTION…  argument
15572 #define MTBDWT_BWR_FCT_FUNCTION(base, index, value) (MTBDWT_WR_FCT_FUNCTION(base, index, value))  argument
15588 #define MTBDWT_RD_FCT_DATAVMATCH(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVMATCH…  argument
15589 #define MTBDWT_BRD_FCT_DATAVMATCH(base, index) (MTBDWT_RD_FCT_DATAVMATCH(base, index))  argument
15592 #define MTBDWT_WR_FCT_DATAVMATCH(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVM…  argument
15593 #define MTBDWT_BWR_FCT_DATAVMATCH(base, index, value) (MTBDWT_WR_FCT_DATAVMATCH(base, index, value))  argument
15611 #define MTBDWT_RD_FCT_DATAVSIZE(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVSIZE_M…  argument
15612 #define MTBDWT_BRD_FCT_DATAVSIZE(base, index) (MTBDWT_RD_FCT_DATAVSIZE(base, index))  argument
15615 #define MTBDWT_WR_FCT_DATAVSIZE(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVSI…  argument
15616 #define MTBDWT_BWR_FCT_DATAVSIZE(base, index, value) (MTBDWT_WR_FCT_DATAVSIZE(base, index, value))  argument
15630 #define MTBDWT_RD_FCT_DATAVADDR0(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVADDR0…  argument
15631 #define MTBDWT_BRD_FCT_DATAVADDR0(base, index) (MTBDWT_RD_FCT_DATAVADDR0(base, index))  argument
15634 #define MTBDWT_WR_FCT_DATAVADDR0(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVA…  argument
15635 #define MTBDWT_BWR_FCT_DATAVADDR0(base, index, value) (MTBDWT_WR_FCT_DATAVADDR0(base, index, value))  argument
15651 #define MTBDWT_RD_FCT_MATCHED(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_MATCHED_MASK)…  argument
15652 #define MTBDWT_BRD_FCT_MATCHED(base, index) (MTBDWT_RD_FCT_MATCHED(base, index))  argument
15676 #define MTBDWT_RD_TBCTRL(base)   (MTBDWT_TBCTRL_REG(base))  argument
15677 #define MTBDWT_WR_TBCTRL(base, value) (MTBDWT_TBCTRL_REG(base) = (value))  argument
15678 #define MTBDWT_RMW_TBCTRL(base, mask, value) (MTBDWT_WR_TBCTRL(base, (MTBDWT_RD_TBCTRL(base) & ~(ma…  argument
15679 #define MTBDWT_SET_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) |  (value)))  argument
15680 #define MTBDWT_CLR_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) & ~(value)))  argument
15681 #define MTBDWT_TOG_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) ^  (value)))  argument
15705 #define MTBDWT_RD_TBCTRL_ACOMP0(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP0_MASK) >> MTB…  argument
15706 #define MTBDWT_BRD_TBCTRL_ACOMP0(base) (MTBDWT_RD_TBCTRL_ACOMP0(base))  argument
15709 #define MTBDWT_WR_TBCTRL_ACOMP0(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP0_MASK, MT…  argument
15710 #define MTBDWT_BWR_TBCTRL_ACOMP0(base, value) (MTBDWT_WR_TBCTRL_ACOMP0(base, value))  argument
15725 #define MTBDWT_RD_TBCTRL_ACOMP1(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP1_MASK) >> MTB…  argument
15726 #define MTBDWT_BRD_TBCTRL_ACOMP1(base) (MTBDWT_RD_TBCTRL_ACOMP1(base))  argument
15729 #define MTBDWT_WR_TBCTRL_ACOMP1(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP1_MASK, MT…  argument
15730 #define MTBDWT_BWR_TBCTRL_ACOMP1(base, value) (MTBDWT_WR_TBCTRL_ACOMP1(base, value))  argument
15741 #define MTBDWT_RD_TBCTRL_NUMCOMP(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_NUMCOMP_MASK) >> M…  argument
15742 #define MTBDWT_BRD_TBCTRL_NUMCOMP(base) (MTBDWT_RD_TBCTRL_NUMCOMP(base))  argument
15761 #define MTBDWT_RD_DEVICECFG(base) (MTBDWT_DEVICECFG_REG(base))  argument
15780 #define MTBDWT_RD_DEVICETYPID(base) (MTBDWT_DEVICETYPID_REG(base))  argument
15799 #define MTBDWT_RD_PERIPHID(base, index) (MTBDWT_PERIPHID_REG(base, index))  argument
15818 #define MTBDWT_RD_COMPID(base, index) (MTBDWT_COMPID_REG(base, index))  argument
15859 #define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))  argument
15875 #define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))  argument
15891 #define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))  argument
15907 #define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))  argument
15923 #define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))  argument
15939 #define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))  argument
15955 #define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))  argument
15971 #define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))  argument
15987 #define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))  argument
16003 #define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))  argument
16019 #define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))  argument
16035 #define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))  argument
16053 #define NV_RD_FSEC(base)         (NV_FSEC_REG(base))  argument
16069 #define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)  argument
16070 #define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))  argument
16082 #define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)  argument
16083 #define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))  argument
16095 #define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)  argument
16096 #define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))  argument
16108 #define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)  argument
16109 #define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))  argument
16125 #define NV_RD_FOPT(base)         (NV_FOPT_REG(base))  argument
16143 #define NV_RD_FOPT_LPBOOT0(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT0_MASK) >> NV_FOPT_LPBOOT0_SHI…  argument
16144 #define NV_BRD_FOPT_LPBOOT0(base) (NV_RD_FOPT_LPBOOT0(base))  argument
16156 #define NV_RD_FOPT_NMI_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_NMI_DIS_MASK) >> NV_FOPT_NMI_DIS_SHI…  argument
16157 #define NV_BRD_FOPT_NMI_DIS(base) (NV_RD_FOPT_NMI_DIS(base))  argument
16170 #define NV_RD_FOPT_RESET_PIN_CFG(base) ((NV_FOPT_REG(base) & NV_FOPT_RESET_PIN_CFG_MASK) >> NV_FOPT…  argument
16171 #define NV_BRD_FOPT_RESET_PIN_CFG(base) (NV_RD_FOPT_RESET_PIN_CFG(base))  argument
16185 #define NV_RD_FOPT_LPBOOT1(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT1_MASK) >> NV_FOPT_LPBOOT1_SHI…  argument
16186 #define NV_BRD_FOPT_LPBOOT1(base) (NV_RD_FOPT_LPBOOT1(base))  argument
16198 #define NV_RD_FOPT_FAST_INIT(base) ((NV_FOPT_REG(base) & NV_FOPT_FAST_INIT_MASK) >> NV_FOPT_FAST_IN…  argument
16199 #define NV_BRD_FOPT_FAST_INIT(base) (NV_RD_FOPT_FAST_INIT(base))  argument
16237 #define PIT_RD_MCR(base)         (PIT_MCR_REG(base))  argument
16238 #define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))  argument
16239 #define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))  argument
16240 #define PIT_SET_MCR(base, value) (BME_OR32(&PIT_MCR_REG(base), (uint32_t)(value)))  argument
16241 #define PIT_CLR_MCR(base, value) (BME_AND32(&PIT_MCR_REG(base), (uint32_t)(~(value))))  argument
16242 #define PIT_TOG_MCR(base, value) (BME_XOR32(&PIT_MCR_REG(base), (uint32_t)(value)))  argument
16260 #define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)  argument
16261 #define PIT_BRD_MCR_FRZ(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))  argument
16264 #define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))  argument
16265 #define PIT_BWR_MCR_FRZ(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_F…  argument
16280 #define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)  argument
16281 #define PIT_BRD_MCR_MDIS(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WID…  argument
16284 #define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))  argument
16285 #define PIT_BWR_MCR_MDIS(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_…  argument
16304 #define PIT_RD_LTMR64H(base)     (PIT_LTMR64H_REG(base))  argument
16328 #define PIT_RD_LTMR64L(base)     (PIT_LTMR64L_REG(base))  argument
16347 #define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))  argument
16348 #define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))  argument
16349 #define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, inde…  argument
16350 #define PIT_SET_LDVAL(base, index, value) (BME_OR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))  argument
16351 #define PIT_CLR_LDVAL(base, index, value) (BME_AND32(&PIT_LDVAL_REG(base, index), (uint32_t)(~(valu…  argument
16352 #define PIT_TOG_LDVAL(base, index, value) (BME_XOR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)…  argument
16370 #define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))  argument
16389 #define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))  argument
16390 #define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))  argument
16391 #define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, inde…  argument
16392 #define PIT_SET_TCTRL(base, index, value) (BME_OR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))  argument
16393 #define PIT_CLR_TCTRL(base, index, value) (BME_AND32(&PIT_TCTRL_REG(base, index), (uint32_t)(~(valu…  argument
16394 #define PIT_TOG_TCTRL(base, index, value) (BME_XOR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)…  argument
16412 #define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCT…  argument
16413 #define PIT_BRD_TCTRL_TEN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT…  argument
16416 #define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TC…  argument
16417 #define PIT_BWR_TCTRL_TEN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16433 #define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCT…  argument
16434 #define PIT_BRD_TCTRL_TIE(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT…  argument
16437 #define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TC…  argument
16438 #define PIT_BWR_TCTRL_TIE(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16454 #define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCT…  argument
16455 #define PIT_BRD_TCTRL_CHN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT…  argument
16458 #define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TC…  argument
16459 #define PIT_BWR_TCTRL_CHN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(v…  argument
16477 #define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))  argument
16478 #define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))  argument
16479 #define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) …  argument
16480 #define PIT_SET_TFLG(base, index, value) (BME_OR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))  argument
16481 #define PIT_CLR_TFLG(base, index, value) (BME_AND32(&PIT_TFLG_REG(base, index), (uint32_t)(~(value)…  argument
16482 #define PIT_TOG_TFLG(base, index, value) (BME_XOR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))  argument
16502 #define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_T…  argument
16503 #define PIT_BRD_TFLG_TIF(base, index) (BME_UBFX32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT, P…  argument
16506 #define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_…  argument
16507 #define PIT_BWR_TFLG_TIF(base, index, value) (BME_BFI32(&PIT_TFLG_REG(base, index), ((uint32_t)(val…  argument
16549 #define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))  argument
16550 #define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))  argument
16551 #define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (v…  argument
16552 #define PMC_SET_LVDSC1(base, value) (BME_OR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))  argument
16553 #define PMC_CLR_LVDSC1(base, value) (BME_AND8(&PMC_LVDSC1_REG(base), (uint8_t)(~(value))))  argument
16554 #define PMC_TOG_LVDSC1(base, value) (BME_XOR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))  argument
16575 #define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_…  argument
16576 #define PMC_BRD_LVDSC1_LVDV(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDV_SHIFT, PMC_LVDS…  argument
16579 #define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV…  argument
16580 #define PMC_BWR_LVDSC1_LVDV(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_…  argument
16595 #define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVD…  argument
16596 #define PMC_BRD_LVDSC1_LVDRE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT, PMC_LV…  argument
16599 #define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LV…  argument
16600 #define PMC_BWR_LVDSC1_LVDRE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC…  argument
16614 #define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVD…  argument
16615 #define PMC_BRD_LVDSC1_LVDIE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT, PMC_LV…  argument
16618 #define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LV…  argument
16619 #define PMC_BWR_LVDSC1_LVDIE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC…  argument
16630 #define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_…  argument
16631 #define PMC_BWR_LVDSC1_LVDACK(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PM…  argument
16645 #define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_…  argument
16646 #define PMC_BRD_LVDSC1_LVDF(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT, PMC_LVDS…  argument
16670 #define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))  argument
16671 #define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))  argument
16672 #define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (v…  argument
16673 #define PMC_SET_LVDSC2(base, value) (BME_OR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))  argument
16674 #define PMC_CLR_LVDSC2(base, value) (BME_AND8(&PMC_LVDSC2_REG(base), (uint8_t)(~(value))))  argument
16675 #define PMC_TOG_LVDSC2(base, value) (BME_XOR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))  argument
16696 #define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_…  argument
16697 #define PMC_BRD_LVDSC2_LVWV(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWV_SHIFT, PMC_LVDS…  argument
16700 #define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV…  argument
16701 #define PMC_BWR_LVDSC2_LVWV(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_…  argument
16715 #define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVW…  argument
16716 #define PMC_BRD_LVDSC2_LVWIE(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT, PMC_LV…  argument
16719 #define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LV…  argument
16720 #define PMC_BWR_LVDSC2_LVWIE(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC…  argument
16731 #define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_…  argument
16732 #define PMC_BWR_LVDSC2_LVWACK(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PM…  argument
16750 #define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_…  argument
16751 #define PMC_BRD_LVDSC2_LVWF(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT, PMC_LVDS…  argument
16774 #define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))  argument
16775 #define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))  argument
16776 #define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (valu…  argument
16777 #define PMC_SET_REGSC(base, value) (BME_OR8(&PMC_REGSC_REG(base), (uint8_t)(value)))  argument
16778 #define PMC_CLR_REGSC(base, value) (BME_AND8(&PMC_REGSC_REG(base), (uint8_t)(~(value))))  argument
16779 #define PMC_TOG_REGSC(base, value) (BME_XOR8(&PMC_REGSC_REG(base), (uint8_t)(value)))  argument
16797 #define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIF…  argument
16798 #define PMC_BRD_REGSC_BGBE(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT, PMC_REGSC_B…  argument
16801 #define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO…  argument
16802 #define PMC_BWR_REGSC_BGBE(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_RE…  argument
16817 #define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGON…  argument
16818 #define PMC_BRD_REGSC_REGONS(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT, PMC_REG…  argument
16838 #define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKIS…  argument
16839 #define PMC_BRD_REGSC_ACKISO(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT, PMC_REG…  argument
16842 #define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKI…  argument
16843 #define PMC_BWR_REGSC_ACKISO(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_…  argument
16862 #define PMC_RD_REGSC_VLPO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_VLPO_MASK) >> PMC_REGSC_VLPO_SHIF…  argument
16863 #define PMC_BRD_REGSC_VLPO(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_VLPO_SHIFT, PMC_REGSC_V…  argument
16866 #define PMC_WR_REGSC_VLPO(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_VLPO_MASK | PMC_REGSC_ACKISO…  argument
16867 #define PMC_BWR_REGSC_VLPO(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_RE…  argument
16906 #define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))  argument
16907 #define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))  argument
16908 #define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) …  argument
16909 #define PORT_SET_PCR(base, index, value) (BME_OR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))  argument
16910 #define PORT_CLR_PCR(base, index, value) (BME_AND32(&PORT_PCR_REG(base, index), (uint32_t)(~(value)…  argument
16911 #define PORT_TOG_PCR(base, index, value) (BME_XOR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))  argument
16932 #define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_…  argument
16933 #define PORT_BRD_PCR_PS(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT, POR…  argument
16936 #define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_…  argument
16937 #define PORT_BWR_PCR_PS(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…  argument
16956 #define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_…  argument
16957 #define PORT_BRD_PCR_PE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT, POR…  argument
16960 #define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_…  argument
16961 #define PORT_BWR_PCR_PE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(valu…  argument
16978 #define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_S…  argument
16979 #define PORT_BRD_PCR_SRE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT, P…  argument
16982 #define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PC…  argument
16983 #define PORT_BWR_PCR_SRE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17001 #define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_P…  argument
17002 #define PORT_BRD_PCR_PFE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT, P…  argument
17005 #define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PC…  argument
17006 #define PORT_BWR_PCR_PFE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17023 #define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_D…  argument
17024 #define PORT_BRD_PCR_DSE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT, P…  argument
17027 #define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PC…  argument
17028 #define PORT_BWR_PCR_DSE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17051 #define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_M…  argument
17052 #define PORT_BRD_PCR_MUX(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_MUX_SHIFT, P…  argument
17055 #define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PC…  argument
17056 #define PORT_BWR_PCR_MUX(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17086 #define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR…  argument
17087 #define PORT_BRD_PCR_IRQC(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_IRQC_SHIFT,…  argument
17090 #define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_…  argument
17091 #define PORT_BWR_PCR_IRQC(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(va…  argument
17111 #define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_I…  argument
17112 #define PORT_BRD_PCR_ISF(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT, P…  argument
17115 #define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_…  argument
17116 #define PORT_BWR_PCR_ISF(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(val…  argument
17134 #define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))  argument
17135 #define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))  argument
17136 #define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (v…  argument
17151 #define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD…  argument
17152 #define PORT_BWR_GPCLR_GPWD(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PO…  argument
17169 #define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE…  argument
17170 #define PORT_BWR_GPCLR_GPWE(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PO…  argument
17188 #define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))  argument
17189 #define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))  argument
17190 #define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (v…  argument
17205 #define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD…  argument
17206 #define PORT_BWR_GPCHR_GPWD(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PO…  argument
17223 #define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE…  argument
17224 #define PORT_BWR_GPCHR_GPWE(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PO…  argument
17245 #define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))  argument
17246 #define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))  argument
17247 #define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (valu…  argument
17248 #define PORT_SET_ISFR(base, value) (BME_OR32(&PORT_ISFR_REG(base), (uint32_t)(value)))  argument
17249 #define PORT_CLR_ISFR(base, value) (BME_AND32(&PORT_ISFR_REG(base), (uint32_t)(~(value))))  argument
17250 #define PORT_TOG_ISFR(base, value) (BME_XOR32(&PORT_ISFR_REG(base), (uint32_t)(value)))  argument
17288 #define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))  argument
17309 #define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SH…  argument
17310 #define RCM_BRD_SRS0_WAKEUP(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT, RCM_SRS0_W…  argument
17325 #define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)  argument
17326 #define RCM_BRD_SRS0_LVD(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT, RCM_SRS0_LVD_WID…  argument
17342 #define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)  argument
17343 #define RCM_BRD_SRS0_LOC(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT, RCM_SRS0_LOC_WID…  argument
17358 #define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)  argument
17359 #define RCM_BRD_SRS0_WDOG(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT, RCM_SRS0_WDOG_…  argument
17374 #define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)  argument
17375 #define RCM_BRD_SRS0_PIN(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT, RCM_SRS0_PIN_WID…  argument
17392 #define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)  argument
17393 #define RCM_BRD_SRS0_POR(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT, RCM_SRS0_POR_WID…  argument
17415 #define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))  argument
17434 #define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SH…  argument
17435 #define RCM_BRD_SRS1_LOCKUP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT, RCM_SRS1_L…  argument
17450 #define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)  argument
17451 #define RCM_BRD_SRS1_SW(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT, RCM_SRS1_SW_WIDTH))  argument
17468 #define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SH…  argument
17469 #define RCM_BRD_SRS1_MDM_AP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT, RCM_SRS1_M…  argument
17487 #define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR…  argument
17488 #define RCM_BRD_SRS1_SACKERR(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT, RCM_SRS1…  argument
17508 #define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))  argument
17509 #define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))  argument
17510 #define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))  argument
17511 #define RCM_SET_RPFC(base, value) (BME_OR8(&RCM_RPFC_REG(base), (uint8_t)(value)))  argument
17512 #define RCM_CLR_RPFC(base, value) (BME_AND8(&RCM_RPFC_REG(base), (uint8_t)(~(value))))  argument
17513 #define RCM_TOG_RPFC(base, value) (BME_XOR8(&RCM_RPFC_REG(base), (uint8_t)(value)))  argument
17533 #define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RST…  argument
17534 #define RCM_BRD_RPFC_RSTFLTSRW(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSRW_SHIFT, RCM_…  argument
17537 #define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RS…  argument
17538 #define RCM_BWR_RPFC_RSTFLTSRW(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM…  argument
17554 #define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFL…  argument
17555 #define RCM_BRD_RPFC_RSTFLTSS(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT, RCM_RP…  argument
17558 #define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTF…  argument
17559 #define RCM_BWR_RPFC_RSTFLTSS(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM_…  argument
17578 #define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))  argument
17579 #define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))  argument
17580 #define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))  argument
17581 #define RCM_SET_RPFW(base, value) (BME_OR8(&RCM_RPFW_REG(base), (uint8_t)(value)))  argument
17582 #define RCM_CLR_RPFW(base, value) (BME_AND8(&RCM_RPFW_REG(base), (uint8_t)(~(value))))  argument
17583 #define RCM_TOG_RPFW(base, value) (BME_XOR8(&RCM_RPFW_REG(base), (uint8_t)(value)))  argument
17631 #define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RST…  argument
17632 #define RCM_BRD_RPFW_RSTFLTSEL(base) (BME_UBFX8(&RCM_RPFW_REG(base), RCM_RPFW_RSTFLTSEL_SHIFT, RCM_…  argument
17635 #define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RS…  argument
17636 #define RCM_BWR_RPFW_RSTFLTSEL(base, value) (BME_BFI8(&RCM_RPFW_REG(base), ((uint8_t)(value) << RCM…  argument
17680 #define ROM_RD_ENTRY(base, index) (ROM_ENTRY_REG(base, index))  argument
17699 #define ROM_RD_TABLEMARK(base)   (ROM_TABLEMARK_REG(base))  argument
17718 #define ROM_RD_SYSACCESS(base)   (ROM_SYSACCESS_REG(base))  argument
17737 #define ROM_RD_PERIPHID4(base)   (ROM_PERIPHID4_REG(base))  argument
17756 #define ROM_RD_PERIPHID5(base)   (ROM_PERIPHID5_REG(base))  argument
17775 #define ROM_RD_PERIPHID6(base)   (ROM_PERIPHID6_REG(base))  argument
17794 #define ROM_RD_PERIPHID7(base)   (ROM_PERIPHID7_REG(base))  argument
17813 #define ROM_RD_PERIPHID0(base)   (ROM_PERIPHID0_REG(base))  argument
17832 #define ROM_RD_PERIPHID1(base)   (ROM_PERIPHID1_REG(base))  argument
17851 #define ROM_RD_PERIPHID2(base)   (ROM_PERIPHID2_REG(base))  argument
17870 #define ROM_RD_PERIPHID3(base)   (ROM_PERIPHID3_REG(base))  argument
17889 #define ROM_RD_COMPID(base, index) (ROM_COMPID_REG(base, index))  argument
17924 #define RSIM_RD_CONTROL(base)    (RSIM_CONTROL_REG(base))  argument
17925 #define RSIM_WR_CONTROL(base, value) (RSIM_CONTROL_REG(base) = (value))  argument
17926 #define RSIM_RMW_CONTROL(base, mask, value) (RSIM_WR_CONTROL(base, (RSIM_RD_CONTROL(base) & ~(mask)…  argument
17927 #define RSIM_SET_CONTROL(base, value) (BME_OR32(&RSIM_CONTROL_REG(base), (uint32_t)(value)))  argument
17928 #define RSIM_CLR_CONTROL(base, value) (BME_AND32(&RSIM_CONTROL_REG(base), (uint32_t)(~(value))))  argument
17929 #define RSIM_TOG_CONTROL(base, value) (BME_XOR32(&RSIM_CONTROL_REG(base), (uint32_t)(value)))  argument
17948 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC_…  argument
17949 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_…  argument
17952 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_RF…  argument
17953 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint3…  argument
17964 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_STAT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OS…  argument
17965 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_STAT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…  argument
17976 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_INT_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_…  argument
17977 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…  argument
17980 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_INT_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BL…  argument
17981 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…  argument
17993 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_INT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC…  argument
17994 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…  argument
17997 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_INT(base, value) (RSIM_RMW_CONTROL(base, RSIM_CONTROL_BLE_RF…  argument
17998 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…  argument
18019 #define RSIM_RD_CONTROL_RF_OSC_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_EN_MASK) >> …  argument
18020 #define RSIM_BRD_CONTROL_RF_OSC_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_E…  argument
18023 #define RSIM_WR_CONTROL_RF_OSC_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_EN_MASK…  argument
18024 #define RSIM_BWR_CONTROL_RF_OSC_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(val…  argument
18036 #define RSIM_RD_CONTROL_GASKET_BYPASS_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_GASKET_…  argument
18037 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…  argument
18040 #define RSIM_WR_CONTROL_GASKET_BYPASS_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_GA…  argument
18041 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…  argument
18068 #define RSIM_RD_CONTROL_GASKET_BYPASS_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_GASKET_BYP…  argument
18069 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…  argument
18072 #define RSIM_WR_CONTROL_GASKET_BYPASS_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_GASKE…  argument
18073 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…  argument
18086 #define RSIM_RD_CONTROL_RF_OSC_BYPASS_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_BYPAS…  argument
18087 #define RSIM_BRD_CONTROL_RF_OSC_BYPASS_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_R…  argument
18090 #define RSIM_WR_CONTROL_RF_OSC_BYPASS_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_…  argument
18091 #define RSIM_BWR_CONTROL_RF_OSC_BYPASS_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32…  argument
18102 #define RSIM_RD_CONTROL_BLE_ACTIVE_PORT_1_SEL(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_ACT…  argument
18103 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_1_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…  argument
18106 #define RSIM_WR_CONTROL_BLE_ACTIVE_PORT_1_SEL(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BL…  argument
18107 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_1_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…  argument
18118 #define RSIM_RD_CONTROL_BLE_ACTIVE_PORT_2_SEL(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_ACT…  argument
18119 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_2_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONT…  argument
18122 #define RSIM_WR_CONTROL_BLE_ACTIVE_PORT_2_SEL(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BL…  argument
18123 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_2_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((u…  argument
18133 #define RSIM_RD_CONTROL_BLE_DEEP_SLEEP_EXIT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_DEEP_…  argument
18134 #define RSIM_BRD_CONTROL_BLE_DEEP_SLEEP_EXIT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…  argument
18137 #define RSIM_WR_CONTROL_BLE_DEEP_SLEEP_EXIT(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_…  argument
18138 #define RSIM_BWR_CONTROL_BLE_DEEP_SLEEP_EXIT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uin…  argument
18153 #define RSIM_RD_CONTROL_STOP_ACK_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_STOP_ACK_OVR…  argument
18154 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_S…  argument
18157 #define RSIM_WR_CONTROL_STOP_ACK_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_STOP_AC…  argument
18158 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32…  argument
18169 #define RSIM_RD_CONTROL_STOP_ACK_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_STOP_ACK_OVRD_M…  argument
18170 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_STOP…  argument
18173 #define RSIM_WR_CONTROL_STOP_ACK_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_STOP_ACK_O…  argument
18174 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)…  argument
18189 #define RSIM_RD_CONTROL_RF_OSC_READY(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_READY_MAS…  argument
18190 #define RSIM_BRD_CONTROL_RF_OSC_READY(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OS…  argument
18200 #define RSIM_RD_CONTROL_RF_OSC_READY_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_R…  argument
18201 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTR…  argument
18204 #define RSIM_WR_CONTROL_RF_OSC_READY_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_…  argument
18205 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((ui…  argument
18217 #define RSIM_RD_CONTROL_RF_OSC_READY_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_READ…  argument
18218 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_…  argument
18221 #define RSIM_WR_CONTROL_RF_OSC_READY_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC…  argument
18222 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint3…  argument
18235 #define RSIM_RD_CONTROL_BLOCK_RADIO_RESETS(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLOCK_RADI…  argument
18236 #define RSIM_BRD_CONTROL_BLOCK_RADIO_RESETS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL…  argument
18239 #define RSIM_WR_CONTROL_BLOCK_RADIO_RESETS(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLOCK…  argument
18240 #define RSIM_BWR_CONTROL_BLOCK_RADIO_RESETS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint…  argument
18253 #define RSIM_RD_CONTROL_BLOCK_RADIO_OUTPUTS(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLOCK_RAD…  argument
18254 #define RSIM_BRD_CONTROL_BLOCK_RADIO_OUTPUTS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTRO…  argument
18257 #define RSIM_WR_CONTROL_BLOCK_RADIO_OUTPUTS(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLOC…  argument
18258 #define RSIM_BWR_CONTROL_BLOCK_RADIO_OUTPUTS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uin…  argument
18272 #define RSIM_RD_CONTROL_RADIO_RESET(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RADIO_RESET_MASK)…  argument
18273 #define RSIM_BRD_CONTROL_RADIO_RESET(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RADIO_…  argument
18276 #define RSIM_WR_CONTROL_RADIO_RESET(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RADIO_RESET_…  argument
18277 #define RSIM_BWR_CONTROL_RADIO_RESET(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(v…  argument
18296 #define RSIM_RD_ACTIVE_DELAY(base) (RSIM_ACTIVE_DELAY_REG(base))  argument
18297 #define RSIM_WR_ACTIVE_DELAY(base, value) (RSIM_ACTIVE_DELAY_REG(base) = (value))  argument
18298 #define RSIM_RMW_ACTIVE_DELAY(base, mask, value) (RSIM_WR_ACTIVE_DELAY(base, (RSIM_RD_ACTIVE_DELAY(…  argument
18299 #define RSIM_SET_ACTIVE_DELAY(base, value) (BME_OR32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(value…  argument
18300 #define RSIM_CLR_ACTIVE_DELAY(base, value) (BME_AND32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(~(va…  argument
18301 #define RSIM_TOG_ACTIVE_DELAY(base, value) (BME_XOR32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(valu…  argument
18321 #define RSIM_RD_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base) ((RSIM_ACTIVE_DELAY_REG(base) & RSIM_ACTIV…  argument
18322 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base),…  argument
18325 #define RSIM_WR_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base, value) (RSIM_RMW_ACTIVE_DELAY(base, RSIM_A…  argument
18326 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_REG(…  argument
18341 #define RSIM_RD_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base) ((RSIM_ACTIVE_DELAY_REG(base) & RSIM_ACT…  argument
18342 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base…  argument
18345 #define RSIM_WR_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base, value) (RSIM_RMW_ACTIVE_DELAY(base, RSIM…  argument
18346 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_RE…  argument
18365 #define RSIM_RD_MAC_MSB(base)    (RSIM_MAC_MSB_REG(base))  argument
18381 #define RSIM_RD_MAC_MSB_MAC_ADDR_MSB(base) ((RSIM_MAC_MSB_REG(base) & RSIM_MAC_MSB_MAC_ADDR_MSB_MAS…  argument
18382 #define RSIM_BRD_MAC_MSB_MAC_ADDR_MSB(base) (BME_UBFX32(&RSIM_MAC_MSB_REG(base), RSIM_MAC_MSB_MAC_A…  argument
18401 #define RSIM_RD_MAC_LSB(base)    (RSIM_MAC_LSB_REG(base))  argument
18420 #define RSIM_RD_ANA_TEST(base)   (RSIM_ANA_TEST_REG(base))  argument
18421 #define RSIM_WR_ANA_TEST(base, value) (RSIM_ANA_TEST_REG(base) = (value))  argument
18422 #define RSIM_RMW_ANA_TEST(base, mask, value) (RSIM_WR_ANA_TEST(base, (RSIM_RD_ANA_TEST(base) & ~(ma…  argument
18423 #define RSIM_SET_ANA_TEST(base, value) (BME_OR32(&RSIM_ANA_TEST_REG(base), (uint32_t)(value)))  argument
18424 #define RSIM_CLR_ANA_TEST(base, value) (BME_AND32(&RSIM_ANA_TEST_REG(base), (uint32_t)(~(value))))  argument
18425 #define RSIM_TOG_ANA_TEST(base, value) (BME_XOR32(&RSIM_ANA_TEST_REG(base), (uint32_t)(value)))  argument
18441 #define RSIM_RD_ANA_TEST_ATST_GATE_EN(base) ((RSIM_ANA_TEST_REG(base) & RSIM_ANA_TEST_ATST_GATE_EN_…  argument
18442 #define RSIM_BRD_ANA_TEST_ATST_GATE_EN(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_AT…  argument
18445 #define RSIM_WR_ANA_TEST_ATST_GATE_EN(base, value) (RSIM_RMW_ANA_TEST(base, RSIM_ANA_TEST_ATST_GATE…  argument
18446 #define RSIM_BWR_ANA_TEST_ATST_GATE_EN(base, value) (BME_BFI32(&RSIM_ANA_TEST_REG(base), ((uint32_t…  argument
18461 #define RSIM_RD_ANA_TEST_RADIO_ID(base) ((RSIM_ANA_TEST_REG(base) & RSIM_ANA_TEST_RADIO_ID_MASK) >>…  argument
18462 #define RSIM_BRD_ANA_TEST_RADIO_ID(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_RADIO_…  argument
18497 #define RTC_RD_TSR(base)         (RTC_TSR_REG(base))  argument
18498 #define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))  argument
18499 #define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))  argument
18500 #define RTC_SET_TSR(base, value) (BME_OR32(&RTC_TSR_REG(base), (uint32_t)(value)))  argument
18501 #define RTC_CLR_TSR(base, value) (BME_AND32(&RTC_TSR_REG(base), (uint32_t)(~(value))))  argument
18502 #define RTC_TOG_TSR(base, value) (BME_XOR32(&RTC_TSR_REG(base), (uint32_t)(value)))  argument
18518 #define RTC_RD_TPR(base)         (RTC_TPR_REG(base))  argument
18519 #define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))  argument
18520 #define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))  argument
18521 #define RTC_SET_TPR(base, value) (BME_OR32(&RTC_TPR_REG(base), (uint32_t)(value)))  argument
18522 #define RTC_CLR_TPR(base, value) (BME_AND32(&RTC_TPR_REG(base), (uint32_t)(~(value))))  argument
18523 #define RTC_TOG_TPR(base, value) (BME_XOR32(&RTC_TPR_REG(base), (uint32_t)(value)))  argument
18541 #define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)  argument
18542 #define RTC_BRD_TPR_TPR(base) (BME_UBFX32(&RTC_TPR_REG(base), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))  argument
18545 #define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))  argument
18546 #define RTC_BWR_TPR_TPR(base, value) (BME_BFI32(&RTC_TPR_REG(base), ((uint32_t)(value) << RTC_TPR_T…  argument
18562 #define RTC_RD_TAR(base)         (RTC_TAR_REG(base))  argument
18563 #define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))  argument
18564 #define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))  argument
18565 #define RTC_SET_TAR(base, value) (BME_OR32(&RTC_TAR_REG(base), (uint32_t)(value)))  argument
18566 #define RTC_CLR_TAR(base, value) (BME_AND32(&RTC_TAR_REG(base), (uint32_t)(~(value))))  argument
18567 #define RTC_TOG_TAR(base, value) (BME_XOR32(&RTC_TAR_REG(base), (uint32_t)(value)))  argument
18583 #define RTC_RD_TCR(base)         (RTC_TCR_REG(base))  argument
18584 #define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))  argument
18585 #define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))  argument
18586 #define RTC_SET_TCR(base, value) (BME_OR32(&RTC_TCR_REG(base), (uint32_t)(value)))  argument
18587 #define RTC_CLR_TCR(base, value) (BME_AND32(&RTC_TCR_REG(base), (uint32_t)(~(value))))  argument
18588 #define RTC_TOG_TCR(base, value) (BME_XOR32(&RTC_TCR_REG(base), (uint32_t)(value)))  argument
18611 #define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)  argument
18612 #define RTC_BRD_TCR_TCR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))  argument
18615 #define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))  argument
18616 #define RTC_BWR_TCR_TCR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_T…  argument
18631 #define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)  argument
18632 #define RTC_BRD_TCR_CIR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))  argument
18635 #define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))  argument
18636 #define RTC_BWR_TCR_CIR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_C…  argument
18649 #define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)  argument
18650 #define RTC_BRD_TCR_TCV(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCV_SHIFT, RTC_TCR_TCV_WIDTH))  argument
18662 #define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)  argument
18663 #define RTC_BRD_TCR_CIC(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIC_SHIFT, RTC_TCR_CIC_WIDTH))  argument
18679 #define RTC_RD_CR(base)          (RTC_CR_REG(base))  argument
18680 #define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))  argument
18681 #define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))  argument
18682 #define RTC_SET_CR(base, value)  (BME_OR32(&RTC_CR_REG(base), (uint32_t)(value)))  argument
18683 #define RTC_CLR_CR(base, value)  (BME_AND32(&RTC_CR_REG(base), (uint32_t)(~(value))))  argument
18684 #define RTC_TOG_CR(base, value)  (BME_XOR32(&RTC_CR_REG(base), (uint32_t)(value)))  argument
18701 #define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)  argument
18702 #define RTC_BRD_CR_SWR(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))  argument
18705 #define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))  argument
18706 #define RTC_BWR_CR_SWR(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SWR_…  argument
18721 #define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)  argument
18722 #define RTC_BRD_CR_WPE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))  argument
18725 #define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))  argument
18726 #define RTC_BWR_CR_WPE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPE_…  argument
18739 #define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)  argument
18740 #define RTC_BRD_CR_SUP(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))  argument
18743 #define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))  argument
18744 #define RTC_BWR_CR_SUP(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SUP_…  argument
18760 #define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)  argument
18761 #define RTC_BRD_CR_UM(base)  (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))  argument
18764 #define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))  argument
18765 #define RTC_BWR_CR_UM(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_UM_SH…  argument
18781 #define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)  argument
18782 #define RTC_BRD_CR_WPS(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))  argument
18785 #define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))  argument
18786 #define RTC_BWR_CR_WPS(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPS_…  argument
18800 #define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)  argument
18801 #define RTC_BRD_CR_OSCE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))  argument
18804 #define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))  argument
18805 #define RTC_BWR_CR_OSCE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_OSC…  argument
18817 #define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)  argument
18818 #define RTC_BRD_CR_CLKO(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))  argument
18821 #define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))  argument
18822 #define RTC_BWR_CR_CLKO(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_CLK…  argument
18834 #define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)  argument
18835 #define RTC_BRD_CR_SC16P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDT…  argument
18838 #define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))  argument
18839 #define RTC_BWR_CR_SC16P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC…  argument
18851 #define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)  argument
18852 #define RTC_BRD_CR_SC8P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))  argument
18855 #define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))  argument
18856 #define RTC_BWR_CR_SC8P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC8…  argument
18868 #define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)  argument
18869 #define RTC_BRD_CR_SC4P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))  argument
18872 #define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))  argument
18873 #define RTC_BWR_CR_SC4P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC4…  argument
18885 #define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)  argument
18886 #define RTC_BRD_CR_SC2P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))  argument
18889 #define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))  argument
18890 #define RTC_BWR_CR_SC2P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC2…  argument
18906 #define RTC_RD_SR(base)          (RTC_SR_REG(base))  argument
18907 #define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))  argument
18908 #define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))  argument
18909 #define RTC_SET_SR(base, value)  (BME_OR32(&RTC_SR_REG(base), (uint32_t)(value)))  argument
18910 #define RTC_CLR_SR(base, value)  (BME_AND32(&RTC_SR_REG(base), (uint32_t)(~(value))))  argument
18911 #define RTC_TOG_SR(base, value)  (BME_XOR32(&RTC_SR_REG(base), (uint32_t)(value)))  argument
18931 #define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)  argument
18932 #define RTC_BRD_SR_TIF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT, RTC_SR_TIF_WIDTH))  argument
18948 #define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)  argument
18949 #define RTC_BRD_SR_TOF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT, RTC_SR_TOF_WIDTH))  argument
18964 #define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)  argument
18965 #define RTC_BRD_SR_TAF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT, RTC_SR_TAF_WIDTH))  argument
18981 #define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)  argument
18982 #define RTC_BRD_SR_TCE(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))  argument
18985 #define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))  argument
18986 #define RTC_BWR_SR_TCE(base, value) (BME_BFI32(&RTC_SR_REG(base), ((uint32_t)(value) << RTC_SR_TCE_…  argument
19002 #define RTC_RD_LR(base)          (RTC_LR_REG(base))  argument
19003 #define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))  argument
19004 #define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))  argument
19005 #define RTC_SET_LR(base, value)  (BME_OR32(&RTC_LR_REG(base), (uint32_t)(value)))  argument
19006 #define RTC_CLR_LR(base, value)  (BME_AND32(&RTC_LR_REG(base), (uint32_t)(~(value))))  argument
19007 #define RTC_TOG_LR(base, value)  (BME_XOR32(&RTC_LR_REG(base), (uint32_t)(value)))  argument
19026 #define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)  argument
19027 #define RTC_BRD_LR_TCL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))  argument
19030 #define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))  argument
19031 #define RTC_BWR_LR_TCL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_TCL_…  argument
19045 #define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)  argument
19046 #define RTC_BRD_LR_CRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))  argument
19049 #define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))  argument
19050 #define RTC_BWR_LR_CRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_CRL_…  argument
19064 #define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)  argument
19065 #define RTC_BRD_LR_SRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))  argument
19068 #define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))  argument
19069 #define RTC_BWR_LR_SRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_SRL_…  argument
19083 #define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)  argument
19084 #define RTC_BRD_LR_LRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))  argument
19087 #define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))  argument
19088 #define RTC_BWR_LR_LRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_LRL_…  argument
19104 #define RTC_RD_IER(base)         (RTC_IER_REG(base))  argument
19105 #define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))  argument
19106 #define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))  argument
19107 #define RTC_SET_IER(base, value) (BME_OR32(&RTC_IER_REG(base), (uint32_t)(value)))  argument
19108 #define RTC_CLR_IER(base, value) (BME_AND32(&RTC_IER_REG(base), (uint32_t)(~(value))))  argument
19109 #define RTC_TOG_IER(base, value) (BME_XOR32(&RTC_IER_REG(base), (uint32_t)(value)))  argument
19125 #define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)  argument
19126 #define RTC_BRD_IER_TIIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WID…  argument
19129 #define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))  argument
19130 #define RTC_BWR_IER_TIIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…  argument
19142 #define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)  argument
19143 #define RTC_BRD_IER_TOIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WID…  argument
19146 #define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))  argument
19147 #define RTC_BWR_IER_TOIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…  argument
19159 #define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)  argument
19160 #define RTC_BRD_IER_TAIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WID…  argument
19163 #define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))  argument
19164 #define RTC_BWR_IER_TAIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…  argument
19180 #define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)  argument
19181 #define RTC_BRD_IER_TSIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WID…  argument
19184 #define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))  argument
19185 #define RTC_BWR_IER_TSIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…  argument
19200 #define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)  argument
19201 #define RTC_BRD_IER_WPON(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WID…  argument
19204 #define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))  argument
19205 #define RTC_BWR_IER_WPON(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_…  argument
19253 #define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))  argument
19254 #define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))  argument
19255 #define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (valu…  argument
19256 #define SIM_SET_SOPT1(base, value) (BME_OR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))  argument
19257 #define SIM_CLR_SOPT1(base, value) (BME_AND32(&SIM_SOPT1_REG(base), (uint32_t)(~(value))))  argument
19258 #define SIM_TOG_SOPT1(base, value) (BME_XOR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))  argument
19280 #define SIM_RD_SOPT1_OSC32KOUT(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KOUT_MASK) >> SIM_SOPT1…  argument
19281 #define SIM_BRD_SOPT1_OSC32KOUT(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KOUT_SHIFT, …  argument
19284 #define SIM_WR_SOPT1_OSC32KOUT(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KOUT_MASK, SIM_SOPT…  argument
19285 #define SIM_BWR_SOPT1_OSC32KOUT(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) <<…  argument
19302 #define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1…  argument
19303 #define SIM_BRD_SOPT1_OSC32KSEL(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KSEL_SHIFT, …  argument
19306 #define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT…  argument
19307 #define SIM_BWR_SOPT1_OSC32KSEL(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) <<…  argument
19327 #define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))  argument
19328 #define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))  argument
19329 #define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (valu…  argument
19330 #define SIM_SET_SOPT2(base, value) (BME_OR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))  argument
19331 #define SIM_CLR_SOPT2(base, value) (BME_AND32(&SIM_SOPT2_REG(base), (uint32_t)(~(value))))  argument
19332 #define SIM_TOG_SOPT2(base, value) (BME_XOR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))  argument
19356 #define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2…  argument
19357 #define SIM_BRD_SOPT2_CLKOUTSEL(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_CLKOUTSEL_SHIFT, …  argument
19360 #define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT…  argument
19361 #define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) <<…  argument
19377 #define SIM_RD_SOPT2_TPMSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TPMSRC_MASK) >> SIM_SOPT2_TPMSR…  argument
19378 #define SIM_BRD_SOPT2_TPMSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_TPMSRC_SHIFT, SIM_SO…  argument
19381 #define SIM_WR_SOPT2_TPMSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TPMSRC_MASK, SIM_SOPT2_TPMS…  argument
19382 #define SIM_BWR_SOPT2_TPMSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SI…  argument
19398 #define SIM_RD_SOPT2_LPUART0SRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_LPUART0SRC_MASK) >> SIM_SOP…  argument
19399 #define SIM_BRD_SOPT2_LPUART0SRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_LPUART0SRC_SHIFT…  argument
19402 #define SIM_WR_SOPT2_LPUART0SRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_LPUART0SRC_MASK, SIM_SO…  argument
19403 #define SIM_BWR_SOPT2_LPUART0SRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) <…  argument
19419 #define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))  argument
19420 #define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))  argument
19421 #define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (valu…  argument
19422 #define SIM_SET_SOPT4(base, value) (BME_OR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))  argument
19423 #define SIM_CLR_SOPT4(base, value) (BME_AND32(&SIM_SOPT4_REG(base), (uint32_t)(~(value))))  argument
19424 #define SIM_TOG_SOPT4(base, value) (BME_XOR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))  argument
19443 #define SIM_RD_SOPT4_TPM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CH0SRC_MASK) >> SIM_SOP…  argument
19444 #define SIM_BRD_SOPT4_TPM1CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CH0SRC_SHIFT…  argument
19447 #define SIM_WR_SOPT4_TPM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CH0SRC_MASK, SIM_SO…  argument
19448 #define SIM_BWR_SOPT4_TPM1CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…  argument
19463 #define SIM_RD_SOPT4_TPM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CH0SRC_MASK) >> SIM_SOP…  argument
19464 #define SIM_BRD_SOPT4_TPM2CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CH0SRC_SHIFT…  argument
19467 #define SIM_WR_SOPT4_TPM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CH0SRC_MASK, SIM_SO…  argument
19468 #define SIM_BWR_SOPT4_TPM2CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…  argument
19484 #define SIM_RD_SOPT4_TPM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM0CLKSEL_MASK) >> SIM_SOP…  argument
19485 #define SIM_BRD_SOPT4_TPM0CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM0CLKSEL_SHIFT…  argument
19488 #define SIM_WR_SOPT4_TPM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM0CLKSEL_MASK, SIM_SO…  argument
19489 #define SIM_BWR_SOPT4_TPM0CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…  argument
19505 #define SIM_RD_SOPT4_TPM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CLKSEL_MASK) >> SIM_SOP…  argument
19506 #define SIM_BRD_SOPT4_TPM1CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CLKSEL_SHIFT…  argument
19509 #define SIM_WR_SOPT4_TPM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CLKSEL_MASK, SIM_SO…  argument
19510 #define SIM_BWR_SOPT4_TPM1CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…  argument
19526 #define SIM_RD_SOPT4_TPM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CLKSEL_MASK) >> SIM_SOP…  argument
19527 #define SIM_BRD_SOPT4_TPM2CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CLKSEL_SHIFT…  argument
19530 #define SIM_WR_SOPT4_TPM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CLKSEL_MASK, SIM_SO…  argument
19531 #define SIM_BWR_SOPT4_TPM2CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) <…  argument
19547 #define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))  argument
19548 #define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))  argument
19549 #define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (valu…  argument
19550 #define SIM_SET_SOPT5(base, value) (BME_OR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))  argument
19551 #define SIM_CLR_SOPT5(base, value) (BME_AND32(&SIM_SOPT5_REG(base), (uint32_t)(~(value))))  argument
19552 #define SIM_TOG_SOPT5(base, value) (BME_XOR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))  argument
19572 #define SIM_RD_SOPT5_LPUART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0TXSRC_MASK) >> SIM…  argument
19573 #define SIM_BRD_SOPT5_LPUART0TXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0TXSRC_S…  argument
19576 #define SIM_WR_SOPT5_LPUART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0TXSRC_MASK, SI…  argument
19577 #define SIM_BWR_SOPT5_LPUART0TXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value)…  argument
19591 #define SIM_RD_SOPT5_LPUART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0RXSRC_MASK) >> SIM…  argument
19592 #define SIM_BRD_SOPT5_LPUART0RXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0RXSRC_S…  argument
19595 #define SIM_WR_SOPT5_LPUART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0RXSRC_MASK, SI…  argument
19596 #define SIM_BWR_SOPT5_LPUART0RXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value)…  argument
19608 #define SIM_RD_SOPT5_LPUART0ODE(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0ODE_MASK) >> SIM_SOP…  argument
19609 #define SIM_BRD_SOPT5_LPUART0ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0ODE_SHIFT…  argument
19612 #define SIM_WR_SOPT5_LPUART0ODE(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0ODE_MASK, SIM_SO…  argument
19613 #define SIM_BWR_SOPT5_LPUART0ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) <…  argument
19629 #define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))  argument
19630 #define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))  argument
19631 #define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (valu…  argument
19632 #define SIM_SET_SOPT7(base, value) (BME_OR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))  argument
19633 #define SIM_CLR_SOPT7(base, value) (BME_AND32(&SIM_SOPT7_REG(base), (uint32_t)(~(value))))  argument
19634 #define SIM_TOG_SOPT7(base, value) (BME_XOR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))  argument
19667 #define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOP…  argument
19668 #define SIM_BRD_SOPT7_ADC0TRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0TRGSEL_SHIFT…  argument
19671 #define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SO…  argument
19672 #define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) <…  argument
19691 #define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> S…  argument
19692 #define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL…  argument
19695 #define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, …  argument
19696 #define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value…  argument
19719 #define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM…  argument
19720 #define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_S…  argument
19723 #define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SI…  argument
19724 #define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value)…  argument
19742 #define SIM_RD_SDID(base)        (SIM_SDID_REG(base))  argument
19774 #define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)  argument
19775 #define SIM_BRD_SDID_PINID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_PINID_SHIFT, SIM_SDID_PI…  argument
19785 #define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)  argument
19786 #define SIM_BRD_SDID_DIEID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_DIEID_SHIFT, SIM_SDID_DI…  argument
19796 #define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)  argument
19797 #define SIM_BRD_SDID_REVID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_REVID_SHIFT, SIM_SDID_RE…  argument
19807 #define SIM_RD_SDID_SRAMSIZE(base) ((SIM_SDID_REG(base) & SIM_SDID_SRAMSIZE_MASK) >> SIM_SDID_SRAMS…  argument
19808 #define SIM_BRD_SDID_SRAMSIZE(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SRAMSIZE_SHIFT, SIM_S…  argument
19821 #define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIE…  argument
19822 #define SIM_BRD_SDID_SERIESID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SERIESID_SHIFT, SIM_S…  argument
19838 #define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFA…  argument
19839 #define SIM_BRD_SDID_SUBFAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SUBFAMID_SHIFT, SIM_S…  argument
19855 #define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)  argument
19856 #define SIM_BRD_SDID_FAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_FAMID_SHIFT, SIM_SDID_FA…  argument
19872 #define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))  argument
19873 #define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))  argument
19874 #define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (valu…  argument
19875 #define SIM_SET_SCGC4(base, value) (BME_OR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))  argument
19876 #define SIM_CLR_SCGC4(base, value) (BME_AND32(&SIM_SCGC4_REG(base), (uint32_t)(~(value))))  argument
19877 #define SIM_TOG_SCGC4(base, value) (BME_XOR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))  argument
19881 #define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC4_REG(base) + (((uint…  argument
19883 #define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_B…  argument
19884 #define SIM_BRD_SCGC_BIT(base, index)        (BME_UBFX32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SC…  argument
19885 #define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG…  argument
19886 #define SIM_BWR_SCGC_BIT(base, index, value) (BME_BFI32(&SIM_SCGC_BIT_REG((base), (index)), ((uint3…  argument
19903 #define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)  argument
19904 #define SIM_BRD_SCGC4_CMT(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT, SIM_SCGC4_CM…  argument
19907 #define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)…  argument
19908 #define SIM_BWR_SCGC4_CMT(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_S…  argument
19922 #define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIF…  argument
19923 #define SIM_BRD_SCGC4_I2C0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_…  argument
19926 #define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(val…  argument
19927 #define SIM_BWR_SCGC4_I2C0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_…  argument
19941 #define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIF…  argument
19942 #define SIM_BRD_SCGC4_I2C1(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_…  argument
19945 #define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(val…  argument
19946 #define SIM_BWR_SCGC4_I2C1(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_…  argument
19960 #define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)  argument
19961 #define SIM_BRD_SCGC4_CMP(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT, SIM_SCGC4_CM…  argument
19964 #define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)…  argument
19965 #define SIM_BWR_SCGC4_CMP(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_S…  argument
19981 #define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))  argument
19982 #define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))  argument
19983 #define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (valu…  argument
19984 #define SIM_SET_SCGC5(base, value) (BME_OR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))  argument
19985 #define SIM_CLR_SCGC5(base, value) (BME_AND32(&SIM_SCGC5_REG(base), (uint32_t)(~(value))))  argument
19986 #define SIM_TOG_SCGC5(base, value) (BME_XOR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))  argument
20004 #define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_S…  argument
20005 #define SIM_BRD_SCGC5_LPTMR(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC…  argument
20008 #define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(…  argument
20009 #define SIM_BWR_SCGC5_LPTMR(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…  argument
20023 #define SIM_RD_SCGC5_TSI(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_TSI_MASK) >> SIM_SCGC5_TSI_SHIFT)  argument
20024 #define SIM_BRD_SCGC5_TSI(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_TSI_SHIFT, SIM_SCGC5_TS…  argument
20027 #define SIM_WR_SCGC5_TSI(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_TSI_MASK, SIM_SCGC5_TSI(value)…  argument
20028 #define SIM_BWR_SCGC5_TSI(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_S…  argument
20042 #define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_S…  argument
20043 #define SIM_BRD_SCGC5_PORTA(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC…  argument
20046 #define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(…  argument
20047 #define SIM_BWR_SCGC5_PORTA(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…  argument
20061 #define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_S…  argument
20062 #define SIM_BRD_SCGC5_PORTB(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC…  argument
20065 #define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(…  argument
20066 #define SIM_BWR_SCGC5_PORTB(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…  argument
20080 #define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_S…  argument
20081 #define SIM_BRD_SCGC5_PORTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC…  argument
20084 #define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(…  argument
20085 #define SIM_BWR_SCGC5_PORTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM…  argument
20099 #define SIM_RD_SCGC5_LPUART0(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPU…  argument
20100 #define SIM_BRD_SCGC5_LPUART0(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPUART0_SHIFT, SIM_…  argument
20103 #define SIM_WR_SCGC5_LPUART0(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPUART0_MASK, SIM_SCGC5_LP…  argument
20104 #define SIM_BWR_SCGC5_LPUART0(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << S…  argument
20118 #define SIM_RD_SCGC5_LTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LTC_MASK) >> SIM_SCGC5_LTC_SHIFT)  argument
20119 #define SIM_BRD_SCGC5_LTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LTC_SHIFT, SIM_SCGC5_LT…  argument
20122 #define SIM_WR_SCGC5_LTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LTC_MASK, SIM_SCGC5_LTC(value)…  argument
20123 #define SIM_BWR_SCGC5_LTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_S…  argument
20134 #define SIM_RD_SCGC5_RSIM(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_RSIM_MASK) >> SIM_SCGC5_RSIM_SHIF…  argument
20135 #define SIM_BRD_SCGC5_RSIM(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_RSIM_SHIFT, SIM_SCGC5_…  argument
20149 #define SIM_RD_SCGC5_DCDC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_DCDC_MASK) >> SIM_SCGC5_DCDC_SHIF…  argument
20150 #define SIM_BRD_SCGC5_DCDC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_DCDC_SHIFT, SIM_SCGC5_…  argument
20153 #define SIM_WR_SCGC5_DCDC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_DCDC_MASK, SIM_SCGC5_DCDC(val…  argument
20154 #define SIM_BWR_SCGC5_DCDC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_…  argument
20168 #define SIM_RD_SCGC5_BTLL(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_BTLL_MASK) >> SIM_SCGC5_BTLL_SHIF…  argument
20169 #define SIM_BRD_SCGC5_BTLL(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_BTLL_SHIFT, SIM_SCGC5_…  argument
20172 #define SIM_WR_SCGC5_BTLL(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_BTLL_MASK, SIM_SCGC5_BTLL(val…  argument
20173 #define SIM_BWR_SCGC5_BTLL(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_…  argument
20187 #define SIM_RD_SCGC5_PHYDIG(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PHYDIG_MASK) >> SIM_SCGC5_PHYDI…  argument
20188 #define SIM_BRD_SCGC5_PHYDIG(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PHYDIG_SHIFT, SIM_SC…  argument
20191 #define SIM_WR_SCGC5_PHYDIG(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PHYDIG_MASK, SIM_SCGC5_PHYD…  argument
20192 #define SIM_BWR_SCGC5_PHYDIG(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SI…  argument
20206 #define SIM_RD_SCGC5_ZigBee(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_ZigBee_MASK) >> SIM_SCGC5_ZigBe…  argument
20207 #define SIM_BRD_SCGC5_ZigBee(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_ZigBee_SHIFT, SIM_SC…  argument
20210 #define SIM_WR_SCGC5_ZigBee(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_ZigBee_MASK, SIM_SCGC5_ZigB…  argument
20211 #define SIM_BWR_SCGC5_ZigBee(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SI…  argument
20227 #define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))  argument
20228 #define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))  argument
20229 #define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (valu…  argument
20230 #define SIM_SET_SCGC6(base, value) (BME_OR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))  argument
20231 #define SIM_CLR_SCGC6(base, value) (BME_AND32(&SIM_SCGC6_REG(base), (uint32_t)(~(value))))  argument
20232 #define SIM_TOG_SCGC6(base, value) (BME_XOR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))  argument
20252 #define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)  argument
20253 #define SIM_BRD_SCGC6_FTF(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FT…  argument
20256 #define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)…  argument
20257 #define SIM_BWR_SCGC6_FTF(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…  argument
20271 #define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMU…  argument
20272 #define SIM_BRD_SCGC6_DMAMUX(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT, SIM_SC…  argument
20275 #define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAM…  argument
20276 #define SIM_BWR_SCGC6_DMAMUX(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SI…  argument
20290 #define SIM_RD_SCGC6_TRNG(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TRNG_MASK) >> SIM_SCGC6_TRNG_SHIF…  argument
20291 #define SIM_BRD_SCGC6_TRNG(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TRNG_SHIFT, SIM_SCGC6_…  argument
20294 #define SIM_WR_SCGC6_TRNG(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TRNG_MASK, SIM_SCGC6_TRNG(val…  argument
20295 #define SIM_BWR_SCGC6_TRNG(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20309 #define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIF…  argument
20310 #define SIM_BRD_SCGC6_SPI0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT, SIM_SCGC6_…  argument
20313 #define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(val…  argument
20314 #define SIM_BWR_SCGC6_SPI0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20328 #define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIF…  argument
20329 #define SIM_BRD_SCGC6_SPI1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT, SIM_SCGC6_…  argument
20332 #define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(val…  argument
20333 #define SIM_BWR_SCGC6_SPI1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20347 #define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)  argument
20348 #define SIM_BRD_SCGC6_PIT(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PI…  argument
20351 #define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)…  argument
20352 #define SIM_BWR_SCGC6_PIT(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…  argument
20366 #define SIM_RD_SCGC6_TPM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM0_MASK) >> SIM_SCGC6_TPM0_SHIF…  argument
20367 #define SIM_BRD_SCGC6_TPM0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_…  argument
20370 #define SIM_WR_SCGC6_TPM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM0_MASK, SIM_SCGC6_TPM0(val…  argument
20371 #define SIM_BWR_SCGC6_TPM0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20385 #define SIM_RD_SCGC6_TPM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM1_MASK) >> SIM_SCGC6_TPM1_SHIF…  argument
20386 #define SIM_BRD_SCGC6_TPM1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_…  argument
20389 #define SIM_WR_SCGC6_TPM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM1_MASK, SIM_SCGC6_TPM1(val…  argument
20390 #define SIM_BWR_SCGC6_TPM1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20404 #define SIM_RD_SCGC6_TPM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM2_MASK) >> SIM_SCGC6_TPM2_SHIF…  argument
20405 #define SIM_BRD_SCGC6_TPM2(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_…  argument
20408 #define SIM_WR_SCGC6_TPM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM2_MASK, SIM_SCGC6_TPM2(val…  argument
20409 #define SIM_BWR_SCGC6_TPM2(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20423 #define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIF…  argument
20424 #define SIM_BRD_SCGC6_ADC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_…  argument
20427 #define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(val…  argument
20428 #define SIM_BWR_SCGC6_ADC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20442 #define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)  argument
20443 #define SIM_BRD_SCGC6_RTC(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RT…  argument
20446 #define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)…  argument
20447 #define SIM_BWR_SCGC6_RTC(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_S…  argument
20461 #define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIF…  argument
20462 #define SIM_BRD_SCGC6_DAC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_…  argument
20465 #define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(val…  argument
20466 #define SIM_BWR_SCGC6_DAC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_…  argument
20482 #define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))  argument
20483 #define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))  argument
20484 #define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (valu…  argument
20485 #define SIM_SET_SCGC7(base, value) (BME_OR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))  argument
20486 #define SIM_CLR_SCGC7(base, value) (BME_AND32(&SIM_SCGC7_REG(base), (uint32_t)(~(value))))  argument
20487 #define SIM_TOG_SCGC7(base, value) (BME_XOR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))  argument
20505 #define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)  argument
20506 #define SIM_BRD_SCGC7_DMA(base) (BME_UBFX32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DM…  argument
20509 #define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)…  argument
20510 #define SIM_BWR_SCGC7_DMA(base, value) (BME_BFI32(&SIM_SCGC7_REG(base), ((uint32_t)(value) << SIM_S…  argument
20529 #define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))  argument
20530 #define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))  argument
20531 #define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) |…  argument
20532 #define SIM_SET_CLKDIV1(base, value) (BME_OR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))  argument
20533 #define SIM_CLR_CLKDIV1(base, value) (BME_AND32(&SIM_CLKDIV1_REG(base), (uint32_t)(~(value))))  argument
20534 #define SIM_TOG_CLKDIV1(base, value) (BME_XOR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))  argument
20560 #define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLK…  argument
20561 #define SIM_BRD_CLKDIV1_OUTDIV4(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV4_SHIFT…  argument
20564 #define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CL…  argument
20565 #define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) …  argument
20596 #define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLK…  argument
20597 #define SIM_BRD_CLKDIV1_OUTDIV1(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV1_SHIFT…  argument
20600 #define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CL…  argument
20601 #define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) …  argument
20619 #define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))  argument
20620 #define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))  argument
20621 #define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (valu…  argument
20622 #define SIM_SET_FCFG1(base, value) (BME_OR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))  argument
20623 #define SIM_CLR_FCFG1(base, value) (BME_AND32(&SIM_FCFG1_REG(base), (uint32_t)(~(value))))  argument
20624 #define SIM_TOG_FCFG1(base, value) (BME_XOR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))  argument
20645 #define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_F…  argument
20646 #define SIM_BRD_FCFG1_FLASHDIS(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT, SI…  argument
20649 #define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_…  argument
20650 #define SIM_BWR_FCFG1_FLASHDIS(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << …  argument
20669 #define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1…  argument
20670 #define SIM_BRD_FCFG1_FLASHDOZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT, …  argument
20673 #define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG…  argument
20674 #define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) <<…  argument
20685 #define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZ…  argument
20686 #define SIM_BRD_FCFG1_PFSIZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_PFSIZE_SHIFT, SIM_FC…  argument
20705 #define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))  argument
20724 #define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_M…  argument
20725 #define SIM_BRD_FCFG2_MAXADDR1(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR1_SHIFT, SI…  argument
20739 #define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_M…  argument
20740 #define SIM_BRD_FCFG2_MAXADDR0(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR0_SHIFT, SI…  argument
20758 #define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))  argument
20772 #define SIM_RD_UIDMH_UID(base) ((SIM_UIDMH_REG(base) & SIM_UIDMH_UID_MASK) >> SIM_UIDMH_UID_SHIFT)  argument
20773 #define SIM_BRD_UIDMH_UID(base) (BME_UBFX32(&SIM_UIDMH_REG(base), SIM_UIDMH_UID_SHIFT, SIM_UIDMH_UI…  argument
20791 #define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))  argument
20809 #define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))  argument
20828 #define SIM_RD_COPC(base)        (SIM_COPC_REG(base))  argument
20829 #define SIM_WR_COPC(base, value) (SIM_COPC_REG(base) = (value))  argument
20830 #define SIM_RMW_COPC(base, mask, value) (SIM_WR_COPC(base, (SIM_RD_COPC(base) & ~(mask)) | (value)))  argument
20831 #define SIM_SET_COPC(base, value) (BME_OR32(&SIM_COPC_REG(base), (uint32_t)(value)))  argument
20832 #define SIM_CLR_COPC(base, value) (BME_AND32(&SIM_COPC_REG(base), (uint32_t)(~(value))))  argument
20833 #define SIM_TOG_COPC(base, value) (BME_XOR32(&SIM_COPC_REG(base), (uint32_t)(value)))  argument
20854 #define SIM_RD_COPC_COPW(base) ((SIM_COPC_REG(base) & SIM_COPC_COPW_MASK) >> SIM_COPC_COPW_SHIFT)  argument
20855 #define SIM_BRD_COPC_COPW(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW…  argument
20858 #define SIM_WR_COPC_COPW(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPW_MASK, SIM_COPC_COPW(value)))  argument
20859 #define SIM_BWR_COPC_COPW(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_CO…  argument
20874 #define SIM_RD_COPC_COPCLKS(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKS_MASK) >> SIM_COPC_COPCLKS…  argument
20875 #define SIM_BRD_COPC_COPCLKS(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKS_SHIFT, SIM_COP…  argument
20878 #define SIM_WR_COPC_COPCLKS(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKS_MASK, SIM_COPC_COPCLK…  argument
20879 #define SIM_BWR_COPC_COPCLKS(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM…  argument
20899 #define SIM_RD_COPC_COPT(base) ((SIM_COPC_REG(base) & SIM_COPC_COPT_MASK) >> SIM_COPC_COPT_SHIFT)  argument
20900 #define SIM_BRD_COPC_COPT(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT…  argument
20903 #define SIM_WR_COPC_COPT(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPT_MASK, SIM_COPC_COPT(value)))  argument
20904 #define SIM_BWR_COPC_COPT(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_CO…  argument
20916 #define SIM_RD_COPC_COPSTPEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPSTPEN_MASK) >> SIM_COPC_COPST…  argument
20917 #define SIM_BRD_COPC_COPSTPEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPSTPEN_SHIFT, SIM_C…  argument
20920 #define SIM_WR_COPC_COPSTPEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPSTPEN_MASK, SIM_COPC_COPS…  argument
20921 #define SIM_BWR_COPC_COPSTPEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SI…  argument
20933 #define SIM_RD_COPC_COPDBGEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPDBGEN_MASK) >> SIM_COPC_COPDB…  argument
20934 #define SIM_BRD_COPC_COPDBGEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPDBGEN_SHIFT, SIM_C…  argument
20937 #define SIM_WR_COPC_COPDBGEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPDBGEN_MASK, SIM_COPC_COPD…  argument
20938 #define SIM_BWR_COPC_COPDBGEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SI…  argument
20954 #define SIM_RD_COPC_COPCLKSEL(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKSEL_MASK) >> SIM_COPC_COP…  argument
20955 #define SIM_BRD_COPC_COPCLKSEL(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKSEL_SHIFT, SIM…  argument
20958 #define SIM_WR_COPC_COPCLKSEL(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKSEL_MASK, SIM_COPC_CO…  argument
20959 #define SIM_BWR_COPC_COPCLKSEL(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << S…  argument
20978 #define SIM_WR_SRVCOP(base, value) (SIM_SRVCOP_REG(base) = (value))  argument
20993 #define SIM_WR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP(base, SIM_SRVCOP_SRVCOP(value)))  argument
20994 #define SIM_BWR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP_SRVCOP(base, value))  argument
21037 #define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))  argument
21038 #define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))  argument
21039 #define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (v…  argument
21040 #define SMC_SET_PMPROT(base, value) (BME_OR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))  argument
21041 #define SMC_CLR_PMPROT(base, value) (BME_AND8(&SMC_PMPROT_REG(base), (uint8_t)(~(value))))  argument
21042 #define SMC_TOG_PMPROT(base, value) (BME_XOR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))  argument
21061 #define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVL…  argument
21062 #define SMC_BRD_PMPROT_AVLLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT, SMC_PM…  argument
21065 #define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AV…  argument
21066 #define SMC_BWR_PMPROT_AVLLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC…  argument
21081 #define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_…  argument
21082 #define SMC_BRD_PMPROT_ALLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT, SMC_PMPR…  argument
21085 #define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS…  argument
21086 #define SMC_BWR_PMPROT_ALLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_…  argument
21101 #define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_…  argument
21102 #define SMC_BRD_PMPROT_AVLP(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT, SMC_PMPR…  argument
21105 #define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP…  argument
21106 #define SMC_BWR_PMPROT_AVLP(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_…  argument
21129 #define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))  argument
21130 #define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))  argument
21131 #define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (v…  argument
21132 #define SMC_SET_PMCTRL(base, value) (BME_OR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))  argument
21133 #define SMC_CLR_PMCTRL(base, value) (BME_AND8(&SMC_PMCTRL_REG(base), (uint8_t)(~(value))))  argument
21134 #define SMC_TOG_PMCTRL(base, value) (BME_XOR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))  argument
21165 #define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STO…  argument
21166 #define SMC_BRD_PMCTRL_STOPM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPM_SHIFT, SMC_PM…  argument
21169 #define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_ST…  argument
21170 #define SMC_BWR_PMCTRL_STOPM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC…  argument
21187 #define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STO…  argument
21188 #define SMC_BRD_PMCTRL_STOPA(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT, SMC_PM…  argument
21207 #define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_…  argument
21208 #define SMC_BRD_PMCTRL_RUNM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_RUNM_SHIFT, SMC_PMCT…  argument
21211 #define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM…  argument
21212 #define SMC_BWR_PMCTRL_RUNM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC_…  argument
21234 #define SMC_RD_STOPCTRL(base)    (SMC_STOPCTRL_REG(base))  argument
21235 #define SMC_WR_STOPCTRL(base, value) (SMC_STOPCTRL_REG(base) = (value))  argument
21236 #define SMC_RMW_STOPCTRL(base, mask, value) (SMC_WR_STOPCTRL(base, (SMC_RD_STOPCTRL(base) & ~(mask)…  argument
21237 #define SMC_SET_STOPCTRL(base, value) (BME_OR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))  argument
21238 #define SMC_CLR_STOPCTRL(base, value) (BME_AND8(&SMC_STOPCTRL_REG(base), (uint8_t)(~(value))))  argument
21239 #define SMC_TOG_STOPCTRL(base, value) (BME_XOR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))  argument
21264 #define SMC_RD_STOPCTRL_LLSM(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_LLSM_MASK) >> SMC_STOPCT…  argument
21265 #define SMC_BRD_STOPCTRL_LLSM(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_LLSM_SHIFT, SM…  argument
21268 #define SMC_WR_STOPCTRL_LLSM(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_LLSM_MASK, SMC_STOPC…  argument
21269 #define SMC_BWR_STOPCTRL_LLSM(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << …  argument
21283 #define SMC_RD_STOPCTRL_PORPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PORPO_MASK) >> SMC_STOP…  argument
21284 #define SMC_BRD_STOPCTRL_PORPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PORPO_SHIFT, …  argument
21287 #define SMC_WR_STOPCTRL_PORPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PORPO_MASK, SMC_STO…  argument
21288 #define SMC_BWR_STOPCTRL_PORPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) <<…  argument
21310 #define SMC_RD_STOPCTRL_PSTOPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PSTOPO_MASK) >> SMC_ST…  argument
21311 #define SMC_BRD_STOPCTRL_PSTOPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PSTOPO_SHIFT…  argument
21314 #define SMC_WR_STOPCTRL_PSTOPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PSTOPO_MASK, SMC_S…  argument
21315 #define SMC_BWR_STOPCTRL_PSTOPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) <…  argument
21336 #define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))  argument
21386 #define SPI_RD_MCR(base)         (SPI_MCR_REG(base))  argument
21387 #define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))  argument
21388 #define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))  argument
21389 #define SPI_SET_MCR(base, value) (BME_OR32(&SPI_MCR_REG(base), (uint32_t)(value)))  argument
21390 #define SPI_CLR_MCR(base, value) (BME_AND32(&SPI_MCR_REG(base), (uint32_t)(~(value))))  argument
21391 #define SPI_TOG_MCR(base, value) (BME_XOR32(&SPI_MCR_REG(base), (uint32_t)(value)))  argument
21410 #define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)  argument
21411 #define SPI_BRD_MCR_HALT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT, SPI_MCR_HALT_WID…  argument
21414 #define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))  argument
21415 #define SPI_BWR_MCR_HALT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21432 #define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHI…  argument
21433 #define SPI_BRD_MCR_SMPL_PT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_SMPL_PT_SHIFT, SPI_MCR_SM…  argument
21436 #define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(va…  argument
21437 #define SPI_BWR_MCR_SMPL_PT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…  argument
21452 #define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(va…  argument
21453 #define SPI_BWR_MCR_CLR_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…  argument
21468 #define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(va…  argument
21469 #define SPI_BWR_MCR_CLR_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…  argument
21485 #define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHI…  argument
21486 #define SPI_BRD_MCR_DIS_RXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT, SPI_MCR_DI…  argument
21489 #define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(va…  argument
21490 #define SPI_BWR_MCR_DIS_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…  argument
21506 #define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHI…  argument
21507 #define SPI_BRD_MCR_DIS_TXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT, SPI_MCR_DI…  argument
21510 #define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(va…  argument
21511 #define SPI_BWR_MCR_DIS_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_M…  argument
21529 #define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)  argument
21530 #define SPI_BRD_MCR_MDIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT, SPI_MCR_MDIS_WID…  argument
21533 #define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))  argument
21534 #define SPI_BWR_MCR_MDIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21549 #define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)  argument
21550 #define SPI_BRD_MCR_DOZE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT, SPI_MCR_DOZE_WID…  argument
21553 #define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))  argument
21554 #define SPI_BWR_MCR_DOZE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21569 #define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)  argument
21570 #define SPI_BRD_MCR_PCSIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_PCSIS_SHIFT, SPI_MCR_PCSIS_…  argument
21573 #define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))  argument
21574 #define SPI_BWR_MCR_PCSIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR…  argument
21591 #define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)  argument
21592 #define SPI_BRD_MCR_ROOE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT, SPI_MCR_ROOE_WID…  argument
21595 #define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))  argument
21596 #define SPI_BWR_MCR_ROOE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21610 #define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)  argument
21611 #define SPI_BRD_MCR_MTFE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT, SPI_MCR_MTFE_WID…  argument
21614 #define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))  argument
21615 #define SPI_BWR_MCR_MTFE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21630 #define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)  argument
21631 #define SPI_BRD_MCR_FRZ(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT, SPI_MCR_FRZ_WIDTH))  argument
21634 #define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))  argument
21635 #define SPI_BWR_MCR_FRZ(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_F…  argument
21651 #define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)  argument
21652 #define SPI_BRD_MCR_DCONF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DCONF_SHIFT, SPI_MCR_DCONF_…  argument
21666 #define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SC…  argument
21667 #define SPI_BRD_MCR_CONT_SCKE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT, SPI_MC…  argument
21670 #define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_S…  argument
21671 #define SPI_BWR_MCR_CONT_SCKE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI…  argument
21686 #define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)  argument
21687 #define SPI_BRD_MCR_MSTR(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT, SPI_MCR_MSTR_WID…  argument
21690 #define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))  argument
21691 #define SPI_BWR_MCR_MSTR(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_…  argument
21711 #define SPI_RD_TCR(base)         (SPI_TCR_REG(base))  argument
21712 #define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))  argument
21713 #define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))  argument
21714 #define SPI_SET_TCR(base, value) (BME_OR32(&SPI_TCR_REG(base), (uint32_t)(value)))  argument
21715 #define SPI_CLR_TCR(base, value) (BME_AND32(&SPI_TCR_REG(base), (uint32_t)(~(value))))  argument
21716 #define SPI_TOG_TCR(base, value) (BME_XOR32(&SPI_TCR_REG(base), (uint32_t)(value)))  argument
21735 #define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_…  argument
21736 #define SPI_BRD_TCR_SPI_TCNT(base) (BME_UBFX32(&SPI_TCR_REG(base), SPI_TCR_SPI_TCNT_SHIFT, SPI_TCR_…  argument
21739 #define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT…  argument
21740 #define SPI_BWR_TCR_SPI_TCNT(base, value) (BME_BFI32(&SPI_TCR_REG(base), ((uint32_t)(value) << SPI_…  argument
21758 #define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))  argument
21759 #define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))  argument
21760 #define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_S…  argument
21761 #define SPI_SET_CTAR_SLAVE(base, index, value) (BME_OR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_…  argument
21762 #define SPI_CLR_CTAR_SLAVE(base, index, value) (BME_AND32(&SPI_CTAR_SLAVE_REG(base, index), (uint32…  argument
21763 #define SPI_TOG_CTAR_SLAVE(base, index, value) (BME_XOR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32…  argument
21787 #define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA…  argument
21788 #define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21791 #define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21792 #define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21808 #define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL…  argument
21809 #define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21812 #define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21813 #define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21824 #define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ…  argument
21825 #define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR…  argument
21828 #define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_…  argument
21829 #define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((…  argument
21856 #define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))  argument
21857 #define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))  argument
21858 #define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) …  argument
21859 #define SPI_SET_CTAR(base, index, value) (BME_OR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))  argument
21860 #define SPI_CLR_CTAR(base, index, value) (BME_AND32(&SPI_CTAR_REG(base, index), (uint32_t)(~(value)…  argument
21861 #define SPI_TOG_CTAR(base, index, value) (BME_XOR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))  argument
21881 #define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_…  argument
21882 #define SPI_BRD_CTAR_BR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_BR_SHIFT, SPI…  argument
21885 #define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR…  argument
21886 #define SPI_BWR_CTAR_BR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…  argument
21903 #define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_…  argument
21904 #define SPI_BRD_CTAR_DT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DT_SHIFT, SPI…  argument
21907 #define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT…  argument
21908 #define SPI_BWR_CTAR_DT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(valu…  argument
21923 #define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_A…  argument
21924 #define SPI_BRD_CTAR_ASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_ASC_SHIFT, S…  argument
21927 #define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_…  argument
21928 #define SPI_BWR_CTAR_ASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
21946 #define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CT…  argument
21947 #define SPI_BRD_CTAR_CSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CSSCK_SHIF…  argument
21950 #define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_C…  argument
21951 #define SPI_BWR_CTAR_CSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…  argument
21970 #define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_P…  argument
21971 #define SPI_BRD_CTAR_PBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PBR_SHIFT, S…  argument
21974 #define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_…  argument
21975 #define SPI_BWR_CTAR_PBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
21995 #define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_P…  argument
21996 #define SPI_BRD_CTAR_PDT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PDT_SHIFT, S…  argument
21999 #define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_…  argument
22000 #define SPI_BWR_CTAR_PDT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
22018 #define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR…  argument
22019 #define SPI_BRD_CTAR_PASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PASC_SHIFT,…  argument
22022 #define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTA…  argument
22023 #define SPI_BWR_CTAR_PASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22041 #define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_…  argument
22042 #define SPI_BRD_CTAR_PCSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PCSSCK_SH…  argument
22045 #define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI…  argument
22046 #define SPI_BWR_CTAR_PCSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(…  argument
22060 #define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CT…  argument
22061 #define SPI_BRD_CTAR_LSBFE(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIF…  argument
22064 #define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_C…  argument
22065 #define SPI_BWR_CTAR_LSBFE(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(v…  argument
22085 #define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR…  argument
22086 #define SPI_BRD_CTAR_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT,…  argument
22089 #define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTA…  argument
22090 #define SPI_BWR_CTAR_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22111 #define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR…  argument
22112 #define SPI_BRD_CTAR_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT,…  argument
22115 #define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTA…  argument
22116 #define SPI_BWR_CTAR_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22127 #define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR…  argument
22128 #define SPI_BRD_CTAR_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_FMSZ_SHIFT,…  argument
22131 #define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTA…  argument
22132 #define SPI_BWR_CTAR_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(va…  argument
22155 #define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_D…  argument
22156 #define SPI_BRD_CTAR_DBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT, S…  argument
22159 #define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_…  argument
22160 #define SPI_BWR_CTAR_DBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(val…  argument
22182 #define SPI_RD_SR(base)          (SPI_SR_REG(base))  argument
22183 #define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))  argument
22184 #define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))  argument
22185 #define SPI_SET_SR(base, value)  (BME_OR32(&SPI_SR_REG(base), (uint32_t)(value)))  argument
22186 #define SPI_CLR_SR(base, value)  (BME_AND32(&SPI_SR_REG(base), (uint32_t)(~(value))))  argument
22187 #define SPI_TOG_SR(base, value)  (BME_XOR32(&SPI_SR_REG(base), (uint32_t)(value)))  argument
22202 #define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_S…  argument
22203 #define SPI_BRD_SR_POPNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_POPNXTPTR_SHIFT, SPI_SR_PO…  argument
22215 #define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)  argument
22216 #define SPI_BRD_SR_RXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RXCTR_SHIFT, SPI_SR_RXCTR_WIDT…  argument
22228 #define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIF…  argument
22229 #define SPI_BRD_SR_TXNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXNXTPTR_SHIFT, SPI_SR_TXNX…  argument
22241 #define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)  argument
22242 #define SPI_BRD_SR_TXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXCTR_SHIFT, SPI_SR_TXCTR_WIDT…  argument
22259 #define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)  argument
22260 #define SPI_BRD_SR_RFDF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT, SPI_SR_RFDF_WIDTH))  argument
22263 #define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR…  argument
22264 #define SPI_BWR_SR_RFDF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFD…  argument
22280 #define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)  argument
22281 #define SPI_BRD_SR_RFOF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT, SPI_SR_RFOF_WIDTH))  argument
22284 #define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR…  argument
22285 #define SPI_BWR_SR_RFOF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFO…  argument
22302 #define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)  argument
22303 #define SPI_BRD_SR_TFFF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT, SPI_SR_TFFF_WIDTH))  argument
22306 #define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR…  argument
22307 #define SPI_BWR_SR_TFFF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFF…  argument
22325 #define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)  argument
22326 #define SPI_BRD_SR_TFUF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT, SPI_SR_TFUF_WIDTH))  argument
22329 #define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR…  argument
22330 #define SPI_BWR_SR_TFUF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFU…  argument
22348 #define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)  argument
22349 #define SPI_BRD_SR_EOQF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT, SPI_SR_EOQF_WIDTH))  argument
22352 #define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR…  argument
22353 #define SPI_BWR_SR_EOQF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_EOQ…  argument
22369 #define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)  argument
22370 #define SPI_BRD_SR_TXRXS(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT, SPI_SR_TXRXS_WIDT…  argument
22373 #define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_…  argument
22374 #define SPI_BWR_SR_TXRXS(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TX…  argument
22389 #define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)  argument
22390 #define SPI_BRD_SR_TCF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT, SPI_SR_TCF_WIDTH))  argument
22393 #define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_R…  argument
22394 #define SPI_BWR_SR_TCF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TCF_…  argument
22413 #define SPI_RD_RSER(base)        (SPI_RSER_REG(base))  argument
22414 #define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))  argument
22415 #define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))  argument
22416 #define SPI_SET_RSER(base, value) (BME_OR32(&SPI_RSER_REG(base), (uint32_t)(value)))  argument
22417 #define SPI_CLR_RSER(base, value) (BME_AND32(&SPI_RSER_REG(base), (uint32_t)(~(value))))  argument
22418 #define SPI_TOG_RSER(base, value) (BME_XOR32(&SPI_RSER_REG(base), (uint32_t)(value)))  argument
22438 #define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFD…  argument
22439 #define SPI_BRD_RSER_RFDF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT, SPI…  argument
22442 #define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RF…  argument
22443 #define SPI_BWR_RSER_RFDF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << S…  argument
22458 #define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE…  argument
22459 #define SPI_BRD_RSER_RFDF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT, SPI_RSE…  argument
22462 #define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_R…  argument
22463 #define SPI_BWR_RSER_RFDF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…  argument
22477 #define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE…  argument
22478 #define SPI_BRD_RSER_RFOF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT, SPI_RSE…  argument
22481 #define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_R…  argument
22482 #define SPI_BWR_RSER_RFOF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…  argument
22498 #define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFF…  argument
22499 #define SPI_BRD_RSER_TFFF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT, SPI…  argument
22502 #define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TF…  argument
22503 #define SPI_BWR_RSER_TFFF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << S…  argument
22518 #define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE…  argument
22519 #define SPI_BRD_RSER_TFFF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT, SPI_RSE…  argument
22522 #define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_R…  argument
22523 #define SPI_BWR_RSER_TFFF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…  argument
22537 #define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE…  argument
22538 #define SPI_BRD_RSER_TFUF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT, SPI_RSE…  argument
22541 #define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_R…  argument
22542 #define SPI_BWR_RSER_TFUF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…  argument
22556 #define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE…  argument
22557 #define SPI_BRD_RSER_EOQF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT, SPI_RSE…  argument
22560 #define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_R…  argument
22561 #define SPI_BWR_RSER_EOQF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI…  argument
22575 #define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SH…  argument
22576 #define SPI_BRD_RSER_TCF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT, SPI_RSER_…  argument
22579 #define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(v…  argument
22580 #define SPI_BWR_RSER_TCF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_…  argument
22605 #define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))  argument
22606 #define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))  argument
22607 #define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (valu…  argument
22608 #define SPI_SET_PUSHR(base, value) (BME_OR32(&SPI_PUSHR_REG(base), (uint32_t)(value)))  argument
22609 #define SPI_CLR_PUSHR(base, value) (BME_AND32(&SPI_PUSHR_REG(base), (uint32_t)(~(value))))  argument
22610 #define SPI_TOG_PUSHR(base, value) (BME_XOR32(&SPI_PUSHR_REG(base), (uint32_t)(value)))  argument
22624 #define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDAT…  argument
22625 #define SPI_BRD_PUSHR_TXDATA(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_TXDATA_SHIFT, SPI_PU…  argument
22628 #define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDA…  argument
22629 #define SPI_BWR_PUSHR_TXDATA(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SP…  argument
22644 #define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)  argument
22645 #define SPI_BRD_PUSHR_PCS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_PCS_SHIFT, SPI_PUSHR_PC…  argument
22648 #define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)…  argument
22649 #define SPI_BWR_PUSHR_PCS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_P…  argument
22664 #define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_S…  argument
22665 #define SPI_BRD_PUSHR_CTCNT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT, SPI_PUSH…  argument
22668 #define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(…  argument
22669 #define SPI_BWR_PUSHR_CTCNT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI…  argument
22685 #define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)  argument
22686 #define SPI_BRD_PUSHR_EOQ(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT, SPI_PUSHR_EO…  argument
22689 #define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)…  argument
22690 #define SPI_BWR_PUSHR_EOQ(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_P…  argument
22713 #define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIF…  argument
22714 #define SPI_BRD_PUSHR_CTAS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTAS_SHIFT, SPI_PUSHR_…  argument
22717 #define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(val…  argument
22718 #define SPI_BWR_PUSHR_CTAS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_…  argument
22733 #define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIF…  argument
22734 #define SPI_BRD_PUSHR_CONT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT, SPI_PUSHR_…  argument
22737 #define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(val…  argument
22738 #define SPI_BWR_PUSHR_CONT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_…  argument
22760 #define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))  argument
22761 #define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))  argument
22762 #define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) …  argument
22763 #define SPI_SET_PUSHR_SLAVE(base, value) (BME_OR32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(value)))  argument
22764 #define SPI_CLR_PUSHR_SLAVE(base, value) (BME_AND32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(~(value)…  argument
22765 #define SPI_TOG_PUSHR_SLAVE(base, value) (BME_XOR32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(value)))  argument
22785 #define SPI_RD_POPR(base)        (SPI_POPR_REG(base))  argument
22807 #define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))  argument
22821 #define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDAT…  argument
22822 #define SPI_BRD_TXFR0_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXDATA_SHIFT, SPI_TX…  argument
22834 #define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI…  argument
22835 #define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXCMD_TXDATA_S…  argument
22857 #define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))  argument
22871 #define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDAT…  argument
22872 #define SPI_BRD_TXFR1_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXDATA_SHIFT, SPI_TX…  argument
22884 #define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI…  argument
22885 #define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXCMD_TXDATA_S…  argument
22907 #define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))  argument
22921 #define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDAT…  argument
22922 #define SPI_BRD_TXFR2_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXDATA_SHIFT, SPI_TX…  argument
22934 #define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI…  argument
22935 #define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXCMD_TXDATA_S…  argument
22957 #define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))  argument
22971 #define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDAT…  argument
22972 #define SPI_BRD_TXFR3_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXDATA_SHIFT, SPI_TX…  argument
22984 #define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI…  argument
22985 #define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXCMD_TXDATA_S…  argument
23007 #define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))  argument
23029 #define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))  argument
23051 #define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))  argument
23073 #define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))  argument
23116 #define TPM_RD_SC(base)          (TPM_SC_REG(base))  argument
23117 #define TPM_WR_SC(base, value)   (TPM_SC_REG(base) = (value))  argument
23118 #define TPM_RMW_SC(base, mask, value) (TPM_WR_SC(base, (TPM_RD_SC(base) & ~(mask)) | (value)))  argument
23119 #define TPM_SET_SC(base, value)  (BME_OR32(&TPM_SC_REG(base), (uint32_t)(value)))  argument
23120 #define TPM_CLR_SC(base, value)  (BME_AND32(&TPM_SC_REG(base), (uint32_t)(~(value))))  argument
23121 #define TPM_TOG_SC(base, value)  (BME_XOR32(&TPM_SC_REG(base), (uint32_t)(value)))  argument
23146 #define TPM_RD_SC_PS(base)   ((TPM_SC_REG(base) & TPM_SC_PS_MASK) >> TPM_SC_PS_SHIFT)  argument
23147 #define TPM_BRD_SC_PS(base)  (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))  argument
23150 #define TPM_WR_SC_PS(base, value) (TPM_RMW_SC(base, (TPM_SC_PS_MASK | TPM_SC_TOF_MASK), TPM_SC_PS(v…  argument
23151 #define TPM_BWR_SC_PS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_PS_SH…  argument
23169 #define TPM_RD_SC_CMOD(base) ((TPM_SC_REG(base) & TPM_SC_CMOD_MASK) >> TPM_SC_CMOD_SHIFT)  argument
23170 #define TPM_BRD_SC_CMOD(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))  argument
23173 #define TPM_WR_SC_CMOD(base, value) (TPM_RMW_SC(base, (TPM_SC_CMOD_MASK | TPM_SC_TOF_MASK), TPM_SC_…  argument
23174 #define TPM_BWR_SC_CMOD(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CMO…  argument
23190 #define TPM_RD_SC_CPWMS(base) ((TPM_SC_REG(base) & TPM_SC_CPWMS_MASK) >> TPM_SC_CPWMS_SHIFT)  argument
23191 #define TPM_BRD_SC_CPWMS(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDT…  argument
23194 #define TPM_WR_SC_CPWMS(base, value) (TPM_RMW_SC(base, (TPM_SC_CPWMS_MASK | TPM_SC_TOF_MASK), TPM_S…  argument
23195 #define TPM_BWR_SC_CPWMS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CP…  argument
23209 #define TPM_RD_SC_TOIE(base) ((TPM_SC_REG(base) & TPM_SC_TOIE_MASK) >> TPM_SC_TOIE_SHIFT)  argument
23210 #define TPM_BRD_SC_TOIE(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))  argument
23213 #define TPM_WR_SC_TOIE(base, value) (TPM_RMW_SC(base, (TPM_SC_TOIE_MASK | TPM_SC_TOF_MASK), TPM_SC_…  argument
23214 #define TPM_BWR_SC_TOIE(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOI…  argument
23233 #define TPM_RD_SC_TOF(base)  ((TPM_SC_REG(base) & TPM_SC_TOF_MASK) >> TPM_SC_TOF_SHIFT)  argument
23234 #define TPM_BRD_SC_TOF(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))  argument
23237 #define TPM_WR_SC_TOF(base, value) (TPM_RMW_SC(base, TPM_SC_TOF_MASK, TPM_SC_TOF(value)))  argument
23238 #define TPM_BWR_SC_TOF(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOF_…  argument
23252 #define TPM_RD_SC_DMA(base)  ((TPM_SC_REG(base) & TPM_SC_DMA_MASK) >> TPM_SC_DMA_SHIFT)  argument
23253 #define TPM_BRD_SC_DMA(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))  argument
23256 #define TPM_WR_SC_DMA(base, value) (TPM_RMW_SC(base, (TPM_SC_DMA_MASK | TPM_SC_TOF_MASK), TPM_SC_DM…  argument
23257 #define TPM_BWR_SC_DMA(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_DMA_…  argument
23279 #define TPM_RD_CNT(base)         (TPM_CNT_REG(base))  argument
23280 #define TPM_WR_CNT(base, value)  (TPM_CNT_REG(base) = (value))  argument
23281 #define TPM_RMW_CNT(base, mask, value) (TPM_WR_CNT(base, (TPM_RD_CNT(base) & ~(mask)) | (value)))  argument
23282 #define TPM_SET_CNT(base, value) (BME_OR32(&TPM_CNT_REG(base), (uint32_t)(value)))  argument
23283 #define TPM_CLR_CNT(base, value) (BME_AND32(&TPM_CNT_REG(base), (uint32_t)(~(value))))  argument
23284 #define TPM_TOG_CNT(base, value) (BME_XOR32(&TPM_CNT_REG(base), (uint32_t)(value)))  argument
23296 #define TPM_RD_CNT_COUNT(base) ((TPM_CNT_REG(base) & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT)  argument
23297 #define TPM_BRD_CNT_COUNT(base) (BME_UBFX32(&TPM_CNT_REG(base), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_…  argument
23300 #define TPM_WR_CNT_COUNT(base, value) (TPM_RMW_CNT(base, TPM_CNT_COUNT_MASK, TPM_CNT_COUNT(value)))  argument
23301 #define TPM_BWR_CNT_COUNT(base, value) (BME_BFI32(&TPM_CNT_REG(base), ((uint32_t)(value) << TPM_CNT…  argument
23328 #define TPM_RD_MOD(base)         (TPM_MOD_REG(base))  argument
23329 #define TPM_WR_MOD(base, value)  (TPM_MOD_REG(base) = (value))  argument
23330 #define TPM_RMW_MOD(base, mask, value) (TPM_WR_MOD(base, (TPM_RD_MOD(base) & ~(mask)) | (value)))  argument
23331 #define TPM_SET_MOD(base, value) (BME_OR32(&TPM_MOD_REG(base), (uint32_t)(value)))  argument
23332 #define TPM_CLR_MOD(base, value) (BME_AND32(&TPM_MOD_REG(base), (uint32_t)(~(value))))  argument
23333 #define TPM_TOG_MOD(base, value) (BME_XOR32(&TPM_MOD_REG(base), (uint32_t)(value)))  argument
23347 #define TPM_RD_MOD_MOD(base) ((TPM_MOD_REG(base) & TPM_MOD_MOD_MASK) >> TPM_MOD_MOD_SHIFT)  argument
23348 #define TPM_BRD_MOD_MOD(base) (BME_UBFX32(&TPM_MOD_REG(base), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))  argument
23351 #define TPM_WR_MOD_MOD(base, value) (TPM_RMW_MOD(base, TPM_MOD_MOD_MASK, TPM_MOD_MOD(value)))  argument
23352 #define TPM_BWR_MOD_MOD(base, value) (BME_BFI32(&TPM_MOD_REG(base), ((uint32_t)(value) << TPM_MOD_M…  argument
23383 #define TPM_RD_CnSC(base, index) (TPM_CnSC_REG(base, index))  argument
23384 #define TPM_WR_CnSC(base, index, value) (TPM_CnSC_REG(base, index) = (value))  argument
23385 #define TPM_RMW_CnSC(base, index, mask, value) (TPM_WR_CnSC(base, index, (TPM_RD_CnSC(base, index) …  argument
23386 #define TPM_SET_CnSC(base, index, value) (BME_OR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))  argument
23387 #define TPM_CLR_CnSC(base, index, value) (BME_AND32(&TPM_CnSC_REG(base, index), (uint32_t)(~(value)…  argument
23388 #define TPM_TOG_CnSC(base, index, value) (BME_XOR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))  argument
23406 #define TPM_RD_CnSC_DMA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_DMA_MASK) >> TPM_CnSC_D…  argument
23407 #define TPM_BRD_CnSC_DMA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_DMA_SHIFT, T…  argument
23410 #define TPM_WR_CnSC_DMA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_DMA_MASK | TPM_CnS…  argument
23411 #define TPM_BWR_CnSC_DMA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23423 #define TPM_RD_CnSC_ELSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSA_MASK) >> TPM_CnSC…  argument
23424 #define TPM_BRD_CnSC_ELSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSA_SHIFT,…  argument
23427 #define TPM_WR_CnSC_ELSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSA_MASK | TPM_C…  argument
23428 #define TPM_BWR_CnSC_ELSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23440 #define TPM_RD_CnSC_ELSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSB_MASK) >> TPM_CnSC…  argument
23441 #define TPM_BRD_CnSC_ELSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSB_SHIFT,…  argument
23444 #define TPM_WR_CnSC_ELSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSB_MASK | TPM_C…  argument
23445 #define TPM_BWR_CnSC_ELSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23457 #define TPM_RD_CnSC_MSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSA_MASK) >> TPM_CnSC_M…  argument
23458 #define TPM_BRD_CnSC_MSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSA_SHIFT, T…  argument
23461 #define TPM_WR_CnSC_MSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSA_MASK | TPM_CnS…  argument
23462 #define TPM_BWR_CnSC_MSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23474 #define TPM_RD_CnSC_MSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSB_MASK) >> TPM_CnSC_M…  argument
23475 #define TPM_BRD_CnSC_MSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSB_SHIFT, T…  argument
23478 #define TPM_WR_CnSC_MSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSB_MASK | TPM_CnS…  argument
23479 #define TPM_BWR_CnSC_MSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23493 #define TPM_RD_CnSC_CHIE(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHIE_MASK) >> TPM_CnSC…  argument
23494 #define TPM_BRD_CnSC_CHIE(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHIE_SHIFT,…  argument
23497 #define TPM_WR_CnSC_CHIE(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_CHIE_MASK | TPM_C…  argument
23498 #define TPM_BWR_CnSC_CHIE(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(va…  argument
23517 #define TPM_RD_CnSC_CHF(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHF_MASK) >> TPM_CnSC_C…  argument
23518 #define TPM_BRD_CnSC_CHF(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHF_SHIFT, T…  argument
23521 #define TPM_WR_CnSC_CHF(base, index, value) (TPM_RMW_CnSC(base, index, TPM_CnSC_CHF_MASK, TPM_CnSC_…  argument
23522 #define TPM_BWR_CnSC_CHF(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(val…  argument
23545 #define TPM_RD_CnV(base, index)  (TPM_CnV_REG(base, index))  argument
23546 #define TPM_WR_CnV(base, index, value) (TPM_CnV_REG(base, index) = (value))  argument
23547 #define TPM_RMW_CnV(base, index, mask, value) (TPM_WR_CnV(base, index, (TPM_RD_CnV(base, index) & ~…  argument
23548 #define TPM_SET_CnV(base, index, value) (BME_OR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))  argument
23549 #define TPM_CLR_CnV(base, index, value) (BME_AND32(&TPM_CnV_REG(base, index), (uint32_t)(~(value))))  argument
23550 #define TPM_TOG_CnV(base, index, value) (BME_XOR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))  argument
23565 #define TPM_RD_CnV_VAL(base, index) ((TPM_CnV_REG(base, index) & TPM_CnV_VAL_MASK) >> TPM_CnV_VAL_S…  argument
23566 #define TPM_BRD_CnV_VAL(base, index) (BME_UBFX32(&TPM_CnV_REG(base, index), TPM_CnV_VAL_SHIFT, TPM_…  argument
23569 #define TPM_WR_CnV_VAL(base, index, value) (TPM_RMW_CnV(base, index, TPM_CnV_VAL_MASK, TPM_CnV_VAL(…  argument
23570 #define TPM_BWR_CnV_VAL(base, index, value) (BME_BFI32(&TPM_CnV_REG(base, index), ((uint32_t)(value…  argument
23597 #define TPM_RD_STATUS(base)      (TPM_STATUS_REG(base))  argument
23598 #define TPM_WR_STATUS(base, value) (TPM_STATUS_REG(base) = (value))  argument
23599 #define TPM_RMW_STATUS(base, mask, value) (TPM_WR_STATUS(base, (TPM_RD_STATUS(base) & ~(mask)) | (v…  argument
23600 #define TPM_SET_STATUS(base, value) (BME_OR32(&TPM_STATUS_REG(base), (uint32_t)(value)))  argument
23601 #define TPM_CLR_STATUS(base, value) (BME_AND32(&TPM_STATUS_REG(base), (uint32_t)(~(value))))  argument
23602 #define TPM_TOG_STATUS(base, value) (BME_XOR32(&TPM_STATUS_REG(base), (uint32_t)(value)))  argument
23620 #define TPM_RD_STATUS_CH0F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH0F_MASK) >> TPM_STATUS_CH0F_…  argument
23621 #define TPM_BRD_STATUS_CH0F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH0F_SHIFT, TPM_STA…  argument
23624 #define TPM_WR_STATUS_CH0F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH0F_MASK | TPM_STATUS_CH…  argument
23625 #define TPM_BWR_STATUS_CH0F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…  argument
23639 #define TPM_RD_STATUS_CH1F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH1F_MASK) >> TPM_STATUS_CH1F_…  argument
23640 #define TPM_BRD_STATUS_CH1F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH1F_SHIFT, TPM_STA…  argument
23643 #define TPM_WR_STATUS_CH1F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH1F_MASK | TPM_STATUS_CH…  argument
23644 #define TPM_BWR_STATUS_CH1F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…  argument
23658 #define TPM_RD_STATUS_CH2F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH2F_MASK) >> TPM_STATUS_CH2F_…  argument
23659 #define TPM_BRD_STATUS_CH2F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH2F_SHIFT, TPM_STA…  argument
23662 #define TPM_WR_STATUS_CH2F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH2F_MASK | TPM_STATUS_CH…  argument
23663 #define TPM_BWR_STATUS_CH2F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…  argument
23677 #define TPM_RD_STATUS_CH3F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH3F_MASK) >> TPM_STATUS_CH3F_…  argument
23678 #define TPM_BRD_STATUS_CH3F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH3F_SHIFT, TPM_STA…  argument
23681 #define TPM_WR_STATUS_CH3F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH3F_MASK | TPM_STATUS_CH…  argument
23682 #define TPM_BWR_STATUS_CH3F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TP…  argument
23696 #define TPM_RD_STATUS_TOF(base) ((TPM_STATUS_REG(base) & TPM_STATUS_TOF_MASK) >> TPM_STATUS_TOF_SHI…  argument
23697 #define TPM_BRD_STATUS_TOF(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_TOF_SHIFT, TPM_STATU…  argument
23700 #define TPM_WR_STATUS_TOF(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_TOF_MASK | TPM_STATUS_CH0F…  argument
23701 #define TPM_BWR_STATUS_TOF(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM…  argument
23721 #define TPM_RD_COMBINE(base)     (TPM_COMBINE_REG(base))  argument
23722 #define TPM_WR_COMBINE(base, value) (TPM_COMBINE_REG(base) = (value))  argument
23723 #define TPM_RMW_COMBINE(base, mask, value) (TPM_WR_COMBINE(base, (TPM_RD_COMBINE(base) & ~(mask)) |…  argument
23724 #define TPM_SET_COMBINE(base, value) (BME_OR32(&TPM_COMBINE_REG(base), (uint32_t)(value)))  argument
23725 #define TPM_CLR_COMBINE(base, value) (BME_AND32(&TPM_COMBINE_REG(base), (uint32_t)(~(value))))  argument
23726 #define TPM_TOG_COMBINE(base, value) (BME_XOR32(&TPM_COMBINE_REG(base), (uint32_t)(value)))  argument
23748 #define TPM_RD_COMBINE_COMBINE0(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMBINE0_MASK) >> TPM_C…  argument
23749 #define TPM_BRD_COMBINE_COMBINE0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE0_SHI…  argument
23752 #define TPM_WR_COMBINE_COMBINE0(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMBINE0_MASK, TPM_…  argument
23753 #define TPM_BWR_COMBINE_COMBINE0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…  argument
23768 #define TPM_RD_COMBINE_COMSWAP0(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMSWAP0_MASK) >> TPM_C…  argument
23769 #define TPM_BRD_COMBINE_COMSWAP0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP0_SHI…  argument
23772 #define TPM_WR_COMBINE_COMSWAP0(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMSWAP0_MASK, TPM_…  argument
23773 #define TPM_BWR_COMBINE_COMSWAP0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…  argument
23791 #define TPM_RD_COMBINE_COMBINE1(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMBINE1_MASK) >> TPM_C…  argument
23792 #define TPM_BRD_COMBINE_COMBINE1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE1_SHI…  argument
23795 #define TPM_WR_COMBINE_COMBINE1(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMBINE1_MASK, TPM_…  argument
23796 #define TPM_BWR_COMBINE_COMBINE1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…  argument
23811 #define TPM_RD_COMBINE_COMSWAP1(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMSWAP1_MASK) >> TPM_C…  argument
23812 #define TPM_BRD_COMBINE_COMSWAP1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP1_SHI…  argument
23815 #define TPM_WR_COMBINE_COMSWAP1(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMSWAP1_MASK, TPM_…  argument
23816 #define TPM_BWR_COMBINE_COMSWAP1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value)…  argument
23836 #define TPM_RD_FILTER(base)      (TPM_FILTER_REG(base))  argument
23837 #define TPM_WR_FILTER(base, value) (TPM_FILTER_REG(base) = (value))  argument
23838 #define TPM_RMW_FILTER(base, mask, value) (TPM_WR_FILTER(base, (TPM_RD_FILTER(base) & ~(mask)) | (v…  argument
23839 #define TPM_SET_FILTER(base, value) (BME_OR32(&TPM_FILTER_REG(base), (uint32_t)(value)))  argument
23840 #define TPM_CLR_FILTER(base, value) (BME_AND32(&TPM_FILTER_REG(base), (uint32_t)(~(value))))  argument
23841 #define TPM_TOG_FILTER(base, value) (BME_XOR32(&TPM_FILTER_REG(base), (uint32_t)(value)))  argument
23857 #define TPM_RD_FILTER_CH0FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH0FVAL_MASK) >> TPM_FILTER…  argument
23858 #define TPM_BRD_FILTER_CH0FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH0FVAL_SHIFT, T…  argument
23861 #define TPM_WR_FILTER_CH0FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH0FVAL_MASK, TPM_FILTE…  argument
23862 #define TPM_BWR_FILTER_CH0FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…  argument
23874 #define TPM_RD_FILTER_CH1FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH1FVAL_MASK) >> TPM_FILTER…  argument
23875 #define TPM_BRD_FILTER_CH1FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH1FVAL_SHIFT, T…  argument
23878 #define TPM_WR_FILTER_CH1FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH1FVAL_MASK, TPM_FILTE…  argument
23879 #define TPM_BWR_FILTER_CH1FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…  argument
23891 #define TPM_RD_FILTER_CH2FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH2FVAL_MASK) >> TPM_FILTER…  argument
23892 #define TPM_BRD_FILTER_CH2FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH2FVAL_SHIFT, T…  argument
23895 #define TPM_WR_FILTER_CH2FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH2FVAL_MASK, TPM_FILTE…  argument
23896 #define TPM_BWR_FILTER_CH2FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…  argument
23908 #define TPM_RD_FILTER_CH3FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH3FVAL_MASK) >> TPM_FILTER…  argument
23909 #define TPM_BRD_FILTER_CH3FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH3FVAL_SHIFT, T…  argument
23912 #define TPM_WR_FILTER_CH3FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH3FVAL_MASK, TPM_FILTE…  argument
23913 #define TPM_BWR_FILTER_CH3FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) <<…  argument
23931 #define TPM_RD_QDCTRL(base)      (TPM_QDCTRL_REG(base))  argument
23932 #define TPM_WR_QDCTRL(base, value) (TPM_QDCTRL_REG(base) = (value))  argument
23933 #define TPM_RMW_QDCTRL(base, mask, value) (TPM_WR_QDCTRL(base, (TPM_RD_QDCTRL(base) & ~(mask)) | (v…  argument
23934 #define TPM_SET_QDCTRL(base, value) (BME_OR32(&TPM_QDCTRL_REG(base), (uint32_t)(value)))  argument
23935 #define TPM_CLR_QDCTRL(base, value) (BME_AND32(&TPM_QDCTRL_REG(base), (uint32_t)(~(value))))  argument
23936 #define TPM_TOG_QDCTRL(base, value) (BME_XOR32(&TPM_QDCTRL_REG(base), (uint32_t)(value)))  argument
23956 #define TPM_RD_QDCTRL_QUADEN(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADEN_MASK) >> TPM_QDCTRL_Q…  argument
23957 #define TPM_BRD_QDCTRL_QUADEN(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADEN_SHIFT, TPM…  argument
23960 #define TPM_WR_QDCTRL_QUADEN(base, value) (TPM_RMW_QDCTRL(base, TPM_QDCTRL_QUADEN_MASK, TPM_QDCTRL_…  argument
23961 #define TPM_BWR_QDCTRL_QUADEN(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) << …  argument
23979 #define TPM_RD_QDCTRL_TOFDIR(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_TOFDIR_MASK) >> TPM_QDCTRL_T…  argument
23980 #define TPM_BRD_QDCTRL_TOFDIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_TOFDIR_SHIFT, TPM…  argument
23994 #define TPM_RD_QDCTRL_QUADIR(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADIR_MASK) >> TPM_QDCTRL_Q…  argument
23995 #define TPM_BRD_QDCTRL_QUADIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADIR_SHIFT, TPM…  argument
24009 #define TPM_RD_QDCTRL_QUADMODE(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADMODE_MASK) >> TPM_QDCT…  argument
24010 #define TPM_BRD_QDCTRL_QUADMODE(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADMODE_SHIFT,…  argument
24013 #define TPM_WR_QDCTRL_QUADMODE(base, value) (TPM_RMW_QDCTRL(base, TPM_QDCTRL_QUADMODE_MASK, TPM_QDC…  argument
24014 #define TPM_BWR_QDCTRL_QUADMODE(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) <…  argument
24033 #define TPM_RD_CONF(base)        (TPM_CONF_REG(base))  argument
24034 #define TPM_WR_CONF(base, value) (TPM_CONF_REG(base) = (value))  argument
24035 #define TPM_RMW_CONF(base, mask, value) (TPM_WR_CONF(base, (TPM_RD_CONF(base) & ~(mask)) | (value)))  argument
24036 #define TPM_SET_CONF(base, value) (BME_OR32(&TPM_CONF_REG(base), (uint32_t)(value)))  argument
24037 #define TPM_CLR_CONF(base, value) (BME_AND32(&TPM_CONF_REG(base), (uint32_t)(~(value))))  argument
24038 #define TPM_TOG_CONF(base, value) (BME_XOR32(&TPM_CONF_REG(base), (uint32_t)(value)))  argument
24057 #define TPM_RD_CONF_DOZEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_DOZEEN_MASK) >> TPM_CONF_DOZEEN_SH…  argument
24058 #define TPM_BRD_CONF_DOZEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_…  argument
24061 #define TPM_WR_CONF_DOZEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_DOZEEN_MASK, TPM_CONF_DOZEEN(v…  argument
24062 #define TPM_BWR_CONF_DOZEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…  argument
24078 #define TPM_RD_CONF_DBGMODE(base) ((TPM_CONF_REG(base) & TPM_CONF_DBGMODE_MASK) >> TPM_CONF_DBGMODE…  argument
24079 #define TPM_BRD_CONF_DBGMODE(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DBGMODE_SHIFT, TPM_CON…  argument
24082 #define TPM_WR_CONF_DBGMODE(base, value) (TPM_RMW_CONF(base, TPM_CONF_DBGMODE_MASK, TPM_CONF_DBGMOD…  argument
24083 #define TPM_BWR_CONF_DBGMODE(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM…  argument
24102 #define TPM_RD_CONF_GTBEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_GTBEEN_MASK) >> TPM_CONF_GTBEEN_SH…  argument
24103 #define TPM_BRD_CONF_GTBEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_…  argument
24106 #define TPM_WR_CONF_GTBEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_GTBEEN_MASK, TPM_CONF_GTBEEN(v…  argument
24107 #define TPM_BWR_CONF_GTBEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…  argument
24128 #define TPM_RD_CONF_CSOT(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOT_MASK) >> TPM_CONF_CSOT_SHIFT)  argument
24129 #define TPM_BRD_CONF_CSOT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT…  argument
24132 #define TPM_WR_CONF_CSOT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOT_MASK, TPM_CONF_CSOT(value)))  argument
24133 #define TPM_BWR_CONF_CSOT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…  argument
24153 #define TPM_RD_CONF_CSOO(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOO_MASK) >> TPM_CONF_CSOO_SHIFT)  argument
24154 #define TPM_BRD_CONF_CSOO(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO…  argument
24157 #define TPM_WR_CONF_CSOO(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOO_MASK, TPM_CONF_CSOO(value)))  argument
24158 #define TPM_BWR_CONF_CSOO(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…  argument
24178 #define TPM_RD_CONF_CROT(base) ((TPM_CONF_REG(base) & TPM_CONF_CROT_MASK) >> TPM_CONF_CROT_SHIFT)  argument
24179 #define TPM_BRD_CONF_CROT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT…  argument
24182 #define TPM_WR_CONF_CROT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CROT_MASK, TPM_CONF_CROT(value)))  argument
24183 #define TPM_BWR_CONF_CROT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CO…  argument
24195 #define TPM_RD_CONF_TRGSEL(base) ((TPM_CONF_REG(base) & TPM_CONF_TRGSEL_MASK) >> TPM_CONF_TRGSEL_SH…  argument
24196 #define TPM_BRD_CONF_TRGSEL(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_…  argument
24199 #define TPM_WR_CONF_TRGSEL(base, value) (TPM_RMW_CONF(base, TPM_CONF_TRGSEL_MASK, TPM_CONF_TRGSEL(v…  argument
24200 #define TPM_BWR_CONF_TRGSEL(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_…  argument
24278 #define TRNG_RD_MCTL(base)       (TRNG_MCTL_REG(base))  argument
24279 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))  argument
24280 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (valu…  argument
24281 #define TRNG_SET_MCTL(base, value) (BME_OR32(&TRNG_MCTL_REG(base), (uint32_t)(value)))  argument
24282 #define TRNG_CLR_MCTL(base, value) (BME_AND32(&TRNG_MCTL_REG(base), (uint32_t)(~(value))))  argument
24283 #define TRNG_TOG_MCTL(base, value) (BME_XOR32(&TRNG_MCTL_REG(base), (uint32_t)(value)))  argument
24308 #define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL…  argument
24309 #define TRNG_BRD_MCTL_SAMP_MODE(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_SAMP_MODE_SHIFT, …  argument
24312 #define TRNG_WR_MCTL_SAMP_MODE(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_M…  argument
24313 #define TRNG_BWR_MCTL_SAMP_MODE(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) <<…  argument
24332 #define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC…  argument
24333 #define TRNG_BRD_MCTL_OSC_DIV(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_OSC_DIV_SHIFT, TRNG…  argument
24336 #define TRNG_WR_MCTL_OSC_DIV(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_…  argument
24337 #define TRNG_BWR_MCTL_OSC_DIV(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << T…  argument
24347 #define TRNG_RD_MCTL_UNUSED(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_UNUSED_MASK) >> TRNG_MCTL_UNUSE…  argument
24348 #define TRNG_BRD_MCTL_UNUSED(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_UNUSED_SHIFT, TRNG_M…  argument
24351 #define TRNG_WR_MCTL_UNUSED(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_UNUSED_MASK | TRNG_MCTL_ER…  argument
24352 #define TRNG_BWR_MCTL_UNUSED(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TR…  argument
24365 #define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_T…  argument
24366 #define TRNG_BRD_MCTL_TRNG_ACC(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TRNG_ACC_SHIFT, TR…  argument
24369 #define TRNG_WR_MCTL_TRNG_ACC(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCT…  argument
24370 #define TRNG_BWR_MCTL_TRNG_ACC(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << …  argument
24383 #define TRNG_WR_MCTL_RST_DEF(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_…  argument
24384 #define TRNG_BWR_MCTL_RST_DEF(base, value) (TRNG_WR_MCTL_RST_DEF(base, value))  argument
24398 #define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_F…  argument
24399 #define TRNG_BRD_MCTL_FOR_SCLK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FOR_SCLK_SHIFT, TR…  argument
24402 #define TRNG_WR_MCTL_FOR_SCLK(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCT…  argument
24403 #define TRNG_BWR_MCTL_FOR_SCLK(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << …  argument
24416 #define TRNG_RD_MCTL_FCT_FAIL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FCT_FAIL_MASK) >> TRNG_MCTL_F…  argument
24417 #define TRNG_BRD_MCTL_FCT_FAIL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_FAIL_SHIFT, TR…  argument
24428 #define TRNG_RD_MCTL_FCT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FCT_VAL_MASK) >> TRNG_MCTL_FCT…  argument
24429 #define TRNG_BRD_MCTL_FCT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_VAL_SHIFT, TRNG…  argument
24441 #define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT…  argument
24442 #define TRNG_BRD_MCTL_ENT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ENT_VAL_SHIFT, TRNG…  argument
24452 #define TRNG_RD_MCTL_TST_OUT(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TST_OUT_MASK) >> TRNG_MCTL_TST…  argument
24453 #define TRNG_BRD_MCTL_TST_OUT(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TST_OUT_SHIFT, TRNG…  argument
24464 #define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)  argument
24465 #define TRNG_BRD_MCTL_ERR(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ERR_SHIFT, TRNG_MCTL_ER…  argument
24468 #define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)…  argument
24469 #define TRNG_BWR_MCTL_ERR(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_…  argument
24485 #define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_T…  argument
24486 #define TRNG_BRD_MCTL_TSTOP_OK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TSTOP_OK_SHIFT, TR…  argument
24500 #define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIF…  argument
24501 #define TRNG_BRD_MCTL_PRGM(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_PRGM_SHIFT, TRNG_MCTL_…  argument
24504 #define TRNG_WR_MCTL_PRGM(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MA…  argument
24505 #define TRNG_BWR_MCTL_PRGM(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG…  argument
24526 #define TRNG_RD_SCMISC(base)     (TRNG_SCMISC_REG(base))  argument
24527 #define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))  argument
24528 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) |…  argument
24529 #define TRNG_SET_SCMISC(base, value) (BME_OR32(&TRNG_SCMISC_REG(base), (uint32_t)(value)))  argument
24530 #define TRNG_CLR_SCMISC(base, value) (BME_AND32(&TRNG_SCMISC_REG(base), (uint32_t)(~(value))))  argument
24531 #define TRNG_TOG_SCMISC(base, value) (BME_XOR32(&TRNG_SCMISC_REG(base), (uint32_t)(value)))  argument
24549 #define TRNG_RD_SCMISC_LRUN_MAX(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_…  argument
24550 #define TRNG_BRD_SCMISC_LRUN_MAX(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_LRUN_MAX_SHI…  argument
24553 #define TRNG_WR_SCMISC_LRUN_MAX(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG…  argument
24554 #define TRNG_BWR_SCMISC_LRUN_MAX(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value)…  argument
24568 #define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMI…  argument
24569 #define TRNG_BRD_SCMISC_RTY_CT(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_RTY_CT_SHIFT, …  argument
24572 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCM…  argument
24573 #define TRNG_BWR_SCMISC_RTY_CT(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value) <…  argument
24593 #define TRNG_RD_PKRRNG(base)     (TRNG_PKRRNG_REG(base))  argument
24594 #define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))  argument
24595 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) |…  argument
24596 #define TRNG_SET_PKRRNG(base, value) (BME_OR32(&TRNG_PKRRNG_REG(base), (uint32_t)(value)))  argument
24597 #define TRNG_CLR_PKRRNG(base, value) (BME_AND32(&TRNG_PKRRNG_REG(base), (uint32_t)(~(value))))  argument
24598 #define TRNG_TOG_PKRRNG(base, value) (BME_XOR32(&TRNG_PKRRNG_REG(base), (uint32_t)(value)))  argument
24618 #define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PK…  argument
24619 #define TRNG_BRD_PKRRNG_PKR_RNG(base) (BME_UBFX32(&TRNG_PKRRNG_REG(base), TRNG_PKRRNG_PKR_RNG_SHIFT…  argument
24622 #define TRNG_WR_PKRRNG_PKR_RNG(base, value) (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_P…  argument
24623 #define TRNG_BWR_PKRRNG_PKR_RNG(base, value) (BME_BFI32(&TRNG_PKRRNG_REG(base), ((uint32_t)(value) …  argument
24644 #define TRNG_RD_PKRMAX(base)     (TRNG_PKRMAX_REG(base))  argument
24645 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))  argument
24646 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) |…  argument
24647 #define TRNG_SET_PKRMAX(base, value) (BME_OR32(&TRNG_PKRMAX_REG(base), (uint32_t)(value)))  argument
24648 #define TRNG_CLR_PKRMAX(base, value) (BME_AND32(&TRNG_PKRMAX_REG(base), (uint32_t)(~(value))))  argument
24649 #define TRNG_TOG_PKRMAX(base, value) (BME_XOR32(&TRNG_PKRMAX_REG(base), (uint32_t)(value)))  argument
24671 #define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PK…  argument
24672 #define TRNG_BRD_PKRMAX_PKR_MAX(base) (TRNG_RD_PKRMAX_PKR_MAX(base))  argument
24675 #define TRNG_WR_PKRMAX_PKR_MAX(base, value) (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_P…  argument
24676 #define TRNG_BWR_PKRMAX_PKR_MAX(base, value) (TRNG_WR_PKRMAX_PKR_MAX(base, value))  argument
24700 #define TRNG_RD_PKRSQ(base)      (TRNG_PKRSQ_REG(base))  argument
24720 #define TRNG_RD_PKRSQ_PKR_SQ(base) ((TRNG_PKRSQ_REG(base) & TRNG_PKRSQ_PKR_SQ_MASK) >> TRNG_PKRSQ_P…  argument
24721 #define TRNG_BRD_PKRSQ_PKR_SQ(base) (TRNG_RD_PKRSQ_PKR_SQ(base))  argument
24742 #define TRNG_RD_SDCTL(base)      (TRNG_SDCTL_REG(base))  argument
24743 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))  argument
24744 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (v…  argument
24745 #define TRNG_SET_SDCTL(base, value) (BME_OR32(&TRNG_SDCTL_REG(base), (uint32_t)(value)))  argument
24746 #define TRNG_CLR_SDCTL(base, value) (BME_AND32(&TRNG_SDCTL_REG(base), (uint32_t)(~(value))))  argument
24747 #define TRNG_TOG_SDCTL(base, value) (BME_XOR32(&TRNG_SDCTL_REG(base), (uint32_t)(value)))  argument
24764 #define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_S…  argument
24765 #define TRNG_BRD_SDCTL_SAMP_SIZE(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_SAMP_SIZE_SHIF…  argument
24768 #define TRNG_WR_SDCTL_SAMP_SIZE(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_…  argument
24769 #define TRNG_BWR_SDCTL_SAMP_SIZE(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) …  argument
24782 #define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL…  argument
24783 #define TRNG_BRD_SDCTL_ENT_DLY(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_ENT_DLY_SHIFT, T…  argument
24786 #define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCT…  argument
24787 #define TRNG_BWR_SDCTL_ENT_DLY(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) <<…  argument
24809 #define TRNG_RD_SBLIM(base)      (TRNG_SBLIM_REG(base))  argument
24810 #define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))  argument
24811 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (v…  argument
24812 #define TRNG_SET_SBLIM(base, value) (BME_OR32(&TRNG_SBLIM_REG(base), (uint32_t)(value)))  argument
24813 #define TRNG_CLR_SBLIM(base, value) (BME_AND32(&TRNG_SBLIM_REG(base), (uint32_t)(~(value))))  argument
24814 #define TRNG_TOG_SBLIM(base, value) (BME_XOR32(&TRNG_SBLIM_REG(base), (uint32_t)(value)))  argument
24836 #define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_S…  argument
24837 #define TRNG_BRD_SBLIM_SB_LIM(base) (BME_UBFX32(&TRNG_SBLIM_REG(base), TRNG_SBLIM_SB_LIM_SHIFT, TRN…  argument
24840 #define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_…  argument
24841 #define TRNG_BWR_SBLIM_SB_LIM(base, value) (BME_BFI32(&TRNG_SBLIM_REG(base), ((uint32_t)(value) << …  argument
24863 #define TRNG_RD_TOTSAM(base)     (TRNG_TOTSAM_REG(base))  argument
24882 #define TRNG_RD_TOTSAM_TOT_SAM(base) ((TRNG_TOTSAM_REG(base) & TRNG_TOTSAM_TOT_SAM_MASK) >> TRNG_TO…  argument
24883 #define TRNG_BRD_TOTSAM_TOT_SAM(base) (TRNG_RD_TOTSAM_TOT_SAM(base))  argument
24904 #define TRNG_RD_FRQMIN(base)     (TRNG_FRQMIN_REG(base))  argument
24905 #define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))  argument
24906 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) |…  argument
24907 #define TRNG_SET_FRQMIN(base, value) (BME_OR32(&TRNG_FRQMIN_REG(base), (uint32_t)(value)))  argument
24908 #define TRNG_CLR_FRQMIN(base, value) (BME_AND32(&TRNG_FRQMIN_REG(base), (uint32_t)(~(value))))  argument
24909 #define TRNG_TOG_FRQMIN(base, value) (BME_XOR32(&TRNG_FRQMIN_REG(base), (uint32_t)(value)))  argument
24926 #define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FR…  argument
24927 #define TRNG_BRD_FRQMIN_FRQ_MIN(base) (TRNG_RD_FRQMIN_FRQ_MIN(base))  argument
24930 #define TRNG_WR_FRQMIN_FRQ_MIN(base, value) (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_F…  argument
24931 #define TRNG_BWR_FRQMIN_FRQ_MIN(base, value) (TRNG_WR_FRQMIN_FRQ_MIN(base, value))  argument
24954 #define TRNG_RD_FRQMAX(base)     (TRNG_FRQMAX_REG(base))  argument
24955 #define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))  argument
24956 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) |…  argument
24957 #define TRNG_SET_FRQMAX(base, value) (BME_OR32(&TRNG_FRQMAX_REG(base), (uint32_t)(value)))  argument
24958 #define TRNG_CLR_FRQMAX(base, value) (BME_AND32(&TRNG_FRQMAX_REG(base), (uint32_t)(~(value))))  argument
24959 #define TRNG_TOG_FRQMAX(base, value) (BME_XOR32(&TRNG_FRQMAX_REG(base), (uint32_t)(value)))  argument
24977 #define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FR…  argument
24978 #define TRNG_BRD_FRQMAX_FRQ_MAX(base) (TRNG_RD_FRQMAX_FRQ_MAX(base))  argument
24981 #define TRNG_WR_FRQMAX_FRQ_MAX(base, value) (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_F…  argument
24982 #define TRNG_BWR_FRQMAX_FRQ_MAX(base, value) (TRNG_WR_FRQMAX_FRQ_MAX(base, value))  argument
25004 #define TRNG_RD_FRQCNT(base)     (TRNG_FRQCNT_REG(base))  argument
25021 #define TRNG_RD_FRQCNT_FRQ_CT(base) ((TRNG_FRQCNT_REG(base) & TRNG_FRQCNT_FRQ_CT_MASK) >> TRNG_FRQC…  argument
25022 #define TRNG_BRD_FRQCNT_FRQ_CT(base) (TRNG_RD_FRQCNT_FRQ_CT(base))  argument
25045 #define TRNG_RD_SCMC(base)       (TRNG_SCMC_REG(base))  argument
25062 #define TRNG_RD_SCMC_MONO_CT(base) ((TRNG_SCMC_REG(base) & TRNG_SCMC_MONO_CT_MASK) >> TRNG_SCMC_MON…  argument
25063 #define TRNG_BRD_SCMC_MONO_CT(base) (BME_UBFX32(&TRNG_SCMC_REG(base), TRNG_SCMC_MONO_CT_SHIFT, TRNG…  argument
25089 #define TRNG_RD_SCML(base)       (TRNG_SCML_REG(base))  argument
25090 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))  argument
25091 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu…  argument
25092 #define TRNG_SET_SCML(base, value) (BME_OR32(&TRNG_SCML_REG(base), (uint32_t)(value)))  argument
25093 #define TRNG_CLR_SCML(base, value) (BME_AND32(&TRNG_SCML_REG(base), (uint32_t)(~(value))))  argument
25094 #define TRNG_TOG_SCML(base, value) (BME_XOR32(&TRNG_SCML_REG(base), (uint32_t)(value)))  argument
25111 #define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_M…  argument
25112 #define TRNG_BRD_SCML_MONO_MAX(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_MAX_SHIFT, TR…  argument
25115 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_…  argument
25116 #define TRNG_BWR_SCML_MONO_MAX(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << …  argument
25129 #define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_M…  argument
25130 #define TRNG_BRD_SCML_MONO_RNG(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_RNG_SHIFT, TR…  argument
25133 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_…  argument
25134 #define TRNG_BWR_SCML_MONO_RNG(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << …  argument
25161 #define TRNG_RD_SCR1L(base)      (TRNG_SCR1L_REG(base))  argument
25162 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))  argument
25163 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v…  argument
25164 #define TRNG_SET_SCR1L(base, value) (BME_OR32(&TRNG_SCR1L_REG(base), (uint32_t)(value)))  argument
25165 #define TRNG_CLR_SCR1L(base, value) (BME_AND32(&TRNG_SCR1L_REG(base), (uint32_t)(~(value))))  argument
25166 #define TRNG_TOG_SCR1L(base, value) (BME_XOR32(&TRNG_SCR1L_REG(base), (uint32_t)(value)))  argument
25184 #define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR…  argument
25185 #define TRNG_BRD_SCR1L_RUN1_MAX(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_MAX_SHIFT,…  argument
25188 #define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SC…  argument
25189 #define TRNG_BWR_SCR1L_RUN1_MAX(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) <…  argument
25202 #define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR…  argument
25203 #define TRNG_BRD_SCR1L_RUN1_RNG(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_RNG_SHIFT,…  argument
25206 #define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SC…  argument
25207 #define TRNG_BWR_SCR1L_RUN1_RNG(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) <…  argument
25232 #define TRNG_RD_SCR1C(base)      (TRNG_SCR1C_REG(base))  argument
25247 #define TRNG_RD_SCR1C_R1_0_CT(base) ((TRNG_SCR1C_REG(base) & TRNG_SCR1C_R1_0_CT_MASK) >> TRNG_SCR1C…  argument
25248 #define TRNG_BRD_SCR1C_R1_0_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_0_CT_SHIFT, T…  argument
25259 #define TRNG_RD_SCR1C_R1_1_CT(base) ((TRNG_SCR1C_REG(base) & TRNG_SCR1C_R1_1_CT_MASK) >> TRNG_SCR1C…  argument
25260 #define TRNG_BRD_SCR1C_R1_1_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_1_CT_SHIFT, T…  argument
25287 #define TRNG_RD_SCR2L(base)      (TRNG_SCR2L_REG(base))  argument
25288 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))  argument
25289 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (v…  argument
25290 #define TRNG_SET_SCR2L(base, value) (BME_OR32(&TRNG_SCR2L_REG(base), (uint32_t)(value)))  argument
25291 #define TRNG_CLR_SCR2L(base, value) (BME_AND32(&TRNG_SCR2L_REG(base), (uint32_t)(~(value))))  argument
25292 #define TRNG_TOG_SCR2L(base, value) (BME_XOR32(&TRNG_SCR2L_REG(base), (uint32_t)(value)))  argument
25310 #define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR…  argument
25311 #define TRNG_BRD_SCR2L_RUN2_MAX(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_MAX_SHIFT,…  argument
25314 #define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SC…  argument
25315 #define TRNG_BWR_SCR2L_RUN2_MAX(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) <…  argument
25328 #define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR…  argument
25329 #define TRNG_BRD_SCR2L_RUN2_RNG(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_RNG_SHIFT,…  argument
25332 #define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SC…  argument
25333 #define TRNG_BWR_SCR2L_RUN2_RNG(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) <…  argument
25358 #define TRNG_RD_SCR2C(base)      (TRNG_SCR2C_REG(base))  argument
25373 #define TRNG_RD_SCR2C_R2_0_CT(base) ((TRNG_SCR2C_REG(base) & TRNG_SCR2C_R2_0_CT_MASK) >> TRNG_SCR2C…  argument
25374 #define TRNG_BRD_SCR2C_R2_0_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_0_CT_SHIFT, T…  argument
25385 #define TRNG_RD_SCR2C_R2_1_CT(base) ((TRNG_SCR2C_REG(base) & TRNG_SCR2C_R2_1_CT_MASK) >> TRNG_SCR2C…  argument
25386 #define TRNG_BRD_SCR2C_R2_1_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_1_CT_SHIFT, T…  argument
25411 #define TRNG_RD_SCR3C(base)      (TRNG_SCR3C_REG(base))  argument
25426 #define TRNG_RD_SCR3C_R3_0_CT(base) ((TRNG_SCR3C_REG(base) & TRNG_SCR3C_R3_0_CT_MASK) >> TRNG_SCR3C…  argument
25427 #define TRNG_BRD_SCR3C_R3_0_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_0_CT_SHIFT, T…  argument
25438 #define TRNG_RD_SCR3C_R3_1_CT(base) ((TRNG_SCR3C_REG(base) & TRNG_SCR3C_R3_1_CT_MASK) >> TRNG_SCR3C…  argument
25439 #define TRNG_BRD_SCR3C_R3_1_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_1_CT_SHIFT, T…  argument
25466 #define TRNG_RD_SCR3L(base)      (TRNG_SCR3L_REG(base))  argument
25467 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))  argument
25468 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (v…  argument
25469 #define TRNG_SET_SCR3L(base, value) (BME_OR32(&TRNG_SCR3L_REG(base), (uint32_t)(value)))  argument
25470 #define TRNG_CLR_SCR3L(base, value) (BME_AND32(&TRNG_SCR3L_REG(base), (uint32_t)(~(value))))  argument
25471 #define TRNG_TOG_SCR3L(base, value) (BME_XOR32(&TRNG_SCR3L_REG(base), (uint32_t)(value)))  argument
25489 #define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR…  argument
25490 #define TRNG_BRD_SCR3L_RUN3_MAX(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_MAX_SHIFT,…  argument
25493 #define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SC…  argument
25494 #define TRNG_BWR_SCR3L_RUN3_MAX(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) <…  argument
25507 #define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR…  argument
25508 #define TRNG_BRD_SCR3L_RUN3_RNG(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_RNG_SHIFT,…  argument
25511 #define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SC…  argument
25512 #define TRNG_BWR_SCR3L_RUN3_RNG(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) <…  argument
25537 #define TRNG_RD_SCR4C(base)      (TRNG_SCR4C_REG(base))  argument
25552 #define TRNG_RD_SCR4C_R4_0_CT(base) ((TRNG_SCR4C_REG(base) & TRNG_SCR4C_R4_0_CT_MASK) >> TRNG_SCR4C…  argument
25553 #define TRNG_BRD_SCR4C_R4_0_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_0_CT_SHIFT, T…  argument
25564 #define TRNG_RD_SCR4C_R4_1_CT(base) ((TRNG_SCR4C_REG(base) & TRNG_SCR4C_R4_1_CT_MASK) >> TRNG_SCR4C…  argument
25565 #define TRNG_BRD_SCR4C_R4_1_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_1_CT_SHIFT, T…  argument
25592 #define TRNG_RD_SCR4L(base)      (TRNG_SCR4L_REG(base))  argument
25593 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))  argument
25594 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (v…  argument
25595 #define TRNG_SET_SCR4L(base, value) (BME_OR32(&TRNG_SCR4L_REG(base), (uint32_t)(value)))  argument
25596 #define TRNG_CLR_SCR4L(base, value) (BME_AND32(&TRNG_SCR4L_REG(base), (uint32_t)(~(value))))  argument
25597 #define TRNG_TOG_SCR4L(base, value) (BME_XOR32(&TRNG_SCR4L_REG(base), (uint32_t)(value)))  argument
25615 #define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR…  argument
25616 #define TRNG_BRD_SCR4L_RUN4_MAX(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_MAX_SHIFT,…  argument
25619 #define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SC…  argument
25620 #define TRNG_BWR_SCR4L_RUN4_MAX(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) <…  argument
25633 #define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR…  argument
25634 #define TRNG_BRD_SCR4L_RUN4_RNG(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_RNG_SHIFT,…  argument
25637 #define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SC…  argument
25638 #define TRNG_BWR_SCR4L_RUN4_RNG(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) <…  argument
25665 #define TRNG_RD_SCR5L(base)      (TRNG_SCR5L_REG(base))  argument
25666 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))  argument
25667 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (v…  argument
25668 #define TRNG_SET_SCR5L(base, value) (BME_OR32(&TRNG_SCR5L_REG(base), (uint32_t)(value)))  argument
25669 #define TRNG_CLR_SCR5L(base, value) (BME_AND32(&TRNG_SCR5L_REG(base), (uint32_t)(~(value))))  argument
25670 #define TRNG_TOG_SCR5L(base, value) (BME_XOR32(&TRNG_SCR5L_REG(base), (uint32_t)(value)))  argument
25688 #define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR…  argument
25689 #define TRNG_BRD_SCR5L_RUN5_MAX(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_MAX_SHIFT,…  argument
25692 #define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SC…  argument
25693 #define TRNG_BWR_SCR5L_RUN5_MAX(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) <…  argument
25706 #define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR…  argument
25707 #define TRNG_BRD_SCR5L_RUN5_RNG(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_RNG_SHIFT,…  argument
25710 #define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SC…  argument
25711 #define TRNG_BWR_SCR5L_RUN5_RNG(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) <…  argument
25736 #define TRNG_RD_SCR5C(base)      (TRNG_SCR5C_REG(base))  argument
25751 #define TRNG_RD_SCR5C_R5_0_CT(base) ((TRNG_SCR5C_REG(base) & TRNG_SCR5C_R5_0_CT_MASK) >> TRNG_SCR5C…  argument
25752 #define TRNG_BRD_SCR5C_R5_0_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_0_CT_SHIFT, T…  argument
25763 #define TRNG_RD_SCR5C_R5_1_CT(base) ((TRNG_SCR5C_REG(base) & TRNG_SCR5C_R5_1_CT_MASK) >> TRNG_SCR5C…  argument
25764 #define TRNG_BRD_SCR5C_R5_1_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_1_CT_SHIFT, T…  argument
25791 #define TRNG_RD_SCR6PL(base)     (TRNG_SCR6PL_REG(base))  argument
25792 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))  argument
25793 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) |…  argument
25794 #define TRNG_SET_SCR6PL(base, value) (BME_OR32(&TRNG_SCR6PL_REG(base), (uint32_t)(value)))  argument
25795 #define TRNG_CLR_SCR6PL(base, value) (BME_AND32(&TRNG_SCR6PL_REG(base), (uint32_t)(~(value))))  argument
25796 #define TRNG_TOG_SCR6PL(base, value) (BME_XOR32(&TRNG_SCR6PL_REG(base), (uint32_t)(value)))  argument
25814 #define TRNG_RD_SCR6PL_RUN6P_MAX(base) ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRN…  argument
25815 #define TRNG_BRD_SCR6PL_RUN6P_MAX(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_MAX_S…  argument
25818 #define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TR…  argument
25819 #define TRNG_BWR_SCR6PL_RUN6P_MAX(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value…  argument
25832 #define TRNG_RD_SCR6PL_RUN6P_RNG(base) ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRN…  argument
25833 #define TRNG_BRD_SCR6PL_RUN6P_RNG(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_RNG_S…  argument
25836 #define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TR…  argument
25837 #define TRNG_BWR_SCR6PL_RUN6P_RNG(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value…  argument
25862 #define TRNG_RD_SCR6PC(base)     (TRNG_SCR6PC_REG(base))  argument
25877 #define TRNG_RD_SCR6PC_R6P_0_CT(base) ((TRNG_SCR6PC_REG(base) & TRNG_SCR6PC_R6P_0_CT_MASK) >> TRNG_…  argument
25878 #define TRNG_BRD_SCR6PC_R6P_0_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_0_CT_SHI…  argument
25889 #define TRNG_RD_SCR6PC_R6P_1_CT(base) ((TRNG_SCR6PC_REG(base) & TRNG_SCR6PC_R6P_1_CT_MASK) >> TRNG_…  argument
25890 #define TRNG_BRD_SCR6PC_R6P_1_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_1_CT_SHI…  argument
25924 #define TRNG_RD_STATUS(base)     (TRNG_STATUS_REG(base))  argument
25939 #define TRNG_RD_STATUS_TF1BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF1BR0_MASK) >> TRNG_STAT…  argument
25940 #define TRNG_BRD_STATUS_TF1BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR0_SHIFT, …  argument
25951 #define TRNG_RD_STATUS_TF1BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF1BR1_MASK) >> TRNG_STAT…  argument
25952 #define TRNG_BRD_STATUS_TF1BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR1_SHIFT, …  argument
25963 #define TRNG_RD_STATUS_TF2BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF2BR0_MASK) >> TRNG_STAT…  argument
25964 #define TRNG_BRD_STATUS_TF2BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR0_SHIFT, …  argument
25975 #define TRNG_RD_STATUS_TF2BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF2BR1_MASK) >> TRNG_STAT…  argument
25976 #define TRNG_BRD_STATUS_TF2BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR1_SHIFT, …  argument
25987 #define TRNG_RD_STATUS_TF3BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF3BR0_MASK) >> TRNG_STAT…  argument
25988 #define TRNG_BRD_STATUS_TF3BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR0_SHIFT, …  argument
25999 #define TRNG_RD_STATUS_TF3BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF3BR1_MASK) >> TRNG_STAT…  argument
26000 #define TRNG_BRD_STATUS_TF3BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR1_SHIFT, …  argument
26011 #define TRNG_RD_STATUS_TF4BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF4BR0_MASK) >> TRNG_STAT…  argument
26012 #define TRNG_BRD_STATUS_TF4BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR0_SHIFT, …  argument
26023 #define TRNG_RD_STATUS_TF4BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF4BR1_MASK) >> TRNG_STAT…  argument
26024 #define TRNG_BRD_STATUS_TF4BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR1_SHIFT, …  argument
26035 #define TRNG_RD_STATUS_TF5BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF5BR0_MASK) >> TRNG_STAT…  argument
26036 #define TRNG_BRD_STATUS_TF5BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR0_SHIFT, …  argument
26047 #define TRNG_RD_STATUS_TF5BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF5BR1_MASK) >> TRNG_STAT…  argument
26048 #define TRNG_BRD_STATUS_TF5BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR1_SHIFT, …  argument
26059 #define TRNG_RD_STATUS_TF6PBR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF6PBR0_MASK) >> TRNG_ST…  argument
26060 #define TRNG_BRD_STATUS_TF6PBR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR0_SHIFT…  argument
26071 #define TRNG_RD_STATUS_TF6PBR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF6PBR1_MASK) >> TRNG_ST…  argument
26072 #define TRNG_BRD_STATUS_TF6PBR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR1_SHIFT…  argument
26082 #define TRNG_RD_STATUS_TFSB(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFSB_MASK) >> TRNG_STATUS_T…  argument
26083 #define TRNG_BRD_STATUS_TFSB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFSB_SHIFT, TRNG…  argument
26093 #define TRNG_RD_STATUS_TFLR(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFLR_MASK) >> TRNG_STATUS_T…  argument
26094 #define TRNG_BRD_STATUS_TFLR(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFLR_SHIFT, TRNG…  argument
26104 #define TRNG_RD_STATUS_TFP(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFP_MASK) >> TRNG_STATUS_TFP…  argument
26105 #define TRNG_BRD_STATUS_TFP(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFP_SHIFT, TRNG_S…  argument
26115 #define TRNG_RD_STATUS_TFMB(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFMB_MASK) >> TRNG_STATUS_T…  argument
26116 #define TRNG_BRD_STATUS_TFMB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFMB_SHIFT, TRNG…  argument
26128 #define TRNG_RD_STATUS_RETRY_CT(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_RETRY_CT_MASK) >> TRNG_…  argument
26129 #define TRNG_BRD_STATUS_RETRY_CT(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_RETRY_CT_SHI…  argument
26154 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))  argument
26177 #define TRNG_RD_PKRCNT10(base)   (TRNG_PKRCNT10_REG(base))  argument
26192 #define TRNG_RD_PKRCNT10_PKR_0_CT(base) ((TRNG_PKRCNT10_REG(base) & TRNG_PKRCNT10_PKR_0_CT_MASK) >>…  argument
26193 #define TRNG_BRD_PKRCNT10_PKR_0_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_0_…  argument
26204 #define TRNG_RD_PKRCNT10_PKR_1_CT(base) ((TRNG_PKRCNT10_REG(base) & TRNG_PKRCNT10_PKR_1_CT_MASK) >>…  argument
26205 #define TRNG_BRD_PKRCNT10_PKR_1_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_1_…  argument
26228 #define TRNG_RD_PKRCNT32(base)   (TRNG_PKRCNT32_REG(base))  argument
26243 #define TRNG_RD_PKRCNT32_PKR_2_CT(base) ((TRNG_PKRCNT32_REG(base) & TRNG_PKRCNT32_PKR_2_CT_MASK) >>…  argument
26244 #define TRNG_BRD_PKRCNT32_PKR_2_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_2_…  argument
26255 #define TRNG_RD_PKRCNT32_PKR_3_CT(base) ((TRNG_PKRCNT32_REG(base) & TRNG_PKRCNT32_PKR_3_CT_MASK) >>…  argument
26256 #define TRNG_BRD_PKRCNT32_PKR_3_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_3_…  argument
26279 #define TRNG_RD_PKRCNT54(base)   (TRNG_PKRCNT54_REG(base))  argument
26294 #define TRNG_RD_PKRCNT54_PKR_4_CT(base) ((TRNG_PKRCNT54_REG(base) & TRNG_PKRCNT54_PKR_4_CT_MASK) >>…  argument
26295 #define TRNG_BRD_PKRCNT54_PKR_4_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_4_…  argument
26306 #define TRNG_RD_PKRCNT54_PKR_5_CT(base) ((TRNG_PKRCNT54_REG(base) & TRNG_PKRCNT54_PKR_5_CT_MASK) >>…  argument
26307 #define TRNG_BRD_PKRCNT54_PKR_5_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_5_…  argument
26330 #define TRNG_RD_PKRCNT76(base)   (TRNG_PKRCNT76_REG(base))  argument
26345 #define TRNG_RD_PKRCNT76_PKR_6_CT(base) ((TRNG_PKRCNT76_REG(base) & TRNG_PKRCNT76_PKR_6_CT_MASK) >>…  argument
26346 #define TRNG_BRD_PKRCNT76_PKR_6_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_6_…  argument
26357 #define TRNG_RD_PKRCNT76_PKR_7_CT(base) ((TRNG_PKRCNT76_REG(base) & TRNG_PKRCNT76_PKR_7_CT_MASK) >>…  argument
26358 #define TRNG_BRD_PKRCNT76_PKR_7_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_7_…  argument
26381 #define TRNG_RD_PKRCNT98(base)   (TRNG_PKRCNT98_REG(base))  argument
26396 #define TRNG_RD_PKRCNT98_PKR_8_CT(base) ((TRNG_PKRCNT98_REG(base) & TRNG_PKRCNT98_PKR_8_CT_MASK) >>…  argument
26397 #define TRNG_BRD_PKRCNT98_PKR_8_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_8_…  argument
26408 #define TRNG_RD_PKRCNT98_PKR_9_CT(base) ((TRNG_PKRCNT98_REG(base) & TRNG_PKRCNT98_PKR_9_CT_MASK) >>…  argument
26409 #define TRNG_BRD_PKRCNT98_PKR_9_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_9_…  argument
26432 #define TRNG_RD_PKRCNTBA(base)   (TRNG_PKRCNTBA_REG(base))  argument
26447 #define TRNG_RD_PKRCNTBA_PKR_A_CT(base) ((TRNG_PKRCNTBA_REG(base) & TRNG_PKRCNTBA_PKR_A_CT_MASK) >>…  argument
26448 #define TRNG_BRD_PKRCNTBA_PKR_A_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_A_…  argument
26459 #define TRNG_RD_PKRCNTBA_PKR_B_CT(base) ((TRNG_PKRCNTBA_REG(base) & TRNG_PKRCNTBA_PKR_B_CT_MASK) >>…  argument
26460 #define TRNG_BRD_PKRCNTBA_PKR_B_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_B_…  argument
26483 #define TRNG_RD_PKRCNTDC(base)   (TRNG_PKRCNTDC_REG(base))  argument
26498 #define TRNG_RD_PKRCNTDC_PKR_C_CT(base) ((TRNG_PKRCNTDC_REG(base) & TRNG_PKRCNTDC_PKR_C_CT_MASK) >>…  argument
26499 #define TRNG_BRD_PKRCNTDC_PKR_C_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_C_…  argument
26510 #define TRNG_RD_PKRCNTDC_PKR_D_CT(base) ((TRNG_PKRCNTDC_REG(base) & TRNG_PKRCNTDC_PKR_D_CT_MASK) >>…  argument
26511 #define TRNG_BRD_PKRCNTDC_PKR_D_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_D_…  argument
26534 #define TRNG_RD_PKRCNTFE(base)   (TRNG_PKRCNTFE_REG(base))  argument
26549 #define TRNG_RD_PKRCNTFE_PKR_E_CT(base) ((TRNG_PKRCNTFE_REG(base) & TRNG_PKRCNTFE_PKR_E_CT_MASK) >>…  argument
26550 #define TRNG_BRD_PKRCNTFE_PKR_E_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_E_…  argument
26561 #define TRNG_RD_PKRCNTFE_PKR_F_CT(base) ((TRNG_PKRCNTFE_REG(base) & TRNG_PKRCNTFE_PKR_F_CT_MASK) >>…  argument
26562 #define TRNG_BRD_PKRCNTFE_PKR_F_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_F_…  argument
26585 #define TRNG_RD_SEC_CFG(base)    (TRNG_SEC_CFG_REG(base))  argument
26586 #define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))  argument
26587 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)…  argument
26588 #define TRNG_SET_SEC_CFG(base, value) (BME_OR32(&TRNG_SEC_CFG_REG(base), (uint32_t)(value)))  argument
26589 #define TRNG_CLR_SEC_CFG(base, value) (BME_AND32(&TRNG_SEC_CFG_REG(base), (uint32_t)(~(value))))  argument
26590 #define TRNG_TOG_SEC_CFG(base, value) (BME_XOR32(&TRNG_SEC_CFG_REG(base), (uint32_t)(value)))  argument
26608 #define TRNG_RD_SEC_CFG_SH0(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_SH0_MASK) >> TRNG_SEC_CFG…  argument
26609 #define TRNG_BRD_SEC_CFG_SH0(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SH0_SHIFT, TRN…  argument
26612 #define TRNG_WR_SEC_CFG_SH0(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_SH0_MASK, TRNG_SEC_CF…  argument
26613 #define TRNG_BWR_SEC_CFG_SH0(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value) <<…  argument
26630 #define TRNG_RD_SEC_CFG_NO_PRGM(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG…  argument
26631 #define TRNG_BRD_SEC_CFG_NO_PRGM(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_NO_PRGM_SH…  argument
26634 #define TRNG_WR_SEC_CFG_NO_PRGM(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRN…  argument
26635 #define TRNG_BWR_SEC_CFG_NO_PRGM(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value…  argument
26649 #define TRNG_RD_SEC_CFG_SK_VAL(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_SK_VAL_MASK) >> TRNG_S…  argument
26650 #define TRNG_BRD_SEC_CFG_SK_VAL(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SK_VAL_SHIF…  argument
26653 #define TRNG_WR_SEC_CFG_SK_VAL(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_SK_VAL_MASK, TRNG_…  argument
26654 #define TRNG_BWR_SEC_CFG_SK_VAL(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value)…  argument
26678 #define TRNG_RD_INT_CTRL(base)   (TRNG_INT_CTRL_REG(base))  argument
26679 #define TRNG_WR_INT_CTRL(base, value) (TRNG_INT_CTRL_REG(base) = (value))  argument
26680 #define TRNG_RMW_INT_CTRL(base, mask, value) (TRNG_WR_INT_CTRL(base, (TRNG_RD_INT_CTRL(base) & ~(ma…  argument
26681 #define TRNG_SET_INT_CTRL(base, value) (BME_OR32(&TRNG_INT_CTRL_REG(base), (uint32_t)(value)))  argument
26682 #define TRNG_CLR_INT_CTRL(base, value) (BME_AND32(&TRNG_INT_CTRL_REG(base), (uint32_t)(~(value))))  argument
26683 #define TRNG_TOG_INT_CTRL(base, value) (BME_XOR32(&TRNG_INT_CTRL_REG(base), (uint32_t)(value)))  argument
26702 #define TRNG_RD_INT_CTRL_HW_ERR(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_HW_ERR_MASK) >> TRN…  argument
26703 #define TRNG_BRD_INT_CTRL_HW_ERR(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_HW_ERR_S…  argument
26706 #define TRNG_WR_INT_CTRL_HW_ERR(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_HW_ERR_MASK, TR…  argument
26707 #define TRNG_BWR_INT_CTRL_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(valu…  argument
26721 #define TRNG_RD_INT_CTRL_ENT_VAL(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_ENT_VAL_MASK) >> T…  argument
26722 #define TRNG_BRD_INT_CTRL_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_ENT_VAL…  argument
26725 #define TRNG_WR_INT_CTRL_ENT_VAL(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_ENT_VAL_MASK, …  argument
26726 #define TRNG_BWR_INT_CTRL_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(val…  argument
26740 #define TRNG_RD_INT_CTRL_FRQ_CT_FAIL(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_FRQ_CT_FAIL_MA…  argument
26741 #define TRNG_BRD_INT_CTRL_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_FRQ…  argument
26744 #define TRNG_WR_INT_CTRL_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_FRQ_CT_FAI…  argument
26745 #define TRNG_BWR_INT_CTRL_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)…  argument
26755 #define TRNG_RD_INT_CTRL_UNUSED(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_UNUSED_MASK) >> TRN…  argument
26756 #define TRNG_BRD_INT_CTRL_UNUSED(base) (TRNG_RD_INT_CTRL_UNUSED(base))  argument
26759 #define TRNG_WR_INT_CTRL_UNUSED(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_UNUSED_MASK, TR…  argument
26760 #define TRNG_BWR_INT_CTRL_UNUSED(base, value) (TRNG_WR_INT_CTRL_UNUSED(base, value))  argument
26784 #define TRNG_RD_INT_MASK(base)   (TRNG_INT_MASK_REG(base))  argument
26785 #define TRNG_WR_INT_MASK(base, value) (TRNG_INT_MASK_REG(base) = (value))  argument
26786 #define TRNG_RMW_INT_MASK(base, mask, value) (TRNG_WR_INT_MASK(base, (TRNG_RD_INT_MASK(base) & ~(ma…  argument
26787 #define TRNG_SET_INT_MASK(base, value) (BME_OR32(&TRNG_INT_MASK_REG(base), (uint32_t)(value)))  argument
26788 #define TRNG_CLR_INT_MASK(base, value) (BME_AND32(&TRNG_INT_MASK_REG(base), (uint32_t)(~(value))))  argument
26789 #define TRNG_TOG_INT_MASK(base, value) (BME_XOR32(&TRNG_INT_MASK_REG(base), (uint32_t)(value)))  argument
26808 #define TRNG_RD_INT_MASK_HW_ERR(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_HW_ERR_MASK) >> TRN…  argument
26809 #define TRNG_BRD_INT_MASK_HW_ERR(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_HW_ERR_S…  argument
26812 #define TRNG_WR_INT_MASK_HW_ERR(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_HW_ERR_MASK, TR…  argument
26813 #define TRNG_BWR_INT_MASK_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(valu…  argument
26827 #define TRNG_RD_INT_MASK_ENT_VAL(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_ENT_VAL_MASK) >> T…  argument
26828 #define TRNG_BRD_INT_MASK_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_ENT_VAL…  argument
26831 #define TRNG_WR_INT_MASK_ENT_VAL(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_ENT_VAL_MASK, …  argument
26832 #define TRNG_BWR_INT_MASK_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(val…  argument
26846 #define TRNG_RD_INT_MASK_FRQ_CT_FAIL(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_FRQ_CT_FAIL_MA…  argument
26847 #define TRNG_BRD_INT_MASK_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_FRQ…  argument
26850 #define TRNG_WR_INT_MASK_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_FRQ_CT_FAI…  argument
26851 #define TRNG_BWR_INT_MASK_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)…  argument
26879 #define TRNG_RD_INT_STATUS(base) (TRNG_INT_STATUS_REG(base))  argument
26880 #define TRNG_WR_INT_STATUS(base, value) (TRNG_INT_STATUS_REG(base) = (value))  argument
26881 #define TRNG_RMW_INT_STATUS(base, mask, value) (TRNG_WR_INT_STATUS(base, (TRNG_RD_INT_STATUS(base) …  argument
26882 #define TRNG_SET_INT_STATUS(base, value) (BME_OR32(&TRNG_INT_STATUS_REG(base), (uint32_t)(value)))  argument
26883 #define TRNG_CLR_INT_STATUS(base, value) (BME_AND32(&TRNG_INT_STATUS_REG(base), (uint32_t)(~(value)…  argument
26884 #define TRNG_TOG_INT_STATUS(base, value) (BME_XOR32(&TRNG_INT_STATUS_REG(base), (uint32_t)(value)))  argument
26903 #define TRNG_RD_INT_STATUS_HW_ERR(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_HW_ERR_MASK) …  argument
26904 #define TRNG_BRD_INT_STATUS_HW_ERR(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_HW…  argument
26920 #define TRNG_RD_INT_STATUS_ENT_VAL(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_ENT_VAL_MASK…  argument
26921 #define TRNG_BRD_INT_STATUS_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_E…  argument
26937 #define TRNG_RD_INT_STATUS_FRQ_CT_FAIL(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_FRQ_CT_F…  argument
26938 #define TRNG_BRD_INT_STATUS_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STAT…  argument
26941 #define TRNG_WR_INT_STATUS_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_STATUS(base, TRNG_INT_STATUS_FRQ_…  argument
26942 #define TRNG_BWR_INT_STATUS_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_STATUS_REG(base), ((uint3…  argument
26962 #define TRNG_RD_VID1(base)       (TRNG_VID1_REG(base))  argument
26979 #define TRNG_RD_VID1_RNG_MIN_REV(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_MIN_REV_MASK) >> TRNG_…  argument
26980 #define TRNG_BRD_VID1_RNG_MIN_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MIN_REV_SHI…  argument
26993 #define TRNG_RD_VID1_RNG_MAJ_REV(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_MAJ_REV_MASK) >> TRNG_…  argument
26994 #define TRNG_BRD_VID1_RNG_MAJ_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MAJ_REV_SHI…  argument
27004 #define TRNG_RD_VID1_RNG_IP_ID(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_IP_ID_MASK) >> TRNG_VID1…  argument
27005 #define TRNG_BRD_VID1_RNG_IP_ID(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_IP_ID_SHIFT, …  argument
27025 #define TRNG_RD_VID2(base)       (TRNG_VID2_REG(base))  argument
27042 #define TRNG_RD_VID2_RNG_CONFIG_OPT(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_CONFIG_OPT_MASK) >>…  argument
27043 #define TRNG_BRD_VID2_RNG_CONFIG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_CONFIG_O…  argument
27056 #define TRNG_RD_VID2_RNG_ECO_REV(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_ECO_REV_MASK) >> TRNG_…  argument
27057 #define TRNG_BRD_VID2_RNG_ECO_REV(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ECO_REV_SHI…  argument
27070 #define TRNG_RD_VID2_RNG_INTG_OPT(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_INTG_OPT_MASK) >> TRN…  argument
27071 #define TRNG_BRD_VID2_RNG_INTG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_INTG_OPT_S…  argument
27084 #define TRNG_RD_VID2_RNG_ERA(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_ERA_MASK) >> TRNG_VID2_RNG…  argument
27085 #define TRNG_BRD_VID2_RNG_ERA(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ERA_SHIFT, TRNG…  argument
27120 #define TSI_RD_GENCS(base)       (TSI_GENCS_REG(base))  argument
27121 #define TSI_WR_GENCS(base, value) (TSI_GENCS_REG(base) = (value))  argument
27122 #define TSI_RMW_GENCS(base, mask, value) (TSI_WR_GENCS(base, (TSI_RD_GENCS(base) & ~(mask)) | (valu…  argument
27123 #define TSI_SET_GENCS(base, value) (BME_OR32(&TSI_GENCS_REG(base), (uint32_t)(value)))  argument
27124 #define TSI_CLR_GENCS(base, value) (BME_AND32(&TSI_GENCS_REG(base), (uint32_t)(~(value))))  argument
27125 #define TSI_TOG_GENCS(base, value) (BME_XOR32(&TSI_GENCS_REG(base), (uint32_t)(value)))  argument
27144 #define TSI_RD_GENCS_CURSW(base) ((TSI_GENCS_REG(base) & TSI_GENCS_CURSW_MASK) >> TSI_GENCS_CURSW_S…  argument
27145 #define TSI_BRD_GENCS_CURSW(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_CURSW_SHIFT, TSI_GENC…  argument
27148 #define TSI_WR_GENCS_CURSW(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_CURSW_MASK | TSI_GENCS_EOSF…  argument
27149 #define TSI_BWR_GENCS_CURSW(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…  argument
27164 #define TSI_RD_GENCS_EOSF(base) ((TSI_GENCS_REG(base) & TSI_GENCS_EOSF_MASK) >> TSI_GENCS_EOSF_SHIF…  argument
27165 #define TSI_BRD_GENCS_EOSF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EOSF_SHIFT, TSI_GENCS_…  argument
27168 #define TSI_WR_GENCS_EOSF(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF…  argument
27169 #define TSI_BWR_GENCS_EOSF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…  argument
27185 #define TSI_RD_GENCS_SCNIP(base) ((TSI_GENCS_REG(base) & TSI_GENCS_SCNIP_MASK) >> TSI_GENCS_SCNIP_S…  argument
27186 #define TSI_BRD_GENCS_SCNIP(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_SCNIP_SHIFT, TSI_GENC…  argument
27201 #define TSI_RD_GENCS_STM(base) ((TSI_GENCS_REG(base) & TSI_GENCS_STM_MASK) >> TSI_GENCS_STM_SHIFT)  argument
27202 #define TSI_BRD_GENCS_STM(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STM_SHIFT, TSI_GENCS_ST…  argument
27205 #define TSI_WR_GENCS_STM(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_STM_MASK | TSI_GENCS_EOSF_MAS…  argument
27206 #define TSI_BWR_GENCS_STM(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_G…  argument
27221 #define TSI_RD_GENCS_STPE(base) ((TSI_GENCS_REG(base) & TSI_GENCS_STPE_MASK) >> TSI_GENCS_STPE_SHIF…  argument
27222 #define TSI_BRD_GENCS_STPE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STPE_SHIFT, TSI_GENCS_…  argument
27225 #define TSI_WR_GENCS_STPE(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_STPE_MASK | TSI_GENCS_EOSF_M…  argument
27226 #define TSI_BWR_GENCS_STPE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…  argument
27241 #define TSI_RD_GENCS_TSIIEN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_TSIIEN_MASK) >> TSI_GENCS_TSIIE…  argument
27242 #define TSI_BRD_GENCS_TSIIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIIEN_SHIFT, TSI_GE…  argument
27245 #define TSI_WR_GENCS_TSIIEN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_TSIIEN_MASK | TSI_GENCS_EO…  argument
27246 #define TSI_BWR_GENCS_TSIIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TS…  argument
27260 #define TSI_RD_GENCS_TSIEN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_TSIEN_MASK) >> TSI_GENCS_TSIEN_S…  argument
27261 #define TSI_BRD_GENCS_TSIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIEN_SHIFT, TSI_GENC…  argument
27264 #define TSI_WR_GENCS_TSIEN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_TSIEN_MASK | TSI_GENCS_EOSF…  argument
27265 #define TSI_BWR_GENCS_TSIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…  argument
27312 #define TSI_RD_GENCS_NSCN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_NSCN_MASK) >> TSI_GENCS_NSCN_SHIF…  argument
27313 #define TSI_BRD_GENCS_NSCN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_NSCN_SHIFT, TSI_GENCS_…  argument
27316 #define TSI_WR_GENCS_NSCN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_NSCN_MASK | TSI_GENCS_EOSF_M…  argument
27317 #define TSI_BWR_GENCS_NSCN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…  argument
27337 #define TSI_RD_GENCS_PS(base) ((TSI_GENCS_REG(base) & TSI_GENCS_PS_MASK) >> TSI_GENCS_PS_SHIFT)  argument
27338 #define TSI_BRD_GENCS_PS(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_PS_SHIFT, TSI_GENCS_PS_W…  argument
27341 #define TSI_WR_GENCS_PS(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_PS_MASK | TSI_GENCS_EOSF_MASK …  argument
27342 #define TSI_BWR_GENCS_PS(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GE…  argument
27363 #define TSI_RD_GENCS_EXTCHRG(base) ((TSI_GENCS_REG(base) & TSI_GENCS_EXTCHRG_MASK) >> TSI_GENCS_EXT…  argument
27364 #define TSI_BRD_GENCS_EXTCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EXTCHRG_SHIFT, TSI_…  argument
27367 #define TSI_WR_GENCS_EXTCHRG(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_EXTCHRG_MASK | TSI_GENCS_…  argument
27368 #define TSI_BWR_GENCS_EXTCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << T…  argument
27384 #define TSI_RD_GENCS_DVOLT(base) ((TSI_GENCS_REG(base) & TSI_GENCS_DVOLT_MASK) >> TSI_GENCS_DVOLT_S…  argument
27385 #define TSI_BRD_GENCS_DVOLT(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_DVOLT_SHIFT, TSI_GENC…  argument
27388 #define TSI_WR_GENCS_DVOLT(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_DVOLT_MASK | TSI_GENCS_EOSF…  argument
27389 #define TSI_BWR_GENCS_DVOLT(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI…  argument
27410 #define TSI_RD_GENCS_REFCHRG(base) ((TSI_GENCS_REG(base) & TSI_GENCS_REFCHRG_MASK) >> TSI_GENCS_REF…  argument
27411 #define TSI_BRD_GENCS_REFCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_REFCHRG_SHIFT, TSI_…  argument
27414 #define TSI_WR_GENCS_REFCHRG(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_REFCHRG_MASK | TSI_GENCS_…  argument
27415 #define TSI_BWR_GENCS_REFCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << T…  argument
27438 #define TSI_RD_GENCS_MODE(base) ((TSI_GENCS_REG(base) & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIF…  argument
27439 #define TSI_BRD_GENCS_MODE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_MODE_SHIFT, TSI_GENCS_…  argument
27442 #define TSI_WR_GENCS_MODE(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_MODE_MASK | TSI_GENCS_EOSF_M…  argument
27443 #define TSI_BWR_GENCS_MODE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…  argument
27458 #define TSI_RD_GENCS_ESOR(base) ((TSI_GENCS_REG(base) & TSI_GENCS_ESOR_MASK) >> TSI_GENCS_ESOR_SHIF…  argument
27459 #define TSI_BRD_GENCS_ESOR(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_ESOR_SHIFT, TSI_GENCS_…  argument
27462 #define TSI_WR_GENCS_ESOR(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_ESOR_MASK | TSI_GENCS_EOSF_M…  argument
27463 #define TSI_BWR_GENCS_ESOR(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_…  argument
27476 #define TSI_RD_GENCS_OUTRGF(base) ((TSI_GENCS_REG(base) & TSI_GENCS_OUTRGF_MASK) >> TSI_GENCS_OUTRG…  argument
27477 #define TSI_BRD_GENCS_OUTRGF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_OUTRGF_SHIFT, TSI_GE…  argument
27480 #define TSI_WR_GENCS_OUTRGF(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_OUTRGF_MASK | TSI_GENCS_EO…  argument
27481 #define TSI_BWR_GENCS_OUTRGF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TS…  argument
27497 #define TSI_RD_DATA(base)        (TSI_DATA_REG(base))  argument
27498 #define TSI_WR_DATA(base, value) (TSI_DATA_REG(base) = (value))  argument
27499 #define TSI_RMW_DATA(base, mask, value) (TSI_WR_DATA(base, (TSI_RD_DATA(base) & ~(mask)) | (value)))  argument
27500 #define TSI_SET_DATA(base, value) (BME_OR32(&TSI_DATA_REG(base), (uint32_t)(value)))  argument
27501 #define TSI_CLR_DATA(base, value) (BME_AND32(&TSI_DATA_REG(base), (uint32_t)(~(value))))  argument
27502 #define TSI_TOG_DATA(base, value) (BME_XOR32(&TSI_DATA_REG(base), (uint32_t)(value)))  argument
27517 #define TSI_RD_DATA_TSICNT(base) ((TSI_DATA_REG(base) & TSI_DATA_TSICNT_MASK) >> TSI_DATA_TSICNT_SH…  argument
27518 #define TSI_BRD_DATA_TSICNT(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICNT_SHIFT, TSI_DATA_…  argument
27535 #define TSI_WR_DATA_SWTS(base, value) (TSI_RMW_DATA(base, TSI_DATA_SWTS_MASK, TSI_DATA_SWTS(value)))  argument
27536 #define TSI_BWR_DATA_SWTS(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_DA…  argument
27553 #define TSI_RD_DATA_DMAEN(base) ((TSI_DATA_REG(base) & TSI_DATA_DMAEN_MASK) >> TSI_DATA_DMAEN_SHIFT)  argument
27554 #define TSI_BRD_DATA_DMAEN(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_DMAEN_SHIFT, TSI_DATA_DM…  argument
27557 #define TSI_WR_DATA_DMAEN(base, value) (TSI_RMW_DATA(base, TSI_DATA_DMAEN_MASK, TSI_DATA_DMAEN(valu…  argument
27558 #define TSI_BWR_DATA_DMAEN(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_D…  argument
27589 #define TSI_RD_DATA_TSICH(base) ((TSI_DATA_REG(base) & TSI_DATA_TSICH_MASK) >> TSI_DATA_TSICH_SHIFT)  argument
27590 #define TSI_BRD_DATA_TSICH(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICH_SHIFT, TSI_DATA_TS…  argument
27593 #define TSI_WR_DATA_TSICH(base, value) (TSI_RMW_DATA(base, TSI_DATA_TSICH_MASK, TSI_DATA_TSICH(valu…  argument
27594 #define TSI_BWR_DATA_TSICH(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_D…  argument
27610 #define TSI_RD_TSHD(base)        (TSI_TSHD_REG(base))  argument
27611 #define TSI_WR_TSHD(base, value) (TSI_TSHD_REG(base) = (value))  argument
27612 #define TSI_RMW_TSHD(base, mask, value) (TSI_WR_TSHD(base, (TSI_RD_TSHD(base) & ~(mask)) | (value)))  argument
27613 #define TSI_SET_TSHD(base, value) (BME_OR32(&TSI_TSHD_REG(base), (uint32_t)(value)))  argument
27614 #define TSI_CLR_TSHD(base, value) (BME_AND32(&TSI_TSHD_REG(base), (uint32_t)(~(value))))  argument
27615 #define TSI_TOG_TSHD(base, value) (BME_XOR32(&TSI_TSHD_REG(base), (uint32_t)(value)))  argument
27629 #define TSI_RD_TSHD_THRESL(base) ((TSI_TSHD_REG(base) & TSI_TSHD_THRESL_MASK) >> TSI_TSHD_THRESL_SH…  argument
27630 #define TSI_BRD_TSHD_THRESL(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESL_SHIFT, TSI_TSHD_…  argument
27633 #define TSI_WR_TSHD_THRESL(base, value) (TSI_RMW_TSHD(base, TSI_TSHD_THRESL_MASK, TSI_TSHD_THRESL(v…  argument
27634 #define TSI_BWR_TSHD_THRESL(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_…  argument
27644 #define TSI_RD_TSHD_THRESH(base) ((TSI_TSHD_REG(base) & TSI_TSHD_THRESH_MASK) >> TSI_TSHD_THRESH_SH…  argument
27645 #define TSI_BRD_TSHD_THRESH(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESH_SHIFT, TSI_TSHD_…  argument
27648 #define TSI_WR_TSHD_THRESH(base, value) (TSI_RMW_TSHD(base, TSI_TSHD_THRESH_MASK, TSI_TSHD_THRESH(v…  argument
27649 #define TSI_BWR_TSHD_THRESH(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_…  argument
27840 #define XCVR_RD_RX_DIG_CTRL(base) (XCVR_RX_DIG_CTRL_REG(base))  argument
27841 #define XCVR_WR_RX_DIG_CTRL(base, value) (XCVR_RX_DIG_CTRL_REG(base) = (value))  argument
27842 #define XCVR_RMW_RX_DIG_CTRL(base, mask, value) (XCVR_WR_RX_DIG_CTRL(base, (XCVR_RD_RX_DIG_CTRL(bas…  argument
27843 #define XCVR_SET_RX_DIG_CTRL(base, value) (BME_OR32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(value)))  argument
27844 #define XCVR_CLR_RX_DIG_CTRL(base, value) (BME_AND32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(~(valu…  argument
27845 #define XCVR_TOG_RX_DIG_CTRL(base, value) (BME_XOR32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(value)…  argument
27863 #define XCVR_RD_RX_DIG_CTRL_RX_ADC_NEGEDGE(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX…  argument
27864 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_NEGEDGE(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_…  argument
27867 #define XCVR_WR_RX_DIG_CTRL_RX_ADC_NEGEDGE(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTR…  argument
27868 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_NEGEDGE(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((…  argument
27882 #define XCVR_RD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL…  argument
27883 #define XCVR_BRD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_…  argument
27886 #define XCVR_WR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_…  argument
27887 #define XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base),…  argument
27901 #define XCVR_RD_RX_DIG_CTRL_RX_ADC_RAW_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_…  argument
27902 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_RAW_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_D…  argument
27905 #define XCVR_WR_RX_DIG_CTRL_RX_ADC_RAW_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL…  argument
27906 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_RAW_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((u…  argument
27920 #define XCVR_RD_RX_DIG_CTRL_RX_DEC_FILT_OSR(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_R…  argument
27921 #define XCVR_BRD_RX_DIG_CTRL_RX_DEC_FILT_OSR(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX…  argument
27924 #define XCVR_WR_RX_DIG_CTRL_RX_DEC_FILT_OSR(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CT…  argument
27925 #define XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), (…  argument
27937 #define XCVR_RD_RX_DIG_CTRL_RX_INTERP_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_I…  argument
27938 #define XCVR_BRD_RX_DIG_CTRL_RX_INTERP_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DI…  argument
27941 #define XCVR_WR_RX_DIG_CTRL_RX_INTERP_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_…  argument
27942 #define XCVR_BWR_RX_DIG_CTRL_RX_INTERP_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((ui…  argument
27954 #define XCVR_RD_RX_DIG_CTRL_RX_NORM_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_NOR…  argument
27955 #define XCVR_BRD_RX_DIG_CTRL_RX_NORM_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…  argument
27958 #define XCVR_WR_RX_DIG_CTRL_RX_NORM_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX…  argument
27959 #define XCVR_BWR_RX_DIG_CTRL_RX_NORM_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…  argument
27971 #define XCVR_RD_RX_DIG_CTRL_RX_RSSI_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_RSS…  argument
27972 #define XCVR_BRD_RX_DIG_CTRL_RX_RSSI_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…  argument
27975 #define XCVR_WR_RX_DIG_CTRL_RX_RSSI_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX…  argument
27976 #define XCVR_BWR_RX_DIG_CTRL_RX_RSSI_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…  argument
27990 #define XCVR_RD_RX_DIG_CTRL_RX_AGC_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_AGC_…  argument
27991 #define XCVR_BRD_RX_DIG_CTRL_RX_AGC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_C…  argument
27994 #define XCVR_WR_RX_DIG_CTRL_RX_AGC_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_…  argument
27995 #define XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint3…  argument
28009 #define XCVR_RD_RX_DIG_CTRL_RX_DCOC_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_DCO…  argument
28010 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…  argument
28013 #define XCVR_WR_RX_DIG_CTRL_RX_DCOC_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX…  argument
28014 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…  argument
28028 #define XCVR_RD_RX_DIG_CTRL_RX_DCOC_CAL_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX…  argument
28029 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_CAL_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_…  argument
28032 #define XCVR_WR_RX_DIG_CTRL_RX_DCOC_CAL_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTR…  argument
28033 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((…  argument
28047 #define XCVR_RD_RX_DIG_CTRL_RX_IQ_SWAP(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_IQ_…  argument
28048 #define XCVR_BRD_RX_DIG_CTRL_RX_IQ_SWAP(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_…  argument
28051 #define XCVR_WR_RX_DIG_CTRL_RX_IQ_SWAP(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX…  argument
28052 #define XCVR_BWR_RX_DIG_CTRL_RX_IQ_SWAP(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint…  argument
28068 #define XCVR_RD_AGC_CTRL_0(base) (XCVR_AGC_CTRL_0_REG(base))  argument
28069 #define XCVR_WR_AGC_CTRL_0(base, value) (XCVR_AGC_CTRL_0_REG(base) = (value))  argument
28070 #define XCVR_RMW_AGC_CTRL_0(base, mask, value) (XCVR_WR_AGC_CTRL_0(base, (XCVR_RD_AGC_CTRL_0(base) …  argument
28071 #define XCVR_SET_AGC_CTRL_0(base, value) (BME_OR32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(value)))  argument
28072 #define XCVR_CLR_AGC_CTRL_0(base, value) (BME_AND32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(~(value)…  argument
28073 #define XCVR_TOG_AGC_CTRL_0(base, value) (BME_XOR32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(value)))  argument
28087 #define XCVR_RD_AGC_CTRL_0_SLOW_AGC_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_SLOW_AGC…  argument
28088 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL…  argument
28091 #define XCVR_WR_AGC_CTRL_0_SLOW_AGC_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_SLOW…  argument
28092 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint3…  argument
28106 #define XCVR_RD_AGC_CTRL_0_SLOW_AGC_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_SLOW_AG…  argument
28107 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTR…  argument
28110 #define XCVR_WR_AGC_CTRL_0_SLOW_AGC_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_SLO…  argument
28111 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint…  argument
28122 #define XCVR_RD_AGC_CTRL_0_AGC_FREEZE_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_FR…  argument
28123 #define XCVR_BRD_AGC_CTRL_0_AGC_FREEZE_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CT…  argument
28126 #define XCVR_WR_AGC_CTRL_0_AGC_FREEZE_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AG…  argument
28127 #define XCVR_BWR_AGC_CTRL_0_AGC_FREEZE_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uin…  argument
28141 #define XCVR_RD_AGC_CTRL_0_FREEZE_AGC_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_FREEZ…  argument
28142 #define XCVR_BRD_AGC_CTRL_0_FREEZE_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_C…  argument
28145 #define XCVR_WR_AGC_CTRL_0_FREEZE_AGC_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_F…  argument
28146 #define XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((ui…  argument
28156 #define XCVR_RD_AGC_CTRL_0_AGC_UP_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_UP_EN_…  argument
28157 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0…  argument
28160 #define XCVR_WR_AGC_CTRL_0_AGC_UP_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_UP…  argument
28161 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_…  argument
28175 #define XCVR_RD_AGC_CTRL_0_AGC_UP_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_UP_SR…  argument
28176 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_…  argument
28179 #define XCVR_WR_AGC_CTRL_0_AGC_UP_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_U…  argument
28180 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32…  argument
28190 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0…  argument
28191 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…  argument
28194 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CT…  argument
28195 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…  argument
28205 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0…  argument
28206 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…  argument
28209 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CT…  argument
28210 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…  argument
28220 #define XCVR_RD_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_A…  argument
28221 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_A…  argument
28224 #define XCVR_WR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL…  argument
28225 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), …  argument
28235 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0…  argument
28236 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR…  argument
28239 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CT…  argument
28240 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base)…  argument
28256 #define XCVR_RD_AGC_CTRL_1(base) (XCVR_AGC_CTRL_1_REG(base))  argument
28257 #define XCVR_WR_AGC_CTRL_1(base, value) (XCVR_AGC_CTRL_1_REG(base) = (value))  argument
28258 #define XCVR_RMW_AGC_CTRL_1(base, mask, value) (XCVR_WR_AGC_CTRL_1(base, (XCVR_RD_AGC_CTRL_1(base) …  argument
28259 #define XCVR_SET_AGC_CTRL_1(base, value) (BME_OR32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(value)))  argument
28260 #define XCVR_CLR_AGC_CTRL_1(base, value) (BME_AND32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(~(value)…  argument
28261 #define XCVR_TOG_AGC_CTRL_1(base, value) (BME_XOR32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(value)))  argument
28276 #define XCVR_RD_AGC_CTRL_1_BBF_ALT_CODE(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_BBF_ALT…  argument
28277 #define XCVR_BRD_AGC_CTRL_1_BBF_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTR…  argument
28280 #define XCVR_WR_AGC_CTRL_1_BBF_ALT_CODE(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_BBF…  argument
28281 #define XCVR_BWR_AGC_CTRL_1_BBF_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint…  argument
28292 #define XCVR_RD_AGC_CTRL_1_LNM_ALT_CODE(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_LNM_ALT…  argument
28293 #define XCVR_BRD_AGC_CTRL_1_LNM_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTR…  argument
28296 #define XCVR_WR_AGC_CTRL_1_LNM_ALT_CODE(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_LNM…  argument
28297 #define XCVR_BWR_AGC_CTRL_1_LNM_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint…  argument
28307 #define XCVR_RD_AGC_CTRL_1_LNM_USER_GAIN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_LNM_US…  argument
28308 #define XCVR_BRD_AGC_CTRL_1_LNM_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CT…  argument
28311 #define XCVR_WR_AGC_CTRL_1_LNM_USER_GAIN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_LN…  argument
28312 #define XCVR_BWR_AGC_CTRL_1_LNM_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uin…  argument
28322 #define XCVR_RD_AGC_CTRL_1_BBF_USER_GAIN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_BBF_US…  argument
28323 #define XCVR_BRD_AGC_CTRL_1_BBF_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CT…  argument
28326 #define XCVR_WR_AGC_CTRL_1_BBF_USER_GAIN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_BB…  argument
28327 #define XCVR_BWR_AGC_CTRL_1_BBF_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uin…  argument
28337 #define XCVR_RD_AGC_CTRL_1_USER_LNM_GAIN_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_USE…  argument
28338 #define XCVR_BRD_AGC_CTRL_1_USER_LNM_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC…  argument
28341 #define XCVR_WR_AGC_CTRL_1_USER_LNM_GAIN_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1…  argument
28342 #define XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((…  argument
28352 #define XCVR_RD_AGC_CTRL_1_USER_BBF_GAIN_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_USE…  argument
28353 #define XCVR_BRD_AGC_CTRL_1_USER_BBF_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC…  argument
28356 #define XCVR_WR_AGC_CTRL_1_USER_BBF_GAIN_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1…  argument
28357 #define XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((…  argument
28371 #define XCVR_RD_AGC_CTRL_1_PRESLOW_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_PRESLOW_E…  argument
28372 #define XCVR_BRD_AGC_CTRL_1_PRESLOW_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_…  argument
28375 #define XCVR_WR_AGC_CTRL_1_PRESLOW_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_PRESL…  argument
28376 #define XCVR_BWR_AGC_CTRL_1_PRESLOW_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32…  argument
28386 #define XCVR_RD_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1…  argument
28387 #define XCVR_BRD_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR…  argument
28390 #define XCVR_WR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CT…  argument
28391 #define XCVR_BWR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base)…  argument
28407 #define XCVR_RD_AGC_CTRL_2(base) (XCVR_AGC_CTRL_2_REG(base))  argument
28408 #define XCVR_WR_AGC_CTRL_2(base, value) (XCVR_AGC_CTRL_2_REG(base) = (value))  argument
28409 #define XCVR_RMW_AGC_CTRL_2(base, mask, value) (XCVR_WR_AGC_CTRL_2(base, (XCVR_RD_AGC_CTRL_2(base) …  argument
28410 #define XCVR_SET_AGC_CTRL_2(base, value) (BME_OR32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(value)))  argument
28411 #define XCVR_CLR_AGC_CTRL_2(base, value) (BME_AND32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(~(value)…  argument
28412 #define XCVR_TOG_AGC_CTRL_2(base, value) (BME_XOR32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(value)))  argument
28426 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_RST(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_BBF_PDE…  argument
28427 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTR…  argument
28430 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_RST(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_BBF…  argument
28431 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint…  argument
28441 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_RST(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_TZA_PDE…  argument
28442 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTR…  argument
28445 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_RST(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_TZA…  argument
28446 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint…  argument
28456 #define XCVR_RD_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2…  argument
28457 #define XCVR_BRD_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR…  argument
28460 #define XCVR_WR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CT…  argument
28461 #define XCVR_BWR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base)…  argument
28481 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_THRESH_LO(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_B…  argument
28482 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…  argument
28485 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_THRESH_LO(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL…  argument
28486 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …  argument
28506 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_THRESH_HI(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_B…  argument
28507 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…  argument
28510 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_THRESH_HI(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL…  argument
28511 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …  argument
28531 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_THRESH_LO(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_T…  argument
28532 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…  argument
28535 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_THRESH_LO(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL…  argument
28536 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …  argument
28556 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_THRESH_HI(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_T…  argument
28557 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_A…  argument
28560 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_THRESH_HI(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL…  argument
28561 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), …  argument
28571 #define XCVR_RD_AGC_CTRL_2_AGC_FAST_EXPIRE(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_AGC_…  argument
28572 #define XCVR_BRD_AGC_CTRL_2_AGC_FAST_EXPIRE(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_…  argument
28575 #define XCVR_WR_AGC_CTRL_2_AGC_FAST_EXPIRE(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_…  argument
28576 #define XCVR_BWR_AGC_CTRL_2_AGC_FAST_EXPIRE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((u…  argument
28592 #define XCVR_RD_AGC_CTRL_3(base) (XCVR_AGC_CTRL_3_REG(base))  argument
28593 #define XCVR_WR_AGC_CTRL_3(base, value) (XCVR_AGC_CTRL_3_REG(base) = (value))  argument
28594 #define XCVR_RMW_AGC_CTRL_3(base, mask, value) (XCVR_WR_AGC_CTRL_3(base, (XCVR_RD_AGC_CTRL_3(base) …  argument
28595 #define XCVR_SET_AGC_CTRL_3(base, value) (BME_OR32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(value)))  argument
28596 #define XCVR_CLR_AGC_CTRL_3(base, value) (BME_AND32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(~(value)…  argument
28597 #define XCVR_TOG_AGC_CTRL_3(base, value) (BME_XOR32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(value)))  argument
28611 #define XCVR_RD_AGC_CTRL_3_AGC_UNFREEZE_TIME(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AG…  argument
28612 #define XCVR_BRD_AGC_CTRL_3_AGC_UNFREEZE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AG…  argument
28615 #define XCVR_WR_AGC_CTRL_3_AGC_UNFREEZE_TIME(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_…  argument
28616 #define XCVR_BWR_AGC_CTRL_3_AGC_UNFREEZE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), (…  argument
28626 #define XCVR_RD_AGC_CTRL_3_AGC_PDET_LO_DLY(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_…  argument
28627 #define XCVR_BRD_AGC_CTRL_3_AGC_PDET_LO_DLY(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_…  argument
28630 #define XCVR_WR_AGC_CTRL_3_AGC_PDET_LO_DLY(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_…  argument
28631 #define XCVR_BWR_AGC_CTRL_3_AGC_PDET_LO_DLY(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((u…  argument
28641 #define XCVR_RD_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AG…  argument
28642 #define XCVR_BRD_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AG…  argument
28645 #define XCVR_WR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_…  argument
28646 #define XCVR_BWR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), (…  argument
28656 #define XCVR_RD_AGC_CTRL_3_AGC_H2S_STEP_SZ(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_…  argument
28657 #define XCVR_BRD_AGC_CTRL_3_AGC_H2S_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_…  argument
28660 #define XCVR_WR_AGC_CTRL_3_AGC_H2S_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_…  argument
28661 #define XCVR_BWR_AGC_CTRL_3_AGC_H2S_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((u…  argument
28671 #define XCVR_RD_AGC_CTRL_3_AGC_UP_STEP_SZ(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_U…  argument
28672 #define XCVR_BRD_AGC_CTRL_3_AGC_UP_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_C…  argument
28675 #define XCVR_WR_AGC_CTRL_3_AGC_UP_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_A…  argument
28676 #define XCVR_BWR_AGC_CTRL_3_AGC_UP_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((ui…  argument
28692 #define XCVR_RD_AGC_STAT(base)   (XCVR_AGC_STAT_REG(base))  argument
28706 #define XCVR_RD_AGC_STAT_BBF_PDET_LO_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_BBF_PDET_…  argument
28707 #define XCVR_BRD_AGC_STAT_BBF_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…  argument
28717 #define XCVR_RD_AGC_STAT_BBF_PDET_HI_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_BBF_PDET_…  argument
28718 #define XCVR_BRD_AGC_STAT_BBF_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…  argument
28728 #define XCVR_RD_AGC_STAT_TZA_PDET_LO_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_TZA_PDET_…  argument
28729 #define XCVR_BRD_AGC_STAT_TZA_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…  argument
28739 #define XCVR_RD_AGC_STAT_TZA_PDET_HI_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_TZA_PDET_…  argument
28740 #define XCVR_BRD_AGC_STAT_TZA_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STA…  argument
28750 #define XCVR_RD_AGC_STAT_CURR_AGC_IDX(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_CURR_AGC_IDX_…  argument
28751 #define XCVR_BRD_AGC_STAT_CURR_AGC_IDX(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_CU…  argument
28765 #define XCVR_RD_AGC_STAT_AGC_FROZEN(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_AGC_FROZEN_MASK…  argument
28766 #define XCVR_BRD_AGC_STAT_AGC_FROZEN(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_AGC_…  argument
28776 #define XCVR_RD_AGC_STAT_RSSI_ADC_RAW(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_RSSI_ADC_RAW_…  argument
28777 #define XCVR_BRD_AGC_STAT_RSSI_ADC_RAW(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_RS…  argument
28793 #define XCVR_RD_RSSI_CTRL_0(base) (XCVR_RSSI_CTRL_0_REG(base))  argument
28794 #define XCVR_WR_RSSI_CTRL_0(base, value) (XCVR_RSSI_CTRL_0_REG(base) = (value))  argument
28795 #define XCVR_RMW_RSSI_CTRL_0(base, mask, value) (XCVR_WR_RSSI_CTRL_0(base, (XCVR_RD_RSSI_CTRL_0(bas…  argument
28796 #define XCVR_SET_RSSI_CTRL_0(base, value) (BME_OR32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(value)))  argument
28797 #define XCVR_CLR_RSSI_CTRL_0(base, value) (BME_AND32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(~(valu…  argument
28798 #define XCVR_TOG_RSSI_CTRL_0(base, value) (BME_XOR32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(value)…  argument
28812 #define XCVR_RD_RSSI_CTRL_0_RSSI_USE_VALS(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSS…  argument
28813 #define XCVR_BRD_RSSI_CTRL_0_RSSI_USE_VALS(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI…  argument
28816 #define XCVR_WR_RSSI_CTRL_0_RSSI_USE_VALS(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0…  argument
28817 #define XCVR_BWR_RSSI_CTRL_0_RSSI_USE_VALS(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((u…  argument
28831 #define XCVR_RD_RSSI_CTRL_0_RSSI_HOLD_SRC(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSS…  argument
28832 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_SRC(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI…  argument
28835 #define XCVR_WR_RSSI_CTRL_0_RSSI_HOLD_SRC(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0…  argument
28836 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_SRC(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((u…  argument
28847 #define XCVR_RD_RSSI_CTRL_0_RSSI_HOLD_EN(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI…  argument
28848 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_…  argument
28851 #define XCVR_WR_RSSI_CTRL_0_RSSI_HOLD_EN(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_…  argument
28852 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((ui…  argument
28862 #define XCVR_RD_RSSI_CTRL_0_RSSI_DEC_EN(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_…  argument
28863 #define XCVR_BRD_RSSI_CTRL_0_RSSI_DEC_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_C…  argument
28866 #define XCVR_WR_RSSI_CTRL_0_RSSI_DEC_EN(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_R…  argument
28867 #define XCVR_BWR_RSSI_CTRL_0_RSSI_DEC_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uin…  argument
28881 #define XCVR_RD_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_…  argument
28882 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR…  argument
28885 #define XCVR_WR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_C…  argument
28886 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base)…  argument
28900 #define XCVR_RD_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_R…  argument
28901 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RS…  argument
28904 #define XCVR_WR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL…  argument
28905 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), (…  argument
28915 #define XCVR_RD_RSSI_CTRL_0_RSSI_ADJ(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_ADJ…  argument
28916 #define XCVR_BRD_RSSI_CTRL_0_RSSI_ADJ(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL…  argument
28919 #define XCVR_WR_RSSI_CTRL_0_RSSI_ADJ(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI…  argument
28920 #define XCVR_BWR_RSSI_CTRL_0_RSSI_ADJ(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32…  argument
28936 #define XCVR_RD_RSSI_CTRL_1(base) (XCVR_RSSI_CTRL_1_REG(base))  argument
28937 #define XCVR_WR_RSSI_CTRL_1(base, value) (XCVR_RSSI_CTRL_1_REG(base) = (value))  argument
28938 #define XCVR_RMW_RSSI_CTRL_1(base, mask, value) (XCVR_WR_RSSI_CTRL_1(base, (XCVR_RD_RSSI_CTRL_1(bas…  argument
28939 #define XCVR_SET_RSSI_CTRL_1(base, value) (BME_OR32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(value)))  argument
28940 #define XCVR_CLR_RSSI_CTRL_1(base, value) (BME_AND32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(~(valu…  argument
28941 #define XCVR_TOG_RSSI_CTRL_1(base, value) (BME_XOR32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(value)…  argument
28955 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH0(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_R…  argument
28956 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RS…  argument
28959 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH0(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL…  argument
28960 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), (…  argument
28970 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH1(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_R…  argument
28971 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RS…  argument
28974 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH1(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL…  argument
28975 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), (…  argument
28985 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1…  argument
28986 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_…  argument
28989 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CT…  argument
28990 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base),…  argument
29000 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1…  argument
29001 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_…  argument
29004 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CT…  argument
29005 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base),…  argument
29015 #define XCVR_RD_RSSI_CTRL_1_RSSI_OUT(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_OUT…  argument
29016 #define XCVR_BRD_RSSI_CTRL_1_RSSI_OUT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL…  argument
29032 #define XCVR_RD_DCOC_CTRL_0(base) (XCVR_DCOC_CTRL_0_REG(base))  argument
29033 #define XCVR_WR_DCOC_CTRL_0(base, value) (XCVR_DCOC_CTRL_0_REG(base) = (value))  argument
29034 #define XCVR_RMW_DCOC_CTRL_0(base, mask, value) (XCVR_WR_DCOC_CTRL_0(base, (XCVR_RD_DCOC_CTRL_0(bas…  argument
29035 #define XCVR_SET_DCOC_CTRL_0(base, value) (BME_OR32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(value)))  argument
29036 #define XCVR_CLR_DCOC_CTRL_0(base, value) (BME_AND32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(~(valu…  argument
29037 #define XCVR_TOG_DCOC_CTRL_0(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(value)…  argument
29053 #define XCVR_RD_DCOC_CTRL_0_DCOC_MAN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_MAN…  argument
29054 #define XCVR_BRD_DCOC_CTRL_0_DCOC_MAN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL…  argument
29057 #define XCVR_WR_DCOC_CTRL_0_DCOC_MAN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC…  argument
29058 #define XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32…  argument
29069 #define XCVR_RD_DCOC_CTRL_0_DCOC_TRACK_EN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCO…  argument
29070 #define XCVR_BRD_DCOC_CTRL_0_DCOC_TRACK_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC…  argument
29073 #define XCVR_WR_DCOC_CTRL_0_DCOC_TRACK_EN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0…  argument
29074 #define XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((u…  argument
29084 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORRECT_EN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_D…  argument
29085 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORRECT_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DC…  argument
29088 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORRECT_EN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL…  argument
29089 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORRECT_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), (…  argument
29106 #define XCVR_RD_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL…  argument
29107 #define XCVR_BRD_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCV…  argument
29110 #define XCVR_WR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_…  argument
29111 #define XCVR_BWR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base…  argument
29128 #define XCVR_RD_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CT…  argument
29129 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), X…  argument
29132 #define XCVR_WR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCO…  argument
29133 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(ba…  argument
29154 #define XCVR_RD_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CT…  argument
29155 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), X…  argument
29158 #define XCVR_WR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCO…  argument
29159 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(ba…  argument
29169 #define XCVR_RD_DCOC_CTRL_0_DCOC_CAL_DURATION(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0…  argument
29170 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CAL_DURATION(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_…  argument
29173 #define XCVR_WR_DCOC_CTRL_0_DCOC_CAL_DURATION(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CT…  argument
29174 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CAL_DURATION(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base),…  argument
29185 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORR_DLY(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCO…  argument
29186 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_DLY(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC…  argument
29189 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORR_DLY(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0…  argument
29190 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_DLY(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((u…  argument
29201 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL…  argument
29202 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCV…  argument
29205 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_…  argument
29206 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base…  argument
29222 #define XCVR_RD_DCOC_CTRL_1(base) (XCVR_DCOC_CTRL_1_REG(base))  argument
29223 #define XCVR_WR_DCOC_CTRL_1(base, value) (XCVR_DCOC_CTRL_1_REG(base) = (value))  argument
29224 #define XCVR_RMW_DCOC_CTRL_1(base, mask, value) (XCVR_WR_DCOC_CTRL_1(base, (XCVR_RD_DCOC_CTRL_1(bas…  argument
29225 #define XCVR_SET_DCOC_CTRL_1(base, value) (BME_OR32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(value)))  argument
29226 #define XCVR_CLR_DCOC_CTRL_1(base, value) (BME_AND32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(~(valu…  argument
29227 #define XCVR_TOG_DCOC_CTRL_1(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(value)…  argument
29245 #define XCVR_RD_DCOC_CTRL_1_BBF_DCOC_STEP(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_BBF…  argument
29246 #define XCVR_BRD_DCOC_CTRL_1_BBF_DCOC_STEP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC…  argument
29249 #define XCVR_WR_DCOC_CTRL_1_BBF_DCOC_STEP(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1…  argument
29250 #define XCVR_BWR_DCOC_CTRL_1_BBF_DCOC_STEP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((u…  argument
29265 #define XCVR_RD_DCOC_CTRL_1_TRACK_FROM_ZERO(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_T…  argument
29266 #define XCVR_BRD_DCOC_CTRL_1_TRACK_FROM_ZERO(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DC…  argument
29269 #define XCVR_WR_DCOC_CTRL_1_TRACK_FROM_ZERO(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL…  argument
29270 #define XCVR_BWR_DCOC_CTRL_1_TRACK_FROM_ZERO(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), (…  argument
29285 #define XCVR_RD_DCOC_CTRL_1_BBA_CORR_POL(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_BBA_…  argument
29286 #define XCVR_BRD_DCOC_CTRL_1_BBA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_…  argument
29289 #define XCVR_WR_DCOC_CTRL_1_BBA_CORR_POL(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_…  argument
29290 #define XCVR_BWR_DCOC_CTRL_1_BBA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((ui…  argument
29305 #define XCVR_RD_DCOC_CTRL_1_TZA_CORR_POL(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_TZA_…  argument
29306 #define XCVR_BRD_DCOC_CTRL_1_TZA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_…  argument
29309 #define XCVR_WR_DCOC_CTRL_1_TZA_CORR_POL(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_…  argument
29310 #define XCVR_BWR_DCOC_CTRL_1_TZA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((ui…  argument
29326 #define XCVR_RD_DCOC_CTRL_2(base) (XCVR_DCOC_CTRL_2_REG(base))  argument
29327 #define XCVR_WR_DCOC_CTRL_2(base, value) (XCVR_DCOC_CTRL_2_REG(base) = (value))  argument
29328 #define XCVR_RMW_DCOC_CTRL_2(base, mask, value) (XCVR_WR_DCOC_CTRL_2(base, (XCVR_RD_DCOC_CTRL_2(bas…  argument
29329 #define XCVR_SET_DCOC_CTRL_2(base, value) (BME_OR32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(value)))  argument
29330 #define XCVR_CLR_DCOC_CTRL_2(base, value) (BME_AND32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(~(valu…  argument
29331 #define XCVR_TOG_DCOC_CTRL_2(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(value)…  argument
29348 #define XCVR_RD_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base) ((XCVR_DCOC_CTRL_2_REG(base) & XCVR_DCOC_CTRL…  argument
29349 #define XCVR_BRD_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_2_REG(base), XCV…  argument
29352 #define XCVR_WR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base, value) (XCVR_RMW_DCOC_CTRL_2(base, XCVR_DCOC_…  argument
29353 #define XCVR_BWR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_2_REG(base…  argument
29369 #define XCVR_RD_DCOC_CTRL_3(base) (XCVR_DCOC_CTRL_3_REG(base))  argument
29370 #define XCVR_WR_DCOC_CTRL_3(base, value) (XCVR_DCOC_CTRL_3_REG(base) = (value))  argument
29371 #define XCVR_RMW_DCOC_CTRL_3(base, mask, value) (XCVR_WR_DCOC_CTRL_3(base, (XCVR_RD_DCOC_CTRL_3(bas…  argument
29372 #define XCVR_SET_DCOC_CTRL_3(base, value) (BME_OR32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(value)))  argument
29373 #define XCVR_CLR_DCOC_CTRL_3(base, value) (BME_AND32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(~(valu…  argument
29374 #define XCVR_TOG_DCOC_CTRL_3(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(value)…  argument
29388 #define XCVR_RD_DCOC_CTRL_3_BBF_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_B…  argument
29389 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…  argument
29392 #define XCVR_WR_DCOC_CTRL_3_BBF_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL…  argument
29393 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…  argument
29403 #define XCVR_RD_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_B…  argument
29404 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…  argument
29407 #define XCVR_WR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL…  argument
29408 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…  argument
29418 #define XCVR_RD_DCOC_CTRL_3_TZA_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_T…  argument
29419 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…  argument
29422 #define XCVR_WR_DCOC_CTRL_3_TZA_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL…  argument
29423 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…  argument
29433 #define XCVR_RD_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_T…  argument
29434 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DC…  argument
29437 #define XCVR_WR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL…  argument
29438 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), (…  argument
29454 #define XCVR_RD_DCOC_CTRL_4(base) (XCVR_DCOC_CTRL_4_REG(base))  argument
29455 #define XCVR_WR_DCOC_CTRL_4(base, value) (XCVR_DCOC_CTRL_4_REG(base) = (value))  argument
29456 #define XCVR_RMW_DCOC_CTRL_4(base, mask, value) (XCVR_WR_DCOC_CTRL_4(base, (XCVR_RD_DCOC_CTRL_4(bas…  argument
29457 #define XCVR_SET_DCOC_CTRL_4(base, value) (BME_OR32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(value)))  argument
29458 #define XCVR_CLR_DCOC_CTRL_4(base, value) (BME_AND32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(~(valu…  argument
29459 #define XCVR_TOG_DCOC_CTRL_4(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(value)…  argument
29474 #define XCVR_RD_DCOC_CTRL_4_DIG_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_4_REG(base) & XCVR_DCOC_CTRL_4_D…  argument
29475 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DC…  argument
29478 #define XCVR_WR_DCOC_CTRL_4_DIG_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_4(base, XCVR_DCOC_CTRL…  argument
29479 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), (…  argument
29490 #define XCVR_RD_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_4_REG(base) & XCVR_DCOC_CTRL_4_D…  argument
29491 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DC…  argument
29494 #define XCVR_WR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_4(base, XCVR_DCOC_CTRL…  argument
29495 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), (…  argument
29511 #define XCVR_RD_DCOC_CAL_GAIN(base) (XCVR_DCOC_CAL_GAIN_REG(base))  argument
29512 #define XCVR_WR_DCOC_CAL_GAIN(base, value) (XCVR_DCOC_CAL_GAIN_REG(base) = (value))  argument
29513 #define XCVR_RMW_DCOC_CAL_GAIN(base, mask, value) (XCVR_WR_DCOC_CAL_GAIN(base, (XCVR_RD_DCOC_CAL_GA…  argument
29514 #define XCVR_SET_DCOC_CAL_GAIN(base, value) (BME_OR32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(val…  argument
29515 #define XCVR_CLR_DCOC_CAL_GAIN(base, value) (BME_AND32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(~(…  argument
29516 #define XCVR_TOG_DCOC_CAL_GAIN(base, value) (BME_XOR32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(va…  argument
29531 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29532 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29535 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29536 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29547 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29548 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29551 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29552 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29563 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29564 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29567 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29568 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29579 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29580 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29583 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29584 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29595 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29596 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29599 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29600 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29611 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_C…  argument
29612 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), …  argument
29615 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DC…  argument
29616 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(b…  argument
29632 #define XCVR_RD_DCOC_STAT(base)  (XCVR_DCOC_STAT_REG(base))  argument
29649 #define XCVR_RD_DCOC_STAT_BBF_DCOC_I(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_BBF_DCOC_I_M…  argument
29650 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_B…  argument
29663 #define XCVR_RD_DCOC_STAT_BBF_DCOC_Q(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_BBF_DCOC_Q_M…  argument
29664 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_B…  argument
29677 #define XCVR_RD_DCOC_STAT_TZA_DCOC_I(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_TZA_DCOC_I_M…  argument
29678 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_T…  argument
29691 #define XCVR_RD_DCOC_STAT_TZA_DCOC_Q(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_TZA_DCOC_Q_M…  argument
29692 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_T…  argument
29708 #define XCVR_RD_DCOC_DC_EST(base) (XCVR_DCOC_DC_EST_REG(base))  argument
29723 #define XCVR_RD_DCOC_DC_EST_DC_EST_I(base) ((XCVR_DCOC_DC_EST_REG(base) & XCVR_DCOC_DC_EST_DC_EST_I…  argument
29724 #define XCVR_BRD_DCOC_DC_EST_DC_EST_I(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_E…  argument
29735 #define XCVR_RD_DCOC_DC_EST_DC_EST_Q(base) ((XCVR_DCOC_DC_EST_REG(base) & XCVR_DCOC_DC_EST_DC_EST_Q…  argument
29736 #define XCVR_BRD_DCOC_DC_EST_DC_EST_Q(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_E…  argument
29752 #define XCVR_RD_DCOC_CAL_RCP(base) (XCVR_DCOC_CAL_RCP_REG(base))  argument
29753 #define XCVR_WR_DCOC_CAL_RCP(base, value) (XCVR_DCOC_CAL_RCP_REG(base) = (value))  argument
29754 #define XCVR_RMW_DCOC_CAL_RCP(base, mask, value) (XCVR_WR_DCOC_CAL_RCP(base, (XCVR_RD_DCOC_CAL_RCP(…  argument
29755 #define XCVR_SET_DCOC_CAL_RCP(base, value) (BME_OR32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(value…  argument
29756 #define XCVR_CLR_DCOC_CAL_RCP(base, value) (BME_AND32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(~(va…  argument
29757 #define XCVR_TOG_DCOC_CAL_RCP(base, value) (BME_XOR32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(valu…  argument
29773 #define XCVR_RD_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base) ((XCVR_DCOC_CAL_RCP_REG(base) & XCVR_DCOC_CA…  argument
29774 #define XCVR_BRD_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), X…  argument
29777 #define XCVR_WR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base, value) (XCVR_RMW_DCOC_CAL_RCP(base, XCVR_DCO…  argument
29778 #define XCVR_BWR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(ba…  argument
29791 #define XCVR_RD_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base) ((XCVR_DCOC_CAL_RCP_REG(base) & XCVR_DCOC_CAL_R…  argument
29792 #define XCVR_BRD_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), XCVR…  argument
29795 #define XCVR_WR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base, value) (XCVR_RMW_DCOC_CAL_RCP(base, XCVR_DCOC_C…  argument
29796 #define XCVR_BWR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(base)…  argument
29812 #define XCVR_RD_IQMC_CTRL(base)  (XCVR_IQMC_CTRL_REG(base))  argument
29813 #define XCVR_WR_IQMC_CTRL(base, value) (XCVR_IQMC_CTRL_REG(base) = (value))  argument
29814 #define XCVR_RMW_IQMC_CTRL(base, mask, value) (XCVR_WR_IQMC_CTRL(base, (XCVR_RD_IQMC_CTRL(base) & ~…  argument
29815 #define XCVR_SET_IQMC_CTRL(base, value) (BME_OR32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(value)))  argument
29816 #define XCVR_CLR_IQMC_CTRL(base, value) (BME_AND32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(~(value))))  argument
29817 #define XCVR_TOG_IQMC_CTRL(base, value) (BME_XOR32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(value)))  argument
29831 #define XCVR_RD_IQMC_CTRL_IQMC_CAL_EN(base) ((XCVR_IQMC_CTRL_REG(base) & XCVR_IQMC_CTRL_IQMC_CAL_EN…  argument
29832 #define XCVR_BRD_IQMC_CTRL_IQMC_CAL_EN(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTRL_…  argument
29835 #define XCVR_WR_IQMC_CTRL_IQMC_CAL_EN(base, value) (XCVR_RMW_IQMC_CTRL(base, XCVR_IQMC_CTRL_IQMC_CA…  argument
29836 #define XCVR_BWR_IQMC_CTRL_IQMC_CAL_EN(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint32_…  argument
29846 #define XCVR_RD_IQMC_CTRL_IQMC_NUM_ITER(base) ((XCVR_IQMC_CTRL_REG(base) & XCVR_IQMC_CTRL_IQMC_NUM_…  argument
29847 #define XCVR_BRD_IQMC_CTRL_IQMC_NUM_ITER(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTR…  argument
29850 #define XCVR_WR_IQMC_CTRL_IQMC_NUM_ITER(base, value) (XCVR_RMW_IQMC_CTRL(base, XCVR_IQMC_CTRL_IQMC_…  argument
29851 #define XCVR_BWR_IQMC_CTRL_IQMC_NUM_ITER(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint3…  argument
29867 #define XCVR_RD_IQMC_CAL(base)   (XCVR_IQMC_CAL_REG(base))  argument
29868 #define XCVR_WR_IQMC_CAL(base, value) (XCVR_IQMC_CAL_REG(base) = (value))  argument
29869 #define XCVR_RMW_IQMC_CAL(base, mask, value) (XCVR_WR_IQMC_CAL(base, (XCVR_RD_IQMC_CAL(base) & ~(ma…  argument
29870 #define XCVR_SET_IQMC_CAL(base, value) (BME_OR32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(value)))  argument
29871 #define XCVR_CLR_IQMC_CAL(base, value) (BME_AND32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(~(value))))  argument
29872 #define XCVR_TOG_IQMC_CAL(base, value) (BME_XOR32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(value)))  argument
29886 #define XCVR_RD_IQMC_CAL_IQMC_GAIN_ADJ(base) ((XCVR_IQMC_CAL_REG(base) & XCVR_IQMC_CAL_IQMC_GAIN_AD…  argument
29887 #define XCVR_BRD_IQMC_CAL_IQMC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_I…  argument
29890 #define XCVR_WR_IQMC_CAL_IQMC_GAIN_ADJ(base, value) (XCVR_RMW_IQMC_CAL(base, XCVR_IQMC_CAL_IQMC_GAI…  argument
29891 #define XCVR_BWR_IQMC_CAL_IQMC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32_…  argument
29901 #define XCVR_RD_IQMC_CAL_IQMC_PHASE_ADJ(base) ((XCVR_IQMC_CAL_REG(base) & XCVR_IQMC_CAL_IQMC_PHASE_…  argument
29902 #define XCVR_BRD_IQMC_CAL_IQMC_PHASE_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_…  argument
29905 #define XCVR_WR_IQMC_CAL_IQMC_PHASE_ADJ(base, value) (XCVR_RMW_IQMC_CAL(base, XCVR_IQMC_CAL_IQMC_PH…  argument
29906 #define XCVR_BWR_IQMC_CAL_IQMC_PHASE_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32…  argument
29922 #define XCVR_RD_TCA_AGC_VAL_3_0(base) (XCVR_TCA_AGC_VAL_3_0_REG(base))  argument
29923 #define XCVR_WR_TCA_AGC_VAL_3_0(base, value) (XCVR_TCA_AGC_VAL_3_0_REG(base) = (value))  argument
29924 #define XCVR_RMW_TCA_AGC_VAL_3_0(base, mask, value) (XCVR_WR_TCA_AGC_VAL_3_0(base, (XCVR_RD_TCA_AGC…  argument
29925 #define XCVR_SET_TCA_AGC_VAL_3_0(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t)…  argument
29926 #define XCVR_CLR_TCA_AGC_VAL_3_0(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t…  argument
29927 #define XCVR_TOG_TCA_AGC_VAL_3_0(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t…  argument
29941 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC…  argument
29942 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…  argument
29945 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA…  argument
29946 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…  argument
29956 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC…  argument
29957 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…  argument
29960 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA…  argument
29961 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…  argument
29971 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC…  argument
29972 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…  argument
29975 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA…  argument
29976 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…  argument
29986 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC…  argument
29987 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), X…  argument
29990 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA…  argument
29991 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(ba…  argument
30007 #define XCVR_RD_TCA_AGC_VAL_7_4(base) (XCVR_TCA_AGC_VAL_7_4_REG(base))  argument
30008 #define XCVR_WR_TCA_AGC_VAL_7_4(base, value) (XCVR_TCA_AGC_VAL_7_4_REG(base) = (value))  argument
30009 #define XCVR_RMW_TCA_AGC_VAL_7_4(base, mask, value) (XCVR_WR_TCA_AGC_VAL_7_4(base, (XCVR_RD_TCA_AGC…  argument
30010 #define XCVR_SET_TCA_AGC_VAL_7_4(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t)…  argument
30011 #define XCVR_CLR_TCA_AGC_VAL_7_4(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t…  argument
30012 #define XCVR_TOG_TCA_AGC_VAL_7_4(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t…  argument
30026 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC…  argument
30027 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…  argument
30030 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA…  argument
30031 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…  argument
30041 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC…  argument
30042 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…  argument
30045 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA…  argument
30046 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…  argument
30056 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC…  argument
30057 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…  argument
30060 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA…  argument
30061 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…  argument
30071 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC…  argument
30072 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), X…  argument
30075 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA…  argument
30076 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(ba…  argument
30092 #define XCVR_RD_TCA_AGC_VAL_8(base) (XCVR_TCA_AGC_VAL_8_REG(base))  argument
30093 #define XCVR_WR_TCA_AGC_VAL_8(base, value) (XCVR_TCA_AGC_VAL_8_REG(base) = (value))  argument
30094 #define XCVR_RMW_TCA_AGC_VAL_8(base, mask, value) (XCVR_WR_TCA_AGC_VAL_8(base, (XCVR_RD_TCA_AGC_VAL…  argument
30095 #define XCVR_SET_TCA_AGC_VAL_8(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(val…  argument
30096 #define XCVR_CLR_TCA_AGC_VAL_8(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(~(…  argument
30097 #define XCVR_TOG_TCA_AGC_VAL_8(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(va…  argument
30111 #define XCVR_RD_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base) ((XCVR_TCA_AGC_VAL_8_REG(base) & XCVR_TCA_AGC_VAL…  argument
30112 #define XCVR_BRD_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_8_REG(base), XCVR_…  argument
30115 #define XCVR_WR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base, value) (XCVR_RMW_TCA_AGC_VAL_8(base, XCVR_TCA_AGC…  argument
30116 #define XCVR_BWR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_8_REG(base),…  argument
30132 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0(base) (XCVR_BBF_RES_TUNE_VAL_7_0_REG(base))  argument
30133 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0(base, value) (XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) = (value))  argument
30134 #define XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_7_0(base, (XCVR_…  argument
30135 #define XCVR_SET_BBF_RES_TUNE_VAL_7_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), …  argument
30136 #define XCVR_CLR_BBF_RES_TUNE_VAL_7_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base),…  argument
30137 #define XCVR_TOG_BBF_RES_TUNE_VAL_7_0(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base),…  argument
30151 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30152 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30155 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30156 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30166 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30167 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30170 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30171 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30181 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30182 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30185 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30186 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30196 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30197 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30200 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30201 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30211 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30212 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30215 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30216 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30226 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30227 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30230 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30231 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30241 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30242 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30245 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30246 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30256 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base)…  argument
30257 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7…  argument
30260 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0…  argument
30261 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE…  argument
30277 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8(base) (XCVR_BBF_RES_TUNE_VAL_10_8_REG(base))  argument
30278 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8(base, value) (XCVR_BBF_RES_TUNE_VAL_10_8_REG(base) = (value))  argument
30279 #define XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_10_8(base, (XCV…  argument
30280 #define XCVR_SET_BBF_RES_TUNE_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base)…  argument
30281 #define XCVR_CLR_BBF_RES_TUNE_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base…  argument
30282 #define XCVR_TOG_BBF_RES_TUNE_VAL_10_8(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base…  argument
30296 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(bas…  argument
30297 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_…  argument
30300 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_10…  argument
30301 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base, value) (BME_BFI32(&XCVR_BBF_RES_TUN…  argument
30311 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(bas…  argument
30312 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_…  argument
30315 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_10…  argument
30316 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base, value) (BME_BFI32(&XCVR_BBF_RES_TUN…  argument
30326 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(ba…  argument
30327 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL…  argument
30330 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_1…  argument
30331 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base, value) (BME_BFI32(&XCVR_BBF_RES_TU…  argument
30347 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0(base) (XCVR_TCA_AGC_LIN_VAL_2_0_REG(base))  argument
30348 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0(base, value) (XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) = (value))  argument
30349 #define XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_2_0(base, (XCVR_RD…  argument
30350 #define XCVR_SET_TCA_AGC_LIN_VAL_2_0(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (u…  argument
30351 #define XCVR_CLR_TCA_AGC_LIN_VAL_2_0(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (…  argument
30352 #define XCVR_TOG_TCA_AGC_LIN_VAL_2_0(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (…  argument
30366 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & …  argument
30367 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…  argument
30370 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(ba…  argument
30371 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30382 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & …  argument
30383 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…  argument
30386 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(ba…  argument
30387 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30398 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & …  argument
30399 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_…  argument
30402 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(ba…  argument
30403 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30419 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3(base) (XCVR_TCA_AGC_LIN_VAL_5_3_REG(base))  argument
30420 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3(base, value) (XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) = (value))  argument
30421 #define XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_5_3(base, (XCVR_RD…  argument
30422 #define XCVR_SET_TCA_AGC_LIN_VAL_5_3(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (u…  argument
30423 #define XCVR_CLR_TCA_AGC_LIN_VAL_5_3(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (…  argument
30424 #define XCVR_TOG_TCA_AGC_LIN_VAL_5_3(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (…  argument
30439 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & …  argument
30440 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…  argument
30443 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(ba…  argument
30444 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30455 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & …  argument
30456 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…  argument
30459 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(ba…  argument
30460 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30471 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & …  argument
30472 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_…  argument
30475 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(ba…  argument
30476 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30492 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6(base) (XCVR_TCA_AGC_LIN_VAL_8_6_REG(base))  argument
30493 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6(base, value) (XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) = (value))  argument
30494 #define XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_8_6(base, (XCVR_RD…  argument
30495 #define XCVR_SET_TCA_AGC_LIN_VAL_8_6(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (u…  argument
30496 #define XCVR_CLR_TCA_AGC_LIN_VAL_8_6(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (…  argument
30497 #define XCVR_TOG_TCA_AGC_LIN_VAL_8_6(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (…  argument
30512 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & …  argument
30513 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…  argument
30516 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(ba…  argument
30517 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30528 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & …  argument
30529 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…  argument
30532 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(ba…  argument
30533 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30544 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & …  argument
30545 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_…  argument
30548 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(ba…  argument
30549 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VA…  argument
30565 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0(base) (XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base))  argument
30566 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) = (v…  argument
30567 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0(base…  argument
30568 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG…  argument
30569 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_RE…  argument
30570 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_RE…  argument
30585 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3…  argument
30586 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30589 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30590 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30601 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3…  argument
30602 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30605 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30606 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30617 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3…  argument
30618 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30621 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30622 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30633 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3…  argument
30634 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30637 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30638 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30654 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4(base) (XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base))  argument
30655 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) = (v…  argument
30656 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4(base…  argument
30657 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG…  argument
30658 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_RE…  argument
30659 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_RE…  argument
30674 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7…  argument
30675 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30678 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30679 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30690 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7…  argument
30691 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30694 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30695 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30706 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7…  argument
30707 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30710 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30711 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30722 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7…  argument
30723 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TU…  argument
30726 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base, value) (XCVR_RMW_BBF_RES_TUNE…  argument
30727 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_…  argument
30743 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8(base) (XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base))  argument
30744 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base) = …  argument
30745 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8(ba…  argument
30746 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_R…  argument
30747 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_…  argument
30748 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_…  argument
30763 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_…  argument
30764 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_T…  argument
30767 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base, value) (XCVR_RMW_BBF_RES_TUN…  argument
30768 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_BBF…  argument
30779 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_…  argument
30780 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_T…  argument
30783 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base, value) (XCVR_RMW_BBF_RES_TUN…  argument
30784 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base, value) (BME_BFI32(&XCVR_BBF…  argument
30795 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base) ((XCVR_BBF_RES_TUNE_LIN_VAL…  argument
30796 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_…  argument
30799 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base, value) (XCVR_RMW_BBF_RES_TU…  argument
30800 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base, value) (BME_BFI32(&XCVR_BB…  argument
30816 #define XCVR_RD_AGC_GAIN_TBL_03_00(base) (XCVR_AGC_GAIN_TBL_03_00_REG(base))  argument
30817 #define XCVR_WR_AGC_GAIN_TBL_03_00(base, value) (XCVR_AGC_GAIN_TBL_03_00_REG(base) = (value))  argument
30818 #define XCVR_RMW_AGC_GAIN_TBL_03_00(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_03_00(base, (XCVR_RD_A…  argument
30819 #define XCVR_SET_AGC_GAIN_TBL_03_00(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (uin…  argument
30820 #define XCVR_CLR_AGC_GAIN_TBL_03_00(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (ui…  argument
30821 #define XCVR_TOG_AGC_GAIN_TBL_03_00(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (ui…  argument
30835 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30836 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30839 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30840 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30850 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30851 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30854 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30855 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30865 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30866 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30869 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30870 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30880 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30881 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30884 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30885 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30895 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30896 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30899 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30900 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30910 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30911 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30914 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30915 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30925 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30926 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30929 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30930 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30940 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC…  argument
30941 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base…  argument
30944 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR…  argument
30945 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_RE…  argument
30961 #define XCVR_RD_AGC_GAIN_TBL_07_04(base) (XCVR_AGC_GAIN_TBL_07_04_REG(base))  argument
30962 #define XCVR_WR_AGC_GAIN_TBL_07_04(base, value) (XCVR_AGC_GAIN_TBL_07_04_REG(base) = (value))  argument
30963 #define XCVR_RMW_AGC_GAIN_TBL_07_04(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_07_04(base, (XCVR_RD_A…  argument
30964 #define XCVR_SET_AGC_GAIN_TBL_07_04(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (uin…  argument
30965 #define XCVR_CLR_AGC_GAIN_TBL_07_04(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (ui…  argument
30966 #define XCVR_TOG_AGC_GAIN_TBL_07_04(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (ui…  argument
30980 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
30981 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
30984 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
30985 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
30995 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
30996 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
30999 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31000 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31010 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31011 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31014 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31015 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31025 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31026 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31029 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31030 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31040 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31041 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31044 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31045 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31055 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31056 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31059 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31060 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31070 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31071 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31074 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31075 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31085 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC…  argument
31086 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base…  argument
31089 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR…  argument
31090 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_RE…  argument
31106 #define XCVR_RD_AGC_GAIN_TBL_11_08(base) (XCVR_AGC_GAIN_TBL_11_08_REG(base))  argument
31107 #define XCVR_WR_AGC_GAIN_TBL_11_08(base, value) (XCVR_AGC_GAIN_TBL_11_08_REG(base) = (value))  argument
31108 #define XCVR_RMW_AGC_GAIN_TBL_11_08(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_11_08(base, (XCVR_RD_A…  argument
31109 #define XCVR_SET_AGC_GAIN_TBL_11_08(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (uin…  argument
31110 #define XCVR_CLR_AGC_GAIN_TBL_11_08(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (ui…  argument
31111 #define XCVR_TOG_AGC_GAIN_TBL_11_08(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (ui…  argument
31125 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31126 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31129 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31130 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31140 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31141 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31144 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31145 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31155 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31156 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31159 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31160 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31170 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31171 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31174 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31175 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31185 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31186 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31189 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31190 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31200 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31201 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31204 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31205 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31215 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31216 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31219 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31220 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31230 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC…  argument
31231 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base…  argument
31234 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR…  argument
31235 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_RE…  argument
31251 #define XCVR_RD_AGC_GAIN_TBL_15_12(base) (XCVR_AGC_GAIN_TBL_15_12_REG(base))  argument
31252 #define XCVR_WR_AGC_GAIN_TBL_15_12(base, value) (XCVR_AGC_GAIN_TBL_15_12_REG(base) = (value))  argument
31253 #define XCVR_RMW_AGC_GAIN_TBL_15_12(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_15_12(base, (XCVR_RD_A…  argument
31254 #define XCVR_SET_AGC_GAIN_TBL_15_12(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (uin…  argument
31255 #define XCVR_CLR_AGC_GAIN_TBL_15_12(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (ui…  argument
31256 #define XCVR_TOG_AGC_GAIN_TBL_15_12(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (ui…  argument
31270 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31271 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31274 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31275 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31285 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31286 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31289 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31290 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31300 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31301 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31304 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31305 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31315 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31316 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31319 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31320 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31330 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31331 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31334 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31335 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31345 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31346 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31349 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31350 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31360 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31361 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31364 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31365 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31375 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC…  argument
31376 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base…  argument
31379 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR…  argument
31380 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_RE…  argument
31396 #define XCVR_RD_AGC_GAIN_TBL_19_16(base) (XCVR_AGC_GAIN_TBL_19_16_REG(base))  argument
31397 #define XCVR_WR_AGC_GAIN_TBL_19_16(base, value) (XCVR_AGC_GAIN_TBL_19_16_REG(base) = (value))  argument
31398 #define XCVR_RMW_AGC_GAIN_TBL_19_16(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_19_16(base, (XCVR_RD_A…  argument
31399 #define XCVR_SET_AGC_GAIN_TBL_19_16(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (uin…  argument
31400 #define XCVR_CLR_AGC_GAIN_TBL_19_16(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (ui…  argument
31401 #define XCVR_TOG_AGC_GAIN_TBL_19_16(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (ui…  argument
31415 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31416 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31419 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31420 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31430 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31431 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31434 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31435 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31445 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31446 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31449 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31450 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31460 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31461 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31464 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31465 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31475 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31476 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31479 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31480 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31490 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31491 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31494 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31495 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31505 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31506 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31509 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31510 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31520 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC…  argument
31521 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base…  argument
31524 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR…  argument
31525 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_RE…  argument
31541 #define XCVR_RD_AGC_GAIN_TBL_23_20(base) (XCVR_AGC_GAIN_TBL_23_20_REG(base))  argument
31542 #define XCVR_WR_AGC_GAIN_TBL_23_20(base, value) (XCVR_AGC_GAIN_TBL_23_20_REG(base) = (value))  argument
31543 #define XCVR_RMW_AGC_GAIN_TBL_23_20(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_23_20(base, (XCVR_RD_A…  argument
31544 #define XCVR_SET_AGC_GAIN_TBL_23_20(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (uin…  argument
31545 #define XCVR_CLR_AGC_GAIN_TBL_23_20(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (ui…  argument
31546 #define XCVR_TOG_AGC_GAIN_TBL_23_20(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (ui…  argument
31560 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31561 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31564 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31565 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31575 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31576 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31579 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31580 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31590 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31591 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31594 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31595 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31605 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31606 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31609 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31610 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31620 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31621 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31624 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31625 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31635 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31636 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31639 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31640 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31650 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31651 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31654 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31655 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31665 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC…  argument
31666 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base…  argument
31669 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR…  argument
31670 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_RE…  argument
31686 #define XCVR_RD_AGC_GAIN_TBL_26_24(base) (XCVR_AGC_GAIN_TBL_26_24_REG(base))  argument
31687 #define XCVR_WR_AGC_GAIN_TBL_26_24(base, value) (XCVR_AGC_GAIN_TBL_26_24_REG(base) = (value))  argument
31688 #define XCVR_RMW_AGC_GAIN_TBL_26_24(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_26_24(base, (XCVR_RD_A…  argument
31689 #define XCVR_SET_AGC_GAIN_TBL_26_24(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (uin…  argument
31690 #define XCVR_CLR_AGC_GAIN_TBL_26_24(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (ui…  argument
31691 #define XCVR_TOG_AGC_GAIN_TBL_26_24(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (ui…  argument
31705 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31706 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31709 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31710 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31720 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31721 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31724 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31725 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31735 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31736 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31739 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31740 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31750 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31751 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31754 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31755 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31765 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31766 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31769 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31770 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31780 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC…  argument
31781 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base…  argument
31784 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR…  argument
31785 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_RE…  argument
31801 #define XCVR_RD_DCOC_OFFSET_(base, index) (XCVR_DCOC_OFFSET__REG(base, index))  argument
31802 #define XCVR_WR_DCOC_OFFSET_(base, index, value) (XCVR_DCOC_OFFSET__REG(base, index) = (value))  argument
31803 #define XCVR_RMW_DCOC_OFFSET_(base, index, mask, value) (XCVR_WR_DCOC_OFFSET_(base, index, (XCVR_RD…  argument
31804 #define XCVR_SET_DCOC_OFFSET_(base, index, value) (BME_OR32(&XCVR_DCOC_OFFSET__REG(base, index), (u…  argument
31805 #define XCVR_CLR_DCOC_OFFSET_(base, index, value) (BME_AND32(&XCVR_DCOC_OFFSET__REG(base, index), (…  argument
31806 #define XCVR_TOG_DCOC_OFFSET_(base, index, value) (BME_XOR32(&XCVR_DCOC_OFFSET__REG(base, index), (…  argument
31822 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31823 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31826 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31827 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31839 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31840 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31843 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31844 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31856 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31857 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31860 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31861 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31873 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & …  argument
31874 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(bas…  argument
31877 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, ind…  argument
31878 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__R…  argument
31894 #define XCVR_RD_DCOC_TZA_STEP_(base, index) (XCVR_DCOC_TZA_STEP__REG(base, index))  argument
31895 #define XCVR_WR_DCOC_TZA_STEP_(base, index, value) (XCVR_DCOC_TZA_STEP__REG(base, index) = (value))  argument
31896 #define XCVR_RMW_DCOC_TZA_STEP_(base, index, mask, value) (XCVR_WR_DCOC_TZA_STEP_(base, index, (XCV…  argument
31897 #define XCVR_SET_DCOC_TZA_STEP_(base, index, value) (BME_OR32(&XCVR_DCOC_TZA_STEP__REG(base, index)…  argument
31898 #define XCVR_CLR_DCOC_TZA_STEP_(base, index, value) (BME_AND32(&XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31899 #define XCVR_TOG_DCOC_TZA_STEP_(base, index, value) (BME_XOR32(&XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31916 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, index…  argument
31917 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__REG…  argument
31920 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base,…  argument
31921 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_STE…  argument
31936 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, inde…  argument
31937 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__RE…  argument
31940 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base…  argument
31941 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_ST…  argument
31957 #define XCVR_RD_DCOC_CAL_ALPHA(base) (XCVR_DCOC_CAL_ALPHA_REG(base))  argument
31973 #define XCVR_RD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(base) ((XCVR_DCOC_CAL_ALPHA_REG(base) & XCVR_DCOC_C…  argument
31974 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), …  argument
31986 #define XCVR_RD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(base) ((XCVR_DCOC_CAL_ALPHA_REG(base) & XCVR_DCOC_C…  argument
31987 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), …  argument
32003 #define XCVR_RD_DCOC_CAL_BETA(base) (XCVR_DCOC_CAL_BETA_REG(base))  argument
32019 #define XCVR_RD_DCOC_CAL_BETA_DCOC_CAL_BETA_I(base) ((XCVR_DCOC_CAL_BETA_REG(base) & XCVR_DCOC_CAL_…  argument
32020 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCV…  argument
32032 #define XCVR_RD_DCOC_CAL_BETA_DCOC_CAL_BETA_Q(base) ((XCVR_DCOC_CAL_BETA_REG(base) & XCVR_DCOC_CAL_…  argument
32033 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCV…  argument
32049 #define XCVR_RD_DCOC_CAL_GAMMA(base) (XCVR_DCOC_CAL_GAMMA_REG(base))  argument
32065 #define XCVR_RD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(base) ((XCVR_DCOC_CAL_GAMMA_REG(base) & XCVR_DCOC_C…  argument
32066 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), …  argument
32078 #define XCVR_RD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(base) ((XCVR_DCOC_CAL_GAMMA_REG(base) & XCVR_DCOC_C…  argument
32079 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), …  argument
32095 #define XCVR_RD_DCOC_CAL_IIR(base) (XCVR_DCOC_CAL_IIR_REG(base))  argument
32096 #define XCVR_WR_DCOC_CAL_IIR(base, value) (XCVR_DCOC_CAL_IIR_REG(base) = (value))  argument
32097 #define XCVR_RMW_DCOC_CAL_IIR(base, mask, value) (XCVR_WR_DCOC_CAL_IIR(base, (XCVR_RD_DCOC_CAL_IIR(…  argument
32098 #define XCVR_SET_DCOC_CAL_IIR(base, value) (BME_OR32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(value…  argument
32099 #define XCVR_CLR_DCOC_CAL_IIR(base, value) (BME_AND32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(~(va…  argument
32100 #define XCVR_TOG_DCOC_CAL_IIR(base, value) (BME_XOR32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(valu…  argument
32119 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL…  argument
32120 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…  argument
32123 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC…  argument
32124 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…  argument
32139 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL…  argument
32140 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…  argument
32143 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC…  argument
32144 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…  argument
32159 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL…  argument
32160 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XC…  argument
32163 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC…  argument
32164 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(bas…  argument
32182 #define XCVR_RD_DCOC_CAL(base, index) (XCVR_DCOC_CAL_REG(base, index))  argument
32198 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_I(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_C…  argument
32199 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_I(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …  argument
32211 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_C…  argument
32212 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), …  argument
32230 #define XCVR_RD_RX_CHF_COEF(base, index) (XCVR_RX_CHF_COEF_REG(base, index))  argument
32231 #define XCVR_WR_RX_CHF_COEF(base, index, value) (XCVR_RX_CHF_COEF_REG(base, index) = (value))  argument
32232 #define XCVR_RMW_RX_CHF_COEF(base, index, mask, value) (XCVR_WR_RX_CHF_COEF(base, index, (XCVR_RD_R…  argument
32233 #define XCVR_SET_RX_CHF_COEF(base, index, value) (BME_OR32(&XCVR_RX_CHF_COEF_REG(base, index), (uin…  argument
32234 #define XCVR_CLR_RX_CHF_COEF(base, index, value) (BME_AND32(&XCVR_RX_CHF_COEF_REG(base, index), (ui…  argument
32235 #define XCVR_TOG_RX_CHF_COEF(base, index, value) (BME_XOR32(&XCVR_RX_CHF_COEF_REG(base, index), (ui…  argument
32249 #define XCVR_RD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) ((XCVR_RX_CHF_COEF_REG(base, index) & XCVR_R…  argument
32250 #define XCVR_BRD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) (BME_UBFX32(&XCVR_RX_CHF_COEF_REG(base, ind…  argument
32253 #define XCVR_WR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (XCVR_RMW_RX_CHF_COEF(base, index, XC…  argument
32254 #define XCVR_BWR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (BME_BFI32(&XCVR_RX_CHF_COEF_REG(bas…  argument
32270 #define XCVR_RD_TX_DIG_CTRL(base) (XCVR_TX_DIG_CTRL_REG(base))  argument
32271 #define XCVR_WR_TX_DIG_CTRL(base, value) (XCVR_TX_DIG_CTRL_REG(base) = (value))  argument
32272 #define XCVR_RMW_TX_DIG_CTRL(base, mask, value) (XCVR_WR_TX_DIG_CTRL(base, (XCVR_RD_TX_DIG_CTRL(bas…  argument
32273 #define XCVR_SET_TX_DIG_CTRL(base, value) (BME_OR32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(value)))  argument
32274 #define XCVR_CLR_TX_DIG_CTRL(base, value) (BME_AND32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(~(valu…  argument
32275 #define XCVR_TOG_TX_DIG_CTRL(base, value) (BME_XOR32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(value)…  argument
32313 #define XCVR_RD_TX_DIG_CTRL_DFT_MODE(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_MODE…  argument
32314 #define XCVR_BRD_TX_DIG_CTRL_DFT_MODE(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CT…  argument
32317 #define XCVR_WR_TX_DIG_CTRL_DFT_MODE(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_…  argument
32318 #define XCVR_BWR_TX_DIG_CTRL_DFT_MODE(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32…  argument
32329 #define XCVR_RD_TX_DIG_CTRL_DFT_EN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_EN_MAS…  argument
32330 #define XCVR_BRD_TX_DIG_CTRL_DFT_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL…  argument
32333 #define XCVR_WR_TX_DIG_CTRL_DFT_EN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_EN…  argument
32334 #define XCVR_BWR_TX_DIG_CTRL_DFT_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t…  argument
32355 #define XCVR_RD_TX_DIG_CTRL_DFT_LFSR_LEN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_…  argument
32356 #define XCVR_BRD_TX_DIG_CTRL_DFT_LFSR_LEN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DI…  argument
32359 #define XCVR_WR_TX_DIG_CTRL_DFT_LFSR_LEN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_…  argument
32360 #define XCVR_BWR_TX_DIG_CTRL_DFT_LFSR_LEN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((ui…  argument
32374 #define XCVR_RD_TX_DIG_CTRL_LFSR_EN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_LFSR_EN_M…  argument
32375 #define XCVR_BRD_TX_DIG_CTRL_LFSR_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTR…  argument
32378 #define XCVR_WR_TX_DIG_CTRL_LFSR_EN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_LFSR_…  argument
32379 #define XCVR_BWR_TX_DIG_CTRL_LFSR_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_…  argument
32400 #define XCVR_RD_TX_DIG_CTRL_DFT_CLK_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_C…  argument
32401 #define XCVR_BRD_TX_DIG_CTRL_DFT_CLK_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG…  argument
32404 #define XCVR_WR_TX_DIG_CTRL_DFT_CLK_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_D…  argument
32405 #define XCVR_BWR_TX_DIG_CTRL_DFT_CLK_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uin…  argument
32426 #define XCVR_RD_TX_DIG_CTRL_TONE_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_TONE_SEL…  argument
32427 #define XCVR_BRD_TX_DIG_CTRL_TONE_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CT…  argument
32430 #define XCVR_WR_TX_DIG_CTRL_TONE_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_TONE…  argument
32431 #define XCVR_BWR_TX_DIG_CTRL_TONE_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32…  argument
32449 #define XCVR_RD_TX_DIG_CTRL_POL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_POL_MASK) >> …  argument
32450 #define XCVR_BRD_TX_DIG_CTRL_POL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_PO…  argument
32453 #define XCVR_WR_TX_DIG_CTRL_POL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_POL_MASK,…  argument
32454 #define XCVR_BWR_TX_DIG_CTRL_POL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(v…  argument
32475 #define XCVR_RD_TX_DIG_CTRL_DP_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DP_SEL_MAS…  argument
32476 #define XCVR_BRD_TX_DIG_CTRL_DP_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL…  argument
32479 #define XCVR_WR_TX_DIG_CTRL_DP_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DP_SEL…  argument
32480 #define XCVR_BWR_TX_DIG_CTRL_DP_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t…  argument
32492 #define XCVR_RD_TX_DIG_CTRL_FREQ_WORD_ADJ(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_FRE…  argument
32493 #define XCVR_BRD_TX_DIG_CTRL_FREQ_WORD_ADJ(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_D…  argument
32496 #define XCVR_WR_TX_DIG_CTRL_FREQ_WORD_ADJ(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL…  argument
32497 #define XCVR_BWR_TX_DIG_CTRL_FREQ_WORD_ADJ(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((u…  argument
32513 #define XCVR_RD_TX_DATA_PAD_PAT(base) (XCVR_TX_DATA_PAD_PAT_REG(base))  argument
32514 #define XCVR_WR_TX_DATA_PAD_PAT(base, value) (XCVR_TX_DATA_PAD_PAT_REG(base) = (value))  argument
32515 #define XCVR_RMW_TX_DATA_PAD_PAT(base, mask, value) (XCVR_WR_TX_DATA_PAD_PAT(base, (XCVR_RD_TX_DATA…  argument
32516 #define XCVR_SET_TX_DATA_PAD_PAT(base, value) (BME_OR32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t)…  argument
32517 #define XCVR_CLR_TX_DATA_PAD_PAT(base, value) (BME_AND32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t…  argument
32518 #define XCVR_TOG_TX_DATA_PAD_PAT(base, value) (BME_XOR32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t…  argument
32533 #define XCVR_RD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX…  argument
32534 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(bas…  argument
32537 #define XCVR_WR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCV…  argument
32538 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_R…  argument
32549 #define XCVR_RD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX…  argument
32550 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(bas…  argument
32553 #define XCVR_WR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCV…  argument
32554 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_R…  argument
32565 #define XCVR_RD_TX_DATA_PAD_PAT_DFT_LFSR_OUT(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_…  argument
32566 #define XCVR_BRD_TX_DATA_PAD_PAT_DFT_LFSR_OUT(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XC…  argument
32579 #define XCVR_RD_TX_DATA_PAD_PAT_LRM(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_PAD_PAT_L…  argument
32580 #define XCVR_BRD_TX_DATA_PAD_PAT_LRM(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DAT…  argument
32583 #define XCVR_WR_TX_DATA_PAD_PAT_LRM(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCVR_TX_DATA_PAD_P…  argument
32584 #define XCVR_BWR_TX_DATA_PAD_PAT_LRM(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_REG(base), ((uin…  argument
32600 #define XCVR_RD_TX_GFSK_MOD_CTRL(base) (XCVR_TX_GFSK_MOD_CTRL_REG(base))  argument
32601 #define XCVR_WR_TX_GFSK_MOD_CTRL(base, value) (XCVR_TX_GFSK_MOD_CTRL_REG(base) = (value))  argument
32602 #define XCVR_RMW_TX_GFSK_MOD_CTRL(base, mask, value) (XCVR_WR_TX_GFSK_MOD_CTRL(base, (XCVR_RD_TX_GF…  argument
32603 #define XCVR_SET_TX_GFSK_MOD_CTRL(base, value) (BME_OR32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32_…  argument
32604 #define XCVR_CLR_TX_GFSK_MOD_CTRL(base, value) (BME_AND32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32…  argument
32605 #define XCVR_TOG_TX_GFSK_MOD_CTRL(base, value) (BME_XOR32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32…  argument
32625 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base)…  argument
32626 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CT…  argument
32629 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL…  argument
32630 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base, value) (BME_BFI32(&XCVR_TX_GFSK_…  argument
32648 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MI(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD…  argument
32649 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MI(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_…  argument
32652 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MI(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK…  argument
32653 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MI(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base),…  argument
32664 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MLD(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MO…  argument
32665 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR…  argument
32668 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MLD(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFS…  argument
32669 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base)…  argument
32691 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX…  argument
32692 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(bas…  argument
32695 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCV…  argument
32696 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_R…  argument
32709 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_FLD(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MO…  argument
32710 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_FLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR…  argument
32713 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_FLD(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFS…  argument
32714 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_FLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base)…  argument
32735 #define XCVR_RD_TX_GFSK_COEFF2(base) (XCVR_TX_GFSK_COEFF2_REG(base))  argument
32736 #define XCVR_WR_TX_GFSK_COEFF2(base, value) (XCVR_TX_GFSK_COEFF2_REG(base) = (value))  argument
32737 #define XCVR_RMW_TX_GFSK_COEFF2(base, mask, value) (XCVR_WR_TX_GFSK_COEFF2(base, (XCVR_RD_TX_GFSK_C…  argument
32738 #define XCVR_SET_TX_GFSK_COEFF2(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(v…  argument
32739 #define XCVR_CLR_TX_GFSK_COEFF2(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(…  argument
32740 #define XCVR_TOG_TX_GFSK_COEFF2(base, value) (BME_XOR32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(…  argument
32761 #define XCVR_RD_TX_GFSK_COEFF1(base) (XCVR_TX_GFSK_COEFF1_REG(base))  argument
32762 #define XCVR_WR_TX_GFSK_COEFF1(base, value) (XCVR_TX_GFSK_COEFF1_REG(base) = (value))  argument
32763 #define XCVR_RMW_TX_GFSK_COEFF1(base, mask, value) (XCVR_WR_TX_GFSK_COEFF1(base, (XCVR_RD_TX_GFSK_C…  argument
32764 #define XCVR_SET_TX_GFSK_COEFF1(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(v…  argument
32765 #define XCVR_CLR_TX_GFSK_COEFF1(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(…  argument
32766 #define XCVR_TOG_TX_GFSK_COEFF1(base, value) (BME_XOR32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(…  argument
32782 #define XCVR_RD_TX_FSK_MOD_SCALE(base) (XCVR_TX_FSK_MOD_SCALE_REG(base))  argument
32783 #define XCVR_WR_TX_FSK_MOD_SCALE(base, value) (XCVR_TX_FSK_MOD_SCALE_REG(base) = (value))  argument
32784 #define XCVR_RMW_TX_FSK_MOD_SCALE(base, mask, value) (XCVR_WR_TX_FSK_MOD_SCALE(base, (XCVR_RD_TX_FS…  argument
32785 #define XCVR_SET_TX_FSK_MOD_SCALE(base, value) (BME_OR32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32_…  argument
32786 #define XCVR_CLR_TX_FSK_MOD_SCALE(base, value) (BME_AND32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32…  argument
32787 #define XCVR_TOG_TX_FSK_MOD_SCALE(base, value) (BME_XOR32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32…  argument
32809 #define XCVR_RD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base) ((XCVR_TX_FSK_MOD_SCALE_REG(base) & X…  argument
32810 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_R…  argument
32813 #define XCVR_WR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base, value) (XCVR_RMW_TX_FSK_MOD_SCALE(bas…  argument
32814 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_S…  argument
32832 #define XCVR_RD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base) ((XCVR_TX_FSK_MOD_SCALE_REG(base) & X…  argument
32833 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_R…  argument
32836 #define XCVR_WR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base, value) (XCVR_RMW_TX_FSK_MOD_SCALE(bas…  argument
32837 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_S…  argument
32853 #define XCVR_RD_TX_DFT_MOD_PAT(base) (XCVR_TX_DFT_MOD_PAT_REG(base))  argument
32854 #define XCVR_WR_TX_DFT_MOD_PAT(base, value) (XCVR_TX_DFT_MOD_PAT_REG(base) = (value))  argument
32855 #define XCVR_RMW_TX_DFT_MOD_PAT(base, mask, value) (XCVR_WR_TX_DFT_MOD_PAT(base, (XCVR_RD_TX_DFT_MO…  argument
32856 #define XCVR_SET_TX_DFT_MOD_PAT(base, value) (BME_OR32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(v…  argument
32857 #define XCVR_CLR_TX_DFT_MOD_PAT(base, value) (BME_AND32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(…  argument
32858 #define XCVR_TOG_TX_DFT_MOD_PAT(base, value) (BME_XOR32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(…  argument
32879 #define XCVR_RD_TX_DFT_TONE_0_1(base) (XCVR_TX_DFT_TONE_0_1_REG(base))  argument
32880 #define XCVR_WR_TX_DFT_TONE_0_1(base, value) (XCVR_TX_DFT_TONE_0_1_REG(base) = (value))  argument
32881 #define XCVR_RMW_TX_DFT_TONE_0_1(base, mask, value) (XCVR_WR_TX_DFT_TONE_0_1(base, (XCVR_RD_TX_DFT_…  argument
32882 #define XCVR_SET_TX_DFT_TONE_0_1(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t)…  argument
32883 #define XCVR_CLR_TX_DFT_TONE_0_1(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t…  argument
32884 #define XCVR_TOG_TX_DFT_TONE_0_1(base, value) (BME_XOR32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t…  argument
32902 #define XCVR_RD_TX_DFT_TONE_0_1_DFT_TONE_1(base) ((XCVR_TX_DFT_TONE_0_1_REG(base) & XCVR_TX_DFT_TON…  argument
32903 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_1(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR…  argument
32906 #define XCVR_WR_TX_DFT_TONE_0_1_DFT_TONE_1(base, value) (XCVR_RMW_TX_DFT_TONE_0_1(base, XCVR_TX_DFT…  argument
32907 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_1(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base)…  argument
32921 #define XCVR_RD_TX_DFT_TONE_0_1_DFT_TONE_0(base) ((XCVR_TX_DFT_TONE_0_1_REG(base) & XCVR_TX_DFT_TON…  argument
32922 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_0(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR…  argument
32925 #define XCVR_WR_TX_DFT_TONE_0_1_DFT_TONE_0(base, value) (XCVR_RMW_TX_DFT_TONE_0_1(base, XCVR_TX_DFT…  argument
32926 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_0(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base)…  argument
32947 #define XCVR_RD_TX_DFT_TONE_2_3(base) (XCVR_TX_DFT_TONE_2_3_REG(base))  argument
32948 #define XCVR_WR_TX_DFT_TONE_2_3(base, value) (XCVR_TX_DFT_TONE_2_3_REG(base) = (value))  argument
32949 #define XCVR_RMW_TX_DFT_TONE_2_3(base, mask, value) (XCVR_WR_TX_DFT_TONE_2_3(base, (XCVR_RD_TX_DFT_…  argument
32950 #define XCVR_SET_TX_DFT_TONE_2_3(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t)…  argument
32951 #define XCVR_CLR_TX_DFT_TONE_2_3(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t…  argument
32952 #define XCVR_TOG_TX_DFT_TONE_2_3(base, value) (BME_XOR32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t…  argument
32970 #define XCVR_RD_TX_DFT_TONE_2_3_DFT_TONE_3(base) ((XCVR_TX_DFT_TONE_2_3_REG(base) & XCVR_TX_DFT_TON…  argument
32971 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_3(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR…  argument
32974 #define XCVR_WR_TX_DFT_TONE_2_3_DFT_TONE_3(base, value) (XCVR_RMW_TX_DFT_TONE_2_3(base, XCVR_TX_DFT…  argument
32975 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_3(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base)…  argument
32989 #define XCVR_RD_TX_DFT_TONE_2_3_DFT_TONE_2(base) ((XCVR_TX_DFT_TONE_2_3_REG(base) & XCVR_TX_DFT_TON…  argument
32990 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_2(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR…  argument
32993 #define XCVR_WR_TX_DFT_TONE_2_3_DFT_TONE_2(base, value) (XCVR_RMW_TX_DFT_TONE_2_3(base, XCVR_TX_DFT…  argument
32994 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_2(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base)…  argument
33010 #define XCVR_RD_PLL_MOD_OVRD(base) (XCVR_PLL_MOD_OVRD_REG(base))  argument
33011 #define XCVR_WR_PLL_MOD_OVRD(base, value) (XCVR_PLL_MOD_OVRD_REG(base) = (value))  argument
33012 #define XCVR_RMW_PLL_MOD_OVRD(base, mask, value) (XCVR_WR_PLL_MOD_OVRD(base, (XCVR_RD_PLL_MOD_OVRD(…  argument
33013 #define XCVR_SET_PLL_MOD_OVRD(base, value) (BME_OR32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(value…  argument
33014 #define XCVR_CLR_PLL_MOD_OVRD(base, value) (BME_AND32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(~(va…  argument
33015 #define XCVR_TOG_PLL_MOD_OVRD(base, value) (BME_XOR32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(valu…  argument
33030 #define XCVR_RD_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_…  argument
33031 #define XCVR_BRD_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base)…  argument
33034 #define XCVR_WR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_…  argument
33035 #define XCVR_BWR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG…  argument
33046 #define XCVR_RD_PLL_MOD_OVRD_MOD_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_MOD_DI…  argument
33047 #define XCVR_BRD_PLL_MOD_OVRD_MOD_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_…  argument
33050 #define XCVR_WR_PLL_MOD_OVRD_MOD_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_MO…  argument
33051 #define XCVR_BWR_PLL_MOD_OVRD_MOD_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint3…  argument
33062 #define XCVR_RD_PLL_MOD_OVRD_HPM_BANK_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVR…  argument
33063 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_…  argument
33066 #define XCVR_WR_PLL_MOD_OVRD_HPM_BANK_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD…  argument
33067 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base),…  argument
33078 #define XCVR_RD_PLL_MOD_OVRD_HPM_BANK_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_H…  argument
33079 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL…  argument
33082 #define XCVR_WR_PLL_MOD_OVRD_HPM_BANK_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OV…  argument
33083 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((…  argument
33094 #define XCVR_RD_PLL_MOD_OVRD_HPM_LSB_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD…  argument
33095 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_P…  argument
33098 #define XCVR_WR_PLL_MOD_OVRD_HPM_LSB_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_…  argument
33099 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), …  argument
33111 #define XCVR_RD_PLL_MOD_OVRD_HPM_LSB_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_HP…  argument
33112 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_…  argument
33115 #define XCVR_WR_PLL_MOD_OVRD_HPM_LSB_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVR…  argument
33116 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((u…  argument
33132 #define XCVR_RD_PLL_CHAN_MAP(base) (XCVR_PLL_CHAN_MAP_REG(base))  argument
33133 #define XCVR_WR_PLL_CHAN_MAP(base, value) (XCVR_PLL_CHAN_MAP_REG(base) = (value))  argument
33134 #define XCVR_RMW_PLL_CHAN_MAP(base, mask, value) (XCVR_WR_PLL_CHAN_MAP(base, (XCVR_RD_PLL_CHAN_MAP(…  argument
33135 #define XCVR_SET_PLL_CHAN_MAP(base, value) (BME_OR32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(value…  argument
33136 #define XCVR_CLR_PLL_CHAN_MAP(base, value) (BME_AND32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(~(va…  argument
33137 #define XCVR_TOG_PLL_CHAN_MAP(base, value) (BME_XOR32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(valu…  argument
33180 #define XCVR_RD_PLL_CHAN_MAP_CHANNEL_NUM(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_CH…  argument
33181 #define XCVR_BRD_PLL_CHAN_MAP_CHANNEL_NUM(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_…  argument
33184 #define XCVR_WR_PLL_CHAN_MAP_CHANNEL_NUM(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MA…  argument
33185 #define XCVR_BWR_PLL_CHAN_MAP_CHANNEL_NUM(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((u…  argument
33199 #define XCVR_RD_PLL_CHAN_MAP_BOC(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_BOC_MASK) …  argument
33200 #define XCVR_BRD_PLL_CHAN_MAP_BOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…  argument
33203 #define XCVR_WR_PLL_CHAN_MAP_BOC(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_BOC_MA…  argument
33204 #define XCVR_BWR_PLL_CHAN_MAP_BOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…  argument
33219 #define XCVR_RD_PLL_CHAN_MAP_BMR(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_BMR_MASK) …  argument
33220 #define XCVR_BRD_PLL_CHAN_MAP_BMR(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…  argument
33223 #define XCVR_WR_PLL_CHAN_MAP_BMR(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_BMR_MA…  argument
33224 #define XCVR_BWR_PLL_CHAN_MAP_BMR(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…  argument
33238 #define XCVR_RD_PLL_CHAN_MAP_ZOC(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_ZOC_MASK) …  argument
33239 #define XCVR_BRD_PLL_CHAN_MAP_ZOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP…  argument
33242 #define XCVR_WR_PLL_CHAN_MAP_ZOC(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_ZOC_MA…  argument
33243 #define XCVR_BWR_PLL_CHAN_MAP_ZOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)…  argument
33259 #define XCVR_RD_PLL_LOCK_DETECT(base) (XCVR_PLL_LOCK_DETECT_REG(base))  argument
33260 #define XCVR_WR_PLL_LOCK_DETECT(base, value) (XCVR_PLL_LOCK_DETECT_REG(base) = (value))  argument
33261 #define XCVR_RMW_PLL_LOCK_DETECT(base, mask, value) (XCVR_WR_PLL_LOCK_DETECT(base, (XCVR_RD_PLL_LOC…  argument
33262 #define XCVR_SET_PLL_LOCK_DETECT(base, value) (BME_OR32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t)…  argument
33263 #define XCVR_CLR_PLL_LOCK_DETECT(base, value) (BME_AND32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t…  argument
33264 #define XCVR_TOG_PLL_LOCK_DETECT(base, value) (BME_XOR32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t…  argument
33279 #define XCVR_RD_PLL_LOCK_DETECT_CT_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETE…  argument
33280 #define XCVR_BRD_PLL_LOCK_DETECT_CT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…  argument
33291 #define XCVR_RD_PLL_LOCK_DETECT_CTFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_…  argument
33292 #define XCVR_BRD_PLL_LOCK_DETECT_CTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…  argument
33295 #define XCVR_WR_PLL_LOCK_DETECT_CTFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DE…  argument
33296 #define XCVR_BWR_PLL_LOCK_DETECT_CTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…  argument
33308 #define XCVR_RD_PLL_LOCK_DETECT_CS_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETE…  argument
33309 #define XCVR_BRD_PLL_LOCK_DETECT_CS_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…  argument
33320 #define XCVR_RD_PLL_LOCK_DETECT_CSFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_…  argument
33321 #define XCVR_BRD_PLL_LOCK_DETECT_CSFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…  argument
33324 #define XCVR_WR_PLL_LOCK_DETECT_CSFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DE…  argument
33325 #define XCVR_BWR_PLL_LOCK_DETECT_CSFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…  argument
33336 #define XCVR_RD_PLL_LOCK_DETECT_FT_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETE…  argument
33337 #define XCVR_BRD_PLL_LOCK_DETECT_FT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PL…  argument
33348 #define XCVR_RD_PLL_LOCK_DETECT_FTFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_…  argument
33349 #define XCVR_BRD_PLL_LOCK_DETECT_FTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…  argument
33352 #define XCVR_WR_PLL_LOCK_DETECT_FTFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DE…  argument
33353 #define XCVR_BWR_PLL_LOCK_DETECT_FTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…  argument
33364 #define XCVR_RD_PLL_LOCK_DETECT_TAFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_…  argument
33365 #define XCVR_BRD_PLL_LOCK_DETECT_TAFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_L…  argument
33368 #define XCVR_WR_PLL_LOCK_DETECT_TAFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DE…  argument
33369 #define XCVR_BWR_PLL_LOCK_DETECT_TAFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((ui…  argument
33381 #define XCVR_RD_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOC…  argument
33382 #define XCVR_BRD_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), X…  argument
33385 #define XCVR_WR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PL…  argument
33386 #define XCVR_BWR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(ba…  argument
33398 #define XCVR_RD_PLL_LOCK_DETECT_FTF_RX_THRSH(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK…  argument
33399 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_RX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XC…  argument
33402 #define XCVR_WR_PLL_LOCK_DETECT_FTF_RX_THRSH(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL…  argument
33403 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_RX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(bas…  argument
33419 #define XCVR_RD_PLL_LOCK_DETECT_FTW_RX(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETEC…  argument
33420 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_RX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL…  argument
33423 #define XCVR_WR_PLL_LOCK_DETECT_FTW_RX(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_…  argument
33424 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_RX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((…  argument
33436 #define XCVR_RD_PLL_LOCK_DETECT_FTF_TX_THRSH(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK…  argument
33437 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_TX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XC…  argument
33440 #define XCVR_WR_PLL_LOCK_DETECT_FTF_TX_THRSH(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL…  argument
33441 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_TX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(bas…  argument
33457 #define XCVR_RD_PLL_LOCK_DETECT_FTW_TX(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETEC…  argument
33458 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_TX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL…  argument
33461 #define XCVR_WR_PLL_LOCK_DETECT_FTW_TX(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_…  argument
33462 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_TX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((…  argument
33478 #define XCVR_RD_PLL_HP_MOD_CTRL(base) (XCVR_PLL_HP_MOD_CTRL_REG(base))  argument
33479 #define XCVR_WR_PLL_HP_MOD_CTRL(base, value) (XCVR_PLL_HP_MOD_CTRL_REG(base) = (value))  argument
33480 #define XCVR_RMW_PLL_HP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_HP_MOD_CTRL(base, (XCVR_RD_PLL_HP_…  argument
33481 #define XCVR_SET_PLL_HP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t)…  argument
33482 #define XCVR_CLR_PLL_HP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t…  argument
33483 #define XCVR_TOG_PLL_HP_MOD_CTRL(base, value) (BME_XOR32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t…  argument
33498 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP…  argument
33499 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), …  argument
33502 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_P…  argument
33503 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(b…  argument
33515 #define XCVR_RD_PLL_HP_MOD_CTRL_HPFF(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_…  argument
33516 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPFF(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_H…  argument
33519 #define XCVR_WR_PLL_HP_MOD_CTRL_HPFF(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, XCVR_PLL_HP_MOD_C…  argument
33520 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPFF(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((ui…  argument
33531 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_SDM_INV(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD…  argument
33532 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…  argument
33535 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_SDM_INV(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_H…  argument
33536 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…  argument
33547 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_SDM_DIS(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD…  argument
33548 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…  argument
33551 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_SDM_DIS(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_H…  argument
33552 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…  argument
33573 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_M…  argument
33574 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XC…  argument
33577 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL…  argument
33578 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(bas…  argument
33589 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_DTH_SCL(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD…  argument
33590 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…  argument
33593 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_DTH_SCL(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_H…  argument
33594 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…  argument
33605 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_DTH_EN(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD…  argument
33606 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_DTH_EN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…  argument
33609 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_DTH_EN(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_H…  argument
33610 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_DTH_EN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…  argument
33627 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_SCALE(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_…  argument
33628 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_…  argument
33631 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_SCALE(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP…  argument
33632 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base),…  argument
33645 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_MOD_INV(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD…  argument
33646 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_MOD_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR…  argument
33649 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_MOD_INV(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_H…  argument
33650 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_MOD_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base)…  argument
33666 #define XCVR_RD_PLL_HPM_CAL_CTRL(base) (XCVR_PLL_HPM_CAL_CTRL_REG(base))  argument
33667 #define XCVR_WR_PLL_HPM_CAL_CTRL(base, value) (XCVR_PLL_HPM_CAL_CTRL_REG(base) = (value))  argument
33668 #define XCVR_RMW_PLL_HPM_CAL_CTRL(base, mask, value) (XCVR_WR_PLL_HPM_CAL_CTRL(base, (XCVR_RD_PLL_H…  argument
33669 #define XCVR_SET_PLL_HPM_CAL_CTRL(base, value) (BME_OR32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32_…  argument
33670 #define XCVR_CLR_PLL_HPM_CAL_CTRL(base, value) (BME_AND32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32…  argument
33671 #define XCVR_TOG_PLL_HPM_CAL_CTRL(base, value) (BME_XOR32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32…  argument
33685 #define XCVR_RD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_…  argument
33686 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base)…  argument
33697 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_…  argument
33698 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XC…  argument
33701 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_…  argument
33702 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(bas…  argument
33713 #define XCVR_RD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XC…  argument
33714 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_RE…  argument
33717 #define XCVR_WR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base…  argument
33718 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_C…  argument
33733 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_…  argument
33734 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XC…  argument
33737 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_…  argument
33738 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(bas…  argument
33753 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM…  argument
33754 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), X…  argument
33757 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL…  argument
33758 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(ba…  argument
33774 #define XCVR_RD_PLL_LD_HPM_CAL1(base) (XCVR_PLL_LD_HPM_CAL1_REG(base))  argument
33775 #define XCVR_WR_PLL_LD_HPM_CAL1(base, value) (XCVR_PLL_LD_HPM_CAL1_REG(base) = (value))  argument
33776 #define XCVR_RMW_PLL_LD_HPM_CAL1(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL1(base, (XCVR_RD_PLL_LD_…  argument
33777 #define XCVR_SET_PLL_LD_HPM_CAL1(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t)…  argument
33778 #define XCVR_CLR_PLL_LD_HPM_CAL1(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t…  argument
33779 #define XCVR_TOG_PLL_LD_HPM_CAL1(base, value) (BME_XOR32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t…  argument
33793 #define XCVR_RD_PLL_LD_HPM_CAL1_CNT_1(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1…  argument
33794 #define XCVR_BRD_PLL_LD_HPM_CAL1_CNT_1(base) (XCVR_RD_PLL_LD_HPM_CAL1_CNT_1(base))  argument
33815 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_WT(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1…  argument
33816 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_WT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_…  argument
33819 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_WT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HPM_…  argument
33820 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_WT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((u…  argument
33841 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_FW(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1…  argument
33842 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FW(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_…  argument
33845 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_FW(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HPM_…  argument
33846 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FW(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((u…  argument
33857 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_FCNT(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CA…  argument
33858 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FCNT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PL…  argument
33861 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_FCNT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HP…  argument
33862 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FCNT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (…  argument
33878 #define XCVR_RD_PLL_LD_HPM_CAL2(base) (XCVR_PLL_LD_HPM_CAL2_REG(base))  argument
33879 #define XCVR_WR_PLL_LD_HPM_CAL2(base, value) (XCVR_PLL_LD_HPM_CAL2_REG(base) = (value))  argument
33880 #define XCVR_RMW_PLL_LD_HPM_CAL2(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL2(base, (XCVR_RD_PLL_LD_…  argument
33881 #define XCVR_SET_PLL_LD_HPM_CAL2(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t)…  argument
33882 #define XCVR_CLR_PLL_LD_HPM_CAL2(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t…  argument
33883 #define XCVR_TOG_PLL_LD_HPM_CAL2(base, value) (BME_XOR32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t…  argument
33897 #define XCVR_RD_PLL_LD_HPM_CAL2_CNT_2(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2…  argument
33898 #define XCVR_BRD_PLL_LD_HPM_CAL2_CNT_2(base) (XCVR_RD_PLL_LD_HPM_CAL2_CNT_2(base))  argument
33909 #define XCVR_RD_PLL_LD_HPM_CAL2_CS_RC(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2…  argument
33910 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_RC(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_…  argument
33913 #define XCVR_WR_PLL_LD_HPM_CAL2_CS_RC(base, value) (XCVR_RMW_PLL_LD_HPM_CAL2(base, XCVR_PLL_LD_HPM_…  argument
33914 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_RC(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((u…  argument
33926 #define XCVR_RD_PLL_LD_HPM_CAL2_CS_FT(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2…  argument
33927 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_FT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_…  argument
33930 #define XCVR_WR_PLL_LD_HPM_CAL2_CS_FT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL2(base, XCVR_PLL_LD_HPM_…  argument
33931 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_FT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((u…  argument
33947 #define XCVR_RD_PLL_HPM_SDM_FRACTION(base) (XCVR_PLL_HPM_SDM_FRACTION_REG(base))  argument
33948 #define XCVR_WR_PLL_HPM_SDM_FRACTION(base, value) (XCVR_PLL_HPM_SDM_FRACTION_REG(base) = (value))  argument
33949 #define XCVR_RMW_PLL_HPM_SDM_FRACTION(base, mask, value) (XCVR_WR_PLL_HPM_SDM_FRACTION(base, (XCVR_…  argument
33950 #define XCVR_SET_PLL_HPM_SDM_FRACTION(base, value) (BME_OR32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), …  argument
33951 #define XCVR_CLR_PLL_HPM_SDM_FRACTION(base, value) (BME_AND32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base),…  argument
33952 #define XCVR_TOG_PLL_HPM_SDM_FRACTION(base, value) (BME_XOR32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base),…  argument
33968 #define XCVR_RD_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED(base) ((XCVR_PLL_HPM_SDM_FRACTION_REG(base) &…  argument
33969 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION…  argument
33984 #define XCVR_RD_PLL_HPM_SDM_FRACTION_HPM_DENOM(base) ((XCVR_PLL_HPM_SDM_FRACTION_REG(base) & XCVR_P…  argument
33985 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_DENOM(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION_REG(ba…  argument
33988 #define XCVR_WR_PLL_HPM_SDM_FRACTION_HPM_DENOM(base, value) (XCVR_RMW_PLL_HPM_SDM_FRACTION(base, XC…  argument
33989 #define XCVR_BWR_PLL_HPM_SDM_FRACTION_HPM_DENOM(base, value) (BME_BFI32(&XCVR_PLL_HPM_SDM_FRACTION_…  argument
34005 #define XCVR_RD_PLL_LP_MOD_CTRL(base) (XCVR_PLL_LP_MOD_CTRL_REG(base))  argument
34006 #define XCVR_WR_PLL_LP_MOD_CTRL(base, value) (XCVR_PLL_LP_MOD_CTRL_REG(base) = (value))  argument
34007 #define XCVR_RMW_PLL_LP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_LP_MOD_CTRL(base, (XCVR_RD_PLL_LP_…  argument
34008 #define XCVR_SET_PLL_LP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t)…  argument
34009 #define XCVR_CLR_PLL_LP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t…  argument
34010 #define XCVR_TOG_PLL_LP_MOD_CTRL(base, value) (BME_XOR32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t…  argument
34025 #define XCVR_RD_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XC…  argument
34026 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_RE…  argument
34029 #define XCVR_WR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base…  argument
34030 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_C…  argument
34042 #define XCVR_RD_PLL_LP_MOD_CTRL_PLL_LD_DIS(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD…  argument
34043 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LD_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…  argument
34046 #define XCVR_WR_PLL_LP_MOD_CTRL_PLL_LD_DIS(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_L…  argument
34047 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LD_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…  argument
34059 #define XCVR_RD_PLL_LP_MOD_CTRL_LPFF(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_…  argument
34060 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPFF(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_L…  argument
34063 #define XCVR_WR_PLL_LP_MOD_CTRL_LPFF(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, XCVR_PLL_LP_MOD_C…  argument
34064 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPFF(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((ui…  argument
34075 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SDM_INV(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MO…  argument
34076 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…  argument
34079 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SDM_INV(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_…  argument
34080 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…  argument
34093 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MO…  argument
34094 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…  argument
34097 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_…  argument
34098 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…  argument
34129 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MO…  argument
34130 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCV…  argument
34133 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_…  argument
34134 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base…  argument
34144 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_D_CTRL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD…  argument
34145 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_CTRL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…  argument
34148 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_D_CTRL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_L…  argument
34149 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_CTRL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…  argument
34164 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_D_OVRD(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD…  argument
34165 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_OVRD(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR…  argument
34168 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_D_OVRD(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_L…  argument
34169 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_OVRD(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base)…  argument
34199 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SCALE(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_…  argument
34200 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_…  argument
34203 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SCALE(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP…  argument
34204 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base),…  argument
34220 #define XCVR_RD_PLL_LP_SDM_CTRL1(base) (XCVR_PLL_LP_SDM_CTRL1_REG(base))  argument
34221 #define XCVR_WR_PLL_LP_SDM_CTRL1(base, value) (XCVR_PLL_LP_SDM_CTRL1_REG(base) = (value))  argument
34222 #define XCVR_RMW_PLL_LP_SDM_CTRL1(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL1(base, (XCVR_RD_PLL_L…  argument
34223 #define XCVR_SET_PLL_LP_SDM_CTRL1(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32_…  argument
34224 #define XCVR_CLR_PLL_LP_SDM_CTRL1(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32…  argument
34225 #define XCVR_TOG_PLL_LP_SDM_CTRL1(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32…  argument
34240 #define XCVR_RD_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_P…  argument
34241 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(ba…  argument
34253 #define XCVR_RD_PLL_LP_SDM_CTRL1_LPM_INTG(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_PLL_LP_SDM…  argument
34254 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), XCVR…  argument
34257 #define XCVR_WR_PLL_LP_SDM_CTRL1_LPM_INTG(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL1(base, XCVR_PLL_LP…  argument
34258 #define XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(base)…  argument
34272 #define XCVR_RD_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_PLL_LP_…  argument
34273 #define XCVR_BRD_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), X…  argument
34276 #define XCVR_WR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL1(base, XCVR_PLL…  argument
34277 #define XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(ba…  argument
34293 #define XCVR_RD_PLL_LP_SDM_CTRL2(base) (XCVR_PLL_LP_SDM_CTRL2_REG(base))  argument
34294 #define XCVR_WR_PLL_LP_SDM_CTRL2(base, value) (XCVR_PLL_LP_SDM_CTRL2_REG(base) = (value))  argument
34295 #define XCVR_RMW_PLL_LP_SDM_CTRL2(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL2(base, (XCVR_RD_PLL_L…  argument
34296 #define XCVR_SET_PLL_LP_SDM_CTRL2(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32_…  argument
34297 #define XCVR_CLR_PLL_LP_SDM_CTRL2(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32…  argument
34298 #define XCVR_TOG_PLL_LP_SDM_CTRL2(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32…  argument
34315 #define XCVR_RD_PLL_LP_SDM_CTRL2_LPM_NUM(base) ((XCVR_PLL_LP_SDM_CTRL2_REG(base) & XCVR_PLL_LP_SDM_…  argument
34316 #define XCVR_BRD_PLL_LP_SDM_CTRL2_LPM_NUM(base) (XCVR_RD_PLL_LP_SDM_CTRL2_LPM_NUM(base))  argument
34319 #define XCVR_WR_PLL_LP_SDM_CTRL2_LPM_NUM(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL2(base, XCVR_PLL_LP_…  argument
34320 #define XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(base, value) (XCVR_WR_PLL_LP_SDM_CTRL2_LPM_NUM(base, valu…  argument
34336 #define XCVR_RD_PLL_LP_SDM_CTRL3(base) (XCVR_PLL_LP_SDM_CTRL3_REG(base))  argument
34337 #define XCVR_WR_PLL_LP_SDM_CTRL3(base, value) (XCVR_PLL_LP_SDM_CTRL3_REG(base) = (value))  argument
34338 #define XCVR_RMW_PLL_LP_SDM_CTRL3(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL3(base, (XCVR_RD_PLL_L…  argument
34339 #define XCVR_SET_PLL_LP_SDM_CTRL3(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32_…  argument
34340 #define XCVR_CLR_PLL_LP_SDM_CTRL3(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32…  argument
34341 #define XCVR_TOG_PLL_LP_SDM_CTRL3(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32…  argument
34361 #define XCVR_RD_PLL_LP_SDM_CTRL3_LPM_DENOM(base) ((XCVR_PLL_LP_SDM_CTRL3_REG(base) & XCVR_PLL_LP_SD…  argument
34362 #define XCVR_BRD_PLL_LP_SDM_CTRL3_LPM_DENOM(base) (XCVR_RD_PLL_LP_SDM_CTRL3_LPM_DENOM(base))  argument
34365 #define XCVR_WR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL3(base, XCVR_PLL_L…  argument
34366 #define XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, value) (XCVR_WR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, …  argument
34382 #define XCVR_RD_PLL_LP_SDM_NUM(base) (XCVR_PLL_LP_SDM_NUM_REG(base))  argument
34398 #define XCVR_RD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(base) ((XCVR_PLL_LP_SDM_NUM_REG(base) & XCVR_PLL_LP…  argument
34399 #define XCVR_BRD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(base) (XCVR_RD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(bas…  argument
34415 #define XCVR_RD_PLL_LP_SDM_DENOM(base) (XCVR_PLL_LP_SDM_DENOM_REG(base))  argument
34431 #define XCVR_RD_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED(base) ((XCVR_PLL_LP_SDM_DENOM_REG(base) & XCVR_…  argument
34432 #define XCVR_BRD_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED(base) (XCVR_RD_PLL_LP_SDM_DENOM_LPM_DENOM_SELE…  argument
34448 #define XCVR_RD_PLL_DELAY_MATCH(base) (XCVR_PLL_DELAY_MATCH_REG(base))  argument
34449 #define XCVR_WR_PLL_DELAY_MATCH(base, value) (XCVR_PLL_DELAY_MATCH_REG(base) = (value))  argument
34450 #define XCVR_RMW_PLL_DELAY_MATCH(base, mask, value) (XCVR_WR_PLL_DELAY_MATCH(base, (XCVR_RD_PLL_DEL…  argument
34451 #define XCVR_SET_PLL_DELAY_MATCH(base, value) (BME_OR32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t)…  argument
34452 #define XCVR_CLR_PLL_DELAY_MATCH(base, value) (BME_AND32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t…  argument
34453 #define XCVR_TOG_PLL_DELAY_MATCH(base, value) (BME_XOR32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t…  argument
34468 #define XCVR_RD_PLL_DELAY_MATCH_LP_SDM_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DELA…  argument
34469 #define XCVR_BRD_PLL_DELAY_MATCH_LP_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), XC…  argument
34472 #define XCVR_WR_PLL_DELAY_MATCH_LP_SDM_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PLL_…  argument
34473 #define XCVR_BWR_PLL_DELAY_MATCH_LP_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(bas…  argument
34486 #define XCVR_RD_PLL_DELAY_MATCH_HPM_SDM_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DEL…  argument
34487 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), X…  argument
34490 #define XCVR_WR_PLL_DELAY_MATCH_HPM_SDM_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PLL…  argument
34491 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(ba…  argument
34503 #define XCVR_RD_PLL_DELAY_MATCH_HPM_BANK_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DE…  argument
34504 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_BANK_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), …  argument
34507 #define XCVR_WR_PLL_DELAY_MATCH_HPM_BANK_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PL…  argument
34508 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_BANK_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(b…  argument
34524 #define XCVR_RD_PLL_CTUNE_CTRL(base) (XCVR_PLL_CTUNE_CTRL_REG(base))  argument
34525 #define XCVR_WR_PLL_CTUNE_CTRL(base, value) (XCVR_PLL_CTUNE_CTRL_REG(base) = (value))  argument
34526 #define XCVR_RMW_PLL_CTUNE_CTRL(base, mask, value) (XCVR_WR_PLL_CTUNE_CTRL(base, (XCVR_RD_PLL_CTUNE…  argument
34527 #define XCVR_SET_PLL_CTUNE_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(v…  argument
34528 #define XCVR_CLR_PLL_CTUNE_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(…  argument
34529 #define XCVR_TOG_PLL_CTUNE_CTRL(base, value) (BME_XOR32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(…  argument
34545 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL…  argument
34546 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base…  argument
34549 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR…  argument
34550 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_RE…  argument
34561 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_TD(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL…  argument
34562 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TD(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL…  argument
34565 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_TD(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_…  argument
34566 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TD(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((…  argument
34578 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_ADJUST(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_…  argument
34579 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_ADJUST(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR…  argument
34582 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_ADJUST(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CT…  argument
34583 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_ADJUST(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base)…  argument
34594 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_MANUAL(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_…  argument
34595 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR…  argument
34598 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_MANUAL(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CT…  argument
34599 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base)…  argument
34610 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_DIS(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTR…  argument
34611 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_DIS(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PL…  argument
34614 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_DIS(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE…  argument
34615 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_DIS(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), (…  argument
34631 #define XCVR_RD_PLL_CTUNE_CNT6(base) (XCVR_PLL_CTUNE_CNT6_REG(base))  argument
34645 #define XCVR_RD_PLL_CTUNE_CNT6_CTUNE_COUNT_6(base) ((XCVR_PLL_CTUNE_CNT6_REG(base) & XCVR_PLL_CTUNE…  argument
34646 #define XCVR_BRD_PLL_CTUNE_CNT6_CTUNE_COUNT_6(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT6_REG(base), XCV…  argument
34662 #define XCVR_RD_PLL_CTUNE_CNT5_4(base) (XCVR_PLL_CTUNE_CNT5_4_REG(base))  argument
34676 #define XCVR_RD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4(base) ((XCVR_PLL_CTUNE_CNT5_4_REG(base) & XCVR_PLL_C…  argument
34677 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base),…  argument
34687 #define XCVR_RD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5(base) ((XCVR_PLL_CTUNE_CNT5_4_REG(base) & XCVR_PLL_C…  argument
34688 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base),…  argument
34704 #define XCVR_RD_PLL_CTUNE_CNT3_2(base) (XCVR_PLL_CTUNE_CNT3_2_REG(base))  argument
34718 #define XCVR_RD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2(base) ((XCVR_PLL_CTUNE_CNT3_2_REG(base) & XCVR_PLL_C…  argument
34719 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base),…  argument
34729 #define XCVR_RD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3(base) ((XCVR_PLL_CTUNE_CNT3_2_REG(base) & XCVR_PLL_C…  argument
34730 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base),…  argument
34746 #define XCVR_RD_PLL_CTUNE_CNT1_0(base) (XCVR_PLL_CTUNE_CNT1_0_REG(base))  argument
34760 #define XCVR_RD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0(base) ((XCVR_PLL_CTUNE_CNT1_0_REG(base) & XCVR_PLL_C…  argument
34761 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base),…  argument
34771 #define XCVR_RD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1(base) ((XCVR_PLL_CTUNE_CNT1_0_REG(base) & XCVR_PLL_C…  argument
34772 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base),…  argument
34788 #define XCVR_RD_PLL_CTUNE_RESULTS(base) (XCVR_PLL_CTUNE_RESULTS_REG(base))  argument
34803 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_SELECTED(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR_PL…  argument
34804 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_SELECTED(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(bas…  argument
34815 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR_P…  argument
34816 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(ba…  argument
34827 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR…  argument
34828 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(…  argument
34844 #define XCVR_RD_CTRL(base)       (XCVR_CTRL_REG(base))  argument
34845 #define XCVR_WR_CTRL(base, value) (XCVR_CTRL_REG(base) = (value))  argument
34846 #define XCVR_RMW_CTRL(base, mask, value) (XCVR_WR_CTRL(base, (XCVR_RD_CTRL(base) & ~(mask)) | (valu…  argument
34847 #define XCVR_SET_CTRL(base, value) (BME_OR32(&XCVR_CTRL_REG(base), (uint32_t)(value)))  argument
34848 #define XCVR_CLR_CTRL(base, value) (BME_AND32(&XCVR_CTRL_REG(base), (uint32_t)(~(value))))  argument
34849 #define XCVR_TOG_CTRL(base, value) (BME_XOR32(&XCVR_CTRL_REG(base), (uint32_t)(value)))  argument
34873 #define XCVR_RD_CTRL_PROTOCOL(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_PROTOCOL_MASK) >> XCVR_CTRL_P…  argument
34874 #define XCVR_BRD_CTRL_PROTOCOL(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_PROTOCOL_SHIFT, XC…  argument
34877 #define XCVR_WR_CTRL_PROTOCOL(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_PROTOCOL_MASK, XCVR_CTRL_…  argument
34878 #define XCVR_BWR_CTRL_PROTOCOL(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) << …  argument
34892 #define XCVR_RD_CTRL_TGT_PWR_SRC(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_TGT_PWR_SRC_MASK) >> XCVR_…  argument
34893 #define XCVR_BRD_CTRL_TGT_PWR_SRC(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_TGT_PWR_SRC_SHI…  argument
34896 #define XCVR_WR_CTRL_TGT_PWR_SRC(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_TGT_PWR_SRC_MASK, XCVR…  argument
34897 #define XCVR_BWR_CTRL_TGT_PWR_SRC(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) …  argument
34913 #define XCVR_RD_CTRL_REF_CLK_FREQ(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_REF_CLK_FREQ_MASK) >> XCV…  argument
34914 #define XCVR_BRD_CTRL_REF_CLK_FREQ(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_REF_CLK_FREQ_S…  argument
34917 #define XCVR_WR_CTRL_REF_CLK_FREQ(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_REF_CLK_FREQ_MASK, XC…  argument
34918 #define XCVR_BWR_CTRL_REF_CLK_FREQ(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value)…  argument
34934 #define XCVR_RD_STATUS(base)     (XCVR_STATUS_REG(base))  argument
34948 #define XCVR_RD_STATUS_TSM_COUNT(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_TSM_COUNT_MASK) >> XCV…  argument
34949 #define XCVR_BRD_STATUS_TSM_COUNT(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TSM_COUNT_S…  argument
34963 #define XCVR_RD_STATUS_PLL_SEQ_STATE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_PLL_SEQ_STATE_MASK…  argument
34964 #define XCVR_BRD_STATUS_PLL_SEQ_STATE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_PLL_SEQ…  argument
34974 #define XCVR_RD_STATUS_RX_MODE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_RX_MODE_MASK) >> XCVR_ST…  argument
34975 #define XCVR_BRD_STATUS_RX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RX_MODE_SHIFT…  argument
34985 #define XCVR_RD_STATUS_TX_MODE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_TX_MODE_MASK) >> XCVR_ST…  argument
34986 #define XCVR_BRD_STATUS_TX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TX_MODE_SHIFT…  argument
35001 #define XCVR_RD_STATUS_BTLE_SYSCLK_REQ(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_BTLE_SYSCLK_REQ_…  argument
35002 #define XCVR_BRD_STATUS_BTLE_SYSCLK_REQ(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_BTLE_…  argument
35015 #define XCVR_RD_STATUS_RIF_LL_ACTIVE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_RIF_LL_ACTIVE_MASK…  argument
35016 #define XCVR_BRD_STATUS_RIF_LL_ACTIVE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RIF_LL_…  argument
35032 #define XCVR_RD_STATUS_XTAL_READY(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_XTAL_READY_MASK) >> X…  argument
35033 #define XCVR_BRD_STATUS_XTAL_READY(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_XTAL_READY…  argument
35044 #define XCVR_RD_STATUS_SOC_USING_RF_OSC_CLK(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_SOC_USING_R…  argument
35045 #define XCVR_BRD_STATUS_SOC_USING_RF_OSC_CLK(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_…  argument
35063 #define XCVR_RD_SOFT_RESET(base) (XCVR_SOFT_RESET_REG(base))  argument
35086 #define XCVR_RD_OVERWRITE_VER(base) (XCVR_OVERWRITE_VER_REG(base))  argument
35087 #define XCVR_WR_OVERWRITE_VER(base, value) (XCVR_OVERWRITE_VER_REG(base) = (value))  argument
35088 #define XCVR_RMW_OVERWRITE_VER(base, mask, value) (XCVR_WR_OVERWRITE_VER(base, (XCVR_RD_OVERWRITE_V…  argument
35089 #define XCVR_SET_OVERWRITE_VER(base, value) (BME_OR32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(val…  argument
35090 #define XCVR_CLR_OVERWRITE_VER(base, value) (BME_AND32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(~(…  argument
35091 #define XCVR_TOG_OVERWRITE_VER(base, value) (BME_XOR32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(va…  argument
35107 #define XCVR_RD_OVERWRITE_VER_OVERWRITE_VER(base) ((XCVR_OVERWRITE_VER_REG(base) & XCVR_OVERWRITE_V…  argument
35108 #define XCVR_BRD_OVERWRITE_VER_OVERWRITE_VER(base) (BME_UBFX32(&XCVR_OVERWRITE_VER_REG(base), XCVR_…  argument
35111 #define XCVR_WR_OVERWRITE_VER_OVERWRITE_VER(base, value) (XCVR_RMW_OVERWRITE_VER(base, XCVR_OVERWRI…  argument
35112 #define XCVR_BWR_OVERWRITE_VER_OVERWRITE_VER(base, value) (BME_BFI32(&XCVR_OVERWRITE_VER_REG(base),…  argument
35133 #define XCVR_RD_DMA_CTRL(base)   (XCVR_DMA_CTRL_REG(base))  argument
35134 #define XCVR_WR_DMA_CTRL(base, value) (XCVR_DMA_CTRL_REG(base) = (value))  argument
35135 #define XCVR_RMW_DMA_CTRL(base, mask, value) (XCVR_WR_DMA_CTRL(base, (XCVR_RD_DMA_CTRL(base) & ~(ma…  argument
35136 #define XCVR_SET_DMA_CTRL(base, value) (BME_OR32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(value)))  argument
35137 #define XCVR_CLR_DMA_CTRL(base, value) (BME_AND32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(~(value))))  argument
35138 #define XCVR_TOG_DMA_CTRL(base, value) (BME_XOR32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(value)))  argument
35157 #define XCVR_RD_DMA_CTRL_DMA_I_EN(base) ((XCVR_DMA_CTRL_REG(base) & XCVR_DMA_CTRL_DMA_I_EN_MASK) >>…  argument
35158 #define XCVR_BRD_DMA_CTRL_DMA_I_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_I_…  argument
35161 #define XCVR_WR_DMA_CTRL_DMA_I_EN(base, value) (XCVR_RMW_DMA_CTRL(base, XCVR_DMA_CTRL_DMA_I_EN_MASK…  argument
35162 #define XCVR_BWR_DMA_CTRL_DMA_I_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(va…  argument
35177 #define XCVR_RD_DMA_CTRL_DMA_Q_EN(base) ((XCVR_DMA_CTRL_REG(base) & XCVR_DMA_CTRL_DMA_Q_EN_MASK) >>…  argument
35178 #define XCVR_BRD_DMA_CTRL_DMA_Q_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_Q_…  argument
35181 #define XCVR_WR_DMA_CTRL_DMA_Q_EN(base, value) (XCVR_RMW_DMA_CTRL(base, XCVR_DMA_CTRL_DMA_Q_EN_MASK…  argument
35182 #define XCVR_BWR_DMA_CTRL_DMA_Q_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(va…  argument
35204 #define XCVR_RD_DMA_DATA(base)   (XCVR_DMA_DATA_REG(base))  argument
35224 #define XCVR_RD_DMA_DATA_DMA_DATA_11_0(base) ((XCVR_DMA_DATA_REG(base) & XCVR_DMA_DATA_DMA_DATA_11_…  argument
35225 #define XCVR_BRD_DMA_DATA_DMA_DATA_11_0(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_D…  argument
35241 #define XCVR_RD_DMA_DATA_DMA_DATA_27_16(base) ((XCVR_DMA_DATA_REG(base) & XCVR_DMA_DATA_DMA_DATA_27…  argument
35242 #define XCVR_BRD_DMA_DATA_DMA_DATA_27_16(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_…  argument
35263 #define XCVR_RD_DTEST_CTRL(base) (XCVR_DTEST_CTRL_REG(base))  argument
35264 #define XCVR_WR_DTEST_CTRL(base, value) (XCVR_DTEST_CTRL_REG(base) = (value))  argument
35265 #define XCVR_RMW_DTEST_CTRL(base, mask, value) (XCVR_WR_DTEST_CTRL(base, (XCVR_RD_DTEST_CTRL(base) …  argument
35266 #define XCVR_SET_DTEST_CTRL(base, value) (BME_OR32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(value)))  argument
35267 #define XCVR_CLR_DTEST_CTRL(base, value) (BME_AND32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(~(value)…  argument
35268 #define XCVR_TOG_DTEST_CTRL(base, value) (BME_XOR32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(value)))  argument
35283 #define XCVR_RD_DTEST_CTRL_DTEST_PAGE(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_PAG…  argument
35284 #define XCVR_BRD_DTEST_CTRL_DTEST_PAGE(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…  argument
35287 #define XCVR_WR_DTEST_CTRL_DTEST_PAGE(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST…  argument
35288 #define XCVR_BWR_DTEST_CTRL_DTEST_PAGE(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…  argument
35303 #define XCVR_RD_DTEST_CTRL_DTEST_EN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_EN_MA…  argument
35304 #define XCVR_BRD_DTEST_CTRL_DTEST_EN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_…  argument
35307 #define XCVR_WR_DTEST_CTRL_DTEST_EN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST_E…  argument
35308 #define XCVR_BWR_DTEST_CTRL_DTEST_EN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t…  argument
35323 #define XCVR_RD_DTEST_CTRL_GPIO0_OVLAY_PIN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_GPIO…  argument
35324 #define XCVR_BRD_DTEST_CTRL_GPIO0_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTES…  argument
35327 #define XCVR_WR_DTEST_CTRL_GPIO0_OVLAY_PIN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_…  argument
35328 #define XCVR_BWR_DTEST_CTRL_GPIO0_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((u…  argument
35343 #define XCVR_RD_DTEST_CTRL_GPIO1_OVLAY_PIN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_GPIO…  argument
35344 #define XCVR_BRD_DTEST_CTRL_GPIO1_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTES…  argument
35347 #define XCVR_WR_DTEST_CTRL_GPIO1_OVLAY_PIN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_…  argument
35348 #define XCVR_BWR_DTEST_CTRL_GPIO1_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((u…  argument
35369 #define XCVR_RD_DTEST_CTRL_TSM_GPIO_OVLAY_0(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_TSM…  argument
35370 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_0(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTE…  argument
35373 #define XCVR_WR_DTEST_CTRL_TSM_GPIO_OVLAY_0(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL…  argument
35374 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_0(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((…  argument
35395 #define XCVR_RD_DTEST_CTRL_TSM_GPIO_OVLAY_1(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_TSM…  argument
35396 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_1(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTE…  argument
35399 #define XCVR_WR_DTEST_CTRL_TSM_GPIO_OVLAY_1(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL…  argument
35400 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_1(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((…  argument
35422 #define XCVR_RD_DTEST_CTRL_DTEST_SHFT(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_SHF…  argument
35423 #define XCVR_BRD_DTEST_CTRL_DTEST_SHFT(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…  argument
35426 #define XCVR_WR_DTEST_CTRL_DTEST_SHFT(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST…  argument
35427 #define XCVR_BWR_DTEST_CTRL_DTEST_SHFT(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…  argument
35444 #define XCVR_RD_DTEST_CTRL_RAW_MODE_I(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_RAW_MODE_…  argument
35445 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_I(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…  argument
35448 #define XCVR_WR_DTEST_CTRL_RAW_MODE_I(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_RAW_M…  argument
35449 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_I(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…  argument
35466 #define XCVR_RD_DTEST_CTRL_RAW_MODE_Q(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_RAW_MODE_…  argument
35467 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_Q(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTR…  argument
35470 #define XCVR_WR_DTEST_CTRL_RAW_MODE_Q(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_RAW_M…  argument
35471 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_Q(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32…  argument
35487 #define XCVR_RD_PB_CTRL(base)    (XCVR_PB_CTRL_REG(base))  argument
35488 #define XCVR_WR_PB_CTRL(base, value) (XCVR_PB_CTRL_REG(base) = (value))  argument
35489 #define XCVR_RMW_PB_CTRL(base, mask, value) (XCVR_WR_PB_CTRL(base, (XCVR_RD_PB_CTRL(base) & ~(mask)…  argument
35490 #define XCVR_SET_PB_CTRL(base, value) (BME_OR32(&XCVR_PB_CTRL_REG(base), (uint32_t)(value)))  argument
35491 #define XCVR_CLR_PB_CTRL(base, value) (BME_AND32(&XCVR_PB_CTRL_REG(base), (uint32_t)(~(value))))  argument
35492 #define XCVR_TOG_PB_CTRL(base, value) (BME_XOR32(&XCVR_PB_CTRL_REG(base), (uint32_t)(value)))  argument
35511 #define XCVR_RD_PB_CTRL_PB_PROTECT(base) ((XCVR_PB_CTRL_REG(base) & XCVR_PB_CTRL_PB_PROTECT_MASK) >…  argument
35512 #define XCVR_BRD_PB_CTRL_PB_PROTECT(base) (BME_UBFX32(&XCVR_PB_CTRL_REG(base), XCVR_PB_CTRL_PB_PROT…  argument
35515 #define XCVR_WR_PB_CTRL_PB_PROTECT(base, value) (XCVR_RMW_PB_CTRL(base, XCVR_PB_CTRL_PB_PROTECT_MAS…  argument
35516 #define XCVR_BWR_PB_CTRL_PB_PROTECT(base, value) (BME_BFI32(&XCVR_PB_CTRL_REG(base), ((uint32_t)(va…  argument
35532 #define XCVR_RD_TSM_CTRL(base)   (XCVR_TSM_CTRL_REG(base))  argument
35533 #define XCVR_WR_TSM_CTRL(base, value) (XCVR_TSM_CTRL_REG(base) = (value))  argument
35534 #define XCVR_RMW_TSM_CTRL(base, mask, value) (XCVR_WR_TSM_CTRL(base, (XCVR_RD_TSM_CTRL(base) & ~(ma…  argument
35535 #define XCVR_SET_TSM_CTRL(base, value) (BME_OR32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(value)))  argument
35536 #define XCVR_CLR_TSM_CTRL(base, value) (BME_AND32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(~(value))))  argument
35537 #define XCVR_TOG_TSM_CTRL(base, value) (BME_XOR32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(value)))  argument
35557 #define XCVR_RD_TSM_CTRL_FORCE_TX_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_FORCE_TX_EN_MA…  argument
35558 #define XCVR_BRD_TSM_CTRL_FORCE_TX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FOR…  argument
35561 #define XCVR_WR_TSM_CTRL_FORCE_TX_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_FORCE_TX_E…  argument
35562 #define XCVR_BWR_TSM_CTRL_FORCE_TX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…  argument
35577 #define XCVR_RD_TSM_CTRL_FORCE_RX_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_FORCE_RX_EN_MA…  argument
35578 #define XCVR_BRD_TSM_CTRL_FORCE_RX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FOR…  argument
35581 #define XCVR_WR_TSM_CTRL_FORCE_RX_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_FORCE_RX_E…  argument
35582 #define XCVR_BWR_TSM_CTRL_FORCE_RX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…  argument
35596 #define XCVR_RD_TSM_CTRL_PA_RAMP_SEL(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_PA_RAMP_SEL_MA…  argument
35597 #define XCVR_BRD_TSM_CTRL_PA_RAMP_SEL(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_PA_…  argument
35600 #define XCVR_WR_TSM_CTRL_PA_RAMP_SEL(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_PA_RAMP_SE…  argument
35601 #define XCVR_BWR_TSM_CTRL_PA_RAMP_SEL(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)…  argument
35617 #define XCVR_RD_TSM_CTRL_DATA_PADDING_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_DATA_PADDI…  argument
35618 #define XCVR_BRD_TSM_CTRL_DATA_PADDING_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL…  argument
35621 #define XCVR_WR_TSM_CTRL_DATA_PADDING_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_DATA_P…  argument
35622 #define XCVR_BWR_TSM_CTRL_DATA_PADDING_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint3…  argument
35633 #define XCVR_RD_TSM_CTRL_TX_ABORT_DIS(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_TX_ABORT_DIS_…  argument
35634 #define XCVR_BRD_TSM_CTRL_TX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_TX…  argument
35637 #define XCVR_WR_TSM_CTRL_TX_ABORT_DIS(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_TX_ABORT_…  argument
35638 #define XCVR_BWR_TSM_CTRL_TX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t…  argument
35649 #define XCVR_RD_TSM_CTRL_RX_ABORT_DIS(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_RX_ABORT_DIS_…  argument
35650 #define XCVR_BRD_TSM_CTRL_RX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_RX…  argument
35653 #define XCVR_WR_TSM_CTRL_RX_ABORT_DIS(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_RX_ABORT_…  argument
35654 #define XCVR_BWR_TSM_CTRL_RX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t…  argument
35666 #define XCVR_RD_TSM_CTRL_ABORT_ON_CTUNE(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_ON_CT…  argument
35667 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CTUNE(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_…  argument
35670 #define XCVR_WR_TSM_CTRL_ABORT_ON_CTUNE(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_ABORT_O…  argument
35671 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CTUNE(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32…  argument
35683 #define XCVR_RD_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_…  argument
35684 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_…  argument
35687 #define XCVR_WR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_AB…  argument
35688 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((u…  argument
35700 #define XCVR_RD_TSM_CTRL_ABORT_ON_FREQ_TARG(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_O…  argument
35701 #define XCVR_BRD_TSM_CTRL_ABORT_ON_FREQ_TARG(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_C…  argument
35704 #define XCVR_WR_TSM_CTRL_ABORT_ON_FREQ_TARG(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_ABO…  argument
35705 #define XCVR_BWR_TSM_CTRL_ABORT_ON_FREQ_TARG(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((ui…  argument
35722 #define XCVR_RD_TSM_CTRL_BKPT(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_BKPT_MASK) >> XCVR_TS…  argument
35723 #define XCVR_BRD_TSM_CTRL_BKPT(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_BKPT_SHIFT…  argument
35726 #define XCVR_WR_TSM_CTRL_BKPT(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_BKPT_MASK, XCVR_T…  argument
35727 #define XCVR_BWR_TSM_CTRL_BKPT(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value)…  argument
35743 #define XCVR_RD_END_OF_SEQ(base) (XCVR_END_OF_SEQ_REG(base))  argument
35744 #define XCVR_WR_END_OF_SEQ(base, value) (XCVR_END_OF_SEQ_REG(base) = (value))  argument
35745 #define XCVR_RMW_END_OF_SEQ(base, mask, value) (XCVR_WR_END_OF_SEQ(base, (XCVR_RD_END_OF_SEQ(base) …  argument
35746 #define XCVR_SET_END_OF_SEQ(base, value) (BME_OR32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(value)))  argument
35747 #define XCVR_CLR_END_OF_SEQ(base, value) (BME_AND32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(~(value)…  argument
35748 #define XCVR_TOG_END_OF_SEQ(base, value) (BME_XOR32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(value)))  argument
35765 #define XCVR_RD_END_OF_SEQ_END_OF_TX_WU(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_…  argument
35766 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…  argument
35769 #define XCVR_WR_END_OF_SEQ_END_OF_TX_WU(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END…  argument
35770 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…  argument
35784 #define XCVR_RD_END_OF_SEQ_END_OF_TX_WD(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_…  argument
35785 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…  argument
35788 #define XCVR_WR_END_OF_SEQ_END_OF_TX_WD(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END…  argument
35789 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…  argument
35802 #define XCVR_RD_END_OF_SEQ_END_OF_RX_WU(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_…  argument
35803 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…  argument
35806 #define XCVR_WR_END_OF_SEQ_END_OF_RX_WU(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END…  argument
35807 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…  argument
35821 #define XCVR_RD_END_OF_SEQ_END_OF_RX_WD(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_…  argument
35822 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_…  argument
35825 #define XCVR_WR_END_OF_SEQ_END_OF_RX_WD(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END…  argument
35826 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint…  argument
35842 #define XCVR_RD_TSM_OVRD0(base)  (XCVR_TSM_OVRD0_REG(base))  argument
35843 #define XCVR_WR_TSM_OVRD0(base, value) (XCVR_TSM_OVRD0_REG(base) = (value))  argument
35844 #define XCVR_RMW_TSM_OVRD0(base, mask, value) (XCVR_WR_TSM_OVRD0(base, (XCVR_RD_TSM_OVRD0(base) & ~…  argument
35845 #define XCVR_SET_TSM_OVRD0(base, value) (BME_OR32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(value)))  argument
35846 #define XCVR_CLR_TSM_OVRD0(base, value) (BME_AND32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(~(value))))  argument
35847 #define XCVR_TOG_TSM_OVRD0(base, value) (BME_XOR32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(value)))  argument
35863 #define XCVR_RD_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_…  argument
35864 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…  argument
35867 #define XCVR_WR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_…  argument
35868 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…  argument
35879 #define XCVR_RD_TSM_OVRD0_PLL_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_REG…  argument
35880 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…  argument
35883 #define XCVR_WR_TSM_OVRD0_PLL_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL…  argument
35884 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…  argument
35897 #define XCVR_RD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_…  argument
35898 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…  argument
35901 #define XCVR_WR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OV…  argument
35902 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…  argument
35914 #define XCVR_RD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL…  argument
35915 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…  argument
35918 #define XCVR_WR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0…  argument
35919 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…  argument
35932 #define XCVR_RD_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_QGE…  argument
35933 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…  argument
35936 #define XCVR_WR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0…  argument
35937 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…  argument
35948 #define XCVR_RD_TSM_OVRD0_QGEN_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_QGEN_R…  argument
35949 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_O…  argument
35952 #define XCVR_WR_TSM_OVRD0_QGEN_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_QG…  argument
35953 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((ui…  argument
35966 #define XCVR_RD_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_T…  argument
35967 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_…  argument
35970 #define XCVR_WR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVR…  argument
35971 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base),…  argument
35982 #define XCVR_RD_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_TCA_…  argument
35983 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…  argument
35986 #define XCVR_WR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_…  argument
35987 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…  argument
36000 #define XCVR_RD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_…  argument
36001 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…  argument
36004 #define XCVR_WR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OV…  argument
36005 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…  argument
36017 #define XCVR_RD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC…  argument
36018 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…  argument
36021 #define XCVR_WR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0…  argument
36022 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…  argument
36035 #define XCVR_RD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_…  argument
36036 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…  argument
36039 #define XCVR_WR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OV…  argument
36040 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…  argument
36052 #define XCVR_RD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC…  argument
36053 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TS…  argument
36056 #define XCVR_WR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0…  argument
36057 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), (…  argument
36070 #define XCVR_RD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_O…  argument
36071 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…  argument
36074 #define XCVR_WR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_T…  argument
36075 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…  argument
36087 #define XCVR_RD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD…  argument
36088 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…  argument
36091 #define XCVR_WR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_…  argument
36092 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…  argument
36105 #define XCVR_RD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_O…  argument
36106 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…  argument
36109 #define XCVR_WR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_T…  argument
36110 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…  argument
36122 #define XCVR_RD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD…  argument
36123 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…  argument
36126 #define XCVR_WR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_…  argument
36127 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…  argument
36140 #define XCVR_RD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_O…  argument
36141 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base),…  argument
36144 #define XCVR_WR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_T…  argument
36145 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(…  argument
36157 #define XCVR_RD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD…  argument
36158 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XC…  argument
36161 #define XCVR_WR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_…  argument
36162 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(bas…  argument
36175 #define XCVR_RD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_…  argument
36176 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base)…  argument
36179 #define XCVR_WR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_…  argument
36180 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG…  argument
36192 #define XCVR_RD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVR…  argument
36193 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…  argument
36196 #define XCVR_WR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM…  argument
36197 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…  argument
36209 #define XCVR_RD_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_…  argument
36210 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…  argument
36213 #define XCVR_WR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_…  argument
36214 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…  argument
36225 #define XCVR_RD_TSM_OVRD0_PLL_VCO_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO…  argument
36226 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…  argument
36229 #define XCVR_WR_TSM_OVRD0_PLL_VCO_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL…  argument
36230 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…  argument
36243 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVR…  argument
36244 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…  argument
36247 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM…  argument
36248 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…  argument
36260 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_…  argument
36261 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…  argument
36264 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OV…  argument
36265 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…  argument
36278 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVR…  argument
36279 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), X…  argument
36282 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM…  argument
36283 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(ba…  argument
36295 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_…  argument
36296 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR…  argument
36299 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OV…  argument
36300 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base)…  argument
36313 #define XCVR_RD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_P…  argument
36314 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_…  argument
36317 #define XCVR_WR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVR…  argument
36318 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base),…  argument
36329 #define XCVR_RD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_…  argument
36330 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…  argument
36333 #define XCVR_WR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_…  argument
36334 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…  argument
36346 #define XCVR_RD_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_…  argument
36347 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM…  argument
36350 #define XCVR_WR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_…  argument
36351 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((…  argument
36362 #define XCVR_RD_TSM_OVRD0_PLL_LDV_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_LDV…  argument
36363 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OV…  argument
36366 #define XCVR_WR_TSM_OVRD0_PLL_LDV_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL…  argument
36367 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uin…  argument
36380 #define XCVR_RD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_…  argument
36381 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(b…  argument
36384 #define XCVR_WR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, X…  argument
36385 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0…  argument
36397 #define XCVR_RD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM…  argument
36398 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base…  argument
36401 #define XCVR_WR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR…  argument
36402 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_RE…  argument
36418 #define XCVR_RD_TSM_OVRD1(base)  (XCVR_TSM_OVRD1_REG(base))  argument
36419 #define XCVR_WR_TSM_OVRD1(base, value) (XCVR_TSM_OVRD1_REG(base) = (value))  argument
36420 #define XCVR_RMW_TSM_OVRD1(base, mask, value) (XCVR_WR_TSM_OVRD1(base, (XCVR_RD_TSM_OVRD1(base) & ~…  argument
36421 #define XCVR_SET_TSM_OVRD1(base, value) (BME_OR32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(value)))  argument
36422 #define XCVR_CLR_TSM_OVRD1(base, value) (BME_AND32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(~(value))))  argument
36423 #define XCVR_TOG_TSM_OVRD1(base, value) (BME_XOR32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(value)))  argument
36440 #define XCVR_RD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_…  argument
36441 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(b…  argument
36444 #define XCVR_WR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, X…  argument
36445 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1…  argument
36457 #define XCVR_RD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM…  argument
36458 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base…  argument
36461 #define XCVR_WR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR…  argument
36462 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_RE…  argument
36475 #define XCVR_RD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_…  argument
36476 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base)…  argument
36479 #define XCVR_WR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_…  argument
36480 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG…  argument
36492 #define XCVR_RD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVR…  argument
36493 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), X…  argument
36496 #define XCVR_WR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM…  argument
36497 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(ba…  argument
36510 #define XCVR_RD_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PL…  argument
36511 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…  argument
36514 #define XCVR_WR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD…  argument
36515 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …  argument
36526 #define XCVR_RD_TSM_OVRD1_PLL_PHDET_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_P…  argument
36527 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…  argument
36530 #define XCVR_WR_TSM_OVRD1_PLL_PHDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_P…  argument
36531 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…  argument
36543 #define XCVR_RD_TSM_OVRD1_QGEN25_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_QGEN2…  argument
36544 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…  argument
36547 #define XCVR_WR_TSM_OVRD1_QGEN25_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_Q…  argument
36548 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…  argument
36559 #define XCVR_RD_TSM_OVRD1_QGEN25_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_QGEN25_E…  argument
36560 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVR…  argument
36563 #define XCVR_WR_TSM_OVRD1_QGEN25_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_QGEN…  argument
36564 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint…  argument
36576 #define XCVR_RD_TSM_OVRD1_TX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_TX_EN_OVR…  argument
36577 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…  argument
36580 #define XCVR_WR_TSM_OVRD1_TX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_TX_EN…  argument
36581 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…  argument
36592 #define XCVR_RD_TSM_OVRD1_TX_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_TX_EN_OVRD_M…  argument
36593 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_T…  argument
36596 #define XCVR_WR_TSM_OVRD1_TX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_TX_EN_OV…  argument
36597 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t…  argument
36609 #define XCVR_RD_TSM_OVRD1_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_EN_O…  argument
36610 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVR…  argument
36613 #define XCVR_WR_TSM_OVRD1_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_…  argument
36614 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint…  argument
36625 #define XCVR_RD_TSM_OVRD1_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_EN_OVRD…  argument
36626 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_…  argument
36629 #define XCVR_WR_TSM_OVRD1_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_EN_…  argument
36630 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_…  argument
36643 #define XCVR_RD_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC…  argument
36644 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…  argument
36647 #define XCVR_WR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1…  argument
36648 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…  argument
36659 #define XCVR_RD_TSM_OVRD1_ADC_BIAS_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_BI…  argument
36660 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36663 #define XCVR_WR_TSM_OVRD1_ADC_BIAS_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_AD…  argument
36664 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36676 #define XCVR_RD_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_…  argument
36677 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM…  argument
36680 #define XCVR_WR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_…  argument
36681 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((…  argument
36692 #define XCVR_RD_TSM_OVRD1_ADC_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_CLK…  argument
36693 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OV…  argument
36696 #define XCVR_WR_TSM_OVRD1_ADC_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC…  argument
36697 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uin…  argument
36710 #define XCVR_RD_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_AD…  argument
36711 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…  argument
36714 #define XCVR_WR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD…  argument
36715 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …  argument
36726 #define XCVR_RD_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_I…  argument
36727 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…  argument
36730 #define XCVR_WR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_A…  argument
36731 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…  argument
36744 #define XCVR_RD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_AD…  argument
36745 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_T…  argument
36748 #define XCVR_WR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD…  argument
36749 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), …  argument
36760 #define XCVR_RD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_Q…  argument
36761 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_…  argument
36764 #define XCVR_WR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_A…  argument
36765 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((u…  argument
36778 #define XCVR_RD_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC…  argument
36779 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…  argument
36782 #define XCVR_WR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1…  argument
36783 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…  argument
36794 #define XCVR_RD_TSM_OVRD1_ADC_DAC1_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DA…  argument
36795 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36798 #define XCVR_WR_TSM_OVRD1_ADC_DAC1_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_AD…  argument
36799 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36812 #define XCVR_RD_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC…  argument
36813 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…  argument
36816 #define XCVR_WR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1…  argument
36817 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…  argument
36828 #define XCVR_RD_TSM_OVRD1_ADC_DAC2_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DA…  argument
36829 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36832 #define XCVR_WR_TSM_OVRD1_ADC_DAC2_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_AD…  argument
36833 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36845 #define XCVR_RD_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_…  argument
36846 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM…  argument
36849 #define XCVR_WR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_…  argument
36850 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((…  argument
36861 #define XCVR_RD_TSM_OVRD1_ADC_RST_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_RST…  argument
36862 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OV…  argument
36865 #define XCVR_WR_TSM_OVRD1_ADC_RST_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC…  argument
36866 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uin…  argument
36878 #define XCVR_RD_TSM_OVRD1_BBF_I_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_I_…  argument
36879 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36882 #define XCVR_WR_TSM_OVRD1_BBF_I_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BB…  argument
36883 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36894 #define XCVR_RD_TSM_OVRD1_BBF_I_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_I_EN_…  argument
36895 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…  argument
36898 #define XCVR_WR_TSM_OVRD1_BBF_I_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_I…  argument
36899 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…  argument
36911 #define XCVR_RD_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_Q_…  argument
36912 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36915 #define XCVR_WR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BB…  argument
36916 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36927 #define XCVR_RD_TSM_OVRD1_BBF_Q_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_Q_EN_…  argument
36928 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD…  argument
36931 #define XCVR_WR_TSM_OVRD1_BBF_Q_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_Q…  argument
36932 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint3…  argument
36945 #define XCVR_RD_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF…  argument
36946 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TS…  argument
36949 #define XCVR_WR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1…  argument
36950 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), (…  argument
36961 #define XCVR_RD_TSM_OVRD1_BBF_PDET_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_PD…  argument
36962 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_O…  argument
36965 #define XCVR_WR_TSM_OVRD1_BBF_PDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BB…  argument
36966 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((ui…  argument
36982 #define XCVR_RD_TSM_OVRD2(base)  (XCVR_TSM_OVRD2_REG(base))  argument
36983 #define XCVR_WR_TSM_OVRD2(base, value) (XCVR_TSM_OVRD2_REG(base) = (value))  argument
36984 #define XCVR_RMW_TSM_OVRD2(base, mask, value) (XCVR_WR_TSM_OVRD2(base, (XCVR_RD_TSM_OVRD2(base) & ~…  argument
36985 #define XCVR_SET_TSM_OVRD2(base, value) (BME_OR32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(value)))  argument
36986 #define XCVR_CLR_TSM_OVRD2(base, value) (BME_AND32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(~(value))))  argument
36987 #define XCVR_TOG_TSM_OVRD2(base, value) (BME_XOR32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(value)))  argument
37004 #define XCVR_RD_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_BBF…  argument
37005 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…  argument
37008 #define XCVR_WR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2…  argument
37009 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…  argument
37020 #define XCVR_RD_TSM_OVRD2_BBF_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_BBF_DC…  argument
37021 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37024 #define XCVR_WR_TSM_OVRD2_BBF_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_BB…  argument
37025 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37037 #define XCVR_RD_TSM_OVRD2_TCA_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TCA_EN_O…  argument
37038 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…  argument
37041 #define XCVR_WR_TSM_OVRD2_TCA_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TCA_…  argument
37042 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…  argument
37053 #define XCVR_RD_TSM_OVRD2_TCA_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TCA_EN_OVRD…  argument
37054 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_…  argument
37057 #define XCVR_WR_TSM_OVRD2_TCA_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TCA_EN_…  argument
37058 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_…  argument
37070 #define XCVR_RD_TSM_OVRD2_TZA_I_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_I_…  argument
37071 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37074 #define XCVR_WR_TSM_OVRD2_TZA_I_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZ…  argument
37075 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37086 #define XCVR_RD_TSM_OVRD2_TZA_I_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_I_EN_…  argument
37087 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD…  argument
37090 #define XCVR_WR_TSM_OVRD2_TZA_I_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_I…  argument
37091 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint3…  argument
37103 #define XCVR_RD_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_Q_…  argument
37104 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37107 #define XCVR_WR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZ…  argument
37108 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37119 #define XCVR_RD_TSM_OVRD2_TZA_Q_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_Q_EN_…  argument
37120 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD…  argument
37123 #define XCVR_WR_TSM_OVRD2_TZA_Q_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_Q…  argument
37124 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint3…  argument
37137 #define XCVR_RD_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA…  argument
37138 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…  argument
37141 #define XCVR_WR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2…  argument
37142 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…  argument
37153 #define XCVR_RD_TSM_OVRD2_TZA_PDET_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_PD…  argument
37154 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37157 #define XCVR_WR_TSM_OVRD2_TZA_PDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZ…  argument
37158 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37171 #define XCVR_RD_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA…  argument
37172 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…  argument
37175 #define XCVR_WR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2…  argument
37176 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…  argument
37187 #define XCVR_RD_TSM_OVRD2_TZA_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_DC…  argument
37188 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37191 #define XCVR_WR_TSM_OVRD2_TZA_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZ…  argument
37192 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37204 #define XCVR_RD_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_PLL_…  argument
37205 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM…  argument
37208 #define XCVR_WR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_…  argument
37209 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((…  argument
37220 #define XCVR_RD_TSM_OVRD2_PLL_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_PLL_DIG…  argument
37221 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…  argument
37224 #define XCVR_WR_TSM_OVRD2_PLL_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_PLL…  argument
37225 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…  argument
37237 #define XCVR_RD_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TX_DI…  argument
37238 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…  argument
37241 #define XCVR_WR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_T…  argument
37242 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…  argument
37253 #define XCVR_RD_TSM_OVRD2_TX_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TX_DIG_E…  argument
37254 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…  argument
37257 #define XCVR_WR_TSM_OVRD2_TX_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TX_D…  argument
37258 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…  argument
37270 #define XCVR_RD_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_DI…  argument
37271 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…  argument
37274 #define XCVR_WR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_R…  argument
37275 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…  argument
37286 #define XCVR_RD_TSM_OVRD2_RX_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_DIG_E…  argument
37287 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…  argument
37290 #define XCVR_WR_TSM_OVRD2_RX_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_D…  argument
37291 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…  argument
37303 #define XCVR_RD_TSM_OVRD2_RX_INIT_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_INIT…  argument
37304 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…  argument
37307 #define XCVR_WR_TSM_OVRD2_RX_INIT_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_…  argument
37308 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…  argument
37319 #define XCVR_RD_TSM_OVRD2_RX_INIT_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_INIT_OV…  argument
37320 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2…  argument
37323 #define XCVR_WR_TSM_OVRD2_RX_INIT_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_INI…  argument
37324 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32…  argument
37337 #define XCVR_RD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_…  argument
37338 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR…  argument
37341 #define XCVR_WR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OV…  argument
37342 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base)…  argument
37354 #define XCVR_RD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SIG…  argument
37355 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…  argument
37358 #define XCVR_WR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2…  argument
37359 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…  argument
37372 #define XCVR_RD_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_ZBD…  argument
37373 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TS…  argument
37376 #define XCVR_WR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2…  argument
37377 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), (…  argument
37388 #define XCVR_RD_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_ZBDEM_…  argument
37389 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_O…  argument
37392 #define XCVR_WR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_ZB…  argument
37393 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((ui…  argument
37405 #define XCVR_RD_TSM_OVRD2_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_EN…  argument
37406 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OV…  argument
37409 #define XCVR_WR_TSM_OVRD2_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCO…  argument
37410 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uin…  argument
37421 #define XCVR_RD_TSM_OVRD2_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_EN_OV…  argument
37422 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2…  argument
37425 #define XCVR_WR_TSM_OVRD2_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC_E…  argument
37426 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32…  argument
37438 #define XCVR_RD_TSM_OVRD2_DCOC_INIT_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_…  argument
37439 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_…  argument
37442 #define XCVR_WR_TSM_OVRD2_DCOC_INIT_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_D…  argument
37443 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((u…  argument
37454 #define XCVR_RD_TSM_OVRD2_DCOC_INIT_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_INI…  argument
37455 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVR…  argument
37458 #define XCVR_WR_TSM_OVRD2_DCOC_INIT_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC…  argument
37459 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint…  argument
37472 #define XCVR_RD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2…  argument
37473 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCV…  argument
37476 #define XCVR_WR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_O…  argument
37477 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base…  argument
37489 #define XCVR_RD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_FR…  argument
37490 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_T…  argument
37493 #define XCVR_WR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD…  argument
37494 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), …  argument
37507 #define XCVR_RD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2…  argument
37508 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCV…  argument
37511 #define XCVR_WR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_O…  argument
37512 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base…  argument
37524 #define XCVR_RD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SA…  argument
37525 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_T…  argument
37528 #define XCVR_WR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD…  argument
37529 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), …  argument
37545 #define XCVR_RD_TSM_OVRD3(base)  (XCVR_TSM_OVRD3_REG(base))  argument
37546 #define XCVR_WR_TSM_OVRD3(base, value) (XCVR_TSM_OVRD3_REG(base) = (value))  argument
37547 #define XCVR_RMW_TSM_OVRD3(base, mask, value) (XCVR_WR_TSM_OVRD3(base, (XCVR_RD_TSM_OVRD3(base) & ~…  argument
37548 #define XCVR_SET_TSM_OVRD3(base, value) (BME_OR32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(value)))  argument
37549 #define XCVR_CLR_TSM_OVRD3(base, value) (BME_AND32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(~(value))))  argument
37550 #define XCVR_TOG_TSM_OVRD3(base, value) (BME_XOR32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(value)))  argument
37567 #define XCVR_RD_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_T…  argument
37568 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…  argument
37571 #define XCVR_WR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVR…  argument
37572 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…  argument
37583 #define XCVR_RD_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_…  argument
37584 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…  argument
37587 #define XCVR_WR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_…  argument
37588 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…  argument
37601 #define XCVR_RD_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_T…  argument
37602 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…  argument
37605 #define XCVR_WR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVR…  argument
37606 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…  argument
37617 #define XCVR_RD_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_…  argument
37618 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…  argument
37621 #define XCVR_WR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_…  argument
37622 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…  argument
37635 #define XCVR_RD_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_T…  argument
37636 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…  argument
37639 #define XCVR_WR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVR…  argument
37640 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…  argument
37651 #define XCVR_RD_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_…  argument
37652 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…  argument
37655 #define XCVR_WR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_…  argument
37656 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…  argument
37669 #define XCVR_RD_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_T…  argument
37670 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_…  argument
37673 #define XCVR_WR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVR…  argument
37674 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base),…  argument
37685 #define XCVR_RD_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_…  argument
37686 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM…  argument
37689 #define XCVR_WR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_…  argument
37690 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((…  argument
37702 #define XCVR_RD_TSM_OVRD3_TX_MODE_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TX_MODE…  argument
37703 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OV…  argument
37706 #define XCVR_WR_TSM_OVRD3_TX_MODE_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TX_…  argument
37707 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uin…  argument
37718 #define XCVR_RD_TSM_OVRD3_TX_MODE_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TX_MODE_OV…  argument
37719 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3…  argument
37722 #define XCVR_WR_TSM_OVRD3_TX_MODE_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TX_MOD…  argument
37723 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32…  argument
37735 #define XCVR_RD_TSM_OVRD3_RX_MODE_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_RX_MODE…  argument
37736 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OV…  argument
37739 #define XCVR_WR_TSM_OVRD3_RX_MODE_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_RX_…  argument
37740 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uin…  argument
37751 #define XCVR_RD_TSM_OVRD3_RX_MODE_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_RX_MODE_OV…  argument
37752 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3…  argument
37755 #define XCVR_WR_TSM_OVRD3_RX_MODE_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_RX_MOD…  argument
37756 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32…  argument
37775 #define XCVR_RD_PA_POWER(base)   (XCVR_PA_POWER_REG(base))  argument
37776 #define XCVR_WR_PA_POWER(base, value) (XCVR_PA_POWER_REG(base) = (value))  argument
37777 #define XCVR_RMW_PA_POWER(base, mask, value) (XCVR_WR_PA_POWER(base, (XCVR_RD_PA_POWER(base) & ~(ma…  argument
37778 #define XCVR_SET_PA_POWER(base, value) (BME_OR32(&XCVR_PA_POWER_REG(base), (uint32_t)(value)))  argument
37779 #define XCVR_CLR_PA_POWER(base, value) (BME_AND32(&XCVR_PA_POWER_REG(base), (uint32_t)(~(value))))  argument
37780 #define XCVR_TOG_PA_POWER(base, value) (BME_XOR32(&XCVR_PA_POWER_REG(base), (uint32_t)(value)))  argument
37794 #define XCVR_RD_PA_POWER_PA_POWER(base) ((XCVR_PA_POWER_REG(base) & XCVR_PA_POWER_PA_POWER_MASK) >>…  argument
37795 #define XCVR_BRD_PA_POWER_PA_POWER(base) (BME_UBFX32(&XCVR_PA_POWER_REG(base), XCVR_PA_POWER_PA_POW…  argument
37798 #define XCVR_WR_PA_POWER_PA_POWER(base, value) (XCVR_RMW_PA_POWER(base, XCVR_PA_POWER_PA_POWER_MASK…  argument
37799 #define XCVR_BWR_PA_POWER_PA_POWER(base, value) (BME_BFI32(&XCVR_PA_POWER_REG(base), ((uint32_t)(va…  argument
37815 #define XCVR_RD_PA_BIAS_TBL0(base) (XCVR_PA_BIAS_TBL0_REG(base))  argument
37816 #define XCVR_WR_PA_BIAS_TBL0(base, value) (XCVR_PA_BIAS_TBL0_REG(base) = (value))  argument
37817 #define XCVR_RMW_PA_BIAS_TBL0(base, mask, value) (XCVR_WR_PA_BIAS_TBL0(base, (XCVR_RD_PA_BIAS_TBL0(…  argument
37818 #define XCVR_SET_PA_BIAS_TBL0(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(value…  argument
37819 #define XCVR_CLR_PA_BIAS_TBL0(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(~(va…  argument
37820 #define XCVR_TOG_PA_BIAS_TBL0(base, value) (BME_XOR32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(valu…  argument
37840 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS0(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BI…  argument
37841 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS0(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…  argument
37844 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS0(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_P…  argument
37845 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS0(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…  argument
37859 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS1(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BI…  argument
37860 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS1(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…  argument
37863 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS1(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_P…  argument
37864 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS1(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…  argument
37878 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS2(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BI…  argument
37879 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS2(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…  argument
37882 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS2(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_P…  argument
37883 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS2(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…  argument
37897 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS3(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BI…  argument
37898 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS3(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS…  argument
37901 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS3(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_P…  argument
37902 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS3(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint…  argument
37918 #define XCVR_RD_PA_BIAS_TBL1(base) (XCVR_PA_BIAS_TBL1_REG(base))  argument
37919 #define XCVR_WR_PA_BIAS_TBL1(base, value) (XCVR_PA_BIAS_TBL1_REG(base) = (value))  argument
37920 #define XCVR_RMW_PA_BIAS_TBL1(base, mask, value) (XCVR_WR_PA_BIAS_TBL1(base, (XCVR_RD_PA_BIAS_TBL1(…  argument
37921 #define XCVR_SET_PA_BIAS_TBL1(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(value…  argument
37922 #define XCVR_CLR_PA_BIAS_TBL1(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(~(va…  argument
37923 #define XCVR_TOG_PA_BIAS_TBL1(base, value) (BME_XOR32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(valu…  argument
37941 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS4(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BI…  argument
37942 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS4(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…  argument
37945 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS4(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_P…  argument
37946 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS4(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…  argument
37960 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS5(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BI…  argument
37961 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS5(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…  argument
37964 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS5(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_P…  argument
37965 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS5(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…  argument
37979 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS6(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BI…  argument
37980 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS6(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…  argument
37983 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS6(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_P…  argument
37984 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS6(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…  argument
37998 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS7(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BI…  argument
37999 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS7(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS…  argument
38002 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS7(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_P…  argument
38003 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS7(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint…  argument
38019 #define XCVR_RD_RECYCLE_COUNT(base) (XCVR_RECYCLE_COUNT_REG(base))  argument
38020 #define XCVR_WR_RECYCLE_COUNT(base, value) (XCVR_RECYCLE_COUNT_REG(base) = (value))  argument
38021 #define XCVR_RMW_RECYCLE_COUNT(base, mask, value) (XCVR_WR_RECYCLE_COUNT(base, (XCVR_RD_RECYCLE_COU…  argument
38022 #define XCVR_SET_RECYCLE_COUNT(base, value) (BME_OR32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(val…  argument
38023 #define XCVR_CLR_RECYCLE_COUNT(base, value) (BME_AND32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(~(…  argument
38024 #define XCVR_TOG_RECYCLE_COUNT(base, value) (BME_XOR32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(va…  argument
38049 #define XCVR_RD_RECYCLE_COUNT_RECYCLE_COUNT0(base) ((XCVR_RECYCLE_COUNT_REG(base) & XCVR_RECYCLE_CO…  argument
38050 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT0(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR…  argument
38053 #define XCVR_WR_RECYCLE_COUNT_RECYCLE_COUNT0(base, value) (XCVR_RMW_RECYCLE_COUNT(base, XCVR_RECYCL…  argument
38054 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT0(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base)…  argument
38075 #define XCVR_RD_RECYCLE_COUNT_RECYCLE_COUNT1(base) ((XCVR_RECYCLE_COUNT_REG(base) & XCVR_RECYCLE_CO…  argument
38076 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT1(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR…  argument
38079 #define XCVR_WR_RECYCLE_COUNT_RECYCLE_COUNT1(base, value) (XCVR_RMW_RECYCLE_COUNT(base, XCVR_RECYCL…  argument
38080 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT1(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base)…  argument
38100 #define XCVR_RD_TSM_TIMING00(base) (XCVR_TSM_TIMING00_REG(base))  argument
38101 #define XCVR_WR_TSM_TIMING00(base, value) (XCVR_TSM_TIMING00_REG(base) = (value))  argument
38102 #define XCVR_RMW_TSM_TIMING00(base, mask, value) (XCVR_WR_TSM_TIMING00(base, (XCVR_RD_TSM_TIMING00(…  argument
38103 #define XCVR_SET_TSM_TIMING00(base, value) (BME_OR32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(value…  argument
38104 #define XCVR_CLR_TSM_TIMING00(base, value) (BME_AND32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(~(va…  argument
38105 #define XCVR_TOG_TSM_TIMING00(base, value) (BME_XOR32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(valu…  argument
38120 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING…  argument
38121 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…  argument
38124 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TI…  argument
38125 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…  argument
38136 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING…  argument
38137 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…  argument
38140 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TI…  argument
38141 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…  argument
38152 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING…  argument
38153 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…  argument
38156 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TI…  argument
38157 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…  argument
38168 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING…  argument
38169 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR…  argument
38172 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TI…  argument
38173 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base)…  argument
38193 #define XCVR_RD_TSM_TIMING01(base) (XCVR_TSM_TIMING01_REG(base))  argument
38194 #define XCVR_WR_TSM_TIMING01(base, value) (XCVR_TSM_TIMING01_REG(base) = (value))  argument
38195 #define XCVR_RMW_TSM_TIMING01(base, mask, value) (XCVR_WR_TSM_TIMING01(base, (XCVR_RD_TSM_TIMING01(…  argument
38196 #define XCVR_SET_TSM_TIMING01(base, value) (BME_OR32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(value…  argument
38197 #define XCVR_CLR_TSM_TIMING01(base, value) (BME_AND32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(~(va…  argument
38198 #define XCVR_TOG_TSM_TIMING01(base, value) (BME_XOR32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(valu…  argument
38213 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TI…  argument
38214 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …  argument
38217 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TS…  argument
38218 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…  argument
38229 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TI…  argument
38230 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …  argument
38233 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TS…  argument
38234 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…  argument
38245 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TI…  argument
38246 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …  argument
38249 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TS…  argument
38250 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…  argument
38261 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TI…  argument
38262 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), …  argument
38265 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TS…  argument
38266 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(b…  argument
38286 #define XCVR_RD_TSM_TIMING02(base) (XCVR_TSM_TIMING02_REG(base))  argument
38287 #define XCVR_WR_TSM_TIMING02(base, value) (XCVR_TSM_TIMING02_REG(base) = (value))  argument
38288 #define XCVR_RMW_TSM_TIMING02(base, mask, value) (XCVR_WR_TSM_TIMING02(base, (XCVR_RD_TSM_TIMING02(…  argument
38289 #define XCVR_SET_TSM_TIMING02(base, value) (BME_OR32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(value…  argument
38290 #define XCVR_CLR_TSM_TIMING02(base, value) (BME_AND32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(~(va…  argument
38291 #define XCVR_TOG_TSM_TIMING02(base, value) (BME_XOR32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(valu…  argument
38306 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMIN…  argument
38307 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…  argument
38310 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_T…  argument
38311 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…  argument
38322 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMIN…  argument
38323 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…  argument
38326 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_T…  argument
38327 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…  argument
38338 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMIN…  argument
38339 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…  argument
38342 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_T…  argument
38343 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…  argument
38354 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMIN…  argument
38355 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCV…  argument
38358 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_T…  argument
38359 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base…  argument
38379 #define XCVR_RD_TSM_TIMING03(base) (XCVR_TSM_TIMING03_REG(base))  argument
38380 #define XCVR_WR_TSM_TIMING03(base, value) (XCVR_TSM_TIMING03_REG(base) = (value))  argument
38381 #define XCVR_RMW_TSM_TIMING03(base, mask, value) (XCVR_WR_TSM_TIMING03(base, (XCVR_RD_TSM_TIMING03(…  argument
38382 #define XCVR_SET_TSM_TIMING03(base, value) (BME_OR32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(value…  argument
38383 #define XCVR_CLR_TSM_TIMING03(base, value) (BME_AND32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(~(va…  argument
38384 #define XCVR_TOG_TSM_TIMING03(base, value) (BME_XOR32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(valu…  argument
38399 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIM…  argument
38400 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…  argument
38403 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM…  argument
38404 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…  argument
38415 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIM…  argument
38416 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…  argument
38419 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM…  argument
38420 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…  argument
38431 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIM…  argument
38432 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…  argument
38435 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM…  argument
38436 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…  argument
38447 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIM…  argument
38448 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), X…  argument
38451 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM…  argument
38452 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(ba…  argument
38472 #define XCVR_RD_TSM_TIMING04(base) (XCVR_TSM_TIMING04_REG(base))  argument
38473 #define XCVR_WR_TSM_TIMING04(base, value) (XCVR_TSM_TIMING04_REG(base) = (value))  argument
38474 #define XCVR_RMW_TSM_TIMING04(base, mask, value) (XCVR_WR_TSM_TIMING04(base, (XCVR_RD_TSM_TIMING04(…  argument
38475 #define XCVR_SET_TSM_TIMING04(base, value) (BME_OR32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(value…  argument
38476 #define XCVR_CLR_TSM_TIMING04(base, value) (BME_AND32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(~(va…  argument
38477 #define XCVR_TOG_TSM_TIMING04(base, value) (BME_XOR32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(valu…  argument
38492 #define XCVR_RD_TSM_TIMING04_ADC_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING04_REG(base) & XCVR_TSM_TIMING…  argument
38493 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR…  argument
38496 #define XCVR_WR_TSM_TIMING04_ADC_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING04(base, XCVR_TSM_TI…  argument
38497 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base)…  argument
38508 #define XCVR_RD_TSM_TIMING04_ADC_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING04_REG(base) & XCVR_TSM_TIMING…  argument
38509 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR…  argument
38512 #define XCVR_WR_TSM_TIMING04_ADC_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING04(base, XCVR_TSM_TI…  argument
38513 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base)…  argument
38533 #define XCVR_RD_TSM_TIMING05(base) (XCVR_TSM_TIMING05_REG(base))  argument
38534 #define XCVR_WR_TSM_TIMING05(base, value) (XCVR_TSM_TIMING05_REG(base) = (value))  argument
38535 #define XCVR_RMW_TSM_TIMING05(base, mask, value) (XCVR_WR_TSM_TIMING05(base, (XCVR_RD_TSM_TIMING05(…  argument
38536 #define XCVR_SET_TSM_TIMING05(base, value) (BME_OR32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(value…  argument
38537 #define XCVR_CLR_TSM_TIMING05(base, value) (BME_AND32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(~(va…  argument
38538 #define XCVR_TOG_TSM_TIMING05(base, value) (BME_XOR32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(valu…  argument
38553 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TI…  argument
38554 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …  argument
38557 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TS…  argument
38558 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…  argument
38569 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TI…  argument
38570 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …  argument
38573 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TS…  argument
38574 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…  argument
38585 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TI…  argument
38586 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …  argument
38589 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TS…  argument
38590 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…  argument
38601 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TI…  argument
38602 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), …  argument
38605 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TS…  argument
38606 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(b…  argument
38626 #define XCVR_RD_TSM_TIMING06(base) (XCVR_TSM_TIMING06_REG(base))  argument
38627 #define XCVR_WR_TSM_TIMING06(base, value) (XCVR_TSM_TIMING06_REG(base) = (value))  argument
38628 #define XCVR_RMW_TSM_TIMING06(base, mask, value) (XCVR_WR_TSM_TIMING06(base, (XCVR_RD_TSM_TIMING06(…  argument
38629 #define XCVR_SET_TSM_TIMING06(base, value) (BME_OR32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(value…  argument
38630 #define XCVR_CLR_TSM_TIMING06(base, value) (BME_AND32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(~(va…  argument
38631 #define XCVR_TOG_TSM_TIMING06(base, value) (BME_XOR32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(valu…  argument
38646 #define XCVR_RD_TSM_TIMING06_ADC_CLK_EN_RX_HI(base) ((XCVR_TSM_TIMING06_REG(base) & XCVR_TSM_TIMING…  argument
38647 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR…  argument
38650 #define XCVR_WR_TSM_TIMING06_ADC_CLK_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING06(base, XCVR_TSM_TI…  argument
38651 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base)…  argument
38662 #define XCVR_RD_TSM_TIMING06_ADC_CLK_EN_RX_LO(base) ((XCVR_TSM_TIMING06_REG(base) & XCVR_TSM_TIMING…  argument
38663 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR…  argument
38666 #define XCVR_WR_TSM_TIMING06_ADC_CLK_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING06(base, XCVR_TSM_TI…  argument
38667 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base)…  argument
38687 #define XCVR_RD_TSM_TIMING07(base) (XCVR_TSM_TIMING07_REG(base))  argument
38688 #define XCVR_WR_TSM_TIMING07(base, value) (XCVR_TSM_TIMING07_REG(base) = (value))  argument
38689 #define XCVR_RMW_TSM_TIMING07(base, mask, value) (XCVR_WR_TSM_TIMING07(base, (XCVR_RD_TSM_TIMING07(…  argument
38690 #define XCVR_SET_TSM_TIMING07(base, value) (BME_OR32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(value…  argument
38691 #define XCVR_CLR_TSM_TIMING07(base, value) (BME_AND32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(~(va…  argument
38692 #define XCVR_TOG_TSM_TIMING07(base, value) (BME_XOR32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(valu…  argument
38708 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_T…  argument
38709 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…  argument
38712 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING07(base, XC…  argument
38713 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…  argument
38725 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_T…  argument
38726 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…  argument
38729 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING07(base, XC…  argument
38730 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…  argument
38742 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_T…  argument
38743 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…  argument
38746 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING07(base, XC…  argument
38747 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…  argument
38759 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_T…  argument
38760 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(ba…  argument
38763 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING07(base, XC…  argument
38764 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_…  argument
38784 #define XCVR_RD_TSM_TIMING08(base) (XCVR_TSM_TIMING08_REG(base))  argument
38785 #define XCVR_WR_TSM_TIMING08(base, value) (XCVR_TSM_TIMING08_REG(base) = (value))  argument
38786 #define XCVR_RMW_TSM_TIMING08(base, mask, value) (XCVR_WR_TSM_TIMING08(base, (XCVR_RD_TSM_TIMING08(…  argument
38787 #define XCVR_SET_TSM_TIMING08(base, value) (BME_OR32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(value…  argument
38788 #define XCVR_CLR_TSM_TIMING08(base, value) (BME_AND32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(~(va…  argument
38789 #define XCVR_TOG_TSM_TIMING08(base, value) (BME_XOR32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(valu…  argument
38805 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_…  argument
38806 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…  argument
38809 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING08(base, X…  argument
38810 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…  argument
38822 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_…  argument
38823 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…  argument
38826 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING08(base, X…  argument
38827 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…  argument
38839 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_…  argument
38840 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…  argument
38843 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING08(base, X…  argument
38844 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…  argument
38856 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_…  argument
38857 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(b…  argument
38860 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING08(base, X…  argument
38861 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08…  argument
38881 #define XCVR_RD_TSM_TIMING09(base) (XCVR_TSM_TIMING09_REG(base))  argument
38882 #define XCVR_WR_TSM_TIMING09(base, value) (XCVR_TSM_TIMING09_REG(base) = (value))  argument
38883 #define XCVR_RMW_TSM_TIMING09(base, mask, value) (XCVR_WR_TSM_TIMING09(base, (XCVR_RD_TSM_TIMING09(…  argument
38884 #define XCVR_SET_TSM_TIMING09(base, value) (BME_OR32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(value…  argument
38885 #define XCVR_CLR_TSM_TIMING09(base, value) (BME_AND32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(~(va…  argument
38886 #define XCVR_TOG_TSM_TIMING09(base, value) (BME_XOR32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(valu…  argument
38901 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_TX_HI(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING…  argument
38902 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…  argument
38905 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TI…  argument
38906 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…  argument
38917 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_TX_LO(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING…  argument
38918 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…  argument
38921 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TI…  argument
38922 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…  argument
38933 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_RX_HI(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING…  argument
38934 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…  argument
38937 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TI…  argument
38938 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…  argument
38949 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_RX_LO(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING…  argument
38950 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR…  argument
38953 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TI…  argument
38954 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base)…  argument
38974 #define XCVR_RD_TSM_TIMING10(base) (XCVR_TSM_TIMING10_REG(base))  argument
38975 #define XCVR_WR_TSM_TIMING10(base, value) (XCVR_TSM_TIMING10_REG(base) = (value))  argument
38976 #define XCVR_RMW_TSM_TIMING10(base, mask, value) (XCVR_WR_TSM_TIMING10(base, (XCVR_RD_TSM_TIMING10(…  argument
38977 #define XCVR_SET_TSM_TIMING10(base, value) (BME_OR32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(value…  argument
38978 #define XCVR_CLR_TSM_TIMING10(base, value) (BME_AND32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(~(va…  argument
38979 #define XCVR_TOG_TSM_TIMING10(base, value) (BME_XOR32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(valu…  argument
38994 #define XCVR_RD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base) ((XCVR_TSM_TIMING10_REG(base) & XCVR_TSM…  argument
38995 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base…  argument
38998 #define XCVR_WR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING10(base, XCVR…  argument
38999 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_RE…  argument
39010 #define XCVR_RD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base) ((XCVR_TSM_TIMING10_REG(base) & XCVR_TSM…  argument
39011 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base…  argument
39014 #define XCVR_WR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING10(base, XCVR…  argument
39015 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_RE…  argument
39035 #define XCVR_RD_TSM_TIMING11(base) (XCVR_TSM_TIMING11_REG(base))  argument
39036 #define XCVR_WR_TSM_TIMING11(base, value) (XCVR_TSM_TIMING11_REG(base) = (value))  argument
39037 #define XCVR_RMW_TSM_TIMING11(base, mask, value) (XCVR_WR_TSM_TIMING11(base, (XCVR_RD_TSM_TIMING11(…  argument
39038 #define XCVR_SET_TSM_TIMING11(base, value) (BME_OR32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(value…  argument
39039 #define XCVR_CLR_TSM_TIMING11(base, value) (BME_AND32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(~(va…  argument
39040 #define XCVR_TOG_TSM_TIMING11(base, value) (BME_XOR32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(valu…  argument
39055 #define XCVR_RD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base) ((XCVR_TSM_TIMING11_REG(base) & XCVR_TSM…  argument
39056 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base…  argument
39059 #define XCVR_WR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING11(base, XCVR…  argument
39060 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_RE…  argument
39071 #define XCVR_RD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base) ((XCVR_TSM_TIMING11_REG(base) & XCVR_TSM…  argument
39072 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base…  argument
39075 #define XCVR_WR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING11(base, XCVR…  argument
39076 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_RE…  argument
39096 #define XCVR_RD_TSM_TIMING12(base) (XCVR_TSM_TIMING12_REG(base))  argument
39097 #define XCVR_WR_TSM_TIMING12(base, value) (XCVR_TSM_TIMING12_REG(base) = (value))  argument
39098 #define XCVR_RMW_TSM_TIMING12(base, mask, value) (XCVR_WR_TSM_TIMING12(base, (XCVR_RD_TSM_TIMING12(…  argument
39099 #define XCVR_SET_TSM_TIMING12(base, value) (BME_OR32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(value…  argument
39100 #define XCVR_CLR_TSM_TIMING12(base, value) (BME_AND32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(~(va…  argument
39101 #define XCVR_TOG_TSM_TIMING12(base, value) (BME_XOR32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(valu…  argument
39116 #define XCVR_RD_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base) ((XCVR_TSM_TIMING12_REG(base) & XCVR_TSM_TIM…  argument
39117 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), X…  argument
39120 #define XCVR_WR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING12(base, XCVR_TSM…  argument
39121 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(ba…  argument
39132 #define XCVR_RD_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base) ((XCVR_TSM_TIMING12_REG(base) & XCVR_TSM_TIM…  argument
39133 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), X…  argument
39136 #define XCVR_WR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING12(base, XCVR_TSM…  argument
39137 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(ba…  argument
39157 #define XCVR_RD_TSM_TIMING13(base) (XCVR_TSM_TIMING13_REG(base))  argument
39158 #define XCVR_WR_TSM_TIMING13(base, value) (XCVR_TSM_TIMING13_REG(base) = (value))  argument
39159 #define XCVR_RMW_TSM_TIMING13(base, mask, value) (XCVR_WR_TSM_TIMING13(base, (XCVR_RD_TSM_TIMING13(…  argument
39160 #define XCVR_SET_TSM_TIMING13(base, value) (BME_OR32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(value…  argument
39161 #define XCVR_CLR_TSM_TIMING13(base, value) (BME_AND32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(~(va…  argument
39162 #define XCVR_TOG_TSM_TIMING13(base, value) (BME_XOR32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(valu…  argument
39177 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_TX_HI(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING…  argument
39178 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…  argument
39181 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TI…  argument
39182 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…  argument
39193 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_TX_LO(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING…  argument
39194 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…  argument
39197 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TI…  argument
39198 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…  argument
39209 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_RX_HI(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING…  argument
39210 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…  argument
39213 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TI…  argument
39214 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…  argument
39225 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_RX_LO(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING…  argument
39226 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR…  argument
39229 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TI…  argument
39230 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base)…  argument
39250 #define XCVR_RD_TSM_TIMING14(base) (XCVR_TSM_TIMING14_REG(base))  argument
39251 #define XCVR_WR_TSM_TIMING14(base, value) (XCVR_TSM_TIMING14_REG(base) = (value))  argument
39252 #define XCVR_RMW_TSM_TIMING14(base, mask, value) (XCVR_WR_TSM_TIMING14(base, (XCVR_RD_TSM_TIMING14(…  argument
39253 #define XCVR_SET_TSM_TIMING14(base, value) (BME_OR32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(value…  argument
39254 #define XCVR_CLR_TSM_TIMING14(base, value) (BME_AND32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(~(va…  argument
39255 #define XCVR_TOG_TSM_TIMING14(base, value) (BME_XOR32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(valu…  argument
39271 #define XCVR_RD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base) ((XCVR_TSM_TIMING14_REG(base) & X…  argument
39272 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING14_R…  argument
39275 #define XCVR_WR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING14(bas…  argument
39276 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMI…  argument
39288 #define XCVR_RD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base) ((XCVR_TSM_TIMING14_REG(base) & X…  argument
39289 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING14_R…  argument
39292 #define XCVR_WR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING14(bas…  argument
39293 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMI…  argument
39313 #define XCVR_RD_TSM_TIMING15(base) (XCVR_TSM_TIMING15_REG(base))  argument
39314 #define XCVR_WR_TSM_TIMING15(base, value) (XCVR_TSM_TIMING15_REG(base) = (value))  argument
39315 #define XCVR_RMW_TSM_TIMING15(base, mask, value) (XCVR_WR_TSM_TIMING15(base, (XCVR_RD_TSM_TIMING15(…  argument
39316 #define XCVR_SET_TSM_TIMING15(base, value) (BME_OR32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(value…  argument
39317 #define XCVR_CLR_TSM_TIMING15(base, value) (BME_AND32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(~(va…  argument
39318 #define XCVR_TOG_TSM_TIMING15(base, value) (BME_XOR32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(valu…  argument
39334 #define XCVR_RD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base) ((XCVR_TSM_TIMING15_REG(base) & X…  argument
39335 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING15_R…  argument
39338 #define XCVR_WR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING15(bas…  argument
39339 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMI…  argument
39351 #define XCVR_RD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base) ((XCVR_TSM_TIMING15_REG(base) & X…  argument
39352 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING15_R…  argument
39355 #define XCVR_WR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING15(bas…  argument
39356 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMI…  argument
39376 #define XCVR_RD_TSM_TIMING16(base) (XCVR_TSM_TIMING16_REG(base))  argument
39377 #define XCVR_WR_TSM_TIMING16(base, value) (XCVR_TSM_TIMING16_REG(base) = (value))  argument
39378 #define XCVR_RMW_TSM_TIMING16(base, mask, value) (XCVR_WR_TSM_TIMING16(base, (XCVR_RD_TSM_TIMING16(…  argument
39379 #define XCVR_SET_TSM_TIMING16(base, value) (BME_OR32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(value…  argument
39380 #define XCVR_CLR_TSM_TIMING16(base, value) (BME_AND32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(~(va…  argument
39381 #define XCVR_TOG_TSM_TIMING16(base, value) (BME_XOR32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(valu…  argument
39397 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_…  argument
39398 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…  argument
39401 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING16(base, X…  argument
39402 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…  argument
39414 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_…  argument
39415 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…  argument
39418 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING16(base, X…  argument
39419 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…  argument
39431 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_…  argument
39432 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…  argument
39435 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING16(base, X…  argument
39436 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…  argument
39448 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_…  argument
39449 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(b…  argument
39452 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING16(base, X…  argument
39453 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16…  argument
39473 #define XCVR_RD_TSM_TIMING17(base) (XCVR_TSM_TIMING17_REG(base))  argument
39474 #define XCVR_WR_TSM_TIMING17(base, value) (XCVR_TSM_TIMING17_REG(base) = (value))  argument
39475 #define XCVR_RMW_TSM_TIMING17(base, mask, value) (XCVR_WR_TSM_TIMING17(base, (XCVR_RD_TSM_TIMING17(…  argument
39476 #define XCVR_SET_TSM_TIMING17(base, value) (BME_OR32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(value…  argument
39477 #define XCVR_CLR_TSM_TIMING17(base, value) (BME_AND32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(~(va…  argument
39478 #define XCVR_TOG_TSM_TIMING17(base, value) (BME_XOR32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(valu…  argument
39493 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMI…  argument
39494 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…  argument
39497 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_…  argument
39498 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…  argument
39509 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMI…  argument
39510 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…  argument
39513 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_…  argument
39514 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…  argument
39525 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMI…  argument
39526 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…  argument
39529 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_…  argument
39530 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…  argument
39541 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMI…  argument
39542 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XC…  argument
39545 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_…  argument
39546 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(bas…  argument
39566 #define XCVR_RD_TSM_TIMING18(base) (XCVR_TSM_TIMING18_REG(base))  argument
39567 #define XCVR_WR_TSM_TIMING18(base, value) (XCVR_TSM_TIMING18_REG(base) = (value))  argument
39568 #define XCVR_RMW_TSM_TIMING18(base, mask, value) (XCVR_WR_TSM_TIMING18(base, (XCVR_RD_TSM_TIMING18(…  argument
39569 #define XCVR_SET_TSM_TIMING18(base, value) (BME_OR32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(value…  argument
39570 #define XCVR_CLR_TSM_TIMING18(base, value) (BME_AND32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(~(va…  argument
39571 #define XCVR_TOG_TSM_TIMING18(base, value) (BME_XOR32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(valu…  argument
39586 #define XCVR_RD_TSM_TIMING18_QGEN25_EN_RX_HI(base) ((XCVR_TSM_TIMING18_REG(base) & XCVR_TSM_TIMING1…  argument
39587 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_…  argument
39590 #define XCVR_WR_TSM_TIMING18_QGEN25_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING18(base, XCVR_TSM_TIM…  argument
39591 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base),…  argument
39602 #define XCVR_RD_TSM_TIMING18_QGEN25_EN_RX_LO(base) ((XCVR_TSM_TIMING18_REG(base) & XCVR_TSM_TIMING1…  argument
39603 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_…  argument
39606 #define XCVR_WR_TSM_TIMING18_QGEN25_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING18(base, XCVR_TSM_TIM…  argument
39607 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base),…  argument
39627 #define XCVR_RD_TSM_TIMING19(base) (XCVR_TSM_TIMING19_REG(base))  argument
39628 #define XCVR_WR_TSM_TIMING19(base, value) (XCVR_TSM_TIMING19_REG(base) = (value))  argument
39629 #define XCVR_RMW_TSM_TIMING19(base, mask, value) (XCVR_WR_TSM_TIMING19(base, (XCVR_RD_TSM_TIMING19(…  argument
39630 #define XCVR_SET_TSM_TIMING19(base, value) (BME_OR32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(value…  argument
39631 #define XCVR_CLR_TSM_TIMING19(base, value) (BME_AND32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(~(va…  argument
39632 #define XCVR_TOG_TSM_TIMING19(base, value) (BME_XOR32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(valu…  argument
39647 #define XCVR_RD_TSM_TIMING19_TX_EN_TX_HI(base) ((XCVR_TSM_TIMING19_REG(base) & XCVR_TSM_TIMING19_TX…  argument
39648 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_…  argument
39651 #define XCVR_WR_TSM_TIMING19_TX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING19(base, XCVR_TSM_TIMING1…  argument
39652 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((u…  argument
39663 #define XCVR_RD_TSM_TIMING19_TX_EN_TX_LO(base) ((XCVR_TSM_TIMING19_REG(base) & XCVR_TSM_TIMING19_TX…  argument
39664 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_…  argument
39667 #define XCVR_WR_TSM_TIMING19_TX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING19(base, XCVR_TSM_TIMING1…  argument
39668 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((u…  argument
39688 #define XCVR_RD_TSM_TIMING20(base) (XCVR_TSM_TIMING20_REG(base))  argument
39689 #define XCVR_WR_TSM_TIMING20(base, value) (XCVR_TSM_TIMING20_REG(base) = (value))  argument
39690 #define XCVR_RMW_TSM_TIMING20(base, mask, value) (XCVR_WR_TSM_TIMING20(base, (XCVR_RD_TSM_TIMING20(…  argument
39691 #define XCVR_SET_TSM_TIMING20(base, value) (BME_OR32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(value…  argument
39692 #define XCVR_CLR_TSM_TIMING20(base, value) (BME_AND32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(~(va…  argument
39693 #define XCVR_TOG_TSM_TIMING20(base, value) (BME_XOR32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(valu…  argument
39708 #define XCVR_RD_TSM_TIMING20_ADC_EN_RX_HI(base) ((XCVR_TSM_TIMING20_REG(base) & XCVR_TSM_TIMING20_A…  argument
39709 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM…  argument
39712 #define XCVR_WR_TSM_TIMING20_ADC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING20(base, XCVR_TSM_TIMING…  argument
39713 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((…  argument
39724 #define XCVR_RD_TSM_TIMING20_ADC_EN_RX_LO(base) ((XCVR_TSM_TIMING20_REG(base) & XCVR_TSM_TIMING20_A…  argument
39725 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM…  argument
39728 #define XCVR_WR_TSM_TIMING20_ADC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING20(base, XCVR_TSM_TIMING…  argument
39729 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((…  argument
39749 #define XCVR_RD_TSM_TIMING21(base) (XCVR_TSM_TIMING21_REG(base))  argument
39750 #define XCVR_WR_TSM_TIMING21(base, value) (XCVR_TSM_TIMING21_REG(base) = (value))  argument
39751 #define XCVR_RMW_TSM_TIMING21(base, mask, value) (XCVR_WR_TSM_TIMING21(base, (XCVR_RD_TSM_TIMING21(…  argument
39752 #define XCVR_SET_TSM_TIMING21(base, value) (BME_OR32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(value…  argument
39753 #define XCVR_CLR_TSM_TIMING21(base, value) (BME_AND32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(~(va…  argument
39754 #define XCVR_TOG_TSM_TIMING21(base, value) (BME_XOR32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(valu…  argument
39769 #define XCVR_RD_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base) ((XCVR_TSM_TIMING21_REG(base) & XCVR_TSM_TIMING…  argument
39770 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR…  argument
39773 #define XCVR_WR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING21(base, XCVR_TSM_TI…  argument
39774 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base)…  argument
39785 #define XCVR_RD_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base) ((XCVR_TSM_TIMING21_REG(base) & XCVR_TSM_TIMING…  argument
39786 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR…  argument
39789 #define XCVR_WR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING21(base, XCVR_TSM_TI…  argument
39790 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base)…  argument
39810 #define XCVR_RD_TSM_TIMING22(base) (XCVR_TSM_TIMING22_REG(base))  argument
39811 #define XCVR_WR_TSM_TIMING22(base, value) (XCVR_TSM_TIMING22_REG(base) = (value))  argument
39812 #define XCVR_RMW_TSM_TIMING22(base, mask, value) (XCVR_WR_TSM_TIMING22(base, (XCVR_RD_TSM_TIMING22(…  argument
39813 #define XCVR_SET_TSM_TIMING22(base, value) (BME_OR32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(value…  argument
39814 #define XCVR_CLR_TSM_TIMING22(base, value) (BME_AND32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(~(va…  argument
39815 #define XCVR_TOG_TSM_TIMING22(base, value) (BME_XOR32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(valu…  argument
39830 #define XCVR_RD_TSM_TIMING22_ADC_DAC_EN_RX_HI(base) ((XCVR_TSM_TIMING22_REG(base) & XCVR_TSM_TIMING…  argument
39831 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR…  argument
39834 #define XCVR_WR_TSM_TIMING22_ADC_DAC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING22(base, XCVR_TSM_TI…  argument
39835 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base)…  argument
39846 #define XCVR_RD_TSM_TIMING22_ADC_DAC_EN_RX_LO(base) ((XCVR_TSM_TIMING22_REG(base) & XCVR_TSM_TIMING…  argument
39847 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR…  argument
39850 #define XCVR_WR_TSM_TIMING22_ADC_DAC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING22(base, XCVR_TSM_TI…  argument
39851 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base)…  argument
39871 #define XCVR_RD_TSM_TIMING23(base) (XCVR_TSM_TIMING23_REG(base))  argument
39872 #define XCVR_WR_TSM_TIMING23(base, value) (XCVR_TSM_TIMING23_REG(base) = (value))  argument
39873 #define XCVR_RMW_TSM_TIMING23(base, mask, value) (XCVR_WR_TSM_TIMING23(base, (XCVR_RD_TSM_TIMING23(…  argument
39874 #define XCVR_SET_TSM_TIMING23(base, value) (BME_OR32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(value…  argument
39875 #define XCVR_CLR_TSM_TIMING23(base, value) (BME_AND32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(~(va…  argument
39876 #define XCVR_TOG_TSM_TIMING23(base, value) (BME_XOR32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(valu…  argument
39891 #define XCVR_RD_TSM_TIMING23_ADC_RST_EN_RX_HI(base) ((XCVR_TSM_TIMING23_REG(base) & XCVR_TSM_TIMING…  argument
39892 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR…  argument
39895 #define XCVR_WR_TSM_TIMING23_ADC_RST_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING23(base, XCVR_TSM_TI…  argument
39896 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base)…  argument
39907 #define XCVR_RD_TSM_TIMING23_ADC_RST_EN_RX_LO(base) ((XCVR_TSM_TIMING23_REG(base) & XCVR_TSM_TIMING…  argument
39908 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR…  argument
39911 #define XCVR_WR_TSM_TIMING23_ADC_RST_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING23(base, XCVR_TSM_TI…  argument
39912 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base)…  argument
39932 #define XCVR_RD_TSM_TIMING24(base) (XCVR_TSM_TIMING24_REG(base))  argument
39933 #define XCVR_WR_TSM_TIMING24(base, value) (XCVR_TSM_TIMING24_REG(base) = (value))  argument
39934 #define XCVR_RMW_TSM_TIMING24(base, mask, value) (XCVR_WR_TSM_TIMING24(base, (XCVR_RD_TSM_TIMING24(…  argument
39935 #define XCVR_SET_TSM_TIMING24(base, value) (BME_OR32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(value…  argument
39936 #define XCVR_CLR_TSM_TIMING24(base, value) (BME_AND32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(~(va…  argument
39937 #define XCVR_TOG_TSM_TIMING24(base, value) (BME_XOR32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(valu…  argument
39952 #define XCVR_RD_TSM_TIMING24_BBF_EN_RX_HI(base) ((XCVR_TSM_TIMING24_REG(base) & XCVR_TSM_TIMING24_B…  argument
39953 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM…  argument
39956 #define XCVR_WR_TSM_TIMING24_BBF_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING24(base, XCVR_TSM_TIMING…  argument
39957 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((…  argument
39968 #define XCVR_RD_TSM_TIMING24_BBF_EN_RX_LO(base) ((XCVR_TSM_TIMING24_REG(base) & XCVR_TSM_TIMING24_B…  argument
39969 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM…  argument
39972 #define XCVR_WR_TSM_TIMING24_BBF_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING24(base, XCVR_TSM_TIMING…  argument
39973 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((…  argument
39993 #define XCVR_RD_TSM_TIMING25(base) (XCVR_TSM_TIMING25_REG(base))  argument
39994 #define XCVR_WR_TSM_TIMING25(base, value) (XCVR_TSM_TIMING25_REG(base) = (value))  argument
39995 #define XCVR_RMW_TSM_TIMING25(base, mask, value) (XCVR_WR_TSM_TIMING25(base, (XCVR_RD_TSM_TIMING25(…  argument
39996 #define XCVR_SET_TSM_TIMING25(base, value) (BME_OR32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(value…  argument
39997 #define XCVR_CLR_TSM_TIMING25(base, value) (BME_AND32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(~(va…  argument
39998 #define XCVR_TOG_TSM_TIMING25(base, value) (BME_XOR32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(valu…  argument
40013 #define XCVR_RD_TSM_TIMING25_TCA_EN_RX_HI(base) ((XCVR_TSM_TIMING25_REG(base) & XCVR_TSM_TIMING25_T…  argument
40014 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM…  argument
40017 #define XCVR_WR_TSM_TIMING25_TCA_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING25(base, XCVR_TSM_TIMING…  argument
40018 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((…  argument
40029 #define XCVR_RD_TSM_TIMING25_TCA_EN_RX_LO(base) ((XCVR_TSM_TIMING25_REG(base) & XCVR_TSM_TIMING25_T…  argument
40030 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM…  argument
40033 #define XCVR_WR_TSM_TIMING25_TCA_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING25(base, XCVR_TSM_TIMING…  argument
40034 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((…  argument
40054 #define XCVR_RD_TSM_TIMING26(base) (XCVR_TSM_TIMING26_REG(base))  argument
40055 #define XCVR_WR_TSM_TIMING26(base, value) (XCVR_TSM_TIMING26_REG(base) = (value))  argument
40056 #define XCVR_RMW_TSM_TIMING26(base, mask, value) (XCVR_WR_TSM_TIMING26(base, (XCVR_RD_TSM_TIMING26(…  argument
40057 #define XCVR_SET_TSM_TIMING26(base, value) (BME_OR32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(value…  argument
40058 #define XCVR_CLR_TSM_TIMING26(base, value) (BME_AND32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(~(va…  argument
40059 #define XCVR_TOG_TSM_TIMING26(base, value) (BME_XOR32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(valu…  argument
40074 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_TX_HI(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING…  argument
40075 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…  argument
40078 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TI…  argument
40079 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…  argument
40090 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_TX_LO(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING…  argument
40091 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…  argument
40094 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TI…  argument
40095 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…  argument
40106 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_RX_HI(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING…  argument
40107 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…  argument
40110 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TI…  argument
40111 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…  argument
40122 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_RX_LO(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING…  argument
40123 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR…  argument
40126 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TI…  argument
40127 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base)…  argument
40147 #define XCVR_RD_TSM_TIMING27(base) (XCVR_TSM_TIMING27_REG(base))  argument
40148 #define XCVR_WR_TSM_TIMING27(base, value) (XCVR_TSM_TIMING27_REG(base) = (value))  argument
40149 #define XCVR_RMW_TSM_TIMING27(base, mask, value) (XCVR_WR_TSM_TIMING27(base, (XCVR_RD_TSM_TIMING27(…  argument
40150 #define XCVR_SET_TSM_TIMING27(base, value) (BME_OR32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(value…  argument
40151 #define XCVR_CLR_TSM_TIMING27(base, value) (BME_AND32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(~(va…  argument
40152 #define XCVR_TOG_TSM_TIMING27(base, value) (BME_XOR32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(valu…  argument
40167 #define XCVR_RD_TSM_TIMING27_TX_DIG_EN_TX_HI(base) ((XCVR_TSM_TIMING27_REG(base) & XCVR_TSM_TIMING2…  argument
40168 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_…  argument
40171 #define XCVR_WR_TSM_TIMING27_TX_DIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING27(base, XCVR_TSM_TIM…  argument
40172 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base),…  argument
40183 #define XCVR_RD_TSM_TIMING27_TX_DIG_EN_TX_LO(base) ((XCVR_TSM_TIMING27_REG(base) & XCVR_TSM_TIMING2…  argument
40184 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_…  argument
40187 #define XCVR_WR_TSM_TIMING27_TX_DIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING27(base, XCVR_TSM_TIM…  argument
40188 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base),…  argument
40208 #define XCVR_RD_TSM_TIMING28(base) (XCVR_TSM_TIMING28_REG(base))  argument
40209 #define XCVR_WR_TSM_TIMING28(base, value) (XCVR_TSM_TIMING28_REG(base) = (value))  argument
40210 #define XCVR_RMW_TSM_TIMING28(base, mask, value) (XCVR_WR_TSM_TIMING28(base, (XCVR_RD_TSM_TIMING28(…  argument
40211 #define XCVR_SET_TSM_TIMING28(base, value) (BME_OR32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(value…  argument
40212 #define XCVR_CLR_TSM_TIMING28(base, value) (BME_AND32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(~(va…  argument
40213 #define XCVR_TOG_TSM_TIMING28(base, value) (BME_XOR32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(valu…  argument
40228 #define XCVR_RD_TSM_TIMING28_RX_DIG_EN_RX_HI(base) ((XCVR_TSM_TIMING28_REG(base) & XCVR_TSM_TIMING2…  argument
40229 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_…  argument
40232 #define XCVR_WR_TSM_TIMING28_RX_DIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING28(base, XCVR_TSM_TIM…  argument
40233 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base),…  argument
40244 #define XCVR_RD_TSM_TIMING28_RX_DIG_EN_RX_LO(base) ((XCVR_TSM_TIMING28_REG(base) & XCVR_TSM_TIMING2…  argument
40245 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_…  argument
40248 #define XCVR_WR_TSM_TIMING28_RX_DIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING28(base, XCVR_TSM_TIM…  argument
40249 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base),…  argument
40269 #define XCVR_RD_TSM_TIMING29(base) (XCVR_TSM_TIMING29_REG(base))  argument
40270 #define XCVR_WR_TSM_TIMING29(base, value) (XCVR_TSM_TIMING29_REG(base) = (value))  argument
40271 #define XCVR_RMW_TSM_TIMING29(base, mask, value) (XCVR_WR_TSM_TIMING29(base, (XCVR_RD_TSM_TIMING29(…  argument
40272 #define XCVR_SET_TSM_TIMING29(base, value) (BME_OR32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(value…  argument
40273 #define XCVR_CLR_TSM_TIMING29(base, value) (BME_AND32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(~(va…  argument
40274 #define XCVR_TOG_TSM_TIMING29(base, value) (BME_XOR32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(valu…  argument
40289 #define XCVR_RD_TSM_TIMING29_RX_INIT_RX_HI(base) ((XCVR_TSM_TIMING29_REG(base) & XCVR_TSM_TIMING29_…  argument
40290 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TS…  argument
40293 #define XCVR_WR_TSM_TIMING29_RX_INIT_RX_HI(base, value) (XCVR_RMW_TSM_TIMING29(base, XCVR_TSM_TIMIN…  argument
40294 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), (…  argument
40305 #define XCVR_RD_TSM_TIMING29_RX_INIT_RX_LO(base) ((XCVR_TSM_TIMING29_REG(base) & XCVR_TSM_TIMING29_…  argument
40306 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TS…  argument
40309 #define XCVR_WR_TSM_TIMING29_RX_INIT_RX_LO(base, value) (XCVR_RMW_TSM_TIMING29(base, XCVR_TSM_TIMIN…  argument
40310 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), (…  argument
40330 #define XCVR_RD_TSM_TIMING30(base) (XCVR_TSM_TIMING30_REG(base))  argument
40331 #define XCVR_WR_TSM_TIMING30(base, value) (XCVR_TSM_TIMING30_REG(base) = (value))  argument
40332 #define XCVR_RMW_TSM_TIMING30(base, mask, value) (XCVR_WR_TSM_TIMING30(base, (XCVR_RD_TSM_TIMING30(…  argument
40333 #define XCVR_SET_TSM_TIMING30(base, value) (BME_OR32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(value…  argument
40334 #define XCVR_CLR_TSM_TIMING30(base, value) (BME_AND32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(~(va…  argument
40335 #define XCVR_TOG_TSM_TIMING30(base, value) (BME_XOR32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(valu…  argument
40350 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TI…  argument
40351 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …  argument
40354 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TS…  argument
40355 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…  argument
40366 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TI…  argument
40367 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …  argument
40370 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TS…  argument
40371 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…  argument
40382 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TI…  argument
40383 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …  argument
40386 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TS…  argument
40387 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…  argument
40398 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TI…  argument
40399 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), …  argument
40402 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TS…  argument
40403 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(b…  argument
40423 #define XCVR_RD_TSM_TIMING31(base) (XCVR_TSM_TIMING31_REG(base))  argument
40424 #define XCVR_WR_TSM_TIMING31(base, value) (XCVR_TSM_TIMING31_REG(base) = (value))  argument
40425 #define XCVR_RMW_TSM_TIMING31(base, mask, value) (XCVR_WR_TSM_TIMING31(base, (XCVR_RD_TSM_TIMING31(…  argument
40426 #define XCVR_SET_TSM_TIMING31(base, value) (BME_OR32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(value…  argument
40427 #define XCVR_CLR_TSM_TIMING31(base, value) (BME_AND32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(~(va…  argument
40428 #define XCVR_TOG_TSM_TIMING31(base, value) (BME_XOR32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(valu…  argument
40443 #define XCVR_RD_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base) ((XCVR_TSM_TIMING31_REG(base) & XCVR_TSM_TIMIN…  argument
40444 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCV…  argument
40447 #define XCVR_WR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING31(base, XCVR_TSM_T…  argument
40448 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base…  argument
40459 #define XCVR_RD_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base) ((XCVR_TSM_TIMING31_REG(base) & XCVR_TSM_TIMIN…  argument
40460 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCV…  argument
40463 #define XCVR_WR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING31(base, XCVR_TSM_T…  argument
40464 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base…  argument
40484 #define XCVR_RD_TSM_TIMING32(base) (XCVR_TSM_TIMING32_REG(base))  argument
40485 #define XCVR_WR_TSM_TIMING32(base, value) (XCVR_TSM_TIMING32_REG(base) = (value))  argument
40486 #define XCVR_RMW_TSM_TIMING32(base, mask, value) (XCVR_WR_TSM_TIMING32(base, (XCVR_RD_TSM_TIMING32(…  argument
40487 #define XCVR_SET_TSM_TIMING32(base, value) (BME_OR32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(value…  argument
40488 #define XCVR_CLR_TSM_TIMING32(base, value) (BME_AND32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(~(va…  argument
40489 #define XCVR_TOG_TSM_TIMING32(base, value) (BME_XOR32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(valu…  argument
40504 #define XCVR_RD_TSM_TIMING32_DCOC_EN_RX_HI(base) ((XCVR_TSM_TIMING32_REG(base) & XCVR_TSM_TIMING32_…  argument
40505 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TS…  argument
40508 #define XCVR_WR_TSM_TIMING32_DCOC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING32(base, XCVR_TSM_TIMIN…  argument
40509 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), (…  argument
40520 #define XCVR_RD_TSM_TIMING32_DCOC_EN_RX_LO(base) ((XCVR_TSM_TIMING32_REG(base) & XCVR_TSM_TIMING32_…  argument
40521 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TS…  argument
40524 #define XCVR_WR_TSM_TIMING32_DCOC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING32(base, XCVR_TSM_TIMIN…  argument
40525 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), (…  argument
40545 #define XCVR_RD_TSM_TIMING33(base) (XCVR_TSM_TIMING33_REG(base))  argument
40546 #define XCVR_WR_TSM_TIMING33(base, value) (XCVR_TSM_TIMING33_REG(base) = (value))  argument
40547 #define XCVR_RMW_TSM_TIMING33(base, mask, value) (XCVR_WR_TSM_TIMING33(base, (XCVR_RD_TSM_TIMING33(…  argument
40548 #define XCVR_SET_TSM_TIMING33(base, value) (BME_OR32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(value…  argument
40549 #define XCVR_CLR_TSM_TIMING33(base, value) (BME_AND32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(~(va…  argument
40550 #define XCVR_TOG_TSM_TIMING33(base, value) (BME_XOR32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(valu…  argument
40565 #define XCVR_RD_TSM_TIMING33_DCOC_INIT_RX_HI(base) ((XCVR_TSM_TIMING33_REG(base) & XCVR_TSM_TIMING3…  argument
40566 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_…  argument
40569 #define XCVR_WR_TSM_TIMING33_DCOC_INIT_RX_HI(base, value) (XCVR_RMW_TSM_TIMING33(base, XCVR_TSM_TIM…  argument
40570 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base),…  argument
40581 #define XCVR_RD_TSM_TIMING33_DCOC_INIT_RX_LO(base) ((XCVR_TSM_TIMING33_REG(base) & XCVR_TSM_TIMING3…  argument
40582 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_…  argument
40585 #define XCVR_WR_TSM_TIMING33_DCOC_INIT_RX_LO(base, value) (XCVR_RMW_TSM_TIMING33(base, XCVR_TSM_TIM…  argument
40586 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base),…  argument
40606 #define XCVR_RD_TSM_TIMING34(base) (XCVR_TSM_TIMING34_REG(base))  argument
40607 #define XCVR_WR_TSM_TIMING34(base, value) (XCVR_TSM_TIMING34_REG(base) = (value))  argument
40608 #define XCVR_RMW_TSM_TIMING34(base, mask, value) (XCVR_WR_TSM_TIMING34(base, (XCVR_RD_TSM_TIMING34(…  argument
40609 #define XCVR_SET_TSM_TIMING34(base, value) (BME_OR32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(value…  argument
40610 #define XCVR_CLR_TSM_TIMING34(base, value) (BME_AND32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(~(va…  argument
40611 #define XCVR_TOG_TSM_TIMING34(base, value) (BME_XOR32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(valu…  argument
40626 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_T…  argument
40627 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…  argument
40630 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_T…  argument
40631 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…  argument
40642 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_T…  argument
40643 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…  argument
40646 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_T…  argument
40647 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…  argument
40658 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_T…  argument
40659 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…  argument
40662 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_T…  argument
40663 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…  argument
40674 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_T…  argument
40675 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base),…  argument
40678 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_T…  argument
40679 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(…  argument
40699 #define XCVR_RD_TSM_TIMING35(base) (XCVR_TSM_TIMING35_REG(base))  argument
40700 #define XCVR_WR_TSM_TIMING35(base, value) (XCVR_TSM_TIMING35_REG(base) = (value))  argument
40701 #define XCVR_RMW_TSM_TIMING35(base, mask, value) (XCVR_WR_TSM_TIMING35(base, (XCVR_RD_TSM_TIMING35(…  argument
40702 #define XCVR_SET_TSM_TIMING35(base, value) (BME_OR32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(value…  argument
40703 #define XCVR_CLR_TSM_TIMING35(base, value) (BME_AND32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(~(va…  argument
40704 #define XCVR_TOG_TSM_TIMING35(base, value) (BME_XOR32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(valu…  argument
40719 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_T…  argument
40720 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…  argument
40723 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_T…  argument
40724 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…  argument
40735 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_T…  argument
40736 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…  argument
40739 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_T…  argument
40740 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…  argument
40751 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_T…  argument
40752 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…  argument
40755 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_T…  argument
40756 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…  argument
40767 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_T…  argument
40768 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base),…  argument
40771 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_T…  argument
40772 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(…  argument
40792 #define XCVR_RD_TSM_TIMING36(base) (XCVR_TSM_TIMING36_REG(base))  argument
40793 #define XCVR_WR_TSM_TIMING36(base, value) (XCVR_TSM_TIMING36_REG(base) = (value))  argument
40794 #define XCVR_RMW_TSM_TIMING36(base, mask, value) (XCVR_WR_TSM_TIMING36(base, (XCVR_RD_TSM_TIMING36(…  argument
40795 #define XCVR_SET_TSM_TIMING36(base, value) (BME_OR32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(value…  argument
40796 #define XCVR_CLR_TSM_TIMING36(base, value) (BME_AND32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(~(va…  argument
40797 #define XCVR_TOG_TSM_TIMING36(base, value) (BME_XOR32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(valu…  argument
40812 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIM…  argument
40813 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…  argument
40816 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM…  argument
40817 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…  argument
40828 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIM…  argument
40829 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…  argument
40832 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM…  argument
40833 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…  argument
40844 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIM…  argument
40845 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…  argument
40848 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM…  argument
40849 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…  argument
40860 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIM…  argument
40861 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), X…  argument
40864 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM…  argument
40865 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(ba…  argument
40885 #define XCVR_RD_TSM_TIMING37(base) (XCVR_TSM_TIMING37_REG(base))  argument
40886 #define XCVR_WR_TSM_TIMING37(base, value) (XCVR_TSM_TIMING37_REG(base) = (value))  argument
40887 #define XCVR_RMW_TSM_TIMING37(base, mask, value) (XCVR_WR_TSM_TIMING37(base, (XCVR_RD_TSM_TIMING37(…  argument
40888 #define XCVR_SET_TSM_TIMING37(base, value) (BME_OR32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(value…  argument
40889 #define XCVR_CLR_TSM_TIMING37(base, value) (BME_AND32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(~(va…  argument
40890 #define XCVR_TOG_TSM_TIMING37(base, value) (BME_XOR32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(valu…  argument
40905 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIM…  argument
40906 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…  argument
40909 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM…  argument
40910 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…  argument
40921 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIM…  argument
40922 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…  argument
40925 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM…  argument
40926 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…  argument
40937 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIM…  argument
40938 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…  argument
40941 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM…  argument
40942 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…  argument
40953 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIM…  argument
40954 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), X…  argument
40957 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM…  argument
40958 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(ba…  argument
40978 #define XCVR_RD_TSM_TIMING38(base) (XCVR_TSM_TIMING38_REG(base))  argument
40979 #define XCVR_WR_TSM_TIMING38(base, value) (XCVR_TSM_TIMING38_REG(base) = (value))  argument
40980 #define XCVR_RMW_TSM_TIMING38(base, mask, value) (XCVR_WR_TSM_TIMING38(base, (XCVR_RD_TSM_TIMING38(…  argument
40981 #define XCVR_SET_TSM_TIMING38(base, value) (BME_OR32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(value…  argument
40982 #define XCVR_CLR_TSM_TIMING38(base, value) (BME_AND32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(~(va…  argument
40983 #define XCVR_TOG_TSM_TIMING38(base, value) (BME_XOR32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(valu…  argument
40998 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIM…  argument
40999 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…  argument
41002 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM…  argument
41003 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…  argument
41014 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIM…  argument
41015 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…  argument
41018 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM…  argument
41019 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…  argument
41030 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIM…  argument
41031 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…  argument
41034 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM…  argument
41035 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…  argument
41046 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIM…  argument
41047 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), X…  argument
41050 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM…  argument
41051 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(ba…  argument
41071 #define XCVR_RD_TSM_TIMING39(base) (XCVR_TSM_TIMING39_REG(base))  argument
41072 #define XCVR_WR_TSM_TIMING39(base, value) (XCVR_TSM_TIMING39_REG(base) = (value))  argument
41073 #define XCVR_RMW_TSM_TIMING39(base, mask, value) (XCVR_WR_TSM_TIMING39(base, (XCVR_RD_TSM_TIMING39(…  argument
41074 #define XCVR_SET_TSM_TIMING39(base, value) (BME_OR32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(value…  argument
41075 #define XCVR_CLR_TSM_TIMING39(base, value) (BME_AND32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(~(va…  argument
41076 #define XCVR_TOG_TSM_TIMING39(base, value) (BME_XOR32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(valu…  argument
41091 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIM…  argument
41092 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…  argument
41095 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM…  argument
41096 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…  argument
41107 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIM…  argument
41108 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…  argument
41111 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM…  argument
41112 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…  argument
41123 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIM…  argument
41124 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…  argument
41127 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM…  argument
41128 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…  argument
41139 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIM…  argument
41140 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), X…  argument
41143 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM…  argument
41144 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(ba…  argument
41164 #define XCVR_RD_TSM_TIMING40(base) (XCVR_TSM_TIMING40_REG(base))  argument
41165 #define XCVR_WR_TSM_TIMING40(base, value) (XCVR_TSM_TIMING40_REG(base) = (value))  argument
41166 #define XCVR_RMW_TSM_TIMING40(base, mask, value) (XCVR_WR_TSM_TIMING40(base, (XCVR_RD_TSM_TIMING40(…  argument
41167 #define XCVR_SET_TSM_TIMING40(base, value) (BME_OR32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(value…  argument
41168 #define XCVR_CLR_TSM_TIMING40(base, value) (BME_AND32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(~(va…  argument
41169 #define XCVR_TOG_TSM_TIMING40(base, value) (BME_XOR32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(valu…  argument
41184 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIM…  argument
41185 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…  argument
41188 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM…  argument
41189 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…  argument
41200 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIM…  argument
41201 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…  argument
41204 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM…  argument
41205 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…  argument
41216 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIM…  argument
41217 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…  argument
41220 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM…  argument
41221 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…  argument
41232 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIM…  argument
41233 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), X…  argument
41236 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM…  argument
41237 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(ba…  argument
41257 #define XCVR_RD_TSM_TIMING41(base) (XCVR_TSM_TIMING41_REG(base))  argument
41258 #define XCVR_WR_TSM_TIMING41(base, value) (XCVR_TSM_TIMING41_REG(base) = (value))  argument
41259 #define XCVR_RMW_TSM_TIMING41(base, mask, value) (XCVR_WR_TSM_TIMING41(base, (XCVR_RD_TSM_TIMING41(…  argument
41260 #define XCVR_SET_TSM_TIMING41(base, value) (BME_OR32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(value…  argument
41261 #define XCVR_CLR_TSM_TIMING41(base, value) (BME_AND32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(~(va…  argument
41262 #define XCVR_TOG_TSM_TIMING41(base, value) (BME_XOR32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(valu…  argument
41277 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIM…  argument
41278 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…  argument
41281 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM…  argument
41282 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…  argument
41293 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIM…  argument
41294 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…  argument
41297 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM…  argument
41298 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…  argument
41309 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIM…  argument
41310 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…  argument
41313 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM…  argument
41314 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…  argument
41325 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIM…  argument
41326 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), X…  argument
41329 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM…  argument
41330 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(ba…  argument
41350 #define XCVR_RD_TSM_TIMING42(base) (XCVR_TSM_TIMING42_REG(base))  argument
41351 #define XCVR_WR_TSM_TIMING42(base, value) (XCVR_TSM_TIMING42_REG(base) = (value))  argument
41352 #define XCVR_RMW_TSM_TIMING42(base, mask, value) (XCVR_WR_TSM_TIMING42(base, (XCVR_RD_TSM_TIMING42(…  argument
41353 #define XCVR_SET_TSM_TIMING42(base, value) (BME_OR32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(value…  argument
41354 #define XCVR_CLR_TSM_TIMING42(base, value) (BME_AND32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(~(va…  argument
41355 #define XCVR_TOG_TSM_TIMING42(base, value) (BME_XOR32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(valu…  argument
41370 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIM…  argument
41371 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…  argument
41374 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM…  argument
41375 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…  argument
41386 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIM…  argument
41387 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…  argument
41390 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM…  argument
41391 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…  argument
41402 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIM…  argument
41403 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…  argument
41406 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM…  argument
41407 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…  argument
41418 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIM…  argument
41419 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), X…  argument
41422 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM…  argument
41423 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(ba…  argument
41443 #define XCVR_RD_TSM_TIMING43(base) (XCVR_TSM_TIMING43_REG(base))  argument
41444 #define XCVR_WR_TSM_TIMING43(base, value) (XCVR_TSM_TIMING43_REG(base) = (value))  argument
41445 #define XCVR_RMW_TSM_TIMING43(base, mask, value) (XCVR_WR_TSM_TIMING43(base, (XCVR_RD_TSM_TIMING43(…  argument
41446 #define XCVR_SET_TSM_TIMING43(base, value) (BME_OR32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(value…  argument
41447 #define XCVR_CLR_TSM_TIMING43(base, value) (BME_AND32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(~(va…  argument
41448 #define XCVR_TOG_TSM_TIMING43(base, value) (BME_XOR32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(valu…  argument
41463 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIM…  argument
41464 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…  argument
41467 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM…  argument
41468 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…  argument
41479 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIM…  argument
41480 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…  argument
41483 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM…  argument
41484 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…  argument
41495 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIM…  argument
41496 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…  argument
41499 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM…  argument
41500 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…  argument
41511 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIM…  argument
41512 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), X…  argument
41515 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM…  argument
41516 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(ba…  argument
41532 #define XCVR_RD_CORR_CTRL(base)  (XCVR_CORR_CTRL_REG(base))  argument
41533 #define XCVR_WR_CORR_CTRL(base, value) (XCVR_CORR_CTRL_REG(base) = (value))  argument
41534 #define XCVR_RMW_CORR_CTRL(base, mask, value) (XCVR_WR_CORR_CTRL(base, (XCVR_RD_CORR_CTRL(base) & ~…  argument
41535 #define XCVR_SET_CORR_CTRL(base, value) (BME_OR32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(value)))  argument
41536 #define XCVR_CLR_CORR_CTRL(base, value) (BME_AND32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(~(value))))  argument
41537 #define XCVR_TOG_CORR_CTRL(base, value) (BME_XOR32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(value)))  argument
41552 #define XCVR_RD_CORR_CTRL_CORR_VT(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_CORR_VT_MASK) >…  argument
41553 #define XCVR_BRD_CORR_CTRL_CORR_VT(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CORR…  argument
41556 #define XCVR_WR_CORR_CTRL_CORR_VT(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_CORR_VT_MAS…  argument
41557 #define XCVR_BWR_CORR_CTRL_CORR_VT(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)(v…  argument
41568 #define XCVR_RD_CORR_CTRL_CORR_NVAL(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_CORR_NVAL_MAS…  argument
41569 #define XCVR_BRD_CORR_CTRL_CORR_NVAL(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CO…  argument
41572 #define XCVR_WR_CORR_CTRL_CORR_NVAL(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_CORR_NVAL…  argument
41573 #define XCVR_BWR_CORR_CTRL_CORR_NVAL(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)…  argument
41584 #define XCVR_RD_CORR_CTRL_MAX_CORR_EN(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_MAX_CORR_EN…  argument
41585 #define XCVR_BRD_CORR_CTRL_MAX_CORR_EN(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_…  argument
41588 #define XCVR_WR_CORR_CTRL_MAX_CORR_EN(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_MAX_COR…  argument
41589 #define XCVR_BWR_CORR_CTRL_MAX_CORR_EN(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_…  argument
41600 #define XCVR_RD_CORR_CTRL_RX_MAX_CORR(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_RX_MAX_CORR…  argument
41601 #define XCVR_BRD_CORR_CTRL_RX_MAX_CORR(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_…  argument
41612 #define XCVR_RD_CORR_CTRL_RX_MAX_PREAMBLE(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_RX_MAX_…  argument
41613 #define XCVR_BRD_CORR_CTRL_RX_MAX_PREAMBLE(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_C…  argument
41629 #define XCVR_RD_PN_TYPE(base)    (XCVR_PN_TYPE_REG(base))  argument
41630 #define XCVR_WR_PN_TYPE(base, value) (XCVR_PN_TYPE_REG(base) = (value))  argument
41631 #define XCVR_RMW_PN_TYPE(base, mask, value) (XCVR_WR_PN_TYPE(base, (XCVR_RD_PN_TYPE(base) & ~(mask)…  argument
41632 #define XCVR_SET_PN_TYPE(base, value) (BME_OR32(&XCVR_PN_TYPE_REG(base), (uint32_t)(value)))  argument
41633 #define XCVR_CLR_PN_TYPE(base, value) (BME_AND32(&XCVR_PN_TYPE_REG(base), (uint32_t)(~(value))))  argument
41634 #define XCVR_TOG_PN_TYPE(base, value) (BME_XOR32(&XCVR_PN_TYPE_REG(base), (uint32_t)(value)))  argument
41648 #define XCVR_RD_PN_TYPE_PN_TYPE(base) ((XCVR_PN_TYPE_REG(base) & XCVR_PN_TYPE_PN_TYPE_MASK) >> XCVR…  argument
41649 #define XCVR_BRD_PN_TYPE_PN_TYPE(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_PN_TYPE_SH…  argument
41652 #define XCVR_WR_PN_TYPE_PN_TYPE(base, value) (XCVR_RMW_PN_TYPE(base, XCVR_PN_TYPE_PN_TYPE_MASK, XCV…  argument
41653 #define XCVR_BWR_PN_TYPE_PN_TYPE(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value…  argument
41663 #define XCVR_RD_PN_TYPE_TX_INV(base) ((XCVR_PN_TYPE_REG(base) & XCVR_PN_TYPE_TX_INV_MASK) >> XCVR_P…  argument
41664 #define XCVR_BRD_PN_TYPE_TX_INV(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_TX_INV_SHIF…  argument
41667 #define XCVR_WR_PN_TYPE_TX_INV(base, value) (XCVR_RMW_PN_TYPE(base, XCVR_PN_TYPE_TX_INV_MASK, XCVR_…  argument
41668 #define XCVR_BWR_PN_TYPE_TX_INV(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value)…  argument
41686 #define XCVR_RD_PN_CODE(base)    (XCVR_PN_CODE_REG(base))  argument
41687 #define XCVR_WR_PN_CODE(base, value) (XCVR_PN_CODE_REG(base) = (value))  argument
41688 #define XCVR_RMW_PN_CODE(base, mask, value) (XCVR_WR_PN_CODE(base, (XCVR_RD_PN_CODE(base) & ~(mask)…  argument
41689 #define XCVR_SET_PN_CODE(base, value) (BME_OR32(&XCVR_PN_CODE_REG(base), (uint32_t)(value)))  argument
41690 #define XCVR_CLR_PN_CODE(base, value) (BME_AND32(&XCVR_PN_CODE_REG(base), (uint32_t)(~(value))))  argument
41691 #define XCVR_TOG_PN_CODE(base, value) (BME_XOR32(&XCVR_PN_CODE_REG(base), (uint32_t)(value)))  argument
41705 #define XCVR_RD_PN_CODE_PN_LSB(base) ((XCVR_PN_CODE_REG(base) & XCVR_PN_CODE_PN_LSB_MASK) >> XCVR_P…  argument
41706 #define XCVR_BRD_PN_CODE_PN_LSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_LSB_SHIF…  argument
41709 #define XCVR_WR_PN_CODE_PN_LSB(base, value) (XCVR_RMW_PN_CODE(base, XCVR_PN_CODE_PN_LSB_MASK, XCVR_…  argument
41710 #define XCVR_BWR_PN_CODE_PN_LSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value)…  argument
41720 #define XCVR_RD_PN_CODE_PN_MSB(base) ((XCVR_PN_CODE_REG(base) & XCVR_PN_CODE_PN_MSB_MASK) >> XCVR_P…  argument
41721 #define XCVR_BRD_PN_CODE_PN_MSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_MSB_SHIF…  argument
41724 #define XCVR_WR_PN_CODE_PN_MSB(base, value) (XCVR_RMW_PN_CODE(base, XCVR_PN_CODE_PN_MSB_MASK, XCVR_…  argument
41725 #define XCVR_BWR_PN_CODE_PN_MSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value)…  argument
41741 #define XCVR_RD_SYNC_CTRL(base)  (XCVR_SYNC_CTRL_REG(base))  argument
41742 #define XCVR_WR_SYNC_CTRL(base, value) (XCVR_SYNC_CTRL_REG(base) = (value))  argument
41743 #define XCVR_RMW_SYNC_CTRL(base, mask, value) (XCVR_WR_SYNC_CTRL(base, (XCVR_RD_SYNC_CTRL(base) & ~…  argument
41744 #define XCVR_SET_SYNC_CTRL(base, value) (BME_OR32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(value)))  argument
41745 #define XCVR_CLR_SYNC_CTRL(base, value) (BME_AND32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(~(value))))  argument
41746 #define XCVR_TOG_SYNC_CTRL(base, value) (BME_XOR32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(value)))  argument
41762 #define XCVR_RD_SYNC_CTRL_SYNC_PER(base) ((XCVR_SYNC_CTRL_REG(base) & XCVR_SYNC_CTRL_SYNC_PER_MASK)…  argument
41763 #define XCVR_BRD_SYNC_CTRL_SYNC_PER(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL_SYN…  argument
41766 #define XCVR_WR_SYNC_CTRL_SYNC_PER(base, value) (XCVR_RMW_SYNC_CTRL(base, XCVR_SYNC_CTRL_SYNC_PER_M…  argument
41767 #define XCVR_BWR_SYNC_CTRL_SYNC_PER(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32_t)(…  argument
41780 #define XCVR_RD_SYNC_CTRL_TRACK_ENABLE(base) ((XCVR_SYNC_CTRL_REG(base) & XCVR_SYNC_CTRL_TRACK_ENAB…  argument
41781 #define XCVR_BRD_SYNC_CTRL_TRACK_ENABLE(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL…  argument
41784 #define XCVR_WR_SYNC_CTRL_TRACK_ENABLE(base, value) (XCVR_RMW_SYNC_CTRL(base, XCVR_SYNC_CTRL_TRACK_…  argument
41785 #define XCVR_BWR_SYNC_CTRL_TRACK_ENABLE(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32…  argument
41801 #define XCVR_RD_SNF_THR(base)    (XCVR_SNF_THR_REG(base))  argument
41802 #define XCVR_WR_SNF_THR(base, value) (XCVR_SNF_THR_REG(base) = (value))  argument
41803 #define XCVR_RMW_SNF_THR(base, mask, value) (XCVR_WR_SNF_THR(base, (XCVR_RD_SNF_THR(base) & ~(mask)…  argument
41804 #define XCVR_SET_SNF_THR(base, value) (BME_OR32(&XCVR_SNF_THR_REG(base), (uint32_t)(value)))  argument
41805 #define XCVR_CLR_SNF_THR(base, value) (BME_AND32(&XCVR_SNF_THR_REG(base), (uint32_t)(~(value))))  argument
41806 #define XCVR_TOG_SNF_THR(base, value) (BME_XOR32(&XCVR_SNF_THR_REG(base), (uint32_t)(value)))  argument
41822 #define XCVR_RD_SNF_THR_SNF_THR(base) ((XCVR_SNF_THR_REG(base) & XCVR_SNF_THR_SNF_THR_MASK) >> XCVR…  argument
41823 #define XCVR_BRD_SNF_THR_SNF_THR(base) (BME_UBFX32(&XCVR_SNF_THR_REG(base), XCVR_SNF_THR_SNF_THR_SH…  argument
41826 #define XCVR_WR_SNF_THR_SNF_THR(base, value) (XCVR_RMW_SNF_THR(base, XCVR_SNF_THR_SNF_THR_MASK, XCV…  argument
41827 #define XCVR_BWR_SNF_THR_SNF_THR(base, value) (BME_BFI32(&XCVR_SNF_THR_REG(base), ((uint32_t)(value…  argument
41843 #define XCVR_RD_FAD_THR(base)    (XCVR_FAD_THR_REG(base))  argument
41844 #define XCVR_WR_FAD_THR(base, value) (XCVR_FAD_THR_REG(base) = (value))  argument
41845 #define XCVR_RMW_FAD_THR(base, mask, value) (XCVR_WR_FAD_THR(base, (XCVR_RD_FAD_THR(base) & ~(mask)…  argument
41846 #define XCVR_SET_FAD_THR(base, value) (BME_OR32(&XCVR_FAD_THR_REG(base), (uint32_t)(value)))  argument
41847 #define XCVR_CLR_FAD_THR(base, value) (BME_AND32(&XCVR_FAD_THR_REG(base), (uint32_t)(~(value))))  argument
41848 #define XCVR_TOG_FAD_THR(base, value) (BME_XOR32(&XCVR_FAD_THR_REG(base), (uint32_t)(value)))  argument
41862 #define XCVR_RD_FAD_THR_FAD_THR(base) ((XCVR_FAD_THR_REG(base) & XCVR_FAD_THR_FAD_THR_MASK) >> XCVR…  argument
41863 #define XCVR_BRD_FAD_THR_FAD_THR(base) (BME_UBFX32(&XCVR_FAD_THR_REG(base), XCVR_FAD_THR_FAD_THR_SH…  argument
41866 #define XCVR_WR_FAD_THR_FAD_THR(base, value) (XCVR_RMW_FAD_THR(base, XCVR_FAD_THR_FAD_THR_MASK, XCV…  argument
41867 #define XCVR_BWR_FAD_THR_FAD_THR(base, value) (BME_BFI32(&XCVR_FAD_THR_REG(base), ((uint32_t)(value…  argument
41883 #define XCVR_RD_ZBDEM_AFC(base)  (XCVR_ZBDEM_AFC_REG(base))  argument
41884 #define XCVR_WR_ZBDEM_AFC(base, value) (XCVR_ZBDEM_AFC_REG(base) = (value))  argument
41885 #define XCVR_RMW_ZBDEM_AFC(base, mask, value) (XCVR_WR_ZBDEM_AFC(base, (XCVR_RD_ZBDEM_AFC(base) & ~…  argument
41886 #define XCVR_SET_ZBDEM_AFC(base, value) (BME_OR32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(value)))  argument
41887 #define XCVR_CLR_ZBDEM_AFC(base, value) (BME_AND32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(~(value))))  argument
41888 #define XCVR_TOG_ZBDEM_AFC(base, value) (BME_XOR32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(value)))  argument
41902 #define XCVR_RD_ZBDEM_AFC_AFC_EN(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_AFC_EN_MASK) >> …  argument
41903 #define XCVR_BRD_ZBDEM_AFC_AFC_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_E…  argument
41906 #define XCVR_WR_ZBDEM_AFC_AFC_EN(base, value) (XCVR_RMW_ZBDEM_AFC(base, XCVR_ZBDEM_AFC_AFC_EN_MASK,…  argument
41907 #define XCVR_BWR_ZBDEM_AFC_AFC_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(va…  argument
41919 #define XCVR_RD_ZBDEM_AFC_DCD_EN(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_DCD_EN_MASK) >> …  argument
41920 #define XCVR_BRD_ZBDEM_AFC_DCD_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_DCD_E…  argument
41923 #define XCVR_WR_ZBDEM_AFC_DCD_EN(base, value) (XCVR_RMW_ZBDEM_AFC(base, XCVR_ZBDEM_AFC_DCD_EN_MASK,…  argument
41924 #define XCVR_BWR_ZBDEM_AFC_DCD_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(va…  argument
41934 #define XCVR_RD_ZBDEM_AFC_AFC_OUT(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_AFC_OUT_MASK) >…  argument
41935 #define XCVR_BRD_ZBDEM_AFC_AFC_OUT(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_…  argument
41951 #define XCVR_RD_LPPS_CTRL(base)  (XCVR_LPPS_CTRL_REG(base))  argument
41952 #define XCVR_WR_LPPS_CTRL(base, value) (XCVR_LPPS_CTRL_REG(base) = (value))  argument
41953 #define XCVR_RMW_LPPS_CTRL(base, mask, value) (XCVR_WR_LPPS_CTRL(base, (XCVR_RD_LPPS_CTRL(base) & ~…  argument
41954 #define XCVR_SET_LPPS_CTRL(base, value) (BME_OR32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(value)))  argument
41955 #define XCVR_CLR_LPPS_CTRL(base, value) (BME_AND32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(~(value))))  argument
41956 #define XCVR_TOG_LPPS_CTRL(base, value) (BME_XOR32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(value)))  argument
41976 #define XCVR_RD_LPPS_CTRL_LPPS_ENABLE(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ENABLE…  argument
41977 #define XCVR_BRD_LPPS_CTRL_LPPS_ENABLE(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_…  argument
41980 #define XCVR_WR_LPPS_CTRL_LPPS_ENABLE(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_EN…  argument
41981 #define XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_…  argument
41993 #define XCVR_RD_LPPS_CTRL_LPPS_QGEN25_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_…  argument
41994 #define XCVR_BRD_LPPS_CTRL_LPPS_QGEN25_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS…  argument
41997 #define XCVR_WR_LPPS_CTRL_LPPS_QGEN25_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_L…  argument
41998 #define XCVR_BWR_LPPS_CTRL_LPPS_QGEN25_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((u…  argument
42012 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ADC…  argument
42013 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…  argument
42016 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS…  argument
42017 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…  argument
42031 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS…  argument
42032 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…  argument
42035 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_…  argument
42036 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…  argument
42050 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS…  argument
42051 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…  argument
42054 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_…  argument
42055 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…  argument
42069 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS…  argument
42070 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPP…  argument
42073 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_…  argument
42074 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((…  argument
42088 #define XCVR_RD_LPPS_CTRL_LPPS_BBF_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_BBF…  argument
42089 #define XCVR_BRD_LPPS_CTRL_LPPS_BBF_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…  argument
42092 #define XCVR_WR_LPPS_CTRL_LPPS_BBF_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS…  argument
42093 #define XCVR_BWR_LPPS_CTRL_LPPS_BBF_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…  argument
42107 #define XCVR_RD_LPPS_CTRL_LPPS_TCA_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_TCA…  argument
42108 #define XCVR_BRD_LPPS_CTRL_LPPS_TCA_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CT…  argument
42111 #define XCVR_WR_LPPS_CTRL_LPPS_TCA_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS…  argument
42112 #define XCVR_BWR_LPPS_CTRL_LPPS_TCA_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint…  argument
42128 #define XCVR_RD_ADC_CTRL(base)   (XCVR_ADC_CTRL_REG(base))  argument
42129 #define XCVR_WR_ADC_CTRL(base, value) (XCVR_ADC_CTRL_REG(base) = (value))  argument
42130 #define XCVR_RMW_ADC_CTRL(base, mask, value) (XCVR_WR_ADC_CTRL(base, (XCVR_RD_ADC_CTRL(base) & ~(ma…  argument
42131 #define XCVR_SET_ADC_CTRL(base, value) (BME_OR32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(value)))  argument
42132 #define XCVR_CLR_ADC_CTRL(base, value) (BME_AND32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(~(value))))  argument
42133 #define XCVR_TOG_ADC_CTRL(base, value) (BME_XOR32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(value)))  argument
42149 #define XCVR_RD_ADC_CTRL_ADC_32MHZ_SEL(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_32MHZ_SE…  argument
42150 #define XCVR_BRD_ADC_CTRL_ADC_32MHZ_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_A…  argument
42153 #define XCVR_WR_ADC_CTRL_ADC_32MHZ_SEL(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_32MH…  argument
42154 #define XCVR_BWR_ADC_CTRL_ADC_32MHZ_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_…  argument
42166 #define XCVR_RD_ADC_CTRL_ADC_2X_CLK_SEL(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_2X_CLK_…  argument
42167 #define XCVR_BRD_ADC_CTRL_ADC_2X_CLK_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_…  argument
42170 #define XCVR_WR_ADC_CTRL_ADC_2X_CLK_SEL(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_2X_…  argument
42171 #define XCVR_BWR_ADC_CTRL_ADC_2X_CLK_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32…  argument
42182 #define XCVR_RD_ADC_CTRL_ADC_DITHER_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_DITHER_O…  argument
42183 #define XCVR_BRD_ADC_CTRL_ADC_DITHER_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_A…  argument
42186 #define XCVR_WR_ADC_CTRL_ADC_DITHER_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_DITH…  argument
42187 #define XCVR_BWR_ADC_CTRL_ADC_DITHER_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_…  argument
42198 #define XCVR_RD_ADC_CTRL_ADC_TEST_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_TEST_ON_MA…  argument
42199 #define XCVR_BRD_ADC_CTRL_ADC_TEST_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC…  argument
42202 #define XCVR_WR_ADC_CTRL_ADC_TEST_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_TEST_O…  argument
42203 #define XCVR_BWR_ADC_CTRL_ADC_TEST_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)…  argument
42215 #define XCVR_RD_ADC_CTRL_ADC_COMP_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_COMP_ON_MA…  argument
42216 #define XCVR_BRD_ADC_CTRL_ADC_COMP_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC…  argument
42219 #define XCVR_WR_ADC_CTRL_ADC_COMP_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_COMP_O…  argument
42220 #define XCVR_BWR_ADC_CTRL_ADC_COMP_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)…  argument
42236 #define XCVR_RD_ADC_TUNE(base)   (XCVR_ADC_TUNE_REG(base))  argument
42237 #define XCVR_WR_ADC_TUNE(base, value) (XCVR_ADC_TUNE_REG(base) = (value))  argument
42238 #define XCVR_RMW_ADC_TUNE(base, mask, value) (XCVR_WR_ADC_TUNE(base, (XCVR_RD_ADC_TUNE(base) & ~(ma…  argument
42239 #define XCVR_SET_ADC_TUNE(base, value) (BME_OR32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(value)))  argument
42240 #define XCVR_CLR_ADC_TUNE(base, value) (BME_AND32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(~(value))))  argument
42241 #define XCVR_TOG_ADC_TUNE(base, value) (BME_XOR32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(value)))  argument
42256 #define XCVR_RD_ADC_TUNE_ADC_R1_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_R1_TUNE_MA…  argument
42257 #define XCVR_BRD_ADC_TUNE_ADC_R1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…  argument
42260 #define XCVR_WR_ADC_TUNE_ADC_R1_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_R1_TUN…  argument
42261 #define XCVR_BWR_ADC_TUNE_ADC_R1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…  argument
42272 #define XCVR_RD_ADC_TUNE_ADC_R2_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_R2_TUNE_MA…  argument
42273 #define XCVR_BRD_ADC_TUNE_ADC_R2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…  argument
42276 #define XCVR_WR_ADC_TUNE_ADC_R2_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_R2_TUN…  argument
42277 #define XCVR_BWR_ADC_TUNE_ADC_R2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…  argument
42288 #define XCVR_RD_ADC_TUNE_ADC_C1_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_C1_TUNE_MA…  argument
42289 #define XCVR_BRD_ADC_TUNE_ADC_C1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…  argument
42292 #define XCVR_WR_ADC_TUNE_ADC_C1_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_C1_TUN…  argument
42293 #define XCVR_BWR_ADC_TUNE_ADC_C1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…  argument
42304 #define XCVR_RD_ADC_TUNE_ADC_C2_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_C2_TUNE_MA…  argument
42305 #define XCVR_BRD_ADC_TUNE_ADC_C2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC…  argument
42308 #define XCVR_WR_ADC_TUNE_ADC_C2_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_C2_TUN…  argument
42309 #define XCVR_BWR_ADC_TUNE_ADC_C2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)…  argument
42325 #define XCVR_RD_ADC_ADJ(base)    (XCVR_ADC_ADJ_REG(base))  argument
42326 #define XCVR_WR_ADC_ADJ(base, value) (XCVR_ADC_ADJ_REG(base) = (value))  argument
42327 #define XCVR_RMW_ADC_ADJ(base, mask, value) (XCVR_WR_ADC_ADJ(base, (XCVR_RD_ADC_ADJ(base) & ~(mask)…  argument
42328 #define XCVR_SET_ADC_ADJ(base, value) (BME_OR32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(value)))  argument
42329 #define XCVR_CLR_ADC_ADJ(base, value) (BME_AND32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(~(value))))  argument
42330 #define XCVR_TOG_ADC_ADJ(base, value) (BME_XOR32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(value)))  argument
42345 #define XCVR_RD_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_OPAM…  argument
42346 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_…  argument
42349 #define XCVR_WR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_…  argument
42350 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint3…  argument
42361 #define XCVR_RD_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_OPAM…  argument
42362 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_…  argument
42365 #define XCVR_WR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_…  argument
42366 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint3…  argument
42376 #define XCVR_RD_ADC_ADJ_ADC_IB_DAC1_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_DAC1_A…  argument
42377 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…  argument
42380 #define XCVR_WR_ADC_ADJ_ADC_IB_DAC1_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_DA…  argument
42381 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…  argument
42391 #define XCVR_RD_ADC_ADJ_ADC_IB_DAC2_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_DAC2_A…  argument
42392 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…  argument
42395 #define XCVR_WR_ADC_ADJ_ADC_IB_DAC2_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_DA…  argument
42396 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…  argument
42407 #define XCVR_RD_ADC_ADJ_ADC_IB_FLSH_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_FLSH_A…  argument
42408 #define XCVR_BRD_ADC_ADJ_ADC_IB_FLSH_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_AD…  argument
42411 #define XCVR_WR_ADC_ADJ_ADC_IB_FLSH_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_FL…  argument
42412 #define XCVR_BWR_ADC_ADJ_ADC_IB_FLSH_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_…  argument
42423 #define XCVR_RD_ADC_ADJ_ADC_FLSH_RES_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_FLSH_RES…  argument
42424 #define XCVR_BRD_ADC_ADJ_ADC_FLSH_RES_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_A…  argument
42427 #define XCVR_WR_ADC_ADJ_ADC_FLSH_RES_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_FLSH…  argument
42428 #define XCVR_BWR_ADC_ADJ_ADC_FLSH_RES_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32…  argument
42444 #define XCVR_RD_ADC_REGS(base)   (XCVR_ADC_REGS_REG(base))  argument
42445 #define XCVR_WR_ADC_REGS(base, value) (XCVR_ADC_REGS_REG(base) = (value))  argument
42446 #define XCVR_RMW_ADC_REGS(base, mask, value) (XCVR_WR_ADC_REGS(base, (XCVR_RD_ADC_REGS(base) & ~(ma…  argument
42447 #define XCVR_SET_ADC_REGS(base, value) (BME_OR32(&XCVR_ADC_REGS_REG(base), (uint32_t)(value)))  argument
42448 #define XCVR_CLR_ADC_REGS(base, value) (BME_AND32(&XCVR_ADC_REGS_REG(base), (uint32_t)(~(value))))  argument
42449 #define XCVR_TOG_ADC_REGS(base, value) (BME_XOR32(&XCVR_ADC_REGS_REG(base), (uint32_t)(value)))  argument
42469 #define XCVR_RD_ADC_REGS_ADC_ANA_REG_SUPPLY(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_ANA…  argument
42470 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_R…  argument
42473 #define XCVR_WR_ADC_REGS_ADC_ANA_REG_SUPPLY(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC…  argument
42474 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((ui…  argument
42490 #define XCVR_RD_ADC_REGS_ADC_REG_DIG_SUPPLY(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_REG…  argument
42491 #define XCVR_BRD_ADC_REGS_ADC_REG_DIG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_R…  argument
42494 #define XCVR_WR_ADC_REGS_ADC_REG_DIG_SUPPLY(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC…  argument
42495 #define XCVR_BWR_ADC_REGS_ADC_REG_DIG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((ui…  argument
42507 #define XCVR_RD_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_…  argument
42508 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_AD…  argument
42511 #define XCVR_WR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_…  argument
42512 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), (…  argument
42524 #define XCVR_RD_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_…  argument
42525 #define XCVR_BRD_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_AD…  argument
42528 #define XCVR_WR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_…  argument
42529 #define XCVR_BWR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), (…  argument
42542 #define XCVR_RD_ADC_REGS_ADC_VCMREF_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_V…  argument
42543 #define XCVR_BRD_ADC_REGS_ADC_VCMREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC…  argument
42546 #define XCVR_WR_ADC_REGS_ADC_VCMREF_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_A…  argument
42547 #define XCVR_BWR_ADC_REGS_ADC_VCMREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((…  argument
42561 #define XCVR_RD_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REG…  argument
42562 #define XCVR_BRD_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), X…  argument
42565 #define XCVR_WR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC…  argument
42566 #define XCVR_BWR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(ba…  argument
42582 #define XCVR_RD_ADC_TRIMS(base)  (XCVR_ADC_TRIMS_REG(base))  argument
42583 #define XCVR_WR_ADC_TRIMS(base, value) (XCVR_ADC_TRIMS_REG(base) = (value))  argument
42584 #define XCVR_RMW_ADC_TRIMS(base, mask, value) (XCVR_WR_ADC_TRIMS(base, (XCVR_RD_ADC_TRIMS(base) & ~…  argument
42585 #define XCVR_SET_ADC_TRIMS(base, value) (BME_OR32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(value)))  argument
42586 #define XCVR_CLR_ADC_TRIMS(base, value) (BME_AND32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(~(value))))  argument
42587 #define XCVR_TOG_ADC_TRIMS(base, value) (BME_XOR32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(value)))  argument
42603 #define XCVR_RD_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIM…  argument
42604 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XC…  argument
42607 #define XCVR_WR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_…  argument
42608 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(bas…  argument
42619 #define XCVR_RD_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIMS_…  argument
42620 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR…  argument
42623 #define XCVR_WR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_TR…  argument
42624 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base)…  argument
42636 #define XCVR_RD_ADC_TRIMS_ADC_VCM_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIMS_ADC_VCM_TR…  argument
42637 #define XCVR_BRD_ADC_TRIMS_ADC_VCM_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR_ADC_TRIMS…  argument
42640 #define XCVR_WR_ADC_TRIMS_ADC_VCM_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_TRIMS_ADC_VC…  argument
42641 #define XCVR_BWR_ADC_TRIMS_ADC_VCM_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base), ((uint32…  argument
42657 #define XCVR_RD_ADC_TEST_CTRL(base) (XCVR_ADC_TEST_CTRL_REG(base))  argument
42658 #define XCVR_WR_ADC_TEST_CTRL(base, value) (XCVR_ADC_TEST_CTRL_REG(base) = (value))  argument
42659 #define XCVR_RMW_ADC_TEST_CTRL(base, mask, value) (XCVR_WR_ADC_TEST_CTRL(base, (XCVR_RD_ADC_TEST_CT…  argument
42660 #define XCVR_SET_ADC_TEST_CTRL(base, value) (BME_OR32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(val…  argument
42661 #define XCVR_CLR_ADC_TEST_CTRL(base, value) (BME_AND32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(~(…  argument
42662 #define XCVR_TOG_ADC_TEST_CTRL(base, value) (BME_XOR32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(va…  argument
42682 #define XCVR_RD_ADC_TEST_CTRL_ADC_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTR…  argument
42683 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_A…  argument
42686 #define XCVR_WR_ADC_TEST_CTRL_ADC_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST…  argument
42687 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), …  argument
42698 #define XCVR_RD_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_…  argument
42699 #define XCVR_BRD_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base)…  argument
42702 #define XCVR_WR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_…  argument
42703 #define XCVR_BWR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG…  argument
42714 #define XCVR_RD_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_…  argument
42715 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base)…  argument
42718 #define XCVR_WR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_…  argument
42719 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG…  argument
42741 #define XCVR_RD_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_…  argument
42742 #define XCVR_BRD_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(b…  argument
42745 #define XCVR_WR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, X…  argument
42746 #define XCVR_BWR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL…  argument
42756 #define XCVR_RD_ADC_TEST_CTRL_ADC_SPARE3(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_…  argument
42757 #define XCVR_BRD_ADC_TEST_CTRL_ADC_SPARE3(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC…  argument
42760 #define XCVR_WR_ADC_TEST_CTRL_ADC_SPARE3(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_C…  argument
42761 #define XCVR_BWR_ADC_TEST_CTRL_ADC_SPARE3(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((…  argument
42777 #define XCVR_RD_BBF_CTRL(base)   (XCVR_BBF_CTRL_REG(base))  argument
42778 #define XCVR_WR_BBF_CTRL(base, value) (XCVR_BBF_CTRL_REG(base) = (value))  argument
42779 #define XCVR_RMW_BBF_CTRL(base, mask, value) (XCVR_WR_BBF_CTRL(base, (XCVR_RD_BBF_CTRL(base) & ~(ma…  argument
42780 #define XCVR_SET_BBF_CTRL(base, value) (BME_OR32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(value)))  argument
42781 #define XCVR_CLR_BBF_CTRL(base, value) (BME_AND32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(~(value))))  argument
42782 #define XCVR_TOG_BBF_CTRL(base, value) (BME_XOR32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(value)))  argument
42809 #define XCVR_RD_BBF_CTRL_BBF_CAP_TUNE(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_CAP_TUNE_…  argument
42810 #define XCVR_BRD_BBF_CTRL_BBF_CAP_TUNE(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BB…  argument
42813 #define XCVR_WR_BBF_CTRL_BBF_CAP_TUNE(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_CAP_T…  argument
42814 #define XCVR_BWR_BBF_CTRL_BBF_CAP_TUNE(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t…  argument
42827 #define XCVR_RD_BBF_CTRL_BBF_RES_TUNE2(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_RES_TUNE…  argument
42828 #define XCVR_BRD_BBF_CTRL_BBF_RES_TUNE2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_B…  argument
42831 #define XCVR_WR_BBF_CTRL_BBF_RES_TUNE2(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_RES_…  argument
42832 #define XCVR_BWR_BBF_CTRL_BBF_RES_TUNE2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_…  argument
42847 #define XCVR_RD_BBF_CTRL_BBF_CUR_CNTL(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_CUR_CNTL_…  argument
42848 #define XCVR_BRD_BBF_CTRL_BBF_CUR_CNTL(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BB…  argument
42851 #define XCVR_WR_BBF_CTRL_BBF_CUR_CNTL(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_CUR_C…  argument
42852 #define XCVR_BWR_BBF_CTRL_BBF_CUR_CNTL(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t…  argument
42862 #define XCVR_RD_BBF_CTRL_BBF_DCOC_ON(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_DCOC_ON_MA…  argument
42863 #define XCVR_BRD_BBF_CTRL_BBF_DCOC_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF…  argument
42866 #define XCVR_WR_BBF_CTRL_BBF_DCOC_ON(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_DCOC_O…  argument
42867 #define XCVR_BWR_BBF_CTRL_BBF_DCOC_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)…  argument
42879 #define XCVR_RD_BBF_CTRL_BBF_TMUX_ON(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_TMUX_ON_MA…  argument
42880 #define XCVR_BRD_BBF_CTRL_BBF_TMUX_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF…  argument
42883 #define XCVR_WR_BBF_CTRL_BBF_TMUX_ON(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_TMUX_O…  argument
42884 #define XCVR_BWR_BBF_CTRL_BBF_TMUX_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)…  argument
42902 #define XCVR_RD_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_D…  argument
42903 #define XCVR_BRD_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR…  argument
42906 #define XCVR_WR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CT…  argument
42907 #define XCVR_BWR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base)…  argument
42917 #define XCVR_RD_BBF_CTRL_BBF_SPARE_3_2(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_SPARE_3_…  argument
42918 #define XCVR_BRD_BBF_CTRL_BBF_SPARE_3_2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_B…  argument
42921 #define XCVR_WR_BBF_CTRL_BBF_SPARE_3_2(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_SPAR…  argument
42922 #define XCVR_BWR_BBF_CTRL_BBF_SPARE_3_2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_…  argument
42938 #define XCVR_RD_RX_ANA_CTRL(base) (XCVR_RX_ANA_CTRL_REG(base))  argument
42939 #define XCVR_WR_RX_ANA_CTRL(base, value) (XCVR_RX_ANA_CTRL_REG(base) = (value))  argument
42940 #define XCVR_RMW_RX_ANA_CTRL(base, mask, value) (XCVR_WR_RX_ANA_CTRL(base, (XCVR_RD_RX_ANA_CTRL(bas…  argument
42941 #define XCVR_SET_RX_ANA_CTRL(base, value) (BME_OR32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(value)))  argument
42942 #define XCVR_CLR_RX_ANA_CTRL(base, value) (BME_AND32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(~(valu…  argument
42943 #define XCVR_TOG_RX_ANA_CTRL(base, value) (BME_XOR32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(value)…  argument
42966 #define XCVR_RD_RX_ANA_CTRL_RX_ATST_SEL(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CTRL_RX_AT…  argument
42967 #define XCVR_BRD_RX_ANA_CTRL_RX_ATST_SEL(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX_ANA…  argument
42970 #define XCVR_WR_RX_ANA_CTRL_RX_ATST_SEL(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_ANA_CTRL_R…  argument
42971 #define XCVR_BWR_RX_ANA_CTRL_RX_ATST_SEL(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), ((uin…  argument
42982 #define XCVR_RD_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CT…  argument
42983 #define XCVR_BRD_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCV…  argument
42986 #define XCVR_WR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_AN…  argument
42987 #define XCVR_BWR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base…  argument
42997 #define XCVR_RD_RX_ANA_CTRL_LNM_SPARE_3_2_1(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CTRL_L…  argument
42998 #define XCVR_BRD_RX_ANA_CTRL_LNM_SPARE_3_2_1(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX…  argument
43001 #define XCVR_WR_RX_ANA_CTRL_LNM_SPARE_3_2_1(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_ANA_CT…  argument
43002 #define XCVR_BWR_RX_ANA_CTRL_LNM_SPARE_3_2_1(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), (…  argument
43018 #define XCVR_RD_XTAL_CTRL(base)  (XCVR_XTAL_CTRL_REG(base))  argument
43019 #define XCVR_WR_XTAL_CTRL(base, value) (XCVR_XTAL_CTRL_REG(base) = (value))  argument
43020 #define XCVR_RMW_XTAL_CTRL(base, mask, value) (XCVR_WR_XTAL_CTRL(base, (XCVR_RD_XTAL_CTRL(base) & ~…  argument
43021 #define XCVR_SET_XTAL_CTRL(base, value) (BME_OR32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(value)))  argument
43022 #define XCVR_CLR_XTAL_CTRL(base, value) (BME_AND32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(~(value))))  argument
43023 #define XCVR_TOG_XTAL_CTRL(base, value) (BME_XOR32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(value)))  argument
43038 #define XCVR_RD_XTAL_CTRL_XTAL_TRIM(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_TRIM_MAS…  argument
43039 #define XCVR_BRD_XTAL_CTRL_XTAL_TRIM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XT…  argument
43042 #define XCVR_WR_XTAL_CTRL_XTAL_TRIM(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_TRIM…  argument
43043 #define XCVR_BWR_XTAL_CTRL_XTAL_TRIM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)…  argument
43054 #define XCVR_RD_XTAL_CTRL_XTAL_GM(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_GM_MASK) >…  argument
43055 #define XCVR_BRD_XTAL_CTRL_XTAL_GM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL…  argument
43058 #define XCVR_WR_XTAL_CTRL_XTAL_GM(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_GM_MAS…  argument
43059 #define XCVR_BWR_XTAL_CTRL_XTAL_GM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(v…  argument
43070 #define XCVR_RD_XTAL_CTRL_XTAL_BYPASS(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_BYPASS…  argument
43071 #define XCVR_BRD_XTAL_CTRL_XTAL_BYPASS(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_…  argument
43074 #define XCVR_WR_XTAL_CTRL_XTAL_BYPASS(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_BY…  argument
43075 #define XCVR_BWR_XTAL_CTRL_XTAL_BYPASS(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_…  argument
43091 #define XCVR_RD_XTAL_CTRL_XTAL_READY_COUNT_SEL(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XT…  argument
43092 #define XCVR_BRD_XTAL_CTRL_XTAL_READY_COUNT_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_X…  argument
43095 #define XCVR_WR_XTAL_CTRL_XTAL_READY_COUNT_SEL(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTR…  argument
43096 #define XCVR_BWR_XTAL_CTRL_XTAL_READY_COUNT_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), …  argument
43107 #define XCVR_RD_XTAL_CTRL_XTAL_COMP_BIAS_LO(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_…  argument
43108 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_LO(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL…  argument
43111 #define XCVR_WR_XTAL_CTRL_XTAL_COMP_BIAS_LO(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_X…  argument
43112 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_LO(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((u…  argument
43124 #define XCVR_RD_XTAL_CTRL_XTAL_ALC_START_512U(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTA…  argument
43125 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_START_512U(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XT…  argument
43128 #define XCVR_WR_XTAL_CTRL_XTAL_ALC_START_512U(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL…  argument
43129 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_START_512U(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), (…  argument
43139 #define XCVR_RD_XTAL_CTRL_XTAL_ALC_ON(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_ALC_ON…  argument
43140 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_…  argument
43143 #define XCVR_WR_XTAL_CTRL_XTAL_ALC_ON(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_AL…  argument
43144 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_…  argument
43155 #define XCVR_RD_XTAL_CTRL_XTAL_COMP_BIAS_HI(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_…  argument
43156 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_HI(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL…  argument
43159 #define XCVR_WR_XTAL_CTRL_XTAL_COMP_BIAS_HI(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_X…  argument
43160 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_HI(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((u…  argument
43171 #define XCVR_RD_XTAL_CTRL_XTAL_READY(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_READY_M…  argument
43172 #define XCVR_BRD_XTAL_CTRL_XTAL_READY(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_X…  argument
43188 #define XCVR_RD_XTAL_CTRL2(base) (XCVR_XTAL_CTRL2_REG(base))  argument
43189 #define XCVR_WR_XTAL_CTRL2(base, value) (XCVR_XTAL_CTRL2_REG(base) = (value))  argument
43190 #define XCVR_RMW_XTAL_CTRL2(base, mask, value) (XCVR_WR_XTAL_CTRL2(base, (XCVR_RD_XTAL_CTRL2(base) …  argument
43191 #define XCVR_SET_XTAL_CTRL2(base, value) (BME_OR32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(value)))  argument
43192 #define XCVR_CLR_XTAL_CTRL2(base, value) (BME_AND32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(~(value)…  argument
43193 #define XCVR_TOG_XTAL_CTRL2(base, value) (BME_XOR32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(value)))  argument
43213 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_SUPPLY(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL…  argument
43214 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL…  argument
43217 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_SUPPLY(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_…  argument
43218 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((u…  argument
43230 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_X…  argument
43231 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_X…  argument
43234 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTR…  argument
43235 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), …  argument
43246 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_…  argument
43247 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_…  argument
43250 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CT…  argument
43251 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base),…  argument
43261 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ON_OVRD(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTA…  argument
43262 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTA…  argument
43265 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ON_OVRD(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2…  argument
43266 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((…  argument
43277 #define XCVR_RD_XTAL_CTRL2_XTAL_ON_OVRD_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL…  argument
43278 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL…  argument
43281 #define XCVR_WR_XTAL_CTRL2_XTAL_ON_OVRD_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_…  argument
43282 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((u…  argument
43292 #define XCVR_RD_XTAL_CTRL2_XTAL_ON_OVRD(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_ON…  argument
43293 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CT…  argument
43296 #define XCVR_WR_XTAL_CTRL2_XTAL_ON_OVRD(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTA…  argument
43297 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint…  argument
43307 #define XCVR_RD_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_…  argument
43308 #define XCVR_BRD_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_…  argument
43311 #define XCVR_WR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CT…  argument
43312 #define XCVR_BWR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base),…  argument
43323 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ATST_SEL(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XT…  argument
43324 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XT…  argument
43327 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ATST_SEL(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL…  argument
43328 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), (…  argument
43340 #define XCVR_RD_XTAL_CTRL2_XTAL_ATST_SEL(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_A…  argument
43341 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_C…  argument
43344 #define XCVR_WR_XTAL_CTRL2_XTAL_ATST_SEL(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XT…  argument
43345 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uin…  argument
43356 #define XCVR_RD_XTAL_CTRL2_XTAL_ATST_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_AT…  argument
43357 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CT…  argument
43360 #define XCVR_WR_XTAL_CTRL2_XTAL_ATST_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTA…  argument
43361 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint…  argument
43371 #define XCVR_RD_XTAL_CTRL2_XTAL_SPARE(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_SPAR…  argument
43372 #define XCVR_BRD_XTAL_CTRL2_XTAL_SPARE(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL…  argument
43375 #define XCVR_WR_XTAL_CTRL2_XTAL_SPARE(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_…  argument
43376 #define XCVR_BWR_XTAL_CTRL2_XTAL_SPARE(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32…  argument
43392 #define XCVR_RD_BGAP_CTRL(base)  (XCVR_BGAP_CTRL_REG(base))  argument
43393 #define XCVR_WR_BGAP_CTRL(base, value) (XCVR_BGAP_CTRL_REG(base) = (value))  argument
43394 #define XCVR_RMW_BGAP_CTRL(base, mask, value) (XCVR_WR_BGAP_CTRL(base, (XCVR_RD_BGAP_CTRL(base) & ~…  argument
43395 #define XCVR_SET_BGAP_CTRL(base, value) (BME_OR32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(value)))  argument
43396 #define XCVR_CLR_BGAP_CTRL(base, value) (BME_AND32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(~(value))))  argument
43397 #define XCVR_TOG_BGAP_CTRL(base, value) (BME_XOR32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(value)))  argument
43411 #define XCVR_RD_BGAP_CTRL_BGAP_CURRENT_TRIM(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_…  argument
43412 #define XCVR_BRD_BGAP_CTRL_BGAP_CURRENT_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP…  argument
43415 #define XCVR_WR_BGAP_CTRL_BGAP_CURRENT_TRIM(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_B…  argument
43416 #define XCVR_BWR_BGAP_CTRL_BGAP_CURRENT_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((u…  argument
43426 #define XCVR_RD_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_…  argument
43427 #define XCVR_BRD_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP…  argument
43430 #define XCVR_WR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_B…  argument
43431 #define XCVR_BWR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((u…  argument
43443 #define XCVR_RD_BGAP_CTRL_BGAP_ATST_SEL(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_ATST…  argument
43444 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_SEL(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTR…  argument
43447 #define XCVR_WR_BGAP_CTRL_BGAP_ATST_SEL(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_…  argument
43448 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_SEL(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint3…  argument
43459 #define XCVR_RD_BGAP_CTRL_BGAP_ATST_ON(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_ATST_…  argument
43460 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_ON(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL…  argument
43463 #define XCVR_WR_BGAP_CTRL_BGAP_ATST_ON(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_A…  argument
43464 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_ON(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32…  argument
43480 #define XCVR_RD_PLL_CTRL(base)   (XCVR_PLL_CTRL_REG(base))  argument
43481 #define XCVR_WR_PLL_CTRL(base, value) (XCVR_PLL_CTRL_REG(base) = (value))  argument
43482 #define XCVR_RMW_PLL_CTRL(base, mask, value) (XCVR_WR_PLL_CTRL(base, (XCVR_RD_PLL_CTRL(base) & ~(ma…  argument
43483 #define XCVR_SET_PLL_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(value)))  argument
43484 #define XCVR_CLR_PLL_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(~(value))))  argument
43485 #define XCVR_TOG_PLL_CTRL(base, value) (BME_XOR32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(value)))  argument
43500 #define XCVR_RD_PLL_CTRL_PLL_VCO_BIAS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO_BIAS_…  argument
43501 #define XCVR_BRD_PLL_CTRL_PLL_VCO_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PL…  argument
43504 #define XCVR_WR_PLL_CTRL_PLL_VCO_BIAS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_VCO_B…  argument
43505 #define XCVR_BWR_PLL_CTRL_PLL_VCO_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t…  argument
43517 #define XCVR_RD_PLL_CTRL_PLL_LFILT_CNTL(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_LFILT_C…  argument
43518 #define XCVR_BRD_PLL_CTRL_PLL_LFILT_CNTL(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…  argument
43521 #define XCVR_WR_PLL_CTRL_PLL_LFILT_CNTL(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_LFI…  argument
43522 #define XCVR_BWR_PLL_CTRL_PLL_LFILT_CNTL(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…  argument
43538 #define XCVR_RD_PLL_CTRL_PLL_REG_SUPPLY(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_REG_SUP…  argument
43539 #define XCVR_BRD_PLL_CTRL_PLL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…  argument
43542 #define XCVR_WR_PLL_CTRL_PLL_REG_SUPPLY(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_REG…  argument
43543 #define XCVR_BWR_PLL_CTRL_PLL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…  argument
43555 #define XCVR_RD_PLL_CTRL_PLL_REG_BYPASS_ON(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_REG_…  argument
43556 #define XCVR_BRD_PLL_CTRL_PLL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CT…  argument
43559 #define XCVR_WR_PLL_CTRL_PLL_REG_BYPASS_ON(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_…  argument
43560 #define XCVR_BWR_PLL_CTRL_PLL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uin…  argument
43572 #define XCVR_RD_PLL_CTRL_PLL_VCO_LDO_BYPASS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO…  argument
43573 #define XCVR_BRD_PLL_CTRL_PLL_VCO_LDO_BYPASS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_C…  argument
43576 #define XCVR_WR_PLL_CTRL_PLL_VCO_LDO_BYPASS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL…  argument
43577 #define XCVR_BWR_PLL_CTRL_PLL_VCO_LDO_BYPASS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((ui…  argument
43588 #define XCVR_RD_PLL_CTRL_HPM_BIAS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_HPM_BIAS_MASK) >>…  argument
43589 #define XCVR_BRD_PLL_CTRL_HPM_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_HPM_BI…  argument
43592 #define XCVR_WR_PLL_CTRL_HPM_BIAS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_HPM_BIAS_MASK…  argument
43593 #define XCVR_BWR_PLL_CTRL_HPM_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(va…  argument
43603 #define XCVR_RD_PLL_CTRL_PLL_VCO_SPARE7(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO_SPA…  argument
43604 #define XCVR_BRD_PLL_CTRL_PLL_VCO_SPARE7(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_…  argument
43607 #define XCVR_WR_PLL_CTRL_PLL_VCO_SPARE7(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_VCO…  argument
43608 #define XCVR_BWR_PLL_CTRL_PLL_VCO_SPARE7(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32…  argument
43624 #define XCVR_RD_PLL_CTRL2(base)  (XCVR_PLL_CTRL2_REG(base))  argument
43625 #define XCVR_WR_PLL_CTRL2(base, value) (XCVR_PLL_CTRL2_REG(base) = (value))  argument
43626 #define XCVR_RMW_PLL_CTRL2(base, mask, value) (XCVR_WR_PLL_CTRL2(base, (XCVR_RD_PLL_CTRL2(base) & ~…  argument
43627 #define XCVR_SET_PLL_CTRL2(base, value) (BME_OR32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(value)))  argument
43628 #define XCVR_CLR_PLL_CTRL2(base, value) (BME_AND32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(~(value))))  argument
43629 #define XCVR_TOG_PLL_CTRL2(base, value) (BME_XOR32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(value)))  argument
43645 #define XCVR_RD_PLL_CTRL2_PLL_VCO_KV(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_VCO_KV_M…  argument
43646 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_KV(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_P…  argument
43649 #define XCVR_WR_PLL_CTRL2_PLL_VCO_KV(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_VCO_…  argument
43650 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_KV(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t…  argument
43661 #define XCVR_RD_PLL_CTRL2_PLL_KMOD_SLOPE(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_KMOD…  argument
43662 #define XCVR_BRD_PLL_CTRL2_PLL_KMOD_SLOPE(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTR…  argument
43665 #define XCVR_WR_PLL_CTRL2_PLL_KMOD_SLOPE(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_…  argument
43666 #define XCVR_BWR_PLL_CTRL2_PLL_KMOD_SLOPE(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint…  argument
43680 #define XCVR_RD_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_…  argument
43681 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL…  argument
43684 #define XCVR_WR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_…  argument
43685 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((…  argument
43696 #define XCVR_RD_PLL_CTRL2_PLL_TMUX_ON(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_TMUX_ON…  argument
43697 #define XCVR_BRD_PLL_CTRL2_PLL_TMUX_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_…  argument
43700 #define XCVR_WR_PLL_CTRL2_PLL_TMUX_ON(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_TMU…  argument
43701 #define XCVR_BWR_PLL_CTRL2_PLL_TMUX_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_…  argument
43717 #define XCVR_RD_PLL_TEST_CTRL(base) (XCVR_PLL_TEST_CTRL_REG(base))  argument
43718 #define XCVR_WR_PLL_TEST_CTRL(base, value) (XCVR_PLL_TEST_CTRL_REG(base) = (value))  argument
43719 #define XCVR_RMW_PLL_TEST_CTRL(base, mask, value) (XCVR_WR_PLL_TEST_CTRL(base, (XCVR_RD_PLL_TEST_CT…  argument
43720 #define XCVR_SET_PLL_TEST_CTRL(base, value) (BME_OR32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(val…  argument
43721 #define XCVR_CLR_PLL_TEST_CTRL(base, value) (BME_AND32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(~(…  argument
43722 #define XCVR_TOG_PLL_TEST_CTRL(base, value) (BME_XOR32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(va…  argument
43741 #define XCVR_RD_PLL_TEST_CTRL_PLL_TMUX_SEL(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTR…  argument
43742 #define XCVR_BRD_PLL_TEST_CTRL_PLL_TMUX_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_P…  argument
43745 #define XCVR_WR_PLL_TEST_CTRL_PLL_TMUX_SEL(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST…  argument
43746 #define XCVR_BWR_PLL_TEST_CTRL_PLL_TMUX_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), …  argument
43757 #define XCVR_RD_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST…  argument
43758 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XC…  argument
43761 #define XCVR_WR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_…  argument
43762 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(bas…  argument
43773 #define XCVR_RD_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST…  argument
43774 #define XCVR_BRD_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XC…  argument
43777 #define XCVR_WR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_…  argument
43778 #define XCVR_BWR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(bas…  argument
43788 #define XCVR_RD_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL…  argument
43789 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base…  argument
43792 #define XCVR_WR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR…  argument
43793 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_RE…  argument
43803 #define XCVR_RD_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCV…  argument
43804 #define XCVR_BRD_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG…  argument
43807 #define XCVR_WR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base, value) (XCVR_RMW_PLL_TEST_CTRL(base,…  argument
43808 #define XCVR_BWR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base, value) (BME_BFI32(&XCVR_PLL_TEST_CT…  argument
43818 #define XCVR_RD_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base) ((XCVR_PLL_TEST_CTRL_REG(base) & X…  argument
43819 #define XCVR_BRD_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_R…  argument
43822 #define XCVR_WR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base, value) (XCVR_RMW_PLL_TEST_CTRL(bas…  argument
43823 #define XCVR_BWR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_…  argument
43839 #define XCVR_RD_QGEN_CTRL(base)  (XCVR_QGEN_CTRL_REG(base))  argument
43840 #define XCVR_WR_QGEN_CTRL(base, value) (XCVR_QGEN_CTRL_REG(base) = (value))  argument
43841 #define XCVR_RMW_QGEN_CTRL(base, mask, value) (XCVR_WR_QGEN_CTRL(base, (XCVR_RD_QGEN_CTRL(base) & ~…  argument
43842 #define XCVR_SET_QGEN_CTRL(base, value) (BME_OR32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(value)))  argument
43843 #define XCVR_CLR_QGEN_CTRL(base, value) (BME_AND32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(~(value))))  argument
43844 #define XCVR_TOG_QGEN_CTRL(base, value) (BME_XOR32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(value)))  argument
43864 #define XCVR_RD_QGEN_CTRL_QGEN_REG_SUPPLY(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN_RE…  argument
43865 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_SUPPLY(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN_C…  argument
43868 #define XCVR_WR_QGEN_CTRL_QGEN_REG_SUPPLY(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_QGE…  argument
43869 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((uin…  argument
43880 #define XCVR_RD_QGEN_CTRL_QGEN_REG_ATST_SEL(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN_…  argument
43881 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN…  argument
43884 #define XCVR_WR_QGEN_CTRL_QGEN_REG_ATST_SEL(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_Q…  argument
43885 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((u…  argument
43897 #define XCVR_RD_QGEN_CTRL_QGEN_REG_BYPASS_ON(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN…  argument
43898 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGE…  argument
43901 #define XCVR_WR_QGEN_CTRL_QGEN_REG_BYPASS_ON(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_…  argument
43902 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((…  argument
43918 #define XCVR_RD_TCA_CTRL(base)   (XCVR_TCA_CTRL_REG(base))  argument
43919 #define XCVR_WR_TCA_CTRL(base, value) (XCVR_TCA_CTRL_REG(base) = (value))  argument
43920 #define XCVR_RMW_TCA_CTRL(base, mask, value) (XCVR_WR_TCA_CTRL(base, (XCVR_RD_TCA_CTRL(base) & ~(ma…  argument
43921 #define XCVR_SET_TCA_CTRL(base, value) (BME_OR32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(value)))  argument
43922 #define XCVR_CLR_TCA_CTRL(base, value) (BME_AND32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(~(value))))  argument
43923 #define XCVR_TOG_TCA_CTRL(base, value) (BME_XOR32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(value)))  argument
43937 #define XCVR_RD_TCA_CTRL_TCA_BIAS_CURR(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_BIAS_CUR…  argument
43938 #define XCVR_BRD_TCA_CTRL_TCA_BIAS_CURR(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_T…  argument
43941 #define XCVR_WR_TCA_CTRL_TCA_BIAS_CURR(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_BIAS…  argument
43942 #define XCVR_BWR_TCA_CTRL_TCA_BIAS_CURR(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_…  argument
43952 #define XCVR_RD_TCA_CTRL_TCA_LOW_PWR_ON(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_LOW_PWR…  argument
43953 #define XCVR_BRD_TCA_CTRL_TCA_LOW_PWR_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_…  argument
43956 #define XCVR_WR_TCA_CTRL_TCA_LOW_PWR_ON(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_LOW…  argument
43957 #define XCVR_BWR_TCA_CTRL_TCA_LOW_PWR_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32…  argument
43969 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_T…  argument
43970 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA…  argument
43973 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_T…  argument
43974 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((…  argument
43990 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_SUPPLY(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_TX_R…  argument
43991 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_SUPPLY(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CT…  argument
43994 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_SUPPLY(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_…  argument
43995 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uin…  argument
44006 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_ATST_SEL(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_TX…  argument
44007 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_…  argument
44010 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_ATST_SEL(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TC…  argument
44011 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((u…  argument
44027 #define XCVR_RD_TZA_CTRL(base)   (XCVR_TZA_CTRL_REG(base))  argument
44028 #define XCVR_WR_TZA_CTRL(base, value) (XCVR_TZA_CTRL_REG(base) = (value))  argument
44029 #define XCVR_RMW_TZA_CTRL(base, mask, value) (XCVR_WR_TZA_CTRL(base, (XCVR_RD_TZA_CTRL(base) & ~(ma…  argument
44030 #define XCVR_SET_TZA_CTRL(base, value) (BME_OR32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(value)))  argument
44031 #define XCVR_CLR_TZA_CTRL(base, value) (BME_AND32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(~(value))))  argument
44032 #define XCVR_TOG_TZA_CTRL(base, value) (BME_XOR32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(value)))  argument
44048 #define XCVR_RD_TZA_CTRL_TZA_CAP_TUNE(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_CAP_TUNE_…  argument
44049 #define XCVR_BRD_TZA_CTRL_TZA_CAP_TUNE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZ…  argument
44052 #define XCVR_WR_TZA_CTRL_TZA_CAP_TUNE(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_CAP_T…  argument
44053 #define XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t…  argument
44063 #define XCVR_RD_TZA_CTRL_TZA_GAIN(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_GAIN_MASK) >>…  argument
44064 #define XCVR_BRD_TZA_CTRL_TZA_GAIN(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_GA…  argument
44067 #define XCVR_WR_TZA_CTRL_TZA_GAIN(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_GAIN_MASK…  argument
44068 #define XCVR_BWR_TZA_CTRL_TZA_GAIN(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(va…  argument
44079 #define XCVR_RD_TZA_CTRL_TZA_DCOC_ON(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_DCOC_ON_MA…  argument
44080 #define XCVR_BRD_TZA_CTRL_TZA_DCOC_ON(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA…  argument
44083 #define XCVR_WR_TZA_CTRL_TZA_DCOC_ON(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_DCOC_O…  argument
44084 #define XCVR_BWR_TZA_CTRL_TZA_DCOC_ON(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)…  argument
44094 #define XCVR_RD_TZA_CTRL_TZA_CUR_CNTL(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_CUR_CNTL_…  argument
44095 #define XCVR_BRD_TZA_CTRL_TZA_CUR_CNTL(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZ…  argument
44098 #define XCVR_WR_TZA_CTRL_TZA_CUR_CNTL(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_CUR_C…  argument
44099 #define XCVR_BWR_TZA_CTRL_TZA_CUR_CNTL(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t…  argument
44109 #define XCVR_RD_TZA_CTRL_TZA_SPARE(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_SPARE_MASK) …  argument
44110 #define XCVR_BRD_TZA_CTRL_TZA_SPARE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_S…  argument
44113 #define XCVR_WR_TZA_CTRL_TZA_SPARE(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_SPARE_MA…  argument
44114 #define XCVR_BWR_TZA_CTRL_TZA_SPARE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(v…  argument
44130 #define XCVR_RD_TX_ANA_CTRL(base) (XCVR_TX_ANA_CTRL_REG(base))  argument
44131 #define XCVR_WR_TX_ANA_CTRL(base, value) (XCVR_TX_ANA_CTRL_REG(base) = (value))  argument
44132 #define XCVR_RMW_TX_ANA_CTRL(base, mask, value) (XCVR_WR_TX_ANA_CTRL(base, (XCVR_RD_TX_ANA_CTRL(bas…  argument
44133 #define XCVR_SET_TX_ANA_CTRL(base, value) (BME_OR32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(value)))  argument
44134 #define XCVR_CLR_TX_ANA_CTRL(base, value) (BME_AND32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(~(valu…  argument
44135 #define XCVR_TOG_TX_ANA_CTRL(base, value) (BME_XOR32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(value)…  argument
44150 #define XCVR_RD_TX_ANA_CTRL_HPM_CAL_ADJUST(base) ((XCVR_TX_ANA_CTRL_REG(base) & XCVR_TX_ANA_CTRL_HP…  argument
44151 #define XCVR_BRD_TX_ANA_CTRL_HPM_CAL_ADJUST(base) (BME_UBFX32(&XCVR_TX_ANA_CTRL_REG(base), XCVR_TX_…  argument
44154 #define XCVR_WR_TX_ANA_CTRL_HPM_CAL_ADJUST(base, value) (XCVR_RMW_TX_ANA_CTRL(base, XCVR_TX_ANA_CTR…  argument
44155 #define XCVR_BWR_TX_ANA_CTRL_HPM_CAL_ADJUST(base, value) (BME_BFI32(&XCVR_TX_ANA_CTRL_REG(base), ((…  argument
44171 #define XCVR_RD_ANA_SPARE(base)  (XCVR_ANA_SPARE_REG(base))  argument
44172 #define XCVR_WR_ANA_SPARE(base, value) (XCVR_ANA_SPARE_REG(base) = (value))  argument
44173 #define XCVR_RMW_ANA_SPARE(base, mask, value) (XCVR_WR_ANA_SPARE(base, (XCVR_RD_ANA_SPARE(base) & ~…  argument
44174 #define XCVR_SET_ANA_SPARE(base, value) (BME_OR32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(value)))  argument
44175 #define XCVR_CLR_ANA_SPARE(base, value) (BME_AND32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(~(value))))  argument
44176 #define XCVR_TOG_ANA_SPARE(base, value) (BME_XOR32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(value)))  argument
44194 #define XCVR_RD_ANA_SPARE_IQMC_DC_GAIN_ADJ(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_IQMC_D…  argument
44195 #define XCVR_BRD_ANA_SPARE_IQMC_DC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_S…  argument
44198 #define XCVR_WR_ANA_SPARE_IQMC_DC_GAIN_ADJ(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_IQ…  argument
44199 #define XCVR_BWR_ANA_SPARE_IQMC_DC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((ui…  argument
44220 #define XCVR_RD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_DCO…  argument
44221 #define XCVR_BRD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_AN…  argument
44224 #define XCVR_WR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE…  argument
44225 #define XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), (…  argument
44235 #define XCVR_RD_ANA_SPARE_HPM_LSB_INVERT(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_HPM_LSB_…  argument
44236 #define XCVR_BRD_ANA_SPARE_HPM_LSB_INVERT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPA…  argument
44239 #define XCVR_WR_ANA_SPARE_HPM_LSB_INVERT(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_HPM_…  argument
44240 #define XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint…  argument
44250 #define XCVR_RD_ANA_SPARE_ANA_DTEST(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_ANA_DTEST_MAS…  argument
44251 #define XCVR_BRD_ANA_SPARE_ANA_DTEST(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_AN…  argument
44321 #define ZLL_RD_IRQSTS(base)      (ZLL_IRQSTS_REG(base))  argument
44322 #define ZLL_WR_IRQSTS(base, value) (ZLL_IRQSTS_REG(base) = (value))  argument
44323 #define ZLL_RMW_IRQSTS(base, mask, value) (ZLL_WR_IRQSTS(base, (ZLL_RD_IRQSTS(base) & ~(mask)) | (v…  argument
44324 #define ZLL_SET_IRQSTS(base, value) (BME_OR32(&ZLL_IRQSTS_REG(base), (uint32_t)(value)))  argument
44325 #define ZLL_CLR_IRQSTS(base, value) (BME_AND32(&ZLL_IRQSTS_REG(base), (uint32_t)(~(value))))  argument
44326 #define ZLL_TOG_IRQSTS(base, value) (BME_XOR32(&ZLL_IRQSTS_REG(base), (uint32_t)(value)))  argument
44342 #define ZLL_RD_IRQSTS_SEQIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_SEQIRQ_MASK) >> ZLL_IRQSTS_S…  argument
44343 #define ZLL_BRD_IRQSTS_SEQIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SEQIRQ_SHIFT, ZLL…  argument
44346 #define ZLL_WR_IRQSTS_SEQIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQST…  argument
44347 #define ZLL_BWR_IRQSTS_SEQIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << …  argument
44359 #define ZLL_RD_IRQSTS_TXIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TXIRQ_MASK) >> ZLL_IRQSTS_TXI…  argument
44360 #define ZLL_BRD_IRQSTS_TXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TXIRQ_SHIFT, ZLL_I…  argument
44363 #define ZLL_WR_IRQSTS_TXIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_…  argument
44364 #define ZLL_BWR_IRQSTS_TXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << Z…  argument
44376 #define ZLL_RD_IRQSTS_RXIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RXIRQ_MASK) >> ZLL_IRQSTS_RXI…  argument
44377 #define ZLL_BRD_IRQSTS_RXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXIRQ_SHIFT, ZLL_I…  argument
44380 #define ZLL_WR_IRQSTS_RXIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_…  argument
44381 #define ZLL_BWR_IRQSTS_RXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << Z…  argument
44393 #define ZLL_RD_IRQSTS_CCAIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CCAIRQ_MASK) >> ZLL_IRQSTS_C…  argument
44394 #define ZLL_BRD_IRQSTS_CCAIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCAIRQ_SHIFT, ZLL…  argument
44397 #define ZLL_WR_IRQSTS_CCAIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQST…  argument
44398 #define ZLL_BWR_IRQSTS_CCAIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << …  argument
44410 #define ZLL_RD_IRQSTS_RXWTRMRKIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) >> ZL…  argument
44411 #define ZLL_BRD_IRQSTS_RXWTRMRKIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXWTRMRKIRQ_…  argument
44414 #define ZLL_WR_IRQSTS_RXWTRMRKIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_RXWTRMRKIRQ_MASK |…  argument
44415 #define ZLL_BWR_IRQSTS_RXWTRMRKIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value…  argument
44427 #define ZLL_RD_IRQSTS_FILTERFAIL_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK)…  argument
44428 #define ZLL_BRD_IRQSTS_FILTERFAIL_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_FILTERFAI…  argument
44431 #define ZLL_WR_IRQSTS_FILTERFAIL_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_FILTERFAIL_IRQ_…  argument
44432 #define ZLL_BWR_IRQSTS_FILTERFAIL_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(va…  argument
44444 #define ZLL_RD_IRQSTS_PLL_UNLOCK_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK)…  argument
44445 #define ZLL_BRD_IRQSTS_PLL_UNLOCK_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PLL_UNLOC…  argument
44448 #define ZLL_WR_IRQSTS_PLL_UNLOCK_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_PLL_UNLOCK_IRQ_…  argument
44449 #define ZLL_BWR_IRQSTS_PLL_UNLOCK_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(va…  argument
44457 #define ZLL_RD_IRQSTS_RX_FRM_PEND(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RX_FRM_PEND_MASK) >> ZL…  argument
44458 #define ZLL_BRD_IRQSTS_RX_FRM_PEND(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRM_PEND_…  argument
44470 #define ZLL_RD_IRQSTS_PB_ERR_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PB_ERR_IRQ_MASK) >> ZLL_…  argument
44471 #define ZLL_BRD_IRQSTS_PB_ERR_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PB_ERR_IRQ_SH…  argument
44474 #define ZLL_WR_IRQSTS_PB_ERR_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_PB_ERR_IRQ_MASK | Z…  argument
44475 #define ZLL_BWR_IRQSTS_PB_ERR_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value)…  argument
44488 #define ZLL_RD_IRQSTS_TMRSTATUS(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMRSTATUS_MASK) >> ZLL_IR…  argument
44489 #define ZLL_BRD_IRQSTS_TMRSTATUS(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMRSTATUS_SHIF…  argument
44503 #define ZLL_RD_IRQSTS_PI(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PI_MASK) >> ZLL_IRQSTS_PI_SHIFT)  argument
44504 #define ZLL_BRD_IRQSTS_PI(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PI_SHIFT, ZLL_IRQSTS_…  argument
44522 #define ZLL_RD_IRQSTS_SRCADDR(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_SRCADDR_MASK) >> ZLL_IRQSTS…  argument
44523 #define ZLL_BRD_IRQSTS_SRCADDR(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SRCADDR_SHIFT, Z…  argument
44538 #define ZLL_RD_IRQSTS_CCA(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CCA_MASK) >> ZLL_IRQSTS_CCA_SHI…  argument
44539 #define ZLL_BRD_IRQSTS_CCA(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCA_SHIFT, ZLL_IRQST…  argument
44555 #define ZLL_RD_IRQSTS_CRCVALID(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CRCVALID_MASK) >> ZLL_IRQS…  argument
44556 #define ZLL_BRD_IRQSTS_CRCVALID(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CRCVALID_SHIFT,…  argument
44567 #define ZLL_RD_IRQSTS_TMR1IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR1IRQ_MASK) >> ZLL_IRQSTS…  argument
44568 #define ZLL_BRD_IRQSTS_TMR1IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1IRQ_SHIFT, Z…  argument
44571 #define ZLL_WR_IRQSTS_TMR1IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQ…  argument
44572 #define ZLL_BWR_IRQSTS_TMR1IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44584 #define ZLL_RD_IRQSTS_TMR2IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR2IRQ_MASK) >> ZLL_IRQSTS…  argument
44585 #define ZLL_BRD_IRQSTS_TMR2IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2IRQ_SHIFT, Z…  argument
44588 #define ZLL_WR_IRQSTS_TMR2IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQ…  argument
44589 #define ZLL_BWR_IRQSTS_TMR2IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44600 #define ZLL_RD_IRQSTS_TMR3IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR3IRQ_MASK) >> ZLL_IRQSTS…  argument
44601 #define ZLL_BRD_IRQSTS_TMR3IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3IRQ_SHIFT, Z…  argument
44604 #define ZLL_WR_IRQSTS_TMR3IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQ…  argument
44605 #define ZLL_BWR_IRQSTS_TMR3IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44616 #define ZLL_RD_IRQSTS_TMR4IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR4IRQ_MASK) >> ZLL_IRQSTS…  argument
44617 #define ZLL_BRD_IRQSTS_TMR4IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4IRQ_SHIFT, Z…  argument
44620 #define ZLL_WR_IRQSTS_TMR4IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR4IRQ_MASK | ZLL_IRQ…  argument
44621 #define ZLL_BWR_IRQSTS_TMR4IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44633 #define ZLL_RD_IRQSTS_TMR1MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR1MSK_MASK) >> ZLL_IRQSTS…  argument
44634 #define ZLL_BRD_IRQSTS_TMR1MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1MSK_SHIFT, Z…  argument
44637 #define ZLL_WR_IRQSTS_TMR1MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR1MSK_MASK | ZLL_IRQ…  argument
44638 #define ZLL_BWR_IRQSTS_TMR1MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44650 #define ZLL_RD_IRQSTS_TMR2MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR2MSK_MASK) >> ZLL_IRQSTS…  argument
44651 #define ZLL_BRD_IRQSTS_TMR2MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2MSK_SHIFT, Z…  argument
44654 #define ZLL_WR_IRQSTS_TMR2MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR2MSK_MASK | ZLL_IRQ…  argument
44655 #define ZLL_BWR_IRQSTS_TMR2MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44667 #define ZLL_RD_IRQSTS_TMR3MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR3MSK_MASK) >> ZLL_IRQSTS…  argument
44668 #define ZLL_BRD_IRQSTS_TMR3MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3MSK_SHIFT, Z…  argument
44671 #define ZLL_WR_IRQSTS_TMR3MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR3MSK_MASK | ZLL_IRQ…  argument
44672 #define ZLL_BWR_IRQSTS_TMR3MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44684 #define ZLL_RD_IRQSTS_TMR4MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR4MSK_MASK) >> ZLL_IRQSTS…  argument
44685 #define ZLL_BRD_IRQSTS_TMR4MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4MSK_SHIFT, Z…  argument
44688 #define ZLL_WR_IRQSTS_TMR4MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR4MSK_MASK | ZLL_IRQ…  argument
44689 #define ZLL_BWR_IRQSTS_TMR4MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) <<…  argument
44700 #define ZLL_RD_IRQSTS_RX_FRAME_LENGTH(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RX_FRAME_LENGTH_MAS…  argument
44701 #define ZLL_BRD_IRQSTS_RX_FRAME_LENGTH(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRAME…  argument
44719 #define ZLL_RD_PHY_CTRL(base)    (ZLL_PHY_CTRL_REG(base))  argument
44720 #define ZLL_WR_PHY_CTRL(base, value) (ZLL_PHY_CTRL_REG(base) = (value))  argument
44721 #define ZLL_RMW_PHY_CTRL(base, mask, value) (ZLL_WR_PHY_CTRL(base, (ZLL_RD_PHY_CTRL(base) & ~(mask)…  argument
44722 #define ZLL_SET_PHY_CTRL(base, value) (BME_OR32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(value)))  argument
44723 #define ZLL_CLR_PHY_CTRL(base, value) (BME_AND32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(~(value))))  argument
44724 #define ZLL_TOG_PHY_CTRL(base, value) (BME_XOR32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(value)))  argument
44748 #define ZLL_RD_PHY_CTRL_XCVSEQ(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PH…  argument
44749 #define ZLL_BRD_PHY_CTRL_XCVSEQ(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_XCVSEQ_SHIF…  argument
44752 #define ZLL_WR_PHY_CTRL_XCVSEQ(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_XCVSEQ_MASK, ZLL_P…  argument
44753 #define ZLL_BWR_PHY_CTRL_XCVSEQ(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…  argument
44770 #define ZLL_RD_PHY_CTRL_AUTOACK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_AUTOACK_MASK) >> ZLL_…  argument
44771 #define ZLL_BRD_PHY_CTRL_AUTOACK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_AUTOACK_SH…  argument
44774 #define ZLL_WR_PHY_CTRL_AUTOACK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_AUTOACK_MASK, ZLL…  argument
44775 #define ZLL_BWR_PHY_CTRL_AUTOACK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…  argument
44791 #define ZLL_RD_PHY_CTRL_RXACKRQD(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RXACKRQD_MASK) >> ZL…  argument
44792 #define ZLL_BRD_PHY_CTRL_RXACKRQD(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXACKRQD_…  argument
44795 #define ZLL_WR_PHY_CTRL_RXACKRQD(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RXACKRQD_MASK, Z…  argument
44796 #define ZLL_BWR_PHY_CTRL_RXACKRQD(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…  argument
44811 #define ZLL_RD_PHY_CTRL_CCABFRTX(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCABFRTX_MASK) >> ZL…  argument
44812 #define ZLL_BRD_PHY_CTRL_CCABFRTX(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCABFRTX_…  argument
44815 #define ZLL_WR_PHY_CTRL_CCABFRTX(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCABFRTX_MASK, Z…  argument
44816 #define ZLL_BWR_PHY_CTRL_CCABFRTX(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…  argument
44830 #define ZLL_RD_PHY_CTRL_SLOTTED(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_SLOTTED_MASK) >> ZLL_…  argument
44831 #define ZLL_BRD_PHY_CTRL_SLOTTED(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SLOTTED_SH…  argument
44834 #define ZLL_WR_PHY_CTRL_SLOTTED(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_SLOTTED_MASK, ZLL…  argument
44835 #define ZLL_BWR_PHY_CTRL_SLOTTED(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…  argument
44848 #define ZLL_RD_PHY_CTRL_TMRTRIGEN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMRTRIGEN_MASK) >> …  argument
44849 #define ZLL_BRD_PHY_CTRL_TMRTRIGEN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMRTRIGE…  argument
44852 #define ZLL_WR_PHY_CTRL_TMRTRIGEN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMRTRIGEN_MASK,…  argument
44853 #define ZLL_BWR_PHY_CTRL_TMRTRIGEN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(val…  argument
44866 #define ZLL_RD_PHY_CTRL_SEQMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_SEQMSK_MASK) >> ZLL_PH…  argument
44867 #define ZLL_BRD_PHY_CTRL_SEQMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SEQMSK_SHIF…  argument
44870 #define ZLL_WR_PHY_CTRL_SEQMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_SEQMSK_MASK, ZLL_P…  argument
44871 #define ZLL_BWR_PHY_CTRL_SEQMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…  argument
44884 #define ZLL_RD_PHY_CTRL_TXMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TXMSK_MASK) >> ZLL_PHY_…  argument
44885 #define ZLL_BRD_PHY_CTRL_TXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TXMSK_SHIFT,…  argument
44888 #define ZLL_WR_PHY_CTRL_TXMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TXMSK_MASK, ZLL_PHY…  argument
44889 #define ZLL_BWR_PHY_CTRL_TXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) …  argument
44902 #define ZLL_RD_PHY_CTRL_RXMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RXMSK_MASK) >> ZLL_PHY_…  argument
44903 #define ZLL_BRD_PHY_CTRL_RXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXMSK_SHIFT,…  argument
44906 #define ZLL_WR_PHY_CTRL_RXMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RXMSK_MASK, ZLL_PHY…  argument
44907 #define ZLL_BWR_PHY_CTRL_RXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) …  argument
44922 #define ZLL_RD_PHY_CTRL_CCAMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCAMSK_MASK) >> ZLL_PH…  argument
44923 #define ZLL_BRD_PHY_CTRL_CCAMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCAMSK_SHIF…  argument
44926 #define ZLL_WR_PHY_CTRL_CCAMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCAMSK_MASK, ZLL_P…  argument
44927 #define ZLL_BWR_PHY_CTRL_CCAMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value)…  argument
44943 #define ZLL_RD_PHY_CTRL_RX_WMRK_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)…  argument
44944 #define ZLL_BRD_PHY_CTRL_RX_WMRK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RX_WMR…  argument
44947 #define ZLL_WR_PHY_CTRL_RX_WMRK_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RX_WMRK_MSK_M…  argument
44948 #define ZLL_BWR_PHY_CTRL_RX_WMRK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…  argument
44964 #define ZLL_RD_PHY_CTRL_FILTERFAIL_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_FILTERFAIL_MSK…  argument
44965 #define ZLL_BRD_PHY_CTRL_FILTERFAIL_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_FIL…  argument
44968 #define ZLL_WR_PHY_CTRL_FILTERFAIL_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_FILTERFAIL…  argument
44969 #define ZLL_BWR_PHY_CTRL_FILTERFAIL_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t…  argument
44982 #define ZLL_RD_PHY_CTRL_PLL_UNLOCK_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK…  argument
44983 #define ZLL_BRD_PHY_CTRL_PLL_UNLOCK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PLL…  argument
44986 #define ZLL_WR_PHY_CTRL_PLL_UNLOCK_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PLL_UNLOCK…  argument
44987 #define ZLL_BWR_PHY_CTRL_PLL_UNLOCK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t…  argument
45005 #define ZLL_RD_PHY_CTRL_CRC_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CRC_MSK_MASK) >> ZLL_…  argument
45006 #define ZLL_BRD_PHY_CTRL_CRC_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CRC_MSK_SH…  argument
45009 #define ZLL_WR_PHY_CTRL_CRC_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CRC_MSK_MASK, ZLL…  argument
45010 #define ZLL_BWR_PHY_CTRL_CRC_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…  argument
45022 #define ZLL_RD_PHY_CTRL_PB_ERR_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PB_ERR_MSK_MASK) >…  argument
45023 #define ZLL_BRD_PHY_CTRL_PB_ERR_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PB_ERR_…  argument
45026 #define ZLL_WR_PHY_CTRL_PB_ERR_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PB_ERR_MSK_MAS…  argument
45027 #define ZLL_BWR_PHY_CTRL_PB_ERR_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…  argument
45039 #define ZLL_RD_PHY_CTRL_TMR1CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK) >…  argument
45040 #define ZLL_BRD_PHY_CTRL_TMR1CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR1CMP…  argument
45043 #define ZLL_WR_PHY_CTRL_TMR1CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR1CMP_EN_MAS…  argument
45044 #define ZLL_BWR_PHY_CTRL_TMR1CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…  argument
45056 #define ZLL_RD_PHY_CTRL_TMR2CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK) >…  argument
45057 #define ZLL_BRD_PHY_CTRL_TMR2CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR2CMP…  argument
45060 #define ZLL_WR_PHY_CTRL_TMR2CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR2CMP_EN_MAS…  argument
45061 #define ZLL_BWR_PHY_CTRL_TMR2CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…  argument
45073 #define ZLL_RD_PHY_CTRL_TMR3CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK) >…  argument
45074 #define ZLL_BRD_PHY_CTRL_TMR3CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR3CMP…  argument
45077 #define ZLL_WR_PHY_CTRL_TMR3CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR3CMP_EN_MAS…  argument
45078 #define ZLL_BWR_PHY_CTRL_TMR3CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…  argument
45090 #define ZLL_RD_PHY_CTRL_TMR4CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK) >…  argument
45091 #define ZLL_BRD_PHY_CTRL_TMR4CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR4CMP…  argument
45094 #define ZLL_WR_PHY_CTRL_TMR4CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR4CMP_EN_MAS…  argument
45095 #define ZLL_BWR_PHY_CTRL_TMR4CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(va…  argument
45109 #define ZLL_RD_PHY_CTRL_TC2PRIME_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK)…  argument
45110 #define ZLL_BRD_PHY_CTRL_TC2PRIME_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC2PRI…  argument
45113 #define ZLL_WR_PHY_CTRL_TC2PRIME_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TC2PRIME_EN_M…  argument
45114 #define ZLL_BWR_PHY_CTRL_TC2PRIME_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…  argument
45129 #define ZLL_RD_PHY_CTRL_PROMISCUOUS(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PROMISCUOUS_MASK)…  argument
45130 #define ZLL_BRD_PHY_CTRL_PROMISCUOUS(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PROMIS…  argument
45133 #define ZLL_WR_PHY_CTRL_PROMISCUOUS(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PROMISCUOUS_M…  argument
45134 #define ZLL_BWR_PHY_CTRL_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…  argument
45147 #define ZLL_WR_PHY_CTRL_TMRLOAD(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMRLOAD_MASK, ZLL…  argument
45148 #define ZLL_BWR_PHY_CTRL_TMRLOAD(base, value) (ZLL_WR_PHY_CTRL_TMRLOAD(base, value))  argument
45163 #define ZLL_RD_PHY_CTRL_CCATYPE(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_…  argument
45164 #define ZLL_BRD_PHY_CTRL_CCATYPE(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCATYPE_SH…  argument
45167 #define ZLL_WR_PHY_CTRL_CCATYPE(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCATYPE_MASK, ZLL…  argument
45168 #define ZLL_BWR_PHY_CTRL_CCATYPE(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value…  argument
45179 #define ZLL_RD_PHY_CTRL_PANCORDNTR0(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PANCORDNTR0_MASK)…  argument
45180 #define ZLL_BRD_PHY_CTRL_PANCORDNTR0(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PANCOR…  argument
45183 #define ZLL_WR_PHY_CTRL_PANCORDNTR0(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PANCORDNTR0_M…  argument
45184 #define ZLL_BWR_PHY_CTRL_PANCORDNTR0(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(v…  argument
45198 #define ZLL_RD_PHY_CTRL_TC3TMOUT(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TC3TMOUT_MASK) >> ZL…  argument
45199 #define ZLL_BRD_PHY_CTRL_TC3TMOUT(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC3TMOUT_…  argument
45202 #define ZLL_WR_PHY_CTRL_TC3TMOUT(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TC3TMOUT_MASK, Z…  argument
45203 #define ZLL_BWR_PHY_CTRL_TC3TMOUT(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…  argument
45217 #define ZLL_RD_PHY_CTRL_TRCV_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TRCV_MSK_MASK) >> ZL…  argument
45218 #define ZLL_BRD_PHY_CTRL_TRCV_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TRCV_MSK_…  argument
45221 #define ZLL_WR_PHY_CTRL_TRCV_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TRCV_MSK_MASK, Z…  argument
45222 #define ZLL_BWR_PHY_CTRL_TRCV_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(valu…  argument
45241 #define ZLL_RD_EVENT_TMR(base)   (ZLL_EVENT_TMR_REG(base))  argument
45253 #define ZLL_RD_EVENT_TMR_EVENT_TMR(base) ((ZLL_EVENT_TMR_REG(base) & ZLL_EVENT_TMR_EVENT_TMR_MASK) …  argument
45254 #define ZLL_BRD_EVENT_TMR_EVENT_TMR(base) (ZLL_RD_EVENT_TMR_EVENT_TMR(base))  argument
45273 #define ZLL_RD_TIMESTAMP(base)   (ZLL_TIMESTAMP_REG(base))  argument
45285 #define ZLL_RD_TIMESTAMP_TIMESTAMP(base) ((ZLL_TIMESTAMP_REG(base) & ZLL_TIMESTAMP_TIMESTAMP_MASK) …  argument
45286 #define ZLL_BRD_TIMESTAMP_TIMESTAMP(base) (ZLL_RD_TIMESTAMP_TIMESTAMP(base))  argument
45305 #define ZLL_RD_T1CMP(base)       (ZLL_T1CMP_REG(base))  argument
45306 #define ZLL_WR_T1CMP(base, value) (ZLL_T1CMP_REG(base) = (value))  argument
45307 #define ZLL_RMW_T1CMP(base, mask, value) (ZLL_WR_T1CMP(base, (ZLL_RD_T1CMP(base) & ~(mask)) | (valu…  argument
45308 #define ZLL_SET_T1CMP(base, value) (BME_OR32(&ZLL_T1CMP_REG(base), (uint32_t)(value)))  argument
45309 #define ZLL_CLR_T1CMP(base, value) (BME_AND32(&ZLL_T1CMP_REG(base), (uint32_t)(~(value))))  argument
45310 #define ZLL_TOG_T1CMP(base, value) (BME_XOR32(&ZLL_T1CMP_REG(base), (uint32_t)(value)))  argument
45322 #define ZLL_RD_T1CMP_T1CMP(base) ((ZLL_T1CMP_REG(base) & ZLL_T1CMP_T1CMP_MASK) >> ZLL_T1CMP_T1CMP_S…  argument
45323 #define ZLL_BRD_T1CMP_T1CMP(base) (ZLL_RD_T1CMP_T1CMP(base))  argument
45326 #define ZLL_WR_T1CMP_T1CMP(base, value) (ZLL_RMW_T1CMP(base, ZLL_T1CMP_T1CMP_MASK, ZLL_T1CMP_T1CMP(…  argument
45327 #define ZLL_BWR_T1CMP_T1CMP(base, value) (ZLL_WR_T1CMP_T1CMP(base, value))  argument
45346 #define ZLL_RD_T2CMP(base)       (ZLL_T2CMP_REG(base))  argument
45347 #define ZLL_WR_T2CMP(base, value) (ZLL_T2CMP_REG(base) = (value))  argument
45348 #define ZLL_RMW_T2CMP(base, mask, value) (ZLL_WR_T2CMP(base, (ZLL_RD_T2CMP(base) & ~(mask)) | (valu…  argument
45349 #define ZLL_SET_T2CMP(base, value) (BME_OR32(&ZLL_T2CMP_REG(base), (uint32_t)(value)))  argument
45350 #define ZLL_CLR_T2CMP(base, value) (BME_AND32(&ZLL_T2CMP_REG(base), (uint32_t)(~(value))))  argument
45351 #define ZLL_TOG_T2CMP(base, value) (BME_XOR32(&ZLL_T2CMP_REG(base), (uint32_t)(value)))  argument
45363 #define ZLL_RD_T2CMP_T2CMP(base) ((ZLL_T2CMP_REG(base) & ZLL_T2CMP_T2CMP_MASK) >> ZLL_T2CMP_T2CMP_S…  argument
45364 #define ZLL_BRD_T2CMP_T2CMP(base) (ZLL_RD_T2CMP_T2CMP(base))  argument
45367 #define ZLL_WR_T2CMP_T2CMP(base, value) (ZLL_RMW_T2CMP(base, ZLL_T2CMP_T2CMP_MASK, ZLL_T2CMP_T2CMP(…  argument
45368 #define ZLL_BWR_T2CMP_T2CMP(base, value) (ZLL_WR_T2CMP_T2CMP(base, value))  argument
45387 #define ZLL_RD_T2PRIMECMP(base)  (ZLL_T2PRIMECMP_REG(base))  argument
45388 #define ZLL_WR_T2PRIMECMP(base, value) (ZLL_T2PRIMECMP_REG(base) = (value))  argument
45389 #define ZLL_RMW_T2PRIMECMP(base, mask, value) (ZLL_WR_T2PRIMECMP(base, (ZLL_RD_T2PRIMECMP(base) & ~…  argument
45390 #define ZLL_SET_T2PRIMECMP(base, value) (BME_OR32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(value)))  argument
45391 #define ZLL_CLR_T2PRIMECMP(base, value) (BME_AND32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(~(value))))  argument
45392 #define ZLL_TOG_T2PRIMECMP(base, value) (BME_XOR32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(value)))  argument
45404 #define ZLL_RD_T2PRIMECMP_T2PRIMECMP(base) ((ZLL_T2PRIMECMP_REG(base) & ZLL_T2PRIMECMP_T2PRIMECMP_M…  argument
45405 #define ZLL_BRD_T2PRIMECMP_T2PRIMECMP(base) (BME_UBFX32(&ZLL_T2PRIMECMP_REG(base), ZLL_T2PRIMECMP_T…  argument
45408 #define ZLL_WR_T2PRIMECMP_T2PRIMECMP(base, value) (ZLL_RMW_T2PRIMECMP(base, ZLL_T2PRIMECMP_T2PRIMEC…  argument
45409 #define ZLL_BWR_T2PRIMECMP_T2PRIMECMP(base, value) (BME_BFI32(&ZLL_T2PRIMECMP_REG(base), ((uint32_t…  argument
45428 #define ZLL_RD_T3CMP(base)       (ZLL_T3CMP_REG(base))  argument
45429 #define ZLL_WR_T3CMP(base, value) (ZLL_T3CMP_REG(base) = (value))  argument
45430 #define ZLL_RMW_T3CMP(base, mask, value) (ZLL_WR_T3CMP(base, (ZLL_RD_T3CMP(base) & ~(mask)) | (valu…  argument
45431 #define ZLL_SET_T3CMP(base, value) (BME_OR32(&ZLL_T3CMP_REG(base), (uint32_t)(value)))  argument
45432 #define ZLL_CLR_T3CMP(base, value) (BME_AND32(&ZLL_T3CMP_REG(base), (uint32_t)(~(value))))  argument
45433 #define ZLL_TOG_T3CMP(base, value) (BME_XOR32(&ZLL_T3CMP_REG(base), (uint32_t)(value)))  argument
45445 #define ZLL_RD_T3CMP_T3CMP(base) ((ZLL_T3CMP_REG(base) & ZLL_T3CMP_T3CMP_MASK) >> ZLL_T3CMP_T3CMP_S…  argument
45446 #define ZLL_BRD_T3CMP_T3CMP(base) (ZLL_RD_T3CMP_T3CMP(base))  argument
45449 #define ZLL_WR_T3CMP_T3CMP(base, value) (ZLL_RMW_T3CMP(base, ZLL_T3CMP_T3CMP_MASK, ZLL_T3CMP_T3CMP(…  argument
45450 #define ZLL_BWR_T3CMP_T3CMP(base, value) (ZLL_WR_T3CMP_T3CMP(base, value))  argument
45469 #define ZLL_RD_T4CMP(base)       (ZLL_T4CMP_REG(base))  argument
45470 #define ZLL_WR_T4CMP(base, value) (ZLL_T4CMP_REG(base) = (value))  argument
45471 #define ZLL_RMW_T4CMP(base, mask, value) (ZLL_WR_T4CMP(base, (ZLL_RD_T4CMP(base) & ~(mask)) | (valu…  argument
45472 #define ZLL_SET_T4CMP(base, value) (BME_OR32(&ZLL_T4CMP_REG(base), (uint32_t)(value)))  argument
45473 #define ZLL_CLR_T4CMP(base, value) (BME_AND32(&ZLL_T4CMP_REG(base), (uint32_t)(~(value))))  argument
45474 #define ZLL_TOG_T4CMP(base, value) (BME_XOR32(&ZLL_T4CMP_REG(base), (uint32_t)(value)))  argument
45486 #define ZLL_RD_T4CMP_T4CMP(base) ((ZLL_T4CMP_REG(base) & ZLL_T4CMP_T4CMP_MASK) >> ZLL_T4CMP_T4CMP_S…  argument
45487 #define ZLL_BRD_T4CMP_T4CMP(base) (ZLL_RD_T4CMP_T4CMP(base))  argument
45490 #define ZLL_WR_T4CMP_T4CMP(base, value) (ZLL_RMW_T4CMP(base, ZLL_T4CMP_T4CMP_MASK, ZLL_T4CMP_T4CMP(…  argument
45491 #define ZLL_BWR_T4CMP_T4CMP(base, value) (ZLL_WR_T4CMP_T4CMP(base, value))  argument
45509 #define ZLL_RD_PA_PWR(base)      (ZLL_PA_PWR_REG(base))  argument
45510 #define ZLL_WR_PA_PWR(base, value) (ZLL_PA_PWR_REG(base) = (value))  argument
45511 #define ZLL_RMW_PA_PWR(base, mask, value) (ZLL_WR_PA_PWR(base, (ZLL_RD_PA_PWR(base) & ~(mask)) | (v…  argument
45512 #define ZLL_SET_PA_PWR(base, value) (BME_OR32(&ZLL_PA_PWR_REG(base), (uint32_t)(value)))  argument
45513 #define ZLL_CLR_PA_PWR(base, value) (BME_AND32(&ZLL_PA_PWR_REG(base), (uint32_t)(~(value))))  argument
45514 #define ZLL_TOG_PA_PWR(base, value) (BME_XOR32(&ZLL_PA_PWR_REG(base), (uint32_t)(value)))  argument
45526 #define ZLL_RD_PA_PWR_PA_PWR(base) ((ZLL_PA_PWR_REG(base) & ZLL_PA_PWR_PA_PWR_MASK) >> ZLL_PA_PWR_P…  argument
45527 #define ZLL_BRD_PA_PWR_PA_PWR(base) (BME_UBFX32(&ZLL_PA_PWR_REG(base), ZLL_PA_PWR_PA_PWR_SHIFT, ZLL…  argument
45530 #define ZLL_WR_PA_PWR_PA_PWR(base, value) (ZLL_RMW_PA_PWR(base, ZLL_PA_PWR_PA_PWR_MASK, ZLL_PA_PWR_…  argument
45531 #define ZLL_BWR_PA_PWR_PA_PWR(base, value) (BME_BFI32(&ZLL_PA_PWR_REG(base), ((uint32_t)(value) << …  argument
45551 #define ZLL_RD_CHANNEL_NUM0(base) (ZLL_CHANNEL_NUM0_REG(base))  argument
45552 #define ZLL_WR_CHANNEL_NUM0(base, value) (ZLL_CHANNEL_NUM0_REG(base) = (value))  argument
45553 #define ZLL_RMW_CHANNEL_NUM0(base, mask, value) (ZLL_WR_CHANNEL_NUM0(base, (ZLL_RD_CHANNEL_NUM0(bas…  argument
45554 #define ZLL_SET_CHANNEL_NUM0(base, value) (BME_OR32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(value)))  argument
45555 #define ZLL_CLR_CHANNEL_NUM0(base, value) (BME_AND32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(~(valu…  argument
45556 #define ZLL_TOG_CHANNEL_NUM0(base, value) (BME_XOR32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(value)…  argument
45568 #define ZLL_RD_CHANNEL_NUM0_CHANNEL_NUM0(base) ((ZLL_CHANNEL_NUM0_REG(base) & ZLL_CHANNEL_NUM0_CHAN…  argument
45569 #define ZLL_BRD_CHANNEL_NUM0_CHANNEL_NUM0(base) (BME_UBFX32(&ZLL_CHANNEL_NUM0_REG(base), ZLL_CHANNE…  argument
45572 #define ZLL_WR_CHANNEL_NUM0_CHANNEL_NUM0(base, value) (ZLL_RMW_CHANNEL_NUM0(base, ZLL_CHANNEL_NUM0_…  argument
45573 #define ZLL_BWR_CHANNEL_NUM0_CHANNEL_NUM0(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM0_REG(base), ((ui…  argument
45589 #define ZLL_RD_LQI_AND_RSSI(base) (ZLL_LQI_AND_RSSI_REG(base))  argument
45604 #define ZLL_RD_LQI_AND_RSSI_LQI_VALUE(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_LQI_VAL…  argument
45605 #define ZLL_BRD_LQI_AND_RSSI_LQI_VALUE(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_R…  argument
45615 #define ZLL_RD_LQI_AND_RSSI_RSSI(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_RSSI_MASK) >…  argument
45616 #define ZLL_BRD_LQI_AND_RSSI_RSSI(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_RSSI_R…  argument
45627 #define ZLL_RD_LQI_AND_RSSI_CCA1_ED_FNL(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_CCA1_…  argument
45628 #define ZLL_BRD_LQI_AND_RSSI_CCA1_ED_FNL(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND…  argument
45644 #define ZLL_RD_MACSHORTADDRS0(base) (ZLL_MACSHORTADDRS0_REG(base))  argument
45645 #define ZLL_WR_MACSHORTADDRS0(base, value) (ZLL_MACSHORTADDRS0_REG(base) = (value))  argument
45646 #define ZLL_RMW_MACSHORTADDRS0(base, mask, value) (ZLL_WR_MACSHORTADDRS0(base, (ZLL_RD_MACSHORTADDR…  argument
45647 #define ZLL_SET_MACSHORTADDRS0(base, value) (BME_OR32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(val…  argument
45648 #define ZLL_CLR_MACSHORTADDRS0(base, value) (BME_AND32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(~(…  argument
45649 #define ZLL_TOG_MACSHORTADDRS0(base, value) (BME_XOR32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(va…  argument
45669 #define ZLL_RD_MACSHORTADDRS0_MACPANID0(base) ((ZLL_MACSHORTADDRS0_REG(base) & ZLL_MACSHORTADDRS0_M…  argument
45670 #define ZLL_BRD_MACSHORTADDRS0_MACPANID0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_MACSH…  argument
45673 #define ZLL_WR_MACSHORTADDRS0_MACPANID0(base, value) (ZLL_RMW_MACSHORTADDRS0(base, ZLL_MACSHORTADDR…  argument
45674 #define ZLL_BWR_MACSHORTADDRS0_MACPANID0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base), ((u…  argument
45686 #define ZLL_RD_MACSHORTADDRS0_MACSHORTADDRS0(base) ((ZLL_MACSHORTADDRS0_REG(base) & ZLL_MACSHORTADD…  argument
45687 #define ZLL_BRD_MACSHORTADDRS0_MACSHORTADDRS0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_…  argument
45690 #define ZLL_WR_MACSHORTADDRS0_MACSHORTADDRS0(base, value) (ZLL_RMW_MACSHORTADDRS0(base, ZLL_MACSHOR…  argument
45691 #define ZLL_BWR_MACSHORTADDRS0_MACSHORTADDRS0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base)…  argument
45711 #define ZLL_RD_MACLONGADDRS0_LSB(base) (ZLL_MACLONGADDRS0_LSB_REG(base))  argument
45712 #define ZLL_WR_MACLONGADDRS0_LSB(base, value) (ZLL_MACLONGADDRS0_LSB_REG(base) = (value))  argument
45713 #define ZLL_RMW_MACLONGADDRS0_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_LSB(base, (ZLL_RD_MACLON…  argument
45714 #define ZLL_SET_MACLONGADDRS0_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32_…  argument
45715 #define ZLL_CLR_MACLONGADDRS0_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32…  argument
45716 #define ZLL_TOG_MACLONGADDRS0_LSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32…  argument
45736 #define ZLL_RD_MACLONGADDRS0_MSB(base) (ZLL_MACLONGADDRS0_MSB_REG(base))  argument
45737 #define ZLL_WR_MACLONGADDRS0_MSB(base, value) (ZLL_MACLONGADDRS0_MSB_REG(base) = (value))  argument
45738 #define ZLL_RMW_MACLONGADDRS0_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_MSB(base, (ZLL_RD_MACLON…  argument
45739 #define ZLL_SET_MACLONGADDRS0_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32_…  argument
45740 #define ZLL_CLR_MACLONGADDRS0_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32…  argument
45741 #define ZLL_TOG_MACLONGADDRS0_MSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32…  argument
45757 #define ZLL_RD_RX_FRAME_FILTER(base) (ZLL_RX_FRAME_FILTER_REG(base))  argument
45758 #define ZLL_WR_RX_FRAME_FILTER(base, value) (ZLL_RX_FRAME_FILTER_REG(base) = (value))  argument
45759 #define ZLL_RMW_RX_FRAME_FILTER(base, mask, value) (ZLL_WR_RX_FRAME_FILTER(base, (ZLL_RD_RX_FRAME_F…  argument
45760 #define ZLL_SET_RX_FRAME_FILTER(base, value) (BME_OR32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(v…  argument
45761 #define ZLL_CLR_RX_FRAME_FILTER(base, value) (BME_AND32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(…  argument
45762 #define ZLL_TOG_RX_FRAME_FILTER(base, value) (BME_XOR32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(…  argument
45778 #define ZLL_RD_RX_FRAME_FILTER_BEACON_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTE…  argument
45779 #define ZLL_BRD_RX_FRAME_FILTER_BEACON_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_…  argument
45782 #define ZLL_WR_RX_FRAME_FILTER_BEACON_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_F…  argument
45783 #define ZLL_BWR_RX_FRAME_FILTER_BEACON_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), (…  argument
45795 #define ZLL_RD_RX_FRAME_FILTER_DATA_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_…  argument
45796 #define ZLL_BRD_RX_FRAME_FILTER_DATA_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FR…  argument
45799 #define ZLL_WR_RX_FRAME_FILTER_DATA_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FIL…  argument
45800 #define ZLL_BWR_RX_FRAME_FILTER_DATA_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((u…  argument
45812 #define ZLL_RD_RX_FRAME_FILTER_ACK_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_A…  argument
45813 #define ZLL_BRD_RX_FRAME_FILTER_ACK_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRA…  argument
45816 #define ZLL_WR_RX_FRAME_FILTER_ACK_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILT…  argument
45817 #define ZLL_BWR_RX_FRAME_FILTER_ACK_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((ui…  argument
45829 #define ZLL_RD_RX_FRAME_FILTER_CMD_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_C…  argument
45830 #define ZLL_BRD_RX_FRAME_FILTER_CMD_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRA…  argument
45833 #define ZLL_WR_RX_FRAME_FILTER_CMD_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILT…  argument
45834 #define ZLL_BWR_RX_FRAME_FILTER_CMD_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((ui…  argument
45848 #define ZLL_RD_RX_FRAME_FILTER_NS_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_NS…  argument
45849 #define ZLL_BRD_RX_FRAME_FILTER_NS_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAM…  argument
45852 #define ZLL_WR_RX_FRAME_FILTER_NS_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTE…  argument
45853 #define ZLL_BWR_RX_FRAME_FILTER_NS_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uin…  argument
45867 #define ZLL_RD_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FR…  argument
45868 #define ZLL_BRD_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base)…  argument
45871 #define ZLL_WR_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_R…  argument
45872 #define ZLL_BWR_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG…  argument
45890 #define ZLL_RD_RX_FRAME_FILTER_FRM_VER(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_…  argument
45891 #define ZLL_BRD_RX_FRAME_FILTER_FRM_VER(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FR…  argument
45894 #define ZLL_WR_RX_FRAME_FILTER_FRM_VER(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FIL…  argument
45895 #define ZLL_BWR_RX_FRAME_FILTER_FRM_VER(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((u…  argument
45911 #define ZLL_RD_CCA_LQI_CTRL(base) (ZLL_CCA_LQI_CTRL_REG(base))  argument
45912 #define ZLL_WR_CCA_LQI_CTRL(base, value) (ZLL_CCA_LQI_CTRL_REG(base) = (value))  argument
45913 #define ZLL_RMW_CCA_LQI_CTRL(base, mask, value) (ZLL_WR_CCA_LQI_CTRL(base, (ZLL_RD_CCA_LQI_CTRL(bas…  argument
45914 #define ZLL_SET_CCA_LQI_CTRL(base, value) (BME_OR32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(value)))  argument
45915 #define ZLL_CLR_CCA_LQI_CTRL(base, value) (BME_AND32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(~(valu…  argument
45916 #define ZLL_TOG_CCA_LQI_CTRL(base, value) (BME_XOR32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(value)…  argument
45930 #define ZLL_RD_CCA_LQI_CTRL_CCA1_THRESH(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_CCA1_…  argument
45931 #define ZLL_BRD_CCA_LQI_CTRL_CCA1_THRESH(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA_LQI…  argument
45934 #define ZLL_WR_CCA_LQI_CTRL_CCA1_THRESH(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CTRL_C…  argument
45935 #define ZLL_BWR_CCA_LQI_CTRL_CCA1_THRESH(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), ((uin…  argument
45945 #define ZLL_RD_CCA_LQI_CTRL_LQI_OFFSET_COMP(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_L…  argument
45946 #define ZLL_BRD_CCA_LQI_CTRL_LQI_OFFSET_COMP(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA…  argument
45949 #define ZLL_WR_CCA_LQI_CTRL_LQI_OFFSET_COMP(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CT…  argument
45950 #define ZLL_BWR_CCA_LQI_CTRL_LQI_OFFSET_COMP(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), (…  argument
45964 #define ZLL_RD_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_C…  argument
45965 #define ZLL_BRD_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA…  argument
45968 #define ZLL_WR_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CT…  argument
45969 #define ZLL_BWR_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), (…  argument
45987 #define ZLL_RD_CCA2_CTRL(base)   (ZLL_CCA2_CTRL_REG(base))  argument
45988 #define ZLL_WR_CCA2_CTRL(base, value) (ZLL_CCA2_CTRL_REG(base) = (value))  argument
45989 #define ZLL_RMW_CCA2_CTRL(base, mask, value) (ZLL_WR_CCA2_CTRL(base, (ZLL_RD_CCA2_CTRL(base) & ~(ma…  argument
45990 #define ZLL_SET_CCA2_CTRL(base, value) (BME_OR32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(value)))  argument
45991 #define ZLL_CLR_CCA2_CTRL(base, value) (BME_AND32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(~(value))))  argument
45992 #define ZLL_TOG_CCA2_CTRL(base, value) (BME_XOR32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(value)))  argument
46007 #define ZLL_RD_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_N…  argument
46008 #define ZLL_BRD_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_…  argument
46022 #define ZLL_RD_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_…  argument
46023 #define ZLL_BRD_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2…  argument
46026 #define ZLL_WR_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base, value) (ZLL_RMW_CCA2_CTRL(base, ZLL_CCA2_CTRL_C…  argument
46027 #define ZLL_BWR_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((…  argument
46041 #define ZLL_RD_CCA2_CTRL_CCA2_CORR_THRESH(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_CORR…  argument
46042 #define ZLL_BRD_CCA2_CTRL_CCA2_CORR_THRESH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_CTR…  argument
46045 #define ZLL_WR_CCA2_CTRL_CCA2_CORR_THRESH(base, value) (ZLL_RMW_CCA2_CTRL(base, ZLL_CCA2_CTRL_CCA2_…  argument
46046 #define ZLL_BWR_CCA2_CTRL_CCA2_CORR_THRESH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((uint…  argument
46064 #define ZLL_RD_FAD_CTRL(base)    (ZLL_FAD_CTRL_REG(base))  argument
46065 #define ZLL_WR_FAD_CTRL(base, value) (ZLL_FAD_CTRL_REG(base) = (value))  argument
46066 #define ZLL_RMW_FAD_CTRL(base, mask, value) (ZLL_WR_FAD_CTRL(base, (ZLL_RD_FAD_CTRL(base) & ~(mask)…  argument
46067 #define ZLL_SET_FAD_CTRL(base, value) (BME_OR32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(value)))  argument
46068 #define ZLL_CLR_FAD_CTRL(base, value) (BME_AND32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(~(value))))  argument
46069 #define ZLL_TOG_FAD_CTRL(base, value) (BME_XOR32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(value)))  argument
46083 #define ZLL_RD_FAD_CTRL_FAD_EN(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_FAD_EN_MASK) >> ZLL_FA…  argument
46084 #define ZLL_BRD_FAD_CTRL_FAD_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_EN_SHIF…  argument
46087 #define ZLL_WR_FAD_CTRL_FAD_EN(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_FAD_EN_MASK, ZLL_F…  argument
46088 #define ZLL_BWR_FAD_CTRL_FAD_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value)…  argument
46102 #define ZLL_RD_FAD_CTRL_ANTX(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_MASK) >> ZLL_FAD_CT…  argument
46103 #define ZLL_BRD_FAD_CTRL_ANTX(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_SHIFT, Z…  argument
46106 #define ZLL_WR_FAD_CTRL_ANTX(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_MASK, ZLL_FAD_C…  argument
46107 #define ZLL_BWR_FAD_CTRL_ANTX(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) <…  argument
46124 #define ZLL_RD_FAD_CTRL_FAD_NOT_GPIO(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_FAD_NOT_GPIO_MAS…  argument
46125 #define ZLL_BRD_FAD_CTRL_FAD_NOT_GPIO(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_N…  argument
46128 #define ZLL_WR_FAD_CTRL_FAD_NOT_GPIO(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_FAD_NOT_GPIO…  argument
46129 #define ZLL_BWR_FAD_CTRL_FAD_NOT_GPIO(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(…  argument
46146 #define ZLL_RD_FAD_CTRL_ANTX_EN(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_EN_MASK) >> ZLL_…  argument
46147 #define ZLL_BRD_FAD_CTRL_ANTX_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_EN_SH…  argument
46150 #define ZLL_WR_FAD_CTRL_ANTX_EN(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_EN_MASK, ZLL…  argument
46151 #define ZLL_BWR_FAD_CTRL_ANTX_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value…  argument
46164 #define ZLL_RD_FAD_CTRL_ANTX_HZ(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_HZ_MASK) >> ZLL_…  argument
46165 #define ZLL_BRD_FAD_CTRL_ANTX_HZ(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_HZ_SH…  argument
46168 #define ZLL_WR_FAD_CTRL_ANTX_HZ(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_HZ_MASK, ZLL…  argument
46169 #define ZLL_BWR_FAD_CTRL_ANTX_HZ(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value…  argument
46187 #define ZLL_RD_FAD_CTRL_ANTX_CTRLMODE(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_CTRLMODE_M…  argument
46188 #define ZLL_BRD_FAD_CTRL_ANTX_CTRLMODE(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX…  argument
46191 #define ZLL_WR_FAD_CTRL_ANTX_CTRLMODE(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_CTRLMO…  argument
46192 #define ZLL_BWR_FAD_CTRL_ANTX_CTRLMODE(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)…  argument
46207 #define ZLL_RD_FAD_CTRL_ANTX_POL(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_POL_MASK) >> ZL…  argument
46208 #define ZLL_BRD_FAD_CTRL_ANTX_POL(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_POL_…  argument
46211 #define ZLL_WR_FAD_CTRL_ANTX_POL(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_POL_MASK, Z…  argument
46212 #define ZLL_BWR_FAD_CTRL_ANTX_POL(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(valu…  argument
46230 #define ZLL_RD_SNF_CTRL(base)    (ZLL_SNF_CTRL_REG(base))  argument
46231 #define ZLL_WR_SNF_CTRL(base, value) (ZLL_SNF_CTRL_REG(base) = (value))  argument
46232 #define ZLL_RMW_SNF_CTRL(base, mask, value) (ZLL_WR_SNF_CTRL(base, (ZLL_RD_SNF_CTRL(base) & ~(mask)…  argument
46233 #define ZLL_SET_SNF_CTRL(base, value) (BME_OR32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(value)))  argument
46234 #define ZLL_CLR_SNF_CTRL(base, value) (BME_AND32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(~(value))))  argument
46235 #define ZLL_TOG_SNF_CTRL(base, value) (BME_XOR32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(value)))  argument
46250 #define ZLL_RD_SNF_CTRL_SNF_EN(base) ((ZLL_SNF_CTRL_REG(base) & ZLL_SNF_CTRL_SNF_EN_MASK) >> ZLL_SN…  argument
46251 #define ZLL_BRD_SNF_CTRL_SNF_EN(base) (BME_UBFX32(&ZLL_SNF_CTRL_REG(base), ZLL_SNF_CTRL_SNF_EN_SHIF…  argument
46254 #define ZLL_WR_SNF_CTRL_SNF_EN(base, value) (ZLL_RMW_SNF_CTRL(base, ZLL_SNF_CTRL_SNF_EN_MASK, ZLL_S…  argument
46255 #define ZLL_BWR_SNF_CTRL_SNF_EN(base, value) (BME_BFI32(&ZLL_SNF_CTRL_REG(base), ((uint32_t)(value)…  argument
46273 #define ZLL_RD_BSM_CTRL(base)    (ZLL_BSM_CTRL_REG(base))  argument
46274 #define ZLL_WR_BSM_CTRL(base, value) (ZLL_BSM_CTRL_REG(base) = (value))  argument
46275 #define ZLL_RMW_BSM_CTRL(base, mask, value) (ZLL_WR_BSM_CTRL(base, (ZLL_RD_BSM_CTRL(base) & ~(mask)…  argument
46276 #define ZLL_SET_BSM_CTRL(base, value) (BME_OR32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(value)))  argument
46277 #define ZLL_CLR_BSM_CTRL(base, value) (BME_AND32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(~(value))))  argument
46278 #define ZLL_TOG_BSM_CTRL(base, value) (BME_XOR32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(value)))  argument
46294 #define ZLL_RD_BSM_CTRL_BSM_EN(base) ((ZLL_BSM_CTRL_REG(base) & ZLL_BSM_CTRL_BSM_EN_MASK) >> ZLL_BS…  argument
46295 #define ZLL_BRD_BSM_CTRL_BSM_EN(base) (BME_UBFX32(&ZLL_BSM_CTRL_REG(base), ZLL_BSM_CTRL_BSM_EN_SHIF…  argument
46298 #define ZLL_WR_BSM_CTRL_BSM_EN(base, value) (ZLL_RMW_BSM_CTRL(base, ZLL_BSM_CTRL_BSM_EN_MASK, ZLL_B…  argument
46299 #define ZLL_BWR_BSM_CTRL_BSM_EN(base, value) (BME_BFI32(&ZLL_BSM_CTRL_REG(base), ((uint32_t)(value)…  argument
46315 #define ZLL_RD_MACSHORTADDRS1(base) (ZLL_MACSHORTADDRS1_REG(base))  argument
46316 #define ZLL_WR_MACSHORTADDRS1(base, value) (ZLL_MACSHORTADDRS1_REG(base) = (value))  argument
46317 #define ZLL_RMW_MACSHORTADDRS1(base, mask, value) (ZLL_WR_MACSHORTADDRS1(base, (ZLL_RD_MACSHORTADDR…  argument
46318 #define ZLL_SET_MACSHORTADDRS1(base, value) (BME_OR32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(val…  argument
46319 #define ZLL_CLR_MACSHORTADDRS1(base, value) (BME_AND32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(~(…  argument
46320 #define ZLL_TOG_MACSHORTADDRS1(base, value) (BME_XOR32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(va…  argument
46340 #define ZLL_RD_MACSHORTADDRS1_MACPANID1(base) ((ZLL_MACSHORTADDRS1_REG(base) & ZLL_MACSHORTADDRS1_M…  argument
46341 #define ZLL_BRD_MACSHORTADDRS1_MACPANID1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_MACSH…  argument
46344 #define ZLL_WR_MACSHORTADDRS1_MACPANID1(base, value) (ZLL_RMW_MACSHORTADDRS1(base, ZLL_MACSHORTADDR…  argument
46345 #define ZLL_BWR_MACSHORTADDRS1_MACPANID1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base), ((u…  argument
46357 #define ZLL_RD_MACSHORTADDRS1_MACSHORTADDRS1(base) ((ZLL_MACSHORTADDRS1_REG(base) & ZLL_MACSHORTADD…  argument
46358 #define ZLL_BRD_MACSHORTADDRS1_MACSHORTADDRS1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_…  argument
46361 #define ZLL_WR_MACSHORTADDRS1_MACSHORTADDRS1(base, value) (ZLL_RMW_MACSHORTADDRS1(base, ZLL_MACSHOR…  argument
46362 #define ZLL_BWR_MACSHORTADDRS1_MACSHORTADDRS1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base)…  argument
46382 #define ZLL_RD_MACLONGADDRS1_LSB(base) (ZLL_MACLONGADDRS1_LSB_REG(base))  argument
46383 #define ZLL_WR_MACLONGADDRS1_LSB(base, value) (ZLL_MACLONGADDRS1_LSB_REG(base) = (value))  argument
46384 #define ZLL_RMW_MACLONGADDRS1_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_LSB(base, (ZLL_RD_MACLON…  argument
46385 #define ZLL_SET_MACLONGADDRS1_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32_…  argument
46386 #define ZLL_CLR_MACLONGADDRS1_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32…  argument
46387 #define ZLL_TOG_MACLONGADDRS1_LSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32…  argument
46407 #define ZLL_RD_MACLONGADDRS1_MSB(base) (ZLL_MACLONGADDRS1_MSB_REG(base))  argument
46408 #define ZLL_WR_MACLONGADDRS1_MSB(base, value) (ZLL_MACLONGADDRS1_MSB_REG(base) = (value))  argument
46409 #define ZLL_RMW_MACLONGADDRS1_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_MSB(base, (ZLL_RD_MACLON…  argument
46410 #define ZLL_SET_MACLONGADDRS1_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32_…  argument
46411 #define ZLL_CLR_MACLONGADDRS1_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32…  argument
46412 #define ZLL_TOG_MACLONGADDRS1_MSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32…  argument
46428 #define ZLL_RD_DUAL_PAN_CTRL(base) (ZLL_DUAL_PAN_CTRL_REG(base))  argument
46429 #define ZLL_WR_DUAL_PAN_CTRL(base, value) (ZLL_DUAL_PAN_CTRL_REG(base) = (value))  argument
46430 #define ZLL_RMW_DUAL_PAN_CTRL(base, mask, value) (ZLL_WR_DUAL_PAN_CTRL(base, (ZLL_RD_DUAL_PAN_CTRL(…  argument
46431 #define ZLL_SET_DUAL_PAN_CTRL(base, value) (BME_OR32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(value…  argument
46432 #define ZLL_CLR_DUAL_PAN_CTRL(base, value) (BME_AND32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(~(va…  argument
46433 #define ZLL_TOG_DUAL_PAN_CTRL(base, value) (BME_XOR32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(valu…  argument
46456 #define ZLL_RD_DUAL_PAN_CTRL_ACTIVE_NETWORK(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL…  argument
46457 #define ZLL_BRD_DUAL_PAN_CTRL_ACTIVE_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DU…  argument
46460 #define ZLL_WR_DUAL_PAN_CTRL_ACTIVE_NETWORK(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_…  argument
46461 #define ZLL_BWR_DUAL_PAN_CTRL_ACTIVE_NETWORK(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), …  argument
46476 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_…  argument
46477 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUA…  argument
46480 #define ZLL_WR_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_C…  argument
46481 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), (…  argument
46492 #define ZLL_RD_DUAL_PAN_CTRL_PANCORDNTR1(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_PA…  argument
46493 #define ZLL_BRD_DUAL_PAN_CTRL_PANCORDNTR1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_…  argument
46496 #define ZLL_WR_DUAL_PAN_CTRL_PANCORDNTR1(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTR…  argument
46497 #define ZLL_BWR_DUAL_PAN_CTRL_PANCORDNTR1(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((u…  argument
46512 #define ZLL_RD_DUAL_PAN_CTRL_CURRENT_NETWORK(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTR…  argument
46513 #define ZLL_BRD_DUAL_PAN_CTRL_CURRENT_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_D…  argument
46540 #define ZLL_RD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_…  argument
46541 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZL…  argument
46544 #define ZLL_WR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_…  argument
46545 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(bas…  argument
46557 #define ZLL_RD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN…  argument
46558 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), Z…  argument
46561 #define ZLL_WR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL…  argument
46562 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(ba…  argument
46586 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL…  argument
46587 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DU…  argument
46590 #define ZLL_WR_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_…  argument
46591 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), …  argument
46608 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTR…  argument
46609 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_D…  argument
46625 #define ZLL_RD_DUAL_PAN_CTRL_RECD_ON_PAN0(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_R…  argument
46626 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN0(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL…  argument
46642 #define ZLL_RD_DUAL_PAN_CTRL_RECD_ON_PAN1(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_R…  argument
46643 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL…  argument
46664 #define ZLL_RD_CHANNEL_NUM1(base) (ZLL_CHANNEL_NUM1_REG(base))  argument
46665 #define ZLL_WR_CHANNEL_NUM1(base, value) (ZLL_CHANNEL_NUM1_REG(base) = (value))  argument
46666 #define ZLL_RMW_CHANNEL_NUM1(base, mask, value) (ZLL_WR_CHANNEL_NUM1(base, (ZLL_RD_CHANNEL_NUM1(bas…  argument
46667 #define ZLL_SET_CHANNEL_NUM1(base, value) (BME_OR32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(value)))  argument
46668 #define ZLL_CLR_CHANNEL_NUM1(base, value) (BME_AND32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(~(valu…  argument
46669 #define ZLL_TOG_CHANNEL_NUM1(base, value) (BME_XOR32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(value)…  argument
46681 #define ZLL_RD_CHANNEL_NUM1_CHANNEL_NUM1(base) ((ZLL_CHANNEL_NUM1_REG(base) & ZLL_CHANNEL_NUM1_CHAN…  argument
46682 #define ZLL_BRD_CHANNEL_NUM1_CHANNEL_NUM1(base) (BME_UBFX32(&ZLL_CHANNEL_NUM1_REG(base), ZLL_CHANNE…  argument
46685 #define ZLL_WR_CHANNEL_NUM1_CHANNEL_NUM1(base, value) (ZLL_RMW_CHANNEL_NUM1(base, ZLL_CHANNEL_NUM1_…  argument
46686 #define ZLL_BWR_CHANNEL_NUM1_CHANNEL_NUM1(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM1_REG(base), ((ui…  argument
46704 #define ZLL_RD_SAM_CTRL(base)    (ZLL_SAM_CTRL_REG(base))  argument
46705 #define ZLL_WR_SAM_CTRL(base, value) (ZLL_SAM_CTRL_REG(base) = (value))  argument
46706 #define ZLL_RMW_SAM_CTRL(base, mask, value) (ZLL_WR_SAM_CTRL(base, (ZLL_RD_SAM_CTRL(base) & ~(mask)…  argument
46707 #define ZLL_SET_SAM_CTRL(base, value) (BME_OR32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(value)))  argument
46708 #define ZLL_CLR_SAM_CTRL(base, value) (BME_AND32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(~(value))))  argument
46709 #define ZLL_TOG_SAM_CTRL(base, value) (BME_XOR32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(value)))  argument
46725 #define ZLL_RD_SAM_CTRL_SAP0_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP0_EN_MASK) >> ZLL_…  argument
46726 #define ZLL_BRD_SAM_CTRL_SAP0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP0_EN_SH…  argument
46729 #define ZLL_WR_SAM_CTRL_SAP0_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP0_EN_MASK, ZLL…  argument
46730 #define ZLL_BWR_SAM_CTRL_SAP0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…  argument
46742 #define ZLL_RD_SAM_CTRL_SAA0_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA0_EN_MASK) >> ZLL_…  argument
46743 #define ZLL_BRD_SAM_CTRL_SAA0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_EN_SH…  argument
46746 #define ZLL_WR_SAM_CTRL_SAA0_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA0_EN_MASK, ZLL…  argument
46747 #define ZLL_BWR_SAM_CTRL_SAA0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…  argument
46759 #define ZLL_RD_SAM_CTRL_SAP1_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP1_EN_MASK) >> ZLL_…  argument
46760 #define ZLL_BRD_SAM_CTRL_SAP1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_EN_SH…  argument
46763 #define ZLL_WR_SAM_CTRL_SAP1_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP1_EN_MASK, ZLL…  argument
46764 #define ZLL_BWR_SAM_CTRL_SAP1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…  argument
46776 #define ZLL_RD_SAM_CTRL_SAA1_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA1_EN_MASK) >> ZLL_…  argument
46777 #define ZLL_BRD_SAM_CTRL_SAA1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_EN_SH…  argument
46780 #define ZLL_WR_SAM_CTRL_SAA1_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA1_EN_MASK, ZLL…  argument
46781 #define ZLL_BWR_SAM_CTRL_SAA1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value…  argument
46789 #define ZLL_RD_SAM_CTRL_SAA0_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA0_START_MASK) >…  argument
46790 #define ZLL_BRD_SAM_CTRL_SAA0_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_ST…  argument
46793 #define ZLL_WR_SAM_CTRL_SAA0_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA0_START_MAS…  argument
46794 #define ZLL_BWR_SAM_CTRL_SAA0_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…  argument
46802 #define ZLL_RD_SAM_CTRL_SAP1_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP1_START_MASK) >…  argument
46803 #define ZLL_BRD_SAM_CTRL_SAP1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_ST…  argument
46806 #define ZLL_WR_SAM_CTRL_SAP1_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP1_START_MAS…  argument
46807 #define ZLL_BWR_SAM_CTRL_SAP1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…  argument
46815 #define ZLL_RD_SAM_CTRL_SAA1_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA1_START_MASK) >…  argument
46816 #define ZLL_BRD_SAM_CTRL_SAA1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_ST…  argument
46819 #define ZLL_WR_SAM_CTRL_SAA1_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA1_START_MAS…  argument
46820 #define ZLL_BWR_SAM_CTRL_SAA1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(va…  argument
46838 #define ZLL_RD_SAM_TABLE(base)   (ZLL_SAM_TABLE_REG(base))  argument
46839 #define ZLL_WR_SAM_TABLE(base, value) (ZLL_SAM_TABLE_REG(base) = (value))  argument
46840 #define ZLL_RMW_SAM_TABLE(base, mask, value) (ZLL_WR_SAM_TABLE(base, (ZLL_RD_SAM_TABLE(base) & ~(ma…  argument
46841 #define ZLL_SET_SAM_TABLE(base, value) (BME_OR32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(value)))  argument
46842 #define ZLL_CLR_SAM_TABLE(base, value) (BME_AND32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(~(value))))  argument
46843 #define ZLL_TOG_SAM_TABLE(base, value) (BME_XOR32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(value)))  argument
46858 #define ZLL_RD_SAM_TABLE_SAM_INDEX(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_INDEX_MASK) …  argument
46859 #define ZLL_BRD_SAM_TABLE_SAM_INDEX(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_I…  argument
46862 #define ZLL_WR_SAM_TABLE_SAM_INDEX(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX_MA…  argument
46863 #define ZLL_BWR_SAM_TABLE_SAM_INDEX(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(v…  argument
46876 #define ZLL_WR_SAM_TABLE_SAM_INDEX_WR(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX…  argument
46877 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_WR(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_WR(base, value))  argument
46895 #define ZLL_RD_SAM_TABLE_SAM_CHECKSUM(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_CHECKSUM_…  argument
46896 #define ZLL_BRD_SAM_TABLE_SAM_CHECKSUM(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SA…  argument
46899 #define ZLL_WR_SAM_TABLE_SAM_CHECKSUM(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_CHECK…  argument
46900 #define ZLL_BWR_SAM_TABLE_SAM_CHECKSUM(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t…  argument
46908 #define ZLL_WR_SAM_TABLE_SAM_INDEX_INV(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDE…  argument
46909 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_INV(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_INV(base, value))  argument
46917 #define ZLL_WR_SAM_TABLE_SAM_INDEX_EN(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX…  argument
46918 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_EN(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_EN(base, value))  argument
46933 #define ZLL_RD_SAM_TABLE_ACK_FRM_PND(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_ACK_FRM_PND_MA…  argument
46934 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_ACK…  argument
46937 #define ZLL_WR_SAM_TABLE_ACK_FRM_PND(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_ACK_FRM_PN…  argument
46938 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)…  argument
46952 #define ZLL_RD_SAM_TABLE_ACK_FRM_PND_CTRL(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_ACK_FRM_P…  argument
46953 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND_CTRL(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABL…  argument
46956 #define ZLL_WR_SAM_TABLE_ACK_FRM_PND_CTRL(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_ACK_F…  argument
46957 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND_CTRL(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint…  argument
46971 #define ZLL_WR_SAM_TABLE_FIND_FREE_IDX(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_FIND_FRE…  argument
46972 #define ZLL_BWR_SAM_TABLE_FIND_FREE_IDX(base, value) (ZLL_WR_SAM_TABLE_FIND_FREE_IDX(base, value))  argument
46984 #define ZLL_WR_SAM_TABLE_INVALIDATE_ALL(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_INVALID…  argument
46985 #define ZLL_BWR_SAM_TABLE_INVALIDATE_ALL(base, value) (ZLL_WR_SAM_TABLE_INVALIDATE_ALL(base, value))  argument
46998 #define ZLL_RD_SAM_TABLE_SAM_BUSY(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_BUSY_MASK) >>…  argument
46999 #define ZLL_BRD_SAM_TABLE_SAM_BUSY(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_BU…  argument
47017 #define ZLL_RD_SAM_MATCH(base)   (ZLL_SAM_MATCH_REG(base))  argument
47029 #define ZLL_RD_SAM_MATCH_SAP0_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP0_MATCH_MASK…  argument
47030 #define ZLL_BRD_SAM_MATCH_SAP0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP0…  argument
47038 #define ZLL_RD_SAM_MATCH_SAP0_ADDR_PRESENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP0_ADD…  argument
47039 #define ZLL_BRD_SAM_MATCH_SAP0_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MAT…  argument
47047 #define ZLL_RD_SAM_MATCH_SAA0_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA0_MATCH_MASK…  argument
47048 #define ZLL_BRD_SAM_MATCH_SAA0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA0…  argument
47056 #define ZLL_RD_SAM_MATCH_SAA0_ADDR_ABSENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA0_ADDR…  argument
47057 #define ZLL_BRD_SAM_MATCH_SAA0_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATC…  argument
47065 #define ZLL_RD_SAM_MATCH_SAP1_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP1_MATCH_MASK…  argument
47066 #define ZLL_BRD_SAM_MATCH_SAP1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP1…  argument
47074 #define ZLL_RD_SAM_MATCH_SAP1_ADDR_PRESENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP1_ADD…  argument
47075 #define ZLL_BRD_SAM_MATCH_SAP1_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MAT…  argument
47083 #define ZLL_RD_SAM_MATCH_SAA1_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA1_MATCH_MASK…  argument
47084 #define ZLL_BRD_SAM_MATCH_SAA1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA1…  argument
47092 #define ZLL_RD_SAM_MATCH_SAA1_ADDR_ABSENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA1_ADDR…  argument
47093 #define ZLL_BRD_SAM_MATCH_SAA1_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATC…  argument
47111 #define ZLL_RD_SAM_FREE_IDX(base) (ZLL_SAM_FREE_IDX_REG(base))  argument
47123 #define ZLL_RD_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX…  argument
47124 #define ZLL_BRD_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…  argument
47132 #define ZLL_RD_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX…  argument
47133 #define ZLL_BRD_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…  argument
47141 #define ZLL_RD_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX…  argument
47142 #define ZLL_BRD_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…  argument
47150 #define ZLL_RD_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX…  argument
47151 #define ZLL_BRD_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_S…  argument
47167 #define ZLL_RD_SEQ_CTRL_STS(base) (ZLL_SEQ_CTRL_STS_REG(base))  argument
47168 #define ZLL_WR_SEQ_CTRL_STS(base, value) (ZLL_SEQ_CTRL_STS_REG(base) = (value))  argument
47169 #define ZLL_RMW_SEQ_CTRL_STS(base, mask, value) (ZLL_WR_SEQ_CTRL_STS(base, (ZLL_RD_SEQ_CTRL_STS(bas…  argument
47170 #define ZLL_SET_SEQ_CTRL_STS(base, value) (BME_OR32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(value)))  argument
47171 #define ZLL_CLR_SEQ_CTRL_STS(base, value) (BME_AND32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(~(valu…  argument
47172 #define ZLL_TOG_SEQ_CTRL_STS(base, value) (BME_XOR32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(value)…  argument
47192 #define ZLL_RD_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_S…  argument
47193 #define ZLL_BRD_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL…  argument
47196 #define ZLL_WR_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CT…  argument
47197 #define ZLL_BWR_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base…  argument
47213 #define ZLL_RD_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTR…  argument
47214 #define ZLL_BRD_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), …  argument
47217 #define ZLL_WR_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ…  argument
47218 #define ZLL_BWR_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(b…  argument
47234 #define ZLL_RD_SEQ_CTRL_STS_LATCH_PREAMBLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_LA…  argument
47235 #define ZLL_BRD_SEQ_CTRL_STS_LATCH_PREAMBLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_…  argument
47238 #define ZLL_WR_SEQ_CTRL_STS_LATCH_PREAMBLE(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_ST…  argument
47239 #define ZLL_BWR_SEQ_CTRL_STS_LATCH_PREAMBLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((…  argument
47255 #define ZLL_RD_SEQ_CTRL_STS_NO_RX_RECYCLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_NO_…  argument
47256 #define ZLL_BRD_SEQ_CTRL_STS_NO_RX_RECYCLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…  argument
47259 #define ZLL_WR_SEQ_CTRL_STS_NO_RX_RECYCLE(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS…  argument
47260 #define ZLL_BWR_SEQ_CTRL_STS_NO_RX_RECYCLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((u…  argument
47272 #define ZLL_RD_SEQ_CTRL_STS_FORCE_CRC_ERROR(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_F…  argument
47273 #define ZLL_BRD_SEQ_CTRL_STS_FORCE_CRC_ERROR(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ…  argument
47276 #define ZLL_WR_SEQ_CTRL_STS_FORCE_CRC_ERROR(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_S…  argument
47277 #define ZLL_BWR_SEQ_CTRL_STS_FORCE_CRC_ERROR(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), (…  argument
47292 #define ZLL_RD_SEQ_CTRL_STS_CONTINUOUS_EN(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_CON…  argument
47293 #define ZLL_BRD_SEQ_CTRL_STS_CONTINUOUS_EN(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…  argument
47296 #define ZLL_WR_SEQ_CTRL_STS_CONTINUOUS_EN(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS…  argument
47297 #define ZLL_BWR_SEQ_CTRL_STS_CONTINUOUS_EN(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((u…  argument
47310 #define ZLL_RD_SEQ_CTRL_STS_XCVSEQ_ACTUAL(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_XCV…  argument
47311 #define ZLL_BRD_SEQ_CTRL_STS_XCVSEQ_ACTUAL(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_C…  argument
47319 #define ZLL_RD_SEQ_CTRL_STS_SEQ_IDLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SEQ_IDLE…  argument
47320 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_IDLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_S…  argument
47336 #define ZLL_RD_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_N…  argument
47337 #define ZLL_BRD_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ…  argument
47352 #define ZLL_RD_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_ST…  argument
47353 #define ZLL_BRD_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_…  argument
47366 #define ZLL_RD_SEQ_CTRL_STS_RX_MODE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_RX_MODE_M…  argument
47367 #define ZLL_BRD_SEQ_CTRL_STS_RX_MODE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_ST…  argument
47384 #define ZLL_RD_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_S…  argument
47385 #define ZLL_BRD_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL…  argument
47401 #define ZLL_RD_SEQ_CTRL_STS_SEQ_T_STATUS(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SEQ_…  argument
47402 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_T_STATUS(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CT…  argument
47415 #define ZLL_RD_SEQ_CTRL_STS_SW_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SW_ABO…  argument
47416 #define ZLL_BRD_SEQ_CTRL_STS_SW_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL…  argument
47429 #define ZLL_RD_SEQ_CTRL_STS_TC3_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_TC3_A…  argument
47430 #define ZLL_BRD_SEQ_CTRL_STS_TC3_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTR…  argument
47442 #define ZLL_RD_SEQ_CTRL_STS_PLL_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_PLL_A…  argument
47443 #define ZLL_BRD_SEQ_CTRL_STS_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTR…  argument
47459 #define ZLL_RD_ACKDELAY(base)    (ZLL_ACKDELAY_REG(base))  argument
47460 #define ZLL_WR_ACKDELAY(base, value) (ZLL_ACKDELAY_REG(base) = (value))  argument
47461 #define ZLL_RMW_ACKDELAY(base, mask, value) (ZLL_WR_ACKDELAY(base, (ZLL_RD_ACKDELAY(base) & ~(mask)…  argument
47462 #define ZLL_SET_ACKDELAY(base, value) (BME_OR32(&ZLL_ACKDELAY_REG(base), (uint32_t)(value)))  argument
47463 #define ZLL_CLR_ACKDELAY(base, value) (BME_AND32(&ZLL_ACKDELAY_REG(base), (uint32_t)(~(value))))  argument
47464 #define ZLL_TOG_ACKDELAY(base, value) (BME_XOR32(&ZLL_ACKDELAY_REG(base), (uint32_t)(value)))  argument
47483 #define ZLL_RD_ACKDELAY_ACKDELAY(base) ((ZLL_ACKDELAY_REG(base) & ZLL_ACKDELAY_ACKDELAY_MASK) >> ZL…  argument
47484 #define ZLL_BRD_ACKDELAY_ACKDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_ACKDELAY_…  argument
47487 #define ZLL_WR_ACKDELAY_ACKDELAY(base, value) (ZLL_RMW_ACKDELAY(base, ZLL_ACKDELAY_ACKDELAY_MASK, Z…  argument
47488 #define ZLL_BWR_ACKDELAY_ACKDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(valu…  argument
47504 #define ZLL_RD_ACKDELAY_TXDELAY(base) ((ZLL_ACKDELAY_REG(base) & ZLL_ACKDELAY_TXDELAY_MASK) >> ZLL_…  argument
47505 #define ZLL_BRD_ACKDELAY_TXDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_TXDELAY_SH…  argument
47508 #define ZLL_WR_ACKDELAY_TXDELAY(base, value) (ZLL_RMW_ACKDELAY(base, ZLL_ACKDELAY_TXDELAY_MASK, ZLL…  argument
47509 #define ZLL_BWR_ACKDELAY_TXDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(value…  argument
47525 #define ZLL_RD_FILTERFAIL_CODE(base) (ZLL_FILTERFAIL_CODE_REG(base))  argument
47526 #define ZLL_WR_FILTERFAIL_CODE(base, value) (ZLL_FILTERFAIL_CODE_REG(base) = (value))  argument
47527 #define ZLL_RMW_FILTERFAIL_CODE(base, mask, value) (ZLL_WR_FILTERFAIL_CODE(base, (ZLL_RD_FILTERFAIL…  argument
47528 #define ZLL_SET_FILTERFAIL_CODE(base, value) (BME_OR32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(v…  argument
47529 #define ZLL_CLR_FILTERFAIL_CODE(base, value) (BME_AND32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(…  argument
47530 #define ZLL_TOG_FILTERFAIL_CODE(base, value) (BME_XOR32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(…  argument
47557 #define ZLL_RD_FILTERFAIL_CODE_FILTERFAIL_CODE(base) ((ZLL_FILTERFAIL_CODE_REG(base) & ZLL_FILTERFA…  argument
47558 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_CODE(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base), Z…  argument
47570 #define ZLL_RD_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base) ((ZLL_FILTERFAIL_CODE_REG(base) & ZLL_FILTE…  argument
47571 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base)…  argument
47574 #define ZLL_WR_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base, value) (ZLL_RMW_FILTERFAIL_CODE(base, ZLL_F…  argument
47575 #define ZLL_BWR_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base, value) (BME_BFI32(&ZLL_FILTERFAIL_CODE_REG…  argument
47596 #define ZLL_RD_RX_WTR_MARK(base) (ZLL_RX_WTR_MARK_REG(base))  argument
47597 #define ZLL_WR_RX_WTR_MARK(base, value) (ZLL_RX_WTR_MARK_REG(base) = (value))  argument
47598 #define ZLL_RMW_RX_WTR_MARK(base, mask, value) (ZLL_WR_RX_WTR_MARK(base, (ZLL_RD_RX_WTR_MARK(base) …  argument
47599 #define ZLL_SET_RX_WTR_MARK(base, value) (BME_OR32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(value)))  argument
47600 #define ZLL_CLR_RX_WTR_MARK(base, value) (BME_AND32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(~(value)…  argument
47601 #define ZLL_TOG_RX_WTR_MARK(base, value) (BME_XOR32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(value)))  argument
47613 #define ZLL_RD_RX_WTR_MARK_RX_WTR_MARK(base) ((ZLL_RX_WTR_MARK_REG(base) & ZLL_RX_WTR_MARK_RX_WTR_M…  argument
47614 #define ZLL_BRD_RX_WTR_MARK_RX_WTR_MARK(base) (BME_UBFX32(&ZLL_RX_WTR_MARK_REG(base), ZLL_RX_WTR_MA…  argument
47617 #define ZLL_WR_RX_WTR_MARK_RX_WTR_MARK(base, value) (ZLL_RMW_RX_WTR_MARK(base, ZLL_RX_WTR_MARK_RX_W…  argument
47618 #define ZLL_BWR_RX_WTR_MARK_RX_WTR_MARK(base, value) (BME_BFI32(&ZLL_RX_WTR_MARK_REG(base), ((uint3…  argument
47643 #define ZLL_RD_SLOT_PRELOAD(base) (ZLL_SLOT_PRELOAD_REG(base))  argument
47644 #define ZLL_WR_SLOT_PRELOAD(base, value) (ZLL_SLOT_PRELOAD_REG(base) = (value))  argument
47645 #define ZLL_RMW_SLOT_PRELOAD(base, mask, value) (ZLL_WR_SLOT_PRELOAD(base, (ZLL_RD_SLOT_PRELOAD(bas…  argument
47646 #define ZLL_SET_SLOT_PRELOAD(base, value) (BME_OR32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(value)))  argument
47647 #define ZLL_CLR_SLOT_PRELOAD(base, value) (BME_AND32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(~(valu…  argument
47648 #define ZLL_TOG_SLOT_PRELOAD(base, value) (BME_XOR32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(value)…  argument
47660 #define ZLL_RD_SLOT_PRELOAD_SLOT_PRELOAD(base) ((ZLL_SLOT_PRELOAD_REG(base) & ZLL_SLOT_PRELOAD_SLOT…  argument
47661 #define ZLL_BRD_SLOT_PRELOAD_SLOT_PRELOAD(base) (BME_UBFX32(&ZLL_SLOT_PRELOAD_REG(base), ZLL_SLOT_P…  argument
47664 #define ZLL_WR_SLOT_PRELOAD_SLOT_PRELOAD(base, value) (ZLL_RMW_SLOT_PRELOAD(base, ZLL_SLOT_PRELOAD_…  argument
47665 #define ZLL_BWR_SLOT_PRELOAD_SLOT_PRELOAD(base, value) (BME_BFI32(&ZLL_SLOT_PRELOAD_REG(base), ((ui…  argument
47683 #define ZLL_RD_SEQ_STATE(base)   (ZLL_SEQ_STATE_REG(base))  argument
47698 #define ZLL_RD_SEQ_STATE_SEQ_STATE(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_SEQ_STATE_MASK) …  argument
47699 #define ZLL_BRD_SEQ_STATE_SEQ_STATE(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SEQ_S…  argument
47717 #define ZLL_RD_SEQ_STATE_PREAMBLE_DET(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PREAMBLE_DET_…  argument
47718 #define ZLL_BRD_SEQ_STATE_PREAMBLE_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PR…  argument
47737 #define ZLL_RD_SEQ_STATE_SFD_DET(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_SFD_DET_MASK) >> Z…  argument
47738 #define ZLL_BRD_SEQ_STATE_SFD_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SFD_DET…  argument
47756 #define ZLL_RD_SEQ_STATE_FILTERFAIL_FLAG_SEL(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_FILTER…  argument
47757 #define ZLL_BRD_SEQ_STATE_FILTERFAIL_FLAG_SEL(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_S…  argument
47773 #define ZLL_RD_SEQ_STATE_CRCVALID(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_CRCVALID_MASK) >>…  argument
47774 #define ZLL_BRD_SEQ_STATE_CRCVALID(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_CRCVAL…  argument
47786 #define ZLL_RD_SEQ_STATE_PLL_ABORT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PLL_ABORT_MASK) …  argument
47787 #define ZLL_BRD_SEQ_STATE_PLL_ABORT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL_A…  argument
47801 #define ZLL_RD_SEQ_STATE_PLL_ABORTED(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PLL_ABORTED_MA…  argument
47802 #define ZLL_BRD_SEQ_STATE_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL…  argument
47815 #define ZLL_RD_SEQ_STATE_RX_BYTE_COUNT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_RX_BYTE_COUN…  argument
47816 #define ZLL_BRD_SEQ_STATE_RX_BYTE_COUNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_R…  argument
47832 #define ZLL_RD_SEQ_STATE_CCCA_BUSY_CNT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_CCCA_BUSY_CN…  argument
47833 #define ZLL_BRD_SEQ_STATE_CCCA_BUSY_CNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_C…  argument
47851 #define ZLL_RD_TMR_PRESCALE(base) (ZLL_TMR_PRESCALE_REG(base))  argument
47852 #define ZLL_WR_TMR_PRESCALE(base, value) (ZLL_TMR_PRESCALE_REG(base) = (value))  argument
47853 #define ZLL_RMW_TMR_PRESCALE(base, mask, value) (ZLL_WR_TMR_PRESCALE(base, (ZLL_RD_TMR_PRESCALE(bas…  argument
47854 #define ZLL_SET_TMR_PRESCALE(base, value) (BME_OR32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(value)))  argument
47855 #define ZLL_CLR_TMR_PRESCALE(base, value) (BME_AND32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(~(valu…  argument
47856 #define ZLL_TOG_TMR_PRESCALE(base, value) (BME_XOR32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(value)…  argument
47881 #define ZLL_RD_TMR_PRESCALE_TMR_PRESCALE(base) ((ZLL_TMR_PRESCALE_REG(base) & ZLL_TMR_PRESCALE_TMR_…  argument
47882 #define ZLL_BRD_TMR_PRESCALE_TMR_PRESCALE(base) (BME_UBFX32(&ZLL_TMR_PRESCALE_REG(base), ZLL_TMR_PR…  argument
47885 #define ZLL_WR_TMR_PRESCALE_TMR_PRESCALE(base, value) (ZLL_RMW_TMR_PRESCALE(base, ZLL_TMR_PRESCALE_…  argument
47886 #define ZLL_BWR_TMR_PRESCALE_TMR_PRESCALE(base, value) (BME_BFI32(&ZLL_TMR_PRESCALE_REG(base), ((ui…  argument
47916 #define ZLL_RD_LENIENCY_LSB(base) (ZLL_LENIENCY_LSB_REG(base))  argument
47917 #define ZLL_WR_LENIENCY_LSB(base, value) (ZLL_LENIENCY_LSB_REG(base) = (value))  argument
47918 #define ZLL_RMW_LENIENCY_LSB(base, mask, value) (ZLL_WR_LENIENCY_LSB(base, (ZLL_RD_LENIENCY_LSB(bas…  argument
47919 #define ZLL_SET_LENIENCY_LSB(base, value) (BME_OR32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(value)))  argument
47920 #define ZLL_CLR_LENIENCY_LSB(base, value) (BME_AND32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(~(valu…  argument
47921 #define ZLL_TOG_LENIENCY_LSB(base, value) (BME_XOR32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(value)…  argument
47951 #define ZLL_RD_LENIENCY_MSB(base) (ZLL_LENIENCY_MSB_REG(base))  argument
47952 #define ZLL_WR_LENIENCY_MSB(base, value) (ZLL_LENIENCY_MSB_REG(base) = (value))  argument
47953 #define ZLL_RMW_LENIENCY_MSB(base, mask, value) (ZLL_WR_LENIENCY_MSB(base, (ZLL_RD_LENIENCY_MSB(bas…  argument
47954 #define ZLL_SET_LENIENCY_MSB(base, value) (BME_OR32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(value)))  argument
47955 #define ZLL_CLR_LENIENCY_MSB(base, value) (BME_AND32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(~(valu…  argument
47956 #define ZLL_TOG_LENIENCY_MSB(base, value) (BME_XOR32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(value)…  argument
47985 #define ZLL_RD_LENIENCY_MSB_LENIENCY_REGISTER(base) ((ZLL_LENIENCY_MSB_REG(base) & ZLL_LENIENCY_MSB…  argument
47986 #define ZLL_BRD_LENIENCY_MSB_LENIENCY_REGISTER(base) (BME_UBFX32(&ZLL_LENIENCY_MSB_REG(base), ZLL_L…  argument
47989 #define ZLL_WR_LENIENCY_MSB_LENIENCY_REGISTER(base, value) (ZLL_RMW_LENIENCY_MSB(base, ZLL_LENIENCY…  argument
47990 #define ZLL_BWR_LENIENCY_MSB_LENIENCY_REGISTER(base, value) (BME_BFI32(&ZLL_LENIENCY_MSB_REG(base),…  argument
48008 #define ZLL_RD_PART_ID(base)     (ZLL_PART_ID_REG(base))  argument
48020 #define ZLL_RD_PART_ID_PART_ID(base) ((ZLL_PART_ID_REG(base) & ZLL_PART_ID_PART_ID_MASK) >> ZLL_PAR…  argument
48021 #define ZLL_BRD_PART_ID_PART_ID(base) (BME_UBFX32(&ZLL_PART_ID_REG(base), ZLL_PART_ID_PART_ID_SHIFT…  argument
48039 #define ZLL_RD_PKT_BUFFER(base, index) (ZLL_PKT_BUFFER_REG(base, index))  argument
48040 #define ZLL_WR_PKT_BUFFER(base, index, value) (ZLL_PKT_BUFFER_REG(base, index) = (value))  argument
48041 #define ZLL_RMW_PKT_BUFFER(base, index, mask, value) (ZLL_WR_PKT_BUFFER(base, index, (ZLL_RD_PKT_BU…  argument
48042 #define ZLL_SET_PKT_BUFFER(base, index, value) (BME_OR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_…  argument
48043 #define ZLL_CLR_PKT_BUFFER(base, index, value) (BME_AND32(&ZLL_PKT_BUFFER_REG(base, index), (uint32…  argument
48044 #define ZLL_TOG_PKT_BUFFER(base, index, value) (BME_XOR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32…  argument