Lines Matching refs:PMC
33 #define PMC PMC0 macro
36 #define PMC PMC1 macro
42 #define PMC_PDRCFG_REG(x) (*((volatile uint32_t *)((uint32_t)(&(PMC->PDRUNCFG0)) + ((x - 1U…
46 #define PMC_REG(off) (*((volatile uint32_t *)(void *)PMC + (off) / 4U))
214 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
217 PMC->CTRL |= PMC_CTRL_APPLYCFG_MASK; in POWER_ApplyPD()
219 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) in POWER_ApplyPD()
247 PMC->FLAGS = statusMask; in POWER_ClearEventFlags()
256 return PMC->FLAGS; in POWER_GetEventFlags()
265 PMC->CTRL |= resetMask; in POWER_EnableResets()
274 PMC->CTRL &= ~resetMask; in POWER_DisableResets()
283 PMC->INTRCTRL |= interruptMask; in POWER_EnableInterrupts()
302 PMC->INTRCTRL &= ~interruptMask; in POWER_DisableInterrupts()
394 …PMC->WAKEUP = (PMC->WAKEUP & 0x3F000000U) | PMC_WAKEUP_WAKETIME(ticks); /* Don't clear the [WKSRCF… in POWER_EnableAutoWake()
395 PMC->INTRCTRL |= PMC_INTRCTRL_AUTOWKIE_MASK; in POWER_EnableAutoWake()
402 PMC->PDRUNCFG0 &= ~POWER_AFBB_BITS_MASK(mask); in POWER_EnableRunAFBB()
403 PMC->PDRUNCFG0 |= mask; in POWER_EnableRunAFBB()
408 PMC->PDRUNCFG0 &= ~mask; /* Clear RBB* bits, set AFBB* bits */ in POWER_EnableRunRBB()
409 PMC->PDRUNCFG0 |= POWER_AFBB_BITS_MASK(mask); in POWER_EnableRunRBB()
415 PMC->PDSLEEPCFG0 &= ~mask; in POWER_EnableSleepRBB()
416 PMC->PDSLEEPCFG0 |= POWER_AFBB_BITS_MASK(mask); in POWER_EnableSleepRBB()
422 PMC->PDRUNCFG0 |= mask | POWER_AFBB_BITS_MASK(mask); in POWER_EnableRunNBB()
428 PMC->PDSLEEPCFG0 |= mask | POWER_AFBB_BITS_MASK(mask); in POWER_EnableSleepNBB()
454 … PMC->DCDCVSEL = PMC_DCDCVSEL_VSEL0(POWER_CalRegValueFromVolt(volt->DCDC.vsel0, 500000U, 6250U)) | in POWER_ConfigRegulatorSetpoints()
456 …PMC->LVDVDDNCTRL = PMC_LVDVDDNCTRL_LVL0(POWER_CalRegValueFromVolt(lvd->VDDN.lvl0, 500000U, 10000U)… in POWER_ConfigRegulatorSetpoints()
506 …PMC->LVDVDDNCTRL = PMC_LVDVDDNCTRL_LVL0(POWER_CalRegValueFromVolt(lvd->VDDN.lvl0, 500000U, 10000U)… in POWER_ConfigLvdSetpoints()
544 reg = PMC->LVDVDDNCTRL; in POWER_GetLvdSetpoints()
570 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_DCDC_VSEL_MASK; in POWER_SelectRunSetpoint()
571 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_DCDC_VSEL(setpoint); in POWER_SelectRunSetpoint()
576 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_LDO2_VSEL_MASK; in POWER_SelectRunSetpoint()
577 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_LDO2_VSEL(setpoint); in POWER_SelectRunSetpoint()
582 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_LDO1_VSEL_MASK; in POWER_SelectRunSetpoint()
583 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_LDO1_VSEL(setpoint); in POWER_SelectRunSetpoint()
592 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_DCDC_VSEL_MASK; in POWER_SelectSleepSetpoint()
593 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_DCDC_VSEL(setpoint); in POWER_SelectSleepSetpoint()
598 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO2_VSEL_MASK; in POWER_SelectSleepSetpoint()
599 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO2_VSEL(setpoint); in POWER_SelectSleepSetpoint()
604 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO1_VSEL_MASK; in POWER_SelectSleepSetpoint()
605 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO1_VSEL(setpoint); in POWER_SelectSleepSetpoint()
613 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_DCDC_LP_MASK; in POWER_SetRunRegulatorMode()
614 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_DCDC_LP(mode); in POWER_SetRunRegulatorMode()
618 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_LDO2_MODE_MASK; in POWER_SetRunRegulatorMode()
619 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_LDO2_MODE(mode); in POWER_SetRunRegulatorMode()
623 PMC->PDRUNCFG0 &= ~PMC_PDRUNCFG0_LDO1_MODE_MASK; in POWER_SetRunRegulatorMode()
624 PMC->PDRUNCFG0 |= PMC_PDRUNCFG0_LDO1_MODE(mode); in POWER_SetRunRegulatorMode()
632 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_DCDC_LP_MASK; in POWER_SetSleepRegulatorMode()
633 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_DCDC_LP(mode); in POWER_SetSleepRegulatorMode()
637 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO2_MODE_MASK; in POWER_SetSleepRegulatorMode()
638 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO2_MODE(mode); in POWER_SetSleepRegulatorMode()
642 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO1_MODE_MASK; in POWER_SetSleepRegulatorMode()
643 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO1_MODE(mode); in POWER_SetSleepRegulatorMode()
650 cfg = PMC->PADCFG; in POWER_ResetIOBank()
653 PMC->PADCFG = cfg | (mask << PMC_PADCFG_RSTCTRL_SHIFT); in POWER_ResetIOBank()
659 cfg = PMC->PADCFG; in POWER_IOBankIsolationHold()
663 PMC->PADCFG = cfg | (mask << PMC_PADCFG_ISOHOLD_SHIFT); in POWER_IOBankIsolationHold()
668 PMC->PADCFG |= mask << PMC_PADCFG_ISOCTRL_SHIFT; /* W1C. */ in POWER_IOBankClearIsolationHold()
674 PMC->BBCTRL = (*((const uint32_t *)(const void *)config)) & in POWER_ConfigRBBVolt()
685 PMC->POWERCFG |= PMC_POWERCFG_DCDCPD_MASK; in POWER_SetVddnSupplySrc()
694 PMC->POWERCFG |= PMC_POWERCFG_LDO1PD_MASK; in POWER_SetVdd1SupplySrc()
703 PMC->POWERCFG |= PMC_POWERCFG_LDO2PD_MASK; in POWER_SetVdd2SupplySrc()
709 PMC->POWERCFG |= mask & 0xFF80U; /* Ignore FDSR related bits. */ in POWER_DisableRegulators()
714 PMC->POWERCFG |= mask & 0x7FU; /* Ignore all mode control bits. */ in POWER_EnableSleepRegulators()
719 PMC->POWERCFG &= ~(mask & 0x7FU); /* Ignore all mode control bits. */ in POWER_DisableSleepRegulators()
724 PMC->POWERCFG &= ~PMC_POWERCFG_MODEDLY_MASK; in POWER_SetPMICModeDelay()
725 PMC->POWERCFG |= PMC_POWERCFG_MODEDLY(value); in POWER_SetPMICModeDelay()
730 PMC->PORCTRL = (*((const uint32_t *)(const void *)porVolt)); in POWER_SetPORVoltage()
1009 pdsleepcfg0 = PMC->PDSLEEPCFG0 & (~PCFG0_DEEP_SLEEP); in AT_QUICKACCESS_SECTION_CODE()
1030 PMC->PDSLEEPCFG0 = pdsleepcfg0 | (PCFG0_DEEP_SLEEP & ~exclude_from_pd[1]); in AT_QUICKACCESS_SECTION_CODE()
1032 if ((PMC->PDSLEEPCFG0 & PMC_PDSLEEPCFG0_VNCOM_DSR_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
1044 PMC->PDSLEEPCFG0 = pdsleepcfg0 | in AT_QUICKACCESS_SECTION_CODE()
1048 if ((PMC->PDSLEEPCFG0 & PMC_PDSLEEPCFG0_V2COM_DSR_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
1053 else if ((PMC->PDSLEEPCFG0 & PMC_PDSLEEPCFG0_VNCOM_DSR_MASK) != in AT_QUICKACCESS_SECTION_CODE()
1070 PMC->PDSLEEPCFG0 = in AT_QUICKACCESS_SECTION_CODE()
1080 PMC->PDSLEEPCFG0 = in AT_QUICKACCESS_SECTION_CODE()
1093 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_PMICMODE(pmic_mode_pins); in AT_QUICKACCESS_SECTION_CODE()
1097 PMC->PDSLEEPCFG0 |= pmicMode << PMC_PDSLEEPCFG0_PMICMODE_SHIFT; in AT_QUICKACCESS_SECTION_CODE()
1101 …PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO1_VSEL_MASK; /* Select lowest LDOVDD1 voltage for aggregat… in AT_QUICKACCESS_SECTION_CODE()
1104 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO1_MODE_MASK; /* Bypass mode. */ in AT_QUICKACCESS_SECTION_CODE()
1108 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO1_MODE_MASK; /* Low power mode. */ in AT_QUICKACCESS_SECTION_CODE()
1112 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO2_MODE_MASK; /* Bypass mode. */ in AT_QUICKACCESS_SECTION_CODE()
1116 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO2_MODE_MASK; /* Low power mode. */ in AT_QUICKACCESS_SECTION_CODE()
1119 …PMC->PDSLEEPCFG1 = (PCFG1_DEEP_SLEEP & ~exclude_from_pd[2]) | (PMC->PDRUNCFG1 & ~exclude_from_pd[2… in AT_QUICKACCESS_SECTION_CODE()
1131 PMC->PDSLEEPCFG1 &= ~PMC_PDSLEEPCFG1_PMCREF_LP_MASK; in AT_QUICKACCESS_SECTION_CODE()
1134 …PMC->PDSLEEPCFG2 = (PCFG2_DEEP_SLEEP & ~exclude_from_pd[3]) | (PMC->PDRUNCFG2 & ~exclude_from_pd[3… in AT_QUICKACCESS_SECTION_CODE()
1135 …PMC->PDSLEEPCFG3 = (PCFG3_DEEP_SLEEP & ~exclude_from_pd[4]) | (PMC->PDRUNCFG3 & ~exclude_from_pd[4… in AT_QUICKACCESS_SECTION_CODE()
1136 …PMC->PDSLEEPCFG4 = (PCFG4_DEEP_SLEEP & ~exclude_from_pd[5]) | (PMC->PDRUNCFG4 & ~exclude_from_pd[5… in AT_QUICKACCESS_SECTION_CODE()
1137 …PMC->PDSLEEPCFG5 = (PCFG5_DEEP_SLEEP & ~exclude_from_pd[6]) | (PMC->PDRUNCFG5 & ~exclude_from_pd[6… in AT_QUICKACCESS_SECTION_CODE()
1140 if ((PMC->PDSLEEPCFG0 & PMC_PDSLEEPCFG0_V2DSP_PD_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
1146 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1149 PMC->CTRL |= PMC_CTRL_APPLYCFG_MASK; in AT_QUICKACCESS_SECTION_CODE()
1150 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
1155 PMC->FLAGS = PMC->FLAGS; in AT_QUICKACCESS_SECTION_CODE()
1156 PMC->PWRFLAGS = PMC->PWRFLAGS; in AT_QUICKACCESS_SECTION_CODE()
1159 pmc_ctrl = PMC->CTRL; in AT_QUICKACCESS_SECTION_CODE()
1160 PMC->CTRL = pmc_ctrl & ~(PMC_CTRL_LVDNRE_MASK | PMC_CTRL_LVD2RE_MASK | PMC_CTRL_LVD1RE_MASK | in AT_QUICKACCESS_SECTION_CODE()
1186 if ((PMC->STATUS & PMC_STATUS_DSSENS_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
1218 PMC->CTRL = pmc_ctrl; in AT_QUICKACCESS_SECTION_CODE()
1315 pdsleepcfg0 = PMC->PDSLEEPCFG0 & (~PCFG0_DEEP_SLEEP); in AT_QUICKACCESS_SECTION_CODE()
1322 PMC->PDSLEEPCFG0 = pdsleepcfg0 | ((PCFG0_DEEP_SLEEP | PCFG0_DSR) & ~exclude_from_pd[1]); in AT_QUICKACCESS_SECTION_CODE()
1329 PMC->PDSLEEPCFG0 = pdsleepcfg0 | (PCFG0_DEEP_SLEEP & ~exclude_from_pd[1]) | PCFG0_DSR | in AT_QUICKACCESS_SECTION_CODE()
1336 PMC->PDSLEEPCFG0 = in AT_QUICKACCESS_SECTION_CODE()
1343 PMC->PDSLEEPCFG0 = in AT_QUICKACCESS_SECTION_CODE()
1356 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_PMICMODE(pmic_mode_pins); in AT_QUICKACCESS_SECTION_CODE()
1360 PMC->PDSLEEPCFG0 |= pmicMode << PMC_PDSLEEPCFG0_PMICMODE_SHIFT; in AT_QUICKACCESS_SECTION_CODE()
1364 …PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO2_VSEL_MASK; /* Select lowest LDOVDD2 voltage for aggr… in AT_QUICKACCESS_SECTION_CODE()
1365 if ((PMC->POWERCFG & PMC_POWERCFG_LDO1PD_MASK) != 0U) /* PMIC used.*/ in AT_QUICKACCESS_SECTION_CODE()
1367 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO1_MODE_MASK; /* Bypass mode. */ in AT_QUICKACCESS_SECTION_CODE()
1371 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO1_MODE_MASK; /* Low power mode. */ in AT_QUICKACCESS_SECTION_CODE()
1373 if ((PMC->POWERCFG & PMC_POWERCFG_LDO2PD_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
1375 PMC->PDSLEEPCFG0 &= ~PMC_PDSLEEPCFG0_LDO2_MODE_MASK; /* Bypass mode. */ in AT_QUICKACCESS_SECTION_CODE()
1379 PMC->PDSLEEPCFG0 |= PMC_PDSLEEPCFG0_LDO2_MODE_MASK; /* Low power mode. */ in AT_QUICKACCESS_SECTION_CODE()
1382 …PMC->PDSLEEPCFG1 = (PCFG1_DEEP_SLEEP & ~exclude_from_pd[2]) | (PMC->PDRUNCFG1 & ~exclude_from_pd[2… in AT_QUICKACCESS_SECTION_CODE()
1393 PMC->PDSLEEPCFG1 &= ~PMC_PDSLEEPCFG1_PMCREF_LP_MASK; in AT_QUICKACCESS_SECTION_CODE()
1396 …PMC->PDSLEEPCFG2 = (PCFG2_DEEP_SLEEP & ~exclude_from_pd[3]) | (PMC->PDRUNCFG2 & ~exclude_from_pd[3… in AT_QUICKACCESS_SECTION_CODE()
1397 …PMC->PDSLEEPCFG3 = (PCFG3_DEEP_SLEEP & ~exclude_from_pd[4]) | (PMC->PDRUNCFG3 & ~exclude_from_pd[4… in AT_QUICKACCESS_SECTION_CODE()
1398 …PMC->PDSLEEPCFG4 = (PCFG4_DEEP_SLEEP & ~exclude_from_pd[5]) | (PMC->PDRUNCFG4 & ~exclude_from_pd[5… in AT_QUICKACCESS_SECTION_CODE()
1399 …PMC->PDSLEEPCFG5 = (PCFG5_DEEP_SLEEP & ~exclude_from_pd[6]) | (PMC->PDRUNCFG5 & ~exclude_from_pd[6… in AT_QUICKACCESS_SECTION_CODE()
1402 while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Cannot set APPLYCFG when ACTIVEFSM is 1 */ in AT_QUICKACCESS_SECTION_CODE()
1405 PMC->CTRL |= PMC_CTRL_APPLYCFG_MASK; in AT_QUICKACCESS_SECTION_CODE()
1406 …while ((PMC->STATUS & PMC_STATUS_BUSY_MASK) != 0U) /* Wait all PMC finite state machines finished.… in AT_QUICKACCESS_SECTION_CODE()
1411 PMC->FLAGS = PMC->FLAGS; in AT_QUICKACCESS_SECTION_CODE()
1412 PMC->PWRFLAGS = PMC->PWRFLAGS; in AT_QUICKACCESS_SECTION_CODE()
1415 pmc_ctrl = PMC->CTRL; in AT_QUICKACCESS_SECTION_CODE()
1416 PMC->CTRL = pmc_ctrl & ~(PMC_CTRL_LVDNRE_MASK | PMC_CTRL_LVD2RE_MASK | PMC_CTRL_LVD1RE_MASK | in AT_QUICKACCESS_SECTION_CODE()
1433 PMC->CTRL = pmc_ctrl; in AT_QUICKACCESS_SECTION_CODE()