Lines Matching full:name
27 /*! @name Driver version */
119 /*! @brief Clock ip name array for CDOG. */
125 /*! @brief Clock ip name array for FREQME. */
131 /*! @brief Clock ip name array for GPU. */
137 /*! @brief Clock ip name array for MIPI DSI. */
143 /*! @brief Clock ip name array for LCDIF. */
149 /*! @brief Clock ip name array for SCT. */
155 /*! @brief Clock ip name array for USB. */
161 /*! @brief Clock ip name array for USBPHY. */
167 /*! @brief Clock ip name array for FlexSPI */
173 /*! @brief Clock ip name array for MMU */
179 /*! @brief Clock ip name array for CACHE64 */
185 /*! @brief Clock ip name array for CACHE64_POLSEL */
191 /*! @brief Clock ip name array for ADC. */
197 /*! @brief Clock ip name array for SDADC. */
203 /*! @brief Clock ip name array for ACMP. */
209 /*! @brief Clock ip name array for uSDHC */
215 /*! @brief Clock ip name array for WWDT. */
221 /*! @brief Clock ip name array for UTICK. */
227 /*! @brief Clock ip name array for FlexIO. */
233 /*! @brief Clock ip name array for LP_FLEXCOMM. */
242 /*! @brief Clock ip name array for LPUART. */
250 /*! @brief Clock ip name array for LPI2C. */
258 /*! @brief Clock ip name array for LSPI. */
266 /*! @brief Clock ip name array for SAI. */
272 /*! @brief Clock ip name array for SEMA */
278 /*! @brief Clock ip name array for MU */
292 /*! @brief Clock ip name array for DMA. */
298 /*! @brief Clock ip name array for SYSPM. */
304 /*! @brief Clock ip name array for TRNG. */
325 /*! @brief Clock ip name array for DMA. */
332 /*! @brief Clock ip name array for CRC. */
339 /*! @brief Clock ip name array for GDET. */
345 /*! @brief Clock ip name array for GDET_REF. */
352 /*! @brief Clock ip name array for GDET. */
358 /*! @brief Clock ip name array for GDET_REF. */
365 /*! @brief Clock ip name array for GPIO. */
374 /*! @brief Clock ip name array for PDM. */
380 /*! @brief Clock ip name array for PINT. */
386 /*! @brief Clock ip name array for PNGDEC. */
392 /*! @brief Clock ip name array for JPEGDEC. */
398 /*! @brief Clock ip name array for I3C. */
404 /*! @brief Clock ip name array for MRT. */
410 /*! @brief Clock ip name array for CT32B. */
417 /*! @brief Clock ip name array for OSTIMER. */
423 /*! @brief Clock ip name array for RTC. */
429 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
479 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
482 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
484 … kCLOCK_Xcache1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Code cache*/
485 …kCLOCK_Xcache0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: System cache*/
486 kCLOCK_Ocotp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 5), /*!< Clock gate name: VDD2 OTP0*/
487 …kCLOCK_Sleepcon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: SLEEPCON_CMPT…
488 … kCLOCK_Syscon0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 13), /*!< Clock gate name: SYSCON_CMPT*/
489 kCLOCK_Glikey0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 14), /*!< Clock gate name: GLIKEY0*/
490 kCLOCK_Glikey3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 15), /*!< Clock gate name: GLIKEY3*/
492 …kCLOCK_TpiuTraceClkin = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: TPIU_TRACECLK…
493 …kCLOCK_SWOTraceClkin = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: SWO_TRACECLKI…
494 kCLOCK_Tsclk = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 4), /*!< Clock gate name: TRACE*/
495 kCLOCK_Dma0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 5), /*!< Clock gate name: DMA0*/
496 kCLOCK_Dma1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 6), /*!< Clock gate name: DMA1*/
497 kCLOCK_PkcRam = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 7), /*!< Clock gate name: PKC RAM */
498 kCLOCK_Pkc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 8), /*!< Clock gate name: PKC*/
499 kCLOCK_Romcp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 9), /*!< Clock gate name: ROMCP*/
500 kCLOCK_Xspi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 10), /*!< Clock gate name: XSPI0*/
501 kCLOCK_Xspi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 11), /*!< Clock gate name: XSPI1*/
502 kCLOCK_Cache64ctrl0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 12), /*!< Clock gate name: CACHE64_0*/
503 kCLOCK_Cache64ctrl1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 13), /*!< Clock gate name: CACHE64_1*/
504 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 14), /*!< Clock gate name: QK_SUBSYS*/
505 kCLOCK_Mmu0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: MMU0*/
506 kCLOCK_Mmu1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 17), /*!< Clock gate name: MMU1*/
507 kCLOCK_Gpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 18), /*!< Clock gate name: GPIO0*/
508 kCLOCK_Gpio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 19), /*!< Clock gate name: GPIO1*/
509 kCLOCK_Gpio2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 20), /*!< Clock gate name: GPIO2*/
510 kCLOCK_Gpio3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 21), /*!< Clock gate name: GPIO3*/
511 kCLOCK_Gpio4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 22), /*!< Clock gate name: GPIO4*/
512 kCLOCK_Gpio5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 23), /*!< Clock gate name: GPIO5*/
513 kCLOCK_Gpio6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: GPIO6*/
514 kCLOCK_Gpio7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 25), /*!< Clock gate name: GPIO7*/
515 kCLOCK_Sct0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 26), /*!< Clock gate name: SCT0*/
516 kCLOCK_Cdog0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 27), /*!< Clock gate name: CDOG0*/
517 kCLOCK_Cdog1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 28), /*!< Clock gate name: CDOG1*/
518 kCLOCK_Cdog2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 29), /*!< Clock gate name: CDOG2*/
519 …kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LP_Flexcomm0*/
520 …kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LP_Flexcomm1*/
521 kCLOCK_LPUart0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPUART0*/
522 kCLOCK_LPUart1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPUART1*/
523 kCLOCK_LPI2c0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPI2C0*/
524 kCLOCK_LPI2c1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPI2C1*/
525 kCLOCK_LPSpi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 30), /*!< Clock gate name: LPSPI0*/
526 kCLOCK_LPSpi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 31), /*!< Clock gate name: LPSPI1*/
527 …kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LP_Flexcomm2*/
528 …kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LP_Flexcomm3*/
529 …kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LP_Flexcomm4*/
530 …kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LP_Flexcomm5*/
531 …kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LP_Flexcomm6*/
532 …kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LP_Flexcomm7*/
533 …kCLOCK_LPFlexComm8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LP_Flexcomm8*/
534 …kCLOCK_LPFlexComm9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LP_Flexcomm9*/
535 …kCLOCK_LPFlexComm10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LP_Flexcomm10…
536 …kCLOCK_LPFlexComm11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LP_Flexcomm11…
537 …kCLOCK_LPFlexComm12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LP_Flexcomm12…
538 …kCLOCK_LPFlexComm13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LP_Flexcomm13…
539 kCLOCK_LPUart2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPUART2*/
540 kCLOCK_LPUart3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPUART3*/
541 kCLOCK_LPUart4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPUART4*/
542 kCLOCK_LPUart5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPUART5*/
543 kCLOCK_LPUart6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPUART6*/
544 kCLOCK_LPUart7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPUART7*/
545 kCLOCK_LPUart8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPUART8*/
546 kCLOCK_LPUart9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPUART9*/
547 kCLOCK_LPUart10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPUART10*/
548 kCLOCK_LPUart11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPUART11*/
549 kCLOCK_LPUart12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPUART12*/
550 kCLOCK_LPUart13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPUART13*/
551 kCLOCK_LPI2c2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPI2C2*/
552 kCLOCK_LPI2c3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPI2C3*/
553 kCLOCK_LPI2c4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPI2C4*/
554 kCLOCK_LPI2c5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPI2C5*/
555 kCLOCK_LPI2c6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPI2C6*/
556 kCLOCK_LPI2c7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPI2C7*/
557 kCLOCK_LPI2c8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPI2C8*/
558 kCLOCK_LPI2c9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPI2C9*/
559 kCLOCK_LPI2c10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPI2C10*/
560 kCLOCK_LPI2c11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPI2C11*/
561 kCLOCK_LPI2c12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPI2C12*/
562 kCLOCK_LPI2c13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPI2C13*/
563 kCLOCK_LPSpi2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: LPSPI2*/
564 kCLOCK_LPSpi3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: LPSPI3*/
565 kCLOCK_LPSpi4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 2), /*!< Clock gate name: LPSPI4*/
566 kCLOCK_LPSpi5 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 3), /*!< Clock gate name: LPSPI5*/
567 kCLOCK_LPSpi6 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 4), /*!< Clock gate name: LPSPI6*/
568 kCLOCK_LPSpi7 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 5), /*!< Clock gate name: LPSPI7*/
569 kCLOCK_LPSpi8 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 6), /*!< Clock gate name: LPSPI8*/
570 kCLOCK_LPSpi9 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 7), /*!< Clock gate name: LPSPI9*/
571 kCLOCK_LPSpi10 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 8), /*!< Clock gate name: LPSPI10*/
572 kCLOCK_LPSpi11 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 9), /*!< Clock gate name: LPSPI11*/
573 kCLOCK_LPSpi12 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 10), /*!< Clock gate name: LPSPI12*/
574 kCLOCK_LPSpi13 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 11), /*!< Clock gate name: LPSPI13*/
575 kCLOCK_Sai0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 13), /*!< Clock gate name: SAI0*/
576 kCLOCK_Sai1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 14), /*!< Clock gate name: SAI1*/
577 kCLOCK_Sai2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 15), /*!< Clock gate name: SAI2*/
578 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 16), /*!< Clock gate name: I3C0*/
579 kCLOCK_I3c1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 17), /*!< Clock gate name: I3C1*/
580 kCLOCK_Crc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 18), /*!< Clock gate name: CRC0*/
581 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 19), /*!< Clock gate name: WWDT0*/
582 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 20), /*!< Clock gate name: WWDT1*/
583 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 21), /*!< Clock gate name: CTIMER0*/
584 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 22), /*!< Clock gate name: CTIMER1*/
585 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 23), /*!< Clock gate name: CTIMER2*/
586 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 24), /*!< Clock gate name: CTIMER3*/
587 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 25), /*!< Clock gate name: CTIMER4*/
588 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 26), /*!< Clock gate name: Mrt0*/
589 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 27), /*!< Clock gate name: Utick0*/
590 kCLOCK_Sema424 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 30), /*!< Clock gate name: SEMA42_4*/
591 kCLOCK_Mu4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 31), /*!< Clock gate name: MU4*/
593 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 5), /*!< Clock gate name: PINT0*/
594 …kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 10), /*!< Clock gate name: PMUX_CMPT_SPL…
596 kCLOCK_Freqme0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 8), /*!< Clock gate name: FREQME0*/
597 kCLOCK_SafoSgi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 12), /*!< Clock gate name: SAFO_SGI*/
598 kCLOCK_Trace = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 13), /*!< Clock gate name: TRACE*/
599 kCLOCK_Prince0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 15), /*!< Clock gate name: PRINCE0*/
600 kCLOCK_Prince1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 16), /*!< Clock gate name: PRINCE1*/
601 … kCLOCK_PrinceExe = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 17), /*!< Clock gate name: PRINCE_EXE*/
602 …kCLOCK_Syspm0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 18), /*!< Clock gate name: CMX_PERFMON0*/
603 …kCLOCK_Syspm1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL3, 19), /*!< Clock gate name: CMX_PERFMON1*/
604 kCLOCK_Hifi4 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL4, 0), /*!< Clock gate name: HIFI4*/
605 kCLOCK_Npu0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 0), /*!< Clock gate name: NPU0*/
607 …CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 2), /*!< Clock gate name: COMP_ACCESS_RAM_A…
608 … kCLOCK_Iopctl0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 3), /*!< Clock gate name: IOMUXC_VDD2*/
610 …CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 4), /*!< Clock gate name: HIFI4_ACCESS_RAM_…
612 …CLK_GATE_DEFINE(CLK_CTL0_PSCCTL5, 5), /*!< Clock gate name: MEDIA_ACCESS_RAM_…
614 …kCLOCK_Sleepcon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 6), /*!< Clock gate name: SLEEPCONCPU1*/
615 …kCLOCK_Syscon1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 7), /*!< Clock gate name: SYSCONSENSE1*/
617 …CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: SENSE_ACCESS_RAM_…
618 kCLOCK_Hifi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HIFI1*/
619 kCLOCK_Dma2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: DMA2*/
620 kCLOCK_Dma3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: DMA3*/
621 …kCLOCK_LPFlexComm17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LP_Flexcomm17…
622 …kCLOCK_LPFlexComm18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LP_Flexcomm18…
623 …kCLOCK_LPFlexComm19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LP_Flexcomm19…
624 …kCLOCK_LPFlexComm20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LP_Flexcomm20…
625 kCLOCK_LPI2c17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPI2C17*/
626 kCLOCK_LPI2c18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPI2C18*/
627 kCLOCK_LPI2c19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPI2C19*/
628 kCLOCK_LPI2c20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPI2C20*/
629 kCLOCK_LPSpi17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPSPI17*/
630 kCLOCK_LPSpi18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPSPI18*/
631 kCLOCK_LPSpi19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPSPI19*/
632 kCLOCK_LPSpi20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPSPI20*/
633 kCLOCK_LPUart17 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: LPUART17*/
634 kCLOCK_LPUart18 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: LPUART18*/
635 kCLOCK_LPUart19 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 8), /*!< Clock gate name: LPUART19*/
636 kCLOCK_LPUart20 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 9), /*!< Clock gate name: LPUART20*/
637 kCLOCK_Sai3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 10), /*!< Clock gate name: SAI3*/
638 kCLOCK_I3c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 11), /*!< Clock gate name: I3C2*/
639 kCLOCK_I3c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 12), /*!< Clock gate name: I3C3*/
640 kCLOCK_Gpio8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 13), /*!< Clock gate name: GPIO8*/
641 kCLOCK_Gpio9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 14), /*!< Clock gate name: GPIO9*/
642 kCLOCK_Gpio10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 15), /*!< Clock gate name: GPIO10*/
644 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: PINT1*/
645 …kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 30), /*!< Clock gate name: PMUX_SNS_SPLI…
647 kCLOCK_Ct32b5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 17), /*!< Clock gate name: CTIMER5*/
648 kCLOCK_Ct32b6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 18), /*!< Clock gate name: CTIMER6*/
649 kCLOCK_Ct32b7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 19), /*!< Clock gate name: CTIMER7*/
650 kCLOCK_Mrt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 20), /*!< Clock gate name: Mrt1*/
651 kCLOCK_Utick1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 21), /*!< Clock gate name: Utick1*/
652 kCLOCK_Cdog3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 22), /*!< Clock gate name: CDOG3*/
653 kCLOCK_Cdog4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: CDOG4*/
654 kCLOCK_Mu3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: MU3*/
655 kCLOCK_Sema423 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 25), /*!< Clock gate name: SEMA42_3*/
656 kCLOCK_Wwdt2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 26), /*!< Clock gate name: WWDT2*/
657 kCLOCK_Wwdt3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 27), /*!< Clock gate name: WWDT3*/
659 …kCLOCK_Syscon2 = CLK_GATE_DEFINE(CLK_CTL2_PSCCTL0, 3), /*!< Clock gate name: SYSCON_COMM */
660 …kCLOCK_Iopctl2 = CLK_GATE_DEFINE(CLK_CTL2_PSCCTL0, 4), /*!< Clock gate name: IOMUXC_VDDN */
662 kCLOCK_Cpu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 0), /*!< Clock gate name: CPU1*/
663 kCLOCK_Mu0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 4), /*!< Clock gate name: MU0*/
664 kCLOCK_Mu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 5), /*!< Clock gate name: MU1*/
665 kCLOCK_Mu2 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 6), /*!< Clock gate name: MU2*/
666 kCLOCK_OsTimer = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 7), /*!< Clock gate name: OsTimer*/
667 kCLOCK_Sema420 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 8), /*!< Clock gate name: SEMA42_0*/
668 kCLOCK_Sdadc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 9), /*!< Clock gate name: SDADC0*/
669 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 10), /*!< Clock gate name: SARADC0*/
670 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 11), /*!< Clock gate name: Acmp0*/
671 … kCLOCK_Pdm = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 12), /*!< Clock gate name: MICFIL(PDM)*/
672 …kCLOCK_Glikey4 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON…
673 kCLOCK_Dbg = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 20), /*!< Clock gate name: DBG*/
674 …kCLOCK_Syscon3 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 21), /*!< Clock gate name: SYSCON_SENSE0…
675 … kCLOCK_Iopctl1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 22), /*!< Clock gate name: IOMUXC_VDD1*/
676 kCLOCK_Glikey1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 23), /*!< Clock gate name: GLIKEY1*/
677 kCLOCK_LPI2c15 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 24), /*!< Clock gate name: LPI2C*/
679 …CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 25), /*!< Clock gate name: MEDIA_ACCESS_RAM_…
680 kCLOCK_Axi0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 0), /*!< Clock gate name: AXI0*/
681 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 2), /*!< Clock gate name: VGPU*/
682 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 4), /*!< Clock gate name: MIPIDSI*/
683 kCLOCK_LPSpi16 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 5), /*!< Clock gate name: LPSPI16*/
684 kCLOCK_LPSpi14 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 6), /*!< Clock gate name: LPSPI14*/
685 kCLOCK_Xspi2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 8), /*!< Clock gate name: XSPI2*/
686 kCLOCK_Mmu2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 11), /*!< Clock gate name: MMU2*/
687 …kCLOCK_Glikey5 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON…
688 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 15), /*!< Clock gate name: FLEXIO0*/
689 … kCLOCK_Lcdif = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 22), /*!< Clock gate name: LCDIF(DCN)*/
690 … kCLOCK_Syscon4 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 23), /*!< Clock gate name: SYSCONMEDIA*/
691 … kCLOCK_JpgDecoder = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 24), /*!< Clock gate name: JPG_DECODER*/
692 … kCLOCK_PngDecoder = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 25), /*!< Clock gate name: PNG_DECODER*/
693 kCLOCK_Ezhv = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 26), /*!< Clock gate name: EZHV*/
694 kCLOCK_AxbsEzh = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 28), /*!< Clock gate name: AXBS_EZH*/
695 kCLOCK_Glikey2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 29), /*!< Clock gate name: GLIKEY2*/
696 kCLOCK_Usb0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 0), /*!< Clock gate name: USB0*/
697 kCLOCK_Usb1 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 2), /*!< Clock gate name: USB1*/
698 kCLOCK_Usdhc0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 4), /*!< Clock gate name: USHDC0*/
699 kCLOCK_Usdhc1 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL1, 5), /*!< Clock gate name: USDHC1*/
703 …kCLOCK_Gdet0Ref = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 0), /*!< Clock gate name: GDET0 R…
704 …kCLOCK_Gdet1Ref = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 1), /*!< Clock gate name: GDET1 R…
705 …kCLOCK_TrngRef = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 2), /*!< Clock gate name: TRNG Re…
706 …kCLOCK_Els = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 3), /*!< Clock gate name: ELS clo…
707 …kCLOCK_ItrcRef = CLK_GATE_DEFINE(SYSCON0_SEC_CLK_CTRL, 4), /*!< Clock gate name: ITRC Re…
709 …kCLOCK_Gdet0 = CLK_GATE_DEFINE(CLKCTL0_ONE_SRC_CLKSLICE_ENABLE, 0U), /*!< Clock gate name: GDET0. …
710 …kCLOCK_Gdet1 = CLK_GATE_DEFINE(CLKCTL0_ONE_SRC_CLKSLICE_ENABLE, 1U), /*!< Clock gate name: GDET1. …
712 …kCLOCK_Gdet2Ref = CLK_GATE_DEFINE(SYSCON3_SEC_CLK_CTRL, 0), /*!< Clock gate name: GDET2 R…
713 …kCLOCK_Gdet3Ref = CLK_GATE_DEFINE(SYSCON3_SEC_CLK_CTRL, 1), /*!< Clock gate name: GDET3 R…
721 /*! @brief Clock name used to get clock frequency. */
1821 * @brief PLL PFD clock name
1953 * @param div_name : Clock divider name
2144 * @param pfd : pfd name to get frequency.
2155 * @param pfd : pfd name to get frequency.