Lines Matching refs:clk
1098 static inline void CLOCK_EnableClock(clock_ip_name_t clk) in CLOCK_EnableClock() argument
1100 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_EnableClock()
1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1108 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1111 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1128 static inline void CLOCK_DisableClock(clock_ip_name_t clk) in CLOCK_DisableClock() argument
1130 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); in CLOCK_DisableClock()
1134 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1137 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1140 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1143 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1149 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()