Lines Matching refs:DMA0
65 #define RTE_USART0_DMA_TX_DMA_BASE DMA0
67 #define RTE_USART0_DMA_RX_DMA_BASE DMA0
72 #define RTE_USART1_DMA_TX_DMA_BASE DMA0
74 #define RTE_USART1_DMA_RX_DMA_BASE DMA0
79 #define RTE_USART2_DMA_TX_DMA_BASE DMA0
81 #define RTE_USART2_DMA_RX_DMA_BASE DMA0
86 #define RTE_USART3_DMA_TX_DMA_BASE DMA0
88 #define RTE_USART3_DMA_RX_DMA_BASE DMA0
93 #define RTE_USART4_DMA_TX_DMA_BASE DMA0
95 #define RTE_USART4_DMA_RX_DMA_BASE DMA0
100 #define RTE_USART5_DMA_TX_DMA_BASE DMA0
102 #define RTE_USART5_DMA_RX_DMA_BASE DMA0
107 #define RTE_USART6_DMA_TX_DMA_BASE DMA0
109 #define RTE_USART6_DMA_RX_DMA_BASE DMA0
114 #define RTE_USART7_DMA_TX_DMA_BASE DMA0
116 #define RTE_USART7_DMA_RX_DMA_BASE DMA0
121 #define RTE_USART8_DMA_TX_DMA_BASE DMA0
123 #define RTE_USART8_DMA_RX_DMA_BASE DMA0
128 #define RTE_USART9_DMA_TX_DMA_BASE DMA0
130 #define RTE_USART9_DMA_RX_DMA_BASE DMA0
135 #define RTE_USART10_DMA_TX_DMA_BASE DMA0
137 #define RTE_USART10_DMA_RX_DMA_BASE DMA0
142 #define RTE_USART11_DMA_TX_DMA_BASE DMA0
144 #define RTE_USART11_DMA_RX_DMA_BASE DMA0
149 #define RTE_USART12_DMA_TX_DMA_BASE DMA0
151 #define RTE_USART12_DMA_RX_DMA_BASE DMA0
156 #define RTE_USART13_DMA_TX_DMA_BASE DMA0
158 #define RTE_USART13_DMA_RX_DMA_BASE DMA0
195 #define RTE_I2C0_Master_DMA_BASE DMA0
198 #define RTE_I2C1_Master_DMA_BASE DMA0
201 #define RTE_I2C2_Master_DMA_BASE DMA0
204 #define RTE_I2C3_Master_DMA_BASE DMA0
207 #define RTE_I2C4_Master_DMA_BASE DMA0
210 #define RTE_I2C5_Master_DMA_BASE DMA0
213 #define RTE_I2C6_Master_DMA_BASE DMA0
216 #define RTE_I2C7_Master_DMA_BASE DMA0
219 #define RTE_I2C8_Master_DMA_BASE DMA0
222 #define RTE_I2C9_Master_DMA_BASE DMA0
225 #define RTE_I2C10_Master_DMA_BASE DMA0
228 #define RTE_I2C11_Master_DMA_BASE DMA0
231 #define RTE_I2C12_Master_DMA_BASE DMA0
234 #define RTE_I2C13_Master_DMA_BASE DMA0
278 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0
280 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0
286 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0
288 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0
294 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0
296 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0
302 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0
304 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0
310 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0
312 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0
318 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0
320 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0
326 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0
328 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0
334 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0
336 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0
342 #define RTE_SPI8_DMA_TX_DMA_BASE DMA0
344 #define RTE_SPI8_DMA_RX_DMA_BASE DMA0
350 #define RTE_SPI9_DMA_TX_DMA_BASE DMA0
352 #define RTE_SPI9_DMA_RX_DMA_BASE DMA0
358 #define RTE_SPI10_DMA_TX_DMA_BASE DMA0
360 #define RTE_SPI10_DMA_RX_DMA_BASE DMA0
366 #define RTE_SPI11_DMA_TX_DMA_BASE DMA0
368 #define RTE_SPI11_DMA_RX_DMA_BASE DMA0
374 #define RTE_SPI12_DMA_TX_DMA_BASE DMA0
376 #define RTE_SPI12_DMA_RX_DMA_BASE DMA0
382 #define RTE_SPI13_DMA_TX_DMA_BASE DMA0
384 #define RTE_SPI13_DMA_RX_DMA_BASE DMA0
390 #define RTE_SPI14_DMA_TX_DMA_BASE DMA0
392 #define RTE_SPI14_DMA_RX_DMA_BASE DMA0
398 #define RTE_SPI16_DMA_TX_DMA_BASE DMA0
400 #define RTE_SPI16_DMA_RX_DMA_BASE DMA0