Lines Matching full:name
28 /*! @name Driver version */
76 /*! @brief Clock ip name array for MIPI DSI. */
82 /*! @brief Clock ip name array for LCDIF. */
88 /*! @brief Clock ip name array for SCT. */
94 /*! @brief Clock ip name array for USBD. */
100 /*! @brief Clock ip name array for FlexSPI */
106 /*! @brief Clock ip name array for Cache64 */
112 /*! @brief Clock ip name array for RNG */
118 /*! @brief Clock ip name array for PUF */
124 /*! @brief Clock ip name array for HashCrypt */
130 /*! @brief Clock ip name array for Casper */
136 /*! @brief Clock ip name array for Powerquad */
142 /*! @brief Clock ip name array for ADC. */
148 /*! @brief Clock ip name array for ACMP. */
154 /*! @brief Clock ip name array for uSDHC */
160 /*! @brief Clock ip name array for WWDT. */
166 /*! @brief Clock ip name array for UTICK. */
172 /*! @brief Clock ip name array for FlexIO. */
178 /*! @brief Clock ip name array for OSTimer */
184 /*! @brief Clock ip name array for FLEXCOMM. */
193 /*! @brief Clock ip name array for LPUART. */
201 /*! @brief Clock ip name array for I2C. */
208 /*! @brief Clock ip name array for SPI. */
215 /*! @brief Clock ip name array for FLEXI2S. */
222 /*! @brief Clock ip name array for DMIC. */
228 /*! @brief Clock ip name array for SEMA */
234 /*! @brief Clock ip name array for MUA */
240 /*! @brief Clock ip name array for DMA. */
246 /*! @brief Clock ip name array for CRC. */
252 /*! @brief Clock ip name array for GPIO. */
259 /*! @brief Clock ip name array for PINT. */
265 /*! @brief Clock ip name array for I3C. */
271 /*! @brief Clock ip name array for MRT. */
277 /*! @brief Clock ip name array for RTC. */
283 /*! @brief Clock ip name array for CT32B. */
289 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
313 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
316 kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */
317 kCLOCK_Dsp = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 1), /*!< Clock gate name: Dsp*/
318 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2), /*!< Clock gate name: RomCtrlr*/
319 kCLOCK_AxiSwitch = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 3), /*!< Clock gate name: AxiSwitch*/
320 kCLOCK_AxiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 4), /*!< Clock gate name: AxiCtrl*/
321 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8), /*!< Clock gate name: PowerQuad*/
322 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9), /*!< Clock gate name: Casper*/
323 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10), /*!< Clock gate name: HashCrypt*/
324 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11), /*!< Clock gate name: Puf*/
325 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12), /*!< Clock gate name: Rng*/
326 kCLOCK_Flexspi0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16), /*!< Clock gate name: Flexspi0*/
327 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17), /*!< Clock gate name: OtpCtrl*/
328 kCLOCK_Flexspi1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 18), /*!< Clock gate name: Flexspi1*/
329 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20), /*!< Clock gate name: UsbhsPhy*/
330 kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21), /*!< Clock gate name: UsbhsDevice*/
331 kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22), /*!< Clock gate name: UsbhsHost*/
332 kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23), /*!< Clock gate name: UsbhsSram*/
333 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24), /*!< Clock gate name: Sct*/
334 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 26), /*!< Clock gate name: Gpu*/
335 kCLOCK_DisplayCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 27), /*!< Clock gate name: DisplayCtrl*/
336 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 28), /*!< Clock gate name: MipiDsiCtrl*/
337 kCLOCK_Smartdma = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 30), /*!< Clock gate name: Smartdma*/
339 kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2), /*!< Clock gate name: Sdio0*/
340 kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3), /*!< Clock gate name: Sdio1*/
341 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15), /*!< Clock gate name: Acmp0*/
342 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16), /*!< Clock gate name: Adc0*/
343 kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24), /*!< Clock gate name: ShsGpio0*/
345 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0), /*!< Clock gate name: Utick0*/
346 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1), /*!< Clock gate name: Wwdt0*/
347 kCLOCK_Pmc = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 29), /*!< Clock gate name: Pmc*/
349 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Flexcomm0*/
350 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Flexcomm1*/
351 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Flexcomm2*/
352 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Flexcomm3*/
353 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Flexcomm4*/
354 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Flexcomm5*/
355 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Flexcomm6*/
356 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Flexcomm7*/
357 kCLOCK_Flexcomm8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Flexcomm8*/
358 kCLOCK_Flexcomm9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Flexcomm9*/
359 kCLOCK_Flexcomm10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Flexcomm10*/
360 kCLOCK_Flexcomm11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Flexcomm11*/
361 kCLOCK_Flexcomm12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Flexcomm12*/
362 kCLOCK_Flexcomm13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Flexcomm13*/
363 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Flexcomm14*/
364 kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: Flexcomm15*/
365 kCLOCK_Flexcomm16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Flexcomm16*/
366 kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Usart0*/
367 kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Usart1*/
368 kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Usart2*/
369 kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Usart3*/
370 kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Usart4*/
371 kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Usart5*/
372 kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Usart6*/
373 kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Usart7*/
374 kCLOCK_Usart8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Usart8*/
375 kCLOCK_Usart9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Usart9*/
376 kCLOCK_Usart10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Usart10*/
377 kCLOCK_Usart11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Usart11*/
378 kCLOCK_Usart12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Usart12*/
379 kCLOCK_Usart13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Usart13*/
380 kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2s0*/
381 kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2s1*/
382 kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2s2*/
383 kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2s3*/
384 kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2s4*/
385 kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2s5*/
386 kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2s6*/
387 kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2s7*/
388 kCLOCK_I2s8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2s8*/
389 kCLOCK_I2s9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2s9*/
390 kCLOCK_I2s10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2s10*/
391 kCLOCK_I2s11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2s11*/
392 kCLOCK_I2s12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2s12*/
393 kCLOCK_I2s13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2s13*/
394 kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: I2c0*/
395 kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: I2c1*/
396 kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: I2c2*/
397 kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: I2c3*/
398 kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: I2c4*/
399 kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: I2c5*/
400 kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: I2c6*/
401 kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: I2c7*/
402 kCLOCK_I2c8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: I2c8*/
403 kCLOCK_I2c9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: I2c9*/
404 kCLOCK_I2c10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: I2c10*/
405 kCLOCK_I2c11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: I2c11*/
406 kCLOCK_I2c12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: I2c12*/
407 kCLOCK_I2c13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: I2c13*/
408 kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23), /*!< Clock gate name: I2c15*/
409 kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8), /*!< Clock gate name: Spi0*/
410 kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9), /*!< Clock gate name: Spi1*/
411 kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10), /*!< Clock gate name: Spi2*/
412 kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11), /*!< Clock gate name: Spi3*/
413 kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12), /*!< Clock gate name: Spi4*/
414 kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13), /*!< Clock gate name: Spi5*/
415 kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14), /*!< Clock gate name: Spi6*/
416 kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15), /*!< Clock gate name: Spi7*/
417 kCLOCK_Spi8 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 16), /*!< Clock gate name: Spi8*/
418 kCLOCK_Spi9 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 17), /*!< Clock gate name: Spi9*/
419 kCLOCK_Spi10 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 18), /*!< Clock gate name: Spi10*/
420 kCLOCK_Spi11 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 19), /*!< Clock gate name: Spi11*/
421 kCLOCK_Spi12 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 20), /*!< Clock gate name: Spi12*/
422 kCLOCK_Spi13 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 21), /*!< Clock gate name: Spi13*/
423 kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22), /*!< Clock gate name: Spi14*/
424 kCLOCK_Spi16 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 25), /*!< Clock gate name: Spi16*/
425 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24), /*!< Clock gate name: Dmic0*/
426 … kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27), /*!< Clock gate name: OsEventTimer*/
427 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 29), /*!< Clock gate name: Flexio*/
429 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0), /*!< Clock gate name: HsGpio0*/
430 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1), /*!< Clock gate name: HsGpio1*/
431 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2), /*!< Clock gate name: HsGpio2*/
432 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3), /*!< Clock gate name: HsGpio3*/
433 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4), /*!< Clock gate name: HsGpio4*/
434 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5), /*!< Clock gate name: HsGpio5*/
435 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6), /*!< Clock gate name: HsGpio6*/
436 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7), /*!< Clock gate name: HsGpio7*/
437 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16), /*!< Clock gate name: Crc*/
438 kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23), /*!< Clock gate name: Dmac0*/
439 kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24), /*!< Clock gate name: Dmac1*/
440 kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28), /*!< Clock gate name: Mu*/
441 kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29), /*!< Clock gate name: Sema*/
442 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31), /*!< Clock gate name: Freqme*/
444 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0), /*!< Clock gate name: Ct32b0*/
445 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1), /*!< Clock gate name: Ct32b1*/
446 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2), /*!< Clock gate name: Ct32b2*/
447 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3), /*!< Clock gate name: Ct32b3*/
448 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4), /*!< Clock gate name: Ct32b4*/
449 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7), /*!< Clock gate name: Rtc*/
450 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8), /*!< Clock gate name: Mrt0*/
451 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10), /*!< Clock gate name: Wwdt1*/
452 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16), /*!< Clock gate name: I3c0*/
453 kCLOCK_I3c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 17), /*!< Clock gate name: I3c1*/
454 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30), /*!< Clock gate name: Pint*/
455 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31) /*!< Clock gate name: InputMux. */
458 /*! @brief Clock name used to get clock frequency. */
505 * @brief PLL PFD clock name
1166 * @param div_name : Clock divider name
1193 * @param pfd : pfd name to get frequency.
1204 * @param pfd : pfd name to get frequency.