195     uint32_t temp32;  in PMU_StaticEnablePllLdo()  local
197     temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0);  in PMU_StaticEnablePllLdo()
199     if (temp32 !=  in PMU_StaticEnablePllLdo()
443     uint32_t temp32 = base->PMU_LDO_LPSR_DIG;  in PMU_StaticLpsrDigLdoInit()  local
445     temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK;  in PMU_StaticLpsrDigLdoInit()
446     temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage);  in PMU_StaticLpsrDigLdoInit()
447     base->PMU_LDO_LPSR_DIG = temp32;  in PMU_StaticLpsrDigLdoInit()
449     temp32 = base->PMU_LDO_LPSR_DIG_2;  in PMU_StaticLpsrDigLdoInit()
450     temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK;  in PMU_StaticLpsrDigLdoInit()
451     temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime);  in PMU_StaticLpsrDigLdoInit()
452     base->PMU_LDO_LPSR_DIG_2 = temp32;  in PMU_StaticLpsrDigLdoInit()
543     uint32_t temp32 = base->PMU_LDO_SNVS_DIG;  in PMU_SnvsDigLdoInit()  local
545     temp32 &= ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK);  in PMU_SnvsDigLdoInit()
547 …temp32 |= (ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(mode) | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS…  in PMU_SnvsDigLdoInit()
549     base->PMU_LDO_SNVS_DIG = temp32;  in PMU_SnvsDigLdoInit()
689     uint32_t temp32;  in PMU_DisableBandgapSelfBiasAfterPowerUp()  local
699     temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);  in PMU_DisableBandgapSelfBiasAfterPowerUp()
700     temp32 |= AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;  in PMU_DisableBandgapSelfBiasAfterPowerUp()
701     ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);  in PMU_DisableBandgapSelfBiasAfterPowerUp()
712     uint32_t temp32;  in PMU_EnableBandgapSelfBiasBeforePowerDown()  local
714     temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);  in PMU_EnableBandgapSelfBiasBeforePowerDown()
715     temp32 &= ~AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK;  in PMU_EnableBandgapSelfBiasBeforePowerDown()
716     ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);  in PMU_EnableBandgapSelfBiasBeforePowerDown()
728     uint32_t temp32;  in PMU_StaticBandgapInit()  local
730     temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0);  in PMU_StaticBandgapInit()
731     temp32 &= ~(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK |  in PMU_StaticBandgapInit()
734     temp32 |= ((uint32_t)(config->powerDownOption) &  in PMU_StaticBandgapInit()
737     temp32 |= AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode);  in PMU_StaticBandgapInit()
738     temp32 |= AI_BANDGAP_CTRL0_REFTOP_VBGADJ(config->outputVoltage);  in PMU_StaticBandgapInit()
739     temp32 |= AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent);  in PMU_StaticBandgapInit()
741     ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32);  in PMU_StaticBandgapInit()
796     uint32_t temp32;  in PMU_SetBodyBiasControlMode()  local
803             temp32 = base->PMU_BIAS_CTRL2;  in PMU_SetBodyBiasControlMode()
804             temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK;  in PMU_SetBodyBiasControlMode()
805             temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(mode);  in PMU_SetBodyBiasControlMode()
806             base->PMU_BIAS_CTRL2 = temp32;  in PMU_SetBodyBiasControlMode()
812             temp32 = base->PMU_BIAS_CTRL2;  in PMU_SetBodyBiasControlMode()
813             temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK;  in PMU_SetBodyBiasControlMode()
814             temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(mode);  in PMU_SetBodyBiasControlMode()
815             base->PMU_BIAS_CTRL2 = temp32;  in PMU_SetBodyBiasControlMode()
820             temp32 = base->PMU_BIAS_CTRL2;  in PMU_SetBodyBiasControlMode()
821             temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK;  in PMU_SetBodyBiasControlMode()
822             temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(mode);  in PMU_SetBodyBiasControlMode()
823             base->PMU_BIAS_CTRL2 = temp32;  in PMU_SetBodyBiasControlMode()
970     uint32_t temp32;  in PMU_GPCSetBodyBiasConfig()  local
972     temp32 = (*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]);  in PMU_GPCSetBodyBiasConfig()
973     temp32 &=  in PMU_GPCSetBodyBiasConfig()
976     temp32 |= ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(config->PWELLRegulatorSize) |  in PMU_GPCSetBodyBiasConfig()
980     (*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]) = temp32;  in PMU_GPCSetBodyBiasConfig()