Lines Matching refs:uint16_t
13862 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
13864 …__IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), …
13865 …__IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0)…
13867 …__IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 …
13869 …__I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an en…
13871 …__IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls,…
13872 …__I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offse…
13874 …__IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: …
13876 …__IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: …
13878 …__IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: …
13880 …__IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: …
13899 #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13913 #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
13927 #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
13937 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13943 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13953 #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_A…
13963 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
13969 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
13975 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_A…
13985 #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
13995 #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14005 #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14015 #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14025 #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14096 __IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */
14098 …__I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-on…
14100 __IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */
14101 …__IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset…
14102 …__I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, o…
14104 …__I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, o…
14106 …__IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid cs…
14108 …__IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the loc…
14110 …__I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Sha…
14129 #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
14139 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14145 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << …
14155 #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14165 #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14175 #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow(x) (((uint16_t)(((uint16_t)(x)) <…
14185 #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow(x) (((uint16_t)(((uint16_t)…
14195 …RPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14205 #define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
14211 #define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_AP…
14217 #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APB…
14223 #define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
14234 #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow(x) (((uint16_t)(((uint16_t)…
14269 __IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */
14271 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
14273 __IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */
14275 …__IO uint16_t VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only …
14277 …__IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14278 __IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */
14280 __IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */
14282 …__IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., of…
14283 __IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */
14284 __IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */
14285 …__IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: …
14286 __IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */
14287 …__IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A…
14289 …__I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset…
14290 …__I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with…
14291 …__I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0x…
14292 __IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */
14293 __I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
14294 __I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
14295 __I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */
14297 __IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */
14299 …__IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14300 …__IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14301 …__IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14302 …__IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14304 …__IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14305 …__IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14306 …__IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14307 …__IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14309 …__IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14310 …__IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14311 …__IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14312 …__IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14313 …__IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14314 …__IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14315 …__IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14317 …__IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14319 …__IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset…
14321 …__IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14322 …__IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14323 …__IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14324 …__IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14326 …__IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14327 …__IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14328 …__IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14329 …__IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14331 …__I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C…
14333 …__IO uint16_t VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only …
14335 …__IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14336 __IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */
14338 __IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */
14340 __IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */
14342 …__IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: …
14344 …__IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29…
14346 __IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */
14348 …__IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14349 …__IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14350 …__IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14351 …__IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14353 …__IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14354 …__IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14355 …__IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14356 …__IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14358 …__IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14359 …__IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14360 …__IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14361 …__IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14362 …__IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14363 …__IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14364 …__IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14366 …__IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14368 …__IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14369 …__IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14370 …__IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14371 …__IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14373 …__IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14374 …__IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14375 …__IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14376 …__IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14378 …__IO uint16_t VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only …
14380 …__IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14382 …__IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14383 …__IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14384 …__IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14385 …__IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14387 …__IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14388 …__IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14389 …__IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14390 …__IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14392 …__IO uint16_t VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only …
14394 …__IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14396 …__IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14397 …__IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14398 …__IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14399 …__IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14401 …__IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14402 …__IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14403 …__IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14404 …__IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14406 …__IO uint16_t VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only …
14408 …__IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14410 …__IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14411 …__IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14412 …__IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14413 …__IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14415 …__IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14416 …__IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14417 …__IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14418 …__IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14420 …__IO uint16_t VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only …
14422 …__IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14424 …__IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14425 …__IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14426 …__IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14427 …__IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14429 …__IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14430 …__IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14431 …__IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14432 …__IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14434 …__IO uint16_t VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only …
14436 …__IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14438 …__IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14439 …__IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14440 …__IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14441 …__IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14443 …__IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14444 …__IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14445 …__IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14446 …__IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14448 …__IO uint16_t VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only …
14450 …__IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14452 …__IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14453 …__IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14454 …__IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14455 …__IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14457 …__IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14458 …__IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14459 …__IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14460 …__IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14462 …__IO uint16_t VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only …
14464 …__IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14466 …__IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14467 …__IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14468 …__IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14469 …__IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14471 …__IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14472 …__IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14473 …__IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14474 …__IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14476 __IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */
14478 …__IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082…
14480 __IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */
14482 …__IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., of…
14483 __IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */
14485 …__IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: …
14486 __IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */
14487 …__IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20…
14489 __IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */
14491 …__IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14492 …__IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14493 …__IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14494 …__IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14496 …__IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14497 …__IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14498 …__IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14499 …__IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14500 …__IO uint16_t RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14501 …__IO uint16_t RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14502 …__IO uint16_t RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14504 …__IO uint16_t RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14506 …__IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14507 …__IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14508 …__IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14509 …__IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14511 …__IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14512 …__IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14513 …__IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14514 …__IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14516 …__IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282…
14518 __IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */
14520 __IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */
14522 …__IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: …
14524 …__IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20…
14526 __IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */
14528 …__IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14529 …__IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14530 …__IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14531 …__IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14533 …__IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14534 …__IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14535 …__IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14536 …__IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14537 …__IO uint16_t RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14538 …__IO uint16_t RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14539 …__IO uint16_t RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14541 …__IO uint16_t RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14543 …__IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14544 …__IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14545 …__IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14546 …__IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14548 …__IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14549 …__IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14550 …__IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14551 …__IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14553 …__IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14554 …__IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14555 …__IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14556 …__IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14558 …__IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14559 …__IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14560 …__IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14561 …__IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14563 …__IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14564 …__IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14565 …__IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14566 …__IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14568 …__IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14569 …__IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14570 …__IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14571 …__IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14573 …__IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14574 …__IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14575 …__IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14576 …__IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14578 …__IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14579 …__IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14580 …__IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14581 …__IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14583 …__IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14584 …__IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14585 …__IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14586 …__IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14588 __IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */
14590 …__IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082…
14592 __IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */
14594 …__IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., of…
14595 __IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */
14597 …__IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: …
14598 __IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */
14599 …__IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40…
14601 __IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */
14603 …__IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14604 …__IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14605 …__IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14606 …__IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14608 …__IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14609 …__IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14610 …__IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14611 …__IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14612 …__IO uint16_t RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14613 …__IO uint16_t RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14614 …__IO uint16_t RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14616 …__IO uint16_t RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14618 …__IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of trai…
14619 …__IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of trai…
14621 …__IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14622 …__IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14623 …__IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14624 …__IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14626 …__IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14627 …__IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14628 …__IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14629 …__IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14631 …__IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282…
14633 __IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */
14635 __IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */
14637 …__IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: …
14639 …__IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40…
14641 __IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */
14643 …__IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14644 …__IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14645 …__IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14646 …__IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14648 …__IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14649 …__IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14650 …__IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14651 …__IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14652 …__IO uint16_t RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14653 …__IO uint16_t RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14654 …__IO uint16_t RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14656 …__IO uint16_t RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14658 …__IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14659 …__IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14660 …__IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14661 …__IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14663 …__IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14664 …__IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14665 …__IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14666 …__IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14668 …__IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14669 …__IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14670 …__IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14671 …__IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14673 …__IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14674 …__IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14675 …__IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14676 …__IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14678 …__IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14679 …__IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14680 …__IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14681 …__IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14683 …__IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14684 …__IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14685 …__IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14686 …__IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14688 …__IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14689 …__IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14690 …__IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14691 …__IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14693 …__IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14694 …__IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14695 …__IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14696 …__IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14698 …__IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14699 …__IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14700 …__IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14701 …__IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14703 __IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */
14705 …__IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082…
14707 __IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */
14709 …__IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., of…
14710 __IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */
14712 …__IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: …
14713 __IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */
14714 …__IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60…
14716 __IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */
14718 …__IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14719 …__IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14720 …__IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14721 …__IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14723 …__IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14724 …__IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14725 …__IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14726 …__IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14727 …__IO uint16_t RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14728 …__IO uint16_t RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14729 …__IO uint16_t RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14731 …__IO uint16_t RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14733 …__IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of trai…
14734 …__IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of trai…
14736 …__IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14737 …__IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14738 …__IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14739 …__IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14741 …__IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14742 …__IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14743 …__IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14744 …__IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14746 …__IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282…
14748 __IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */
14750 __IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */
14752 …__IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: …
14754 …__IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60…
14756 __IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */
14758 …__IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14759 …__IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14760 …__IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14761 …__IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14763 …__IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14764 …__IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14765 …__IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14766 …__IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14767 …__IO uint16_t RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14768 …__IO uint16_t RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14769 …__IO uint16_t RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14771 …__IO uint16_t RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14773 …__IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14774 …__IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14775 …__IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14776 …__IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14778 …__IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14779 …__IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14780 …__IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14781 …__IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14783 …__IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14784 …__IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14785 …__IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14786 …__IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14788 …__IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14789 …__IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14790 …__IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14791 …__IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14793 …__IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14794 …__IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14795 …__IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14796 …__IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14798 …__IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14799 …__IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14800 …__IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14801 …__IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14803 …__IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14804 …__IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14805 …__IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14806 …__IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14808 …__IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14809 …__IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14810 …__IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14811 …__IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14813 …__IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14814 …__IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14815 …__IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14816 …__IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14835 #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
14845 #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14856 #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
14869 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14882 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14893 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14900 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14910 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
14916 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
14924 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14930 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14936 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
14944 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
14955 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
14962 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
14972 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
14978 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
14984 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
14990 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
15001 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
15008 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
15018 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15028 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15034 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15044 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15051 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15057 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15064 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15074 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue(x) (((uint16_t)(((uint16_t)(x)) …
15080 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue(x) (((uint16_t)(((uint16_t)(x)) …
15086 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue(x) (((uint16_t)(((uint16_t)(x))…
15092 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue(x) (((uint16_t)(((uint16_t)(x))…
15102 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBY…
15108 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBY…
15114 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15120 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15133 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
15140 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15146 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15157 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210(x) (((uint16_t)(((uint16_t)(x))…
15168 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654(x) (((uint16_t)(((uint16_t)(x))…
15182 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI(x) (((uint16_t)(((uint16_t)(x)) << DW…
15192 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15198 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15204 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15214 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15224 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15234 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15244 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15255 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15266 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15277 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15288 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15298 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15308 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15318 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15328 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15338 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15348 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15358 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15368 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15378 #define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
15391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15401 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15411 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15421 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15431 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15441 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15451 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15461 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15471 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
15477 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15483 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15489 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15495 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15508 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15521 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15532 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15539 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15549 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15555 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15563 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15569 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15575 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15586 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
15593 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
15604 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
15611 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
15621 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15627 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15637 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15643 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15649 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15659 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15669 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15679 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15689 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15700 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15711 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15722 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15733 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15743 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15753 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15763 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15773 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15783 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15793 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15803 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15813 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15823 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15833 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15843 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15853 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15863 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15873 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15883 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15893 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15906 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15919 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15929 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15939 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15949 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15959 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15969 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15979 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15989 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15999 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16012 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16025 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16035 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16045 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16055 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16065 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16075 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16085 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16095 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16105 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16118 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16131 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16141 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16151 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16161 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16171 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16181 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16191 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16201 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16211 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16224 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16237 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16247 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16257 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16267 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16277 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16287 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16297 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16307 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16317 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16330 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16343 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16353 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16363 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16373 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16383 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16393 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16403 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16413 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16423 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16436 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16449 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16459 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16469 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16479 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16489 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16499 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16509 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16519 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16529 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16542 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16555 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16565 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16575 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16585 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16595 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16605 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16615 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16625 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16635 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16646 #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
16657 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16664 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16674 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16680 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
16688 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16694 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16700 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
16708 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
16719 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
16726 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
16737 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
16744 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
16754 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16764 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16770 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16780 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16786 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16792 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16803 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16814 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16825 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16836 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16846 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16856 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16866 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16876 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16886 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16896 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16906 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16916 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16926 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16936 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16946 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16956 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16966 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16976 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16986 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16996 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17007 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17014 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17024 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17030 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
17038 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
17044 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17050 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
17061 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
17068 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
17079 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
17086 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
17096 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17102 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17112 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17118 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17124 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17135 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17146 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17157 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17168 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17178 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17188 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17198 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17208 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17218 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17228 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17238 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17248 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17258 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17268 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17278 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17288 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17298 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17308 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17318 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17328 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17338 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17348 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17358 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17368 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17378 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17388 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17398 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17408 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17418 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17428 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17438 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17448 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17458 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17468 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17478 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17488 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17498 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17508 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17518 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17528 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17538 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17548 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17558 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17568 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17578 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17588 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17598 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17608 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17619 #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
17630 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17637 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17647 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17653 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
17661 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
17667 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17673 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
17681 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
17692 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
17699 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
17710 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
17717 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
17727 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17737 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17743 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17753 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17759 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17765 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17776 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17787 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17798 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17809 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17819 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17829 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17839 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17849 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17859 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17869 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17879 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17889 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17899 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2(x) (((uint16_t)(((uint16_t)(x…
17909 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2(x) (((uint16_t)(((uint16_t)(x…
17919 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17929 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17939 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17949 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17959 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17969 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17979 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17989 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18000 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18007 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18017 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18023 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
18031 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
18037 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18043 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
18054 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
18061 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
18072 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
18079 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
18089 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18095 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18105 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18111 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18117 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18128 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18139 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18150 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18161 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18171 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18181 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18191 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18201 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18211 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18221 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18231 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18241 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18251 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18261 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18271 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18281 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18291 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18301 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18311 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18321 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18331 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18341 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18351 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18361 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18371 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18381 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18401 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18411 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18421 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18431 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18441 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18451 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18461 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18471 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18481 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18491 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18501 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18511 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18521 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18531 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18541 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18551 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18561 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18571 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18581 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18591 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18601 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18612 #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
18623 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18630 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18640 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18646 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
18654 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
18660 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18666 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
18674 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
18685 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
18692 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
18703 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
18710 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
18720 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18730 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18736 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18746 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18752 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18758 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18769 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18780 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18791 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18802 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18812 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18822 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18832 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18842 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18852 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18862 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18872 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18882 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18892 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3(x) (((uint16_t)(((uint16_t)(x…
18902 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3(x) (((uint16_t)(((uint16_t)(x…
18912 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18922 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18932 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18942 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18952 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18962 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18972 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18982 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18993 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
19000 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
19010 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19016 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
19024 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
19030 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
19036 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
19047 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
19054 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
19065 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
19072 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
19082 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19088 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19098 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
19104 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
19110 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19121 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19132 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19143 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19154 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19164 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19174 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19184 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19194 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19204 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19214 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19224 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19234 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19244 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19254 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19264 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19274 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19284 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19294 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19304 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19314 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19324 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19334 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19344 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19354 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19364 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19374 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19384 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19394 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19404 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19414 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19424 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19434 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19444 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19454 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19464 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19474 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19484 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19494 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19504 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19514 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19524 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19534 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19544 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19554 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19564 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19574 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19584 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19594 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19642 __IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */
19643 __IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */
19645 …__I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0…
19646 …__I uint16_t PUBREV; /**< The hardware version of this PUB, excluding …
19666 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_D…
19673 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DR…
19684 #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DR…
19694 #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTU…
19704 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19710 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19716 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19752 …__IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status…
19771 #define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITEN…
19806 …__IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offs…
19807 __IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */
19809 …__IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to f…
19810 …__I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offse…
19811 …__IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., o…
19813 __IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */
19814 …__IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0…
19816 __IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */
19817 …__IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19818 …__IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19819 …__IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19820 …__IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19821 __I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */
19822 …__IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operation…
19824 __IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */
19826 …__I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offs…
19827 …__I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offs…
19828 …__IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset:…
19829 …__IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset:…
19830 …__IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces …
19831 …__IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Comm…
19832 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
19833 …__IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for deb…
19834 …__IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 …
19836 __IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */
19838 __IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */
19839 …__IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCL…
19840 …__IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dra…
19841 …__IO uint16_t DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause …
19842 …__IO uint16_t DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read an…
19843 …__IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram devi…
19844 …__IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select…
19845 …__IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:…
19846 …__IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training,…
19848 …__IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58…
19849 …__IO uint16_t DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI…
19850 …__IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Val…
19852 …__IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x7…
19854 …__IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offse…
19856 __IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */
19858 …__IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control,…
19859 …__IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offse…
19860 …__IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control,…
19862 …__IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength contro…
19864 …__IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control …
19866 …__IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAl…
19867 …__IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAl…
19869 …__IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, off…
19871 …__IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
19872 __IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */
19873 __I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */
19874 …__IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses …
19875 …__IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE…
19877 …__IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE…
19878 __IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */
19880 …__IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, off…
19881 __IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */
19883 __IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */
19885 …__IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110…
19886 …__IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x1…
19888 __IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */
19890 __IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */
19892 …__IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Don…
19894 …__I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0…
19895 …__IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls…
19897 …__IO uint16_t CALMISC; /**< Controls for disabling the impedance calibra…
19898 __I uint16_t CALVREFS; /**< , offset: 0x136 */
19899 …__I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: …
19900 …__I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: …
19901 …__I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: …
19903 …__IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, of…
19905 …__IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset…
19907 …__IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm tim…
19909 __IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */
19911 …__IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm tim…
19912 …__I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updat…
19913 …__I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interfa…
19914 …__I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interfa…
19915 …__I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Int…
19916 …__I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Int…
19917 …__I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Upd…
19918 …__I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Inter…
19919 …__I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Inter…
19920 …__IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x…
19922 __IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */
19923 __IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */
19924 …__IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, off…
19925 __IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */
19926 …__IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, off…
19927 …__IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 …
19928 __I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */
19929 …__IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of …
19930 __IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */
19931 …__IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, off…
19932 …__I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offse…
19933 …__I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output…
19934 __I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */
19936 …__IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing th…
19937 …__I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C…
19939 …__I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0…
19940 …__I uint16_t PHYREV; /**< The hardware version of this PHY, excluding …
19941 …__IO uint16_t LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit o…
19942 …__IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset…
19943 …__IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset…
19944 …__IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset…
19945 …__IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset…
19946 …__IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset…
19947 …__IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset…
19948 …__IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset…
19949 …__IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset…
19950 …__IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 …
19951 __IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */
19952 __IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */
19953 …__IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of t…
19955 __IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */
19956 …__IO uint16_t MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the…
19957 …__IO uint16_t MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the…
19958 …__IO uint16_t MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the…
19959 …__IO uint16_t MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the…
19960 …__IO uint16_t MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the…
19961 …__IO uint16_t MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the…
19962 …__IO uint16_t MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the…
19963 …__IO uint16_t MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the…
19964 …__IO uint16_t MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the…
19965 …__IO uint16_t MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the…
19967 …__IO uint16_t MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the…
19968 …__IO uint16_t MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the…
19969 …__IO uint16_t MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the…
19970 …__IO uint16_t MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the…
19971 …__IO uint16_t MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the…
19972 …__IO uint16_t MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the…
19973 …__IO uint16_t MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the…
19974 …__IO uint16_t MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the…
19975 …__IO uint16_t MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the…
19976 …__IO uint16_t MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the…
19978 __IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */
19979 …__IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x2…
19980 __IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */
19981 __IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */
19982 __I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */
19983 …__IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, of…
19984 …__IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, of…
19985 …__IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, of…
19986 …__IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, of…
19987 …__IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, of…
19988 …__IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, of…
19989 …__IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, of…
19990 …__IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, of…
19991 …__IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, of…
19992 …__IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, of…
19993 …__IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, of…
19994 …__IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, of…
19995 …__IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, of…
19996 …__IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, of…
19997 …__IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, of…
19998 …__IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, of…
19999 …__IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, of…
20000 …__IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, of…
20001 …__IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, of…
20002 …__IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, of…
20003 …__IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, of…
20004 …__IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, of…
20005 …__IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, of…
20006 …__IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, of…
20007 …__IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, of…
20008 …__IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, of…
20009 …__IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, of…
20011 …__IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshak…
20012 …__IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshak…
20014 …__IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0…
20016 …__IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20017 …__IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20018 …__IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20019 …__IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20021 …__IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operation…
20023 …__IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Comm…
20025 __IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */
20027 …__IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read an…
20029 …__IO uint16_t DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI…
20030 …__IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Val…
20032 …__IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control …
20034 __IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */
20036 …__IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20038 …__IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */
20040 …__IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20042 …__IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, off…
20044 …__IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, off…
20046 …__IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of …
20048 …__IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, off…
20050 __IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */
20052 …__IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0…
20054 …__IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20055 …__IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20056 …__IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20057 …__IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20059 …__IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operation…
20061 …__IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Comm…
20063 __IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */
20065 …__IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read an…
20067 …__IO uint16_t DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI…
20068 …__IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Val…
20070 …__IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control …
20072 __IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */
20074 …__IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20076 …__IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */
20078 …__IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20080 …__IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, off…
20082 …__IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, off…
20084 …__IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of …
20086 …__IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, off…
20088 __IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */
20090 …__IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0…
20092 …__IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20093 …__IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20094 …__IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20095 …__IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20097 …__IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operation…
20099 …__IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Comm…
20101 __IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */
20103 …__IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read an…
20105 …__IO uint16_t DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI…
20106 …__IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Val…
20108 …__IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control …
20110 __IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */
20112 …__IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20114 …__IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */
20116 …__IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20118 …__IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, off…
20120 …__IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, off…
20122 …__IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of …
20124 …__IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, off…
20126 __IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */
20145 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20151 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20163 #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20173 #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate(x) (((uint16_t)(((uint16_t)(x)) …
20183 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20189 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20195 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20205 #define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20215 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20221 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20231 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20238 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20244 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref(x) (((uint16_t)(((uint16_t)(x)) << DW…
20250 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20256 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20266 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20276 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20283 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20289 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20295 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20306 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20317 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20328 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20339 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20349 #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20359 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
20365 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
20375 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20381 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
20391 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20401 #define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20411 #define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20421 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20427 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20437 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20443 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20453 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20459 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20465 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
20475 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20481 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20487 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20497 #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20507 #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20517 #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20527 #define DWC_DDRPHYA_MASTER_PHYTID_PhyTID(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20538 #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20548 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20555 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20561 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20570 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20578 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20589 #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20599 #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20611 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
20618 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
20624 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
20631 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
20637 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
20644 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
20651 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
20661 #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20671 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20677 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20689 #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast(x) (((uint16_t)(((uint16_t)(x)) << D…
20699 #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20710 #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20720 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20730 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20740 #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode(x) (((uint16_t)(((uint16_t)(x)) << D…
20750 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20756 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20762 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20772 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20778 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20784 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20796 #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20808 #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20819 #define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20829 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20835 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20848 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20856 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20866 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20872 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20886 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20892 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20898 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20904 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20910 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20920 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20930 #define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20936 #define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20946 #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20957 #define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20967 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20973 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20983 #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20993 #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21003 #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21014 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21020 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21026 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21032 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21042 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21048 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21054 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21064 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase(x) (((uint16_t)(((uint16_t)…
21070 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x…
21076 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x…
21082 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved(x) (((uint16_t)(((uint16_t)(…
21088 …HYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21094 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase(x) (((uint16_t)(((uint16_t)(x)…
21104 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21111 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21117 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21127 #define DWC_DDRPHYA_MASTER_CALRATE_CalInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21133 #define DWC_DDRPHYA_MASTER_CALRATE_CalRun(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21139 #define DWC_DDRPHYA_MASTER_CALRATE_CalOnce(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21147 #define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates(x) (((uint16_t)(((uint16_t)(x)) << DW…
21157 #define DWC_DDRPHYA_MASTER_CALZAP_CalZap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21167 #define DWC_DDRPHYA_MASTER_PSTATE_PState(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21177 #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21187 #define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21197 #define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21207 #define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21213 #define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21220 #define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21226 #define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21236 #define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21244 #define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21252 #define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21262 #define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21272 #define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21282 #define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21292 #define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21302 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21308 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21314 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21320 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21326 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21336 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21342 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21348 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21359 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21366 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21373 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21380 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21396 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21405 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21411 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21417 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21428 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21435 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21442 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21449 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21459 #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21469 #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21479 #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21489 #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21499 #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21510 #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21521 #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21532 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21542 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21548 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21554 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21560 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21566 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21572 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21578 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21584 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21594 #define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21604 #define DWC_DDRPHYA_MASTER_PLLRESET_PllReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21614 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21624 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21630 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21636 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21643 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21649 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21655 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21661 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21667 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21673 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21679 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21685 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21691 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21697 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21703 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21713 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21719 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21729 #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21735 #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21741 #define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21751 #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21761 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21771 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21777 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21783 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21789 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21795 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21805 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
21811 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21821 #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21831 #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21841 #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21851 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
21857 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21864 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21870 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21883 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21893 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21899 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21905 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21911 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21917 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21927 #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21937 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21943 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21949 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21959 …STER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21965 …TER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21975 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21981 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21987 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21993 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22003 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22009 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22015 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22021 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22031 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22037 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22043 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22049 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22059 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22065 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22071 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22077 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22087 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22093 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22099 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22105 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22115 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22121 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22127 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22133 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22143 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22149 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22155 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22161 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22171 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22177 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22183 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22189 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22200 #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
22211 #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22222 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22232 #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks(x) (((uint16_t)(((uint16_t)(x)) << D…
22243 #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22253 #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22263 #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22273 #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22283 #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22293 #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22303 #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22313 #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22323 #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22333 #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22343 #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22353 #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22363 #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22373 #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22383 #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22393 #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22403 #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22413 #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22423 #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22433 #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22443 #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22453 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22459 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22465 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22471 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DW…
22477 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn(x) (((uint16_t)(((uint16_t)(x)) << …
22483 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn(x) (((uint16_t)(((uint16_t)(x)) << D…
22489 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DW…
22499 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << …
22505 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << …
22511 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW(x) (((uint16_t)(((uint16_t)(x)) << D…
22517 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW(x) (((uint16_t)(((uint16_t)(x)) <<…
22527 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22533 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22539 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22545 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22551 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk(x) (((uint16_t)(((uint16_t)(x)) << D…
22557 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk(x) (((uint16_t)(((uint16_t)(x)) << DW…
22563 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22573 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22579 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22585 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22591 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DW…
22597 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr(x) (((uint16_t)(((uint16_t)(x)) << …
22603 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr(x) (((uint16_t)(((uint16_t)(x)) << D…
22609 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DW…
22619 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22625 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22631 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
22637 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22643 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22649 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22655 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22665 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0(x) (((uint16_t)(((uint16_t)(…
22675 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1(x) (((uint16_t)(((uint16_t)(…
22685 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2(x) (((uint16_t)(((uint16_t)(…
22695 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3(x) (((uint16_t)(((uint16_t)(…
22705 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4(x) (((uint16_t)(((uint16_t)(…
22715 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5(x) (((uint16_t)(((uint16_t)(…
22725 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6(x) (((uint16_t)(((uint16_t)(…
22735 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7(x) (((uint16_t)(((uint16_t)(…
22745 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8(x) (((uint16_t)(((uint16_t)(…
22755 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9(x) (((uint16_t)(((uint16_t)(…
22765 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10(x) (((uint16_t)(((uint16_t…
22775 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11(x) (((uint16_t)(((uint16_t…
22785 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12(x) (((uint16_t)(((uint16_t…
22795 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13(x) (((uint16_t)(((uint16_t…
22805 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14(x) (((uint16_t)(((uint16_t…
22815 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15(x) (((uint16_t)(((uint16_t…
22825 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17(x) (((uint16_t)(((uint16_t…
22835 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN(x) (((uint16_t)(((uint16_t)(x)) << D…
22845 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0(x) (((uint16_t)(((uint16_t)(x)) <<…
22855 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1(x) (((uint16_t)(((uint16_t)(x)) <<…
22865 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2(x) (((uint16_t)(((uint16_t)(x)) <<…
22875 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22885 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22895 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN(x) (((uint16_t)(((uint16_t)(x)) << D…
22905 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN(x) (((uint16_t)(((uint16_t)(x)) << D…
22915 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22925 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn(x) (((uint16_t)(((uint16_t)(…
22936 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << D…
22942 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << D…
22948 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << …
22954 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << …
22965 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << D…
22971 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << D…
22977 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << …
22983 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << …
22993 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23004 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23015 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23026 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23037 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23047 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23053 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23063 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23069 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23075 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23086 #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23098 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23105 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23111 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23118 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23124 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23131 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23138 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23148 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23158 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23171 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23179 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23189 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23196 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23202 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23213 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23220 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23227 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23234 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23250 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23259 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23265 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23271 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23282 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23289 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23296 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23303 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23313 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
23323 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23329 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23339 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23349 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23355 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23366 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23376 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23387 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23398 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23409 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23420 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23430 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23436 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23446 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23452 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23458 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23469 #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23481 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23488 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23494 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23501 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23507 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23514 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23521 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23531 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23541 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23554 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23562 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23572 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23579 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23585 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23596 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23603 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23610 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23617 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23633 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23642 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23648 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23654 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23665 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23672 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23679 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23686 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23696 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
23706 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23712 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23722 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23732 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23738 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23749 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23759 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23770 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23781 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23792 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23803 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23813 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23819 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23829 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23835 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23841 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23852 #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23864 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23871 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23877 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23884 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23890 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23897 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23904 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23914 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23924 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23937 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23945 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23955 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23962 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23968 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23979 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23986 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23993 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24000 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24016 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
24025 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
24031 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
24037 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
24048 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24055 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24062 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24069 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24079 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
24089 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
24095 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
24105 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
24115 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
24121 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
24132 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
33574 __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */
33576 …__IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 …
33578 __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */
33580 __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */
33582 __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */
33599 #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT…
33607 #define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)…
33619 #define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIF…
33627 #define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIF…
33636 #define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT…
33644 #define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIF…
33652 #define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIF…
33660 #define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT…
33672 #define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIF…
33683 #define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT…
33691 #define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT…
33699 #define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT…
33707 #define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT…
33715 #define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIF…
33723 #define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT…
33731 #define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIF…
44112 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */
44113 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */
46435 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46447 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46451 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46459 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46463 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
47240 …__IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enab…
47245 …__I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, arr…
47249 …__IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x…
47251 …__IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, …
47513 #define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_S…
47522 #define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_S…
47531 #define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_S…
47540 #define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_S…
47548 #define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_S…
47556 #define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_S…
47564 #define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_S…
47572 #define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_S…
47581 #define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_…
47590 #define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_…
47599 #define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_…
47608 #define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_…
47617 #define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_…
47626 #define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_…
47635 #define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_S…
47644 #define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_S…
47655 #define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SH…
47659 #define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SH…
47663 #define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SH…
47667 #define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SH…
47671 #define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SH…
47675 #define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SH…
47679 #define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SH…
47683 #define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SH…
47687 #define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_S…
47691 #define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_S…
47695 #define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_S…
47699 #define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_S…
47703 #define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_S…
47707 #define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_S…
47711 #define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SH…
47715 #define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SH…
47726 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM…
47730 #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN…
47738 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNS…
47742 #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNT…
51381 …__I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0…
51385 …__I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset:…
51648 #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCI…
51716 #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCI…
55234 __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
55235 __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
55236 …__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 …
55237 …__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset:…
55238 …__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, off…
55259 #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHI…
55267 #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIF…
55275 #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT…
55283 #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT…
55291 #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT…
55299 #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT…
55307 #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT…
55315 #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT…
55326 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)…
55338 #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT…
55350 #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHI…
55358 #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHI…
55366 #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIF…
55380 #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHI…
55388 #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHI…
55396 #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIF…
55408 #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIF…