Lines Matching refs:uint16_t
13860 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
13862 …__IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), …
13863 …__IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0)…
13865 …__IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 …
13867 …__I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an en…
13869 …__IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls,…
13870 …__I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offse…
13872 …__IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: …
13874 …__IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: …
13876 …__IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: …
13878 …__IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: …
13897 #define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13911 #define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
13925 #define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
13935 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13941 #define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANI…
13951 #define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_A…
13961 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
13967 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
13973 #define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_A…
13983 #define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
13993 #define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14003 #define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14013 #define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14023 #define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_A…
14094 __IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */
14096 …__I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-on…
14098 __IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */
14099 …__IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset…
14100 …__I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, o…
14102 …__I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, o…
14104 …__IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid cs…
14106 …__IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the loc…
14108 …__I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Sha…
14127 #define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
14137 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14143 #define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow(x) (((uint16_t)(((uint16_t)(x)) << …
14153 #define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14163 #define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14173 #define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow(x) (((uint16_t)(((uint16_t)(x)) <…
14183 #define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow(x) (((uint16_t)(((uint16_t)…
14193 …RPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14203 #define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
14209 #define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_AP…
14215 #define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APB…
14221 #define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
14232 #define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow(x) (((uint16_t)(((uint16_t)…
14267 __IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */
14269 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
14271 __IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */
14273 …__IO uint16_t VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only …
14275 …__IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14276 __IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */
14278 __IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */
14280 …__IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., of…
14281 __IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */
14282 __IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */
14283 …__IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: …
14284 __IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */
14285 …__IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A…
14287 …__I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset…
14288 …__I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with…
14289 …__I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0x…
14290 __IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */
14291 __I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
14292 __I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
14293 __I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */
14295 __IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */
14297 …__IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14298 …__IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14299 …__IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14300 …__IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14302 …__IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14303 …__IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14304 …__IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14305 …__IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14307 …__IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14308 …__IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14309 …__IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14310 …__IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14311 …__IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14312 …__IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14313 …__IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14315 …__IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14317 …__IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset…
14319 …__IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14320 …__IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14321 …__IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14322 …__IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14324 …__IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14325 …__IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14326 …__IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14327 …__IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14329 …__I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C…
14331 …__IO uint16_t VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only …
14333 …__IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14334 __IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */
14336 __IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */
14338 __IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */
14340 …__IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: …
14342 …__IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29…
14344 __IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */
14346 …__IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14347 …__IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14348 …__IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14349 …__IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14351 …__IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14352 …__IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14353 …__IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14354 …__IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Gro…
14356 …__IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14357 …__IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14358 …__IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14359 …__IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14360 …__IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14361 …__IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14362 …__IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14364 …__IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14366 …__IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14367 …__IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14368 …__IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14369 …__IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14371 …__IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14372 …__IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14373 …__IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14374 …__IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14376 …__IO uint16_t VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only …
14378 …__IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14380 …__IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14381 …__IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14382 …__IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14383 …__IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14385 …__IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14386 …__IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14387 …__IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14388 …__IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14390 …__IO uint16_t VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only …
14392 …__IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14394 …__IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14395 …__IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14396 …__IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14397 …__IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14399 …__IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14400 …__IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14401 …__IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14402 …__IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14404 …__IO uint16_t VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only …
14406 …__IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14408 …__IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14409 …__IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14410 …__IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14411 …__IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14413 …__IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14414 …__IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14415 …__IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14416 …__IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14418 …__IO uint16_t VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only …
14420 …__IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14422 …__IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14423 …__IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14424 …__IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14425 …__IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14427 …__IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14428 …__IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14429 …__IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14430 …__IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14432 …__IO uint16_t VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only …
14434 …__IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14436 …__IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14437 …__IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14438 …__IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14439 …__IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14441 …__IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14442 …__IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14443 …__IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14444 …__IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14446 …__IO uint16_t VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only …
14448 …__IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14450 …__IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14451 …__IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14452 …__IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14453 …__IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14455 …__IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14456 …__IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14457 …__IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14458 …__IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14460 …__IO uint16_t VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only …
14462 …__IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x…
14464 …__IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0).,…
14465 …__IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1).,…
14466 …__IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2).,…
14467 …__IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3).,…
14469 …__IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14470 …__IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14471 …__IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14472 …__IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14474 __IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */
14476 …__IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082…
14478 __IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */
14480 …__IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., of…
14481 __IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */
14483 …__IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: …
14484 __IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */
14485 …__IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20…
14487 __IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */
14489 …__IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14490 …__IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14491 …__IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14492 …__IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14494 …__IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14495 …__IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14496 …__IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14497 …__IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14498 …__IO uint16_t RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14499 …__IO uint16_t RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14500 …__IO uint16_t RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14502 …__IO uint16_t RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14504 …__IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14505 …__IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14506 …__IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14507 …__IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14509 …__IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14510 …__IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14511 …__IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14512 …__IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14514 …__IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282…
14516 __IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */
14518 __IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */
14520 …__IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: …
14522 …__IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20…
14524 __IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */
14526 …__IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14527 …__IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14528 …__IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14529 …__IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Gro…
14531 …__IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14532 …__IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14533 …__IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14534 …__IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14535 …__IO uint16_t RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14536 …__IO uint16_t RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14537 …__IO uint16_t RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14539 …__IO uint16_t RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14541 …__IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14542 …__IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14543 …__IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14544 …__IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14546 …__IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14547 …__IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14548 …__IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14549 …__IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14551 …__IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14552 …__IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14553 …__IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14554 …__IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14556 …__IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14557 …__IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14558 …__IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14559 …__IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14561 …__IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14562 …__IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14563 …__IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14564 …__IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14566 …__IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14567 …__IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14568 …__IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14569 …__IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14571 …__IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14572 …__IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14573 …__IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14574 …__IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14576 …__IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14577 …__IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14578 …__IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14579 …__IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14581 …__IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14582 …__IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14583 …__IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14584 …__IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14586 __IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */
14588 …__IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082…
14590 __IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */
14592 …__IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., of…
14593 __IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */
14595 …__IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: …
14596 __IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */
14597 …__IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40…
14599 __IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */
14601 …__IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14602 …__IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14603 …__IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14604 …__IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14606 …__IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14607 …__IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14608 …__IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14609 …__IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14610 …__IO uint16_t RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14611 …__IO uint16_t RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14612 …__IO uint16_t RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14614 …__IO uint16_t RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14616 …__IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of trai…
14617 …__IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of trai…
14619 …__IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14620 …__IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14621 …__IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14622 …__IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14624 …__IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14625 …__IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14626 …__IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14627 …__IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14629 …__IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282…
14631 __IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */
14633 __IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */
14635 …__IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: …
14637 …__IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40…
14639 __IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */
14641 …__IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14642 …__IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14643 …__IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14644 …__IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Gro…
14646 …__IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14647 …__IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14648 …__IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14649 …__IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14650 …__IO uint16_t RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14651 …__IO uint16_t RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14652 …__IO uint16_t RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14654 …__IO uint16_t RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14656 …__IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14657 …__IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14658 …__IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14659 …__IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14661 …__IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14662 …__IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14663 …__IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14664 …__IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14666 …__IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14667 …__IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14668 …__IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14669 …__IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14671 …__IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14672 …__IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14673 …__IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14674 …__IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14676 …__IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14677 …__IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14678 …__IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14679 …__IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14681 …__IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14682 …__IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14683 …__IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14684 …__IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14686 …__IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14687 …__IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14688 …__IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14689 …__IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14691 …__IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14692 …__IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14693 …__IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14694 …__IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14696 …__IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14697 …__IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14698 …__IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14699 …__IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14701 __IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */
14703 …__IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082…
14705 __IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */
14707 …__IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., of…
14708 __IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */
14710 …__IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: …
14711 __IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */
14712 …__IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60…
14714 __IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */
14716 …__IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14717 …__IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14718 …__IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14719 …__IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14721 …__IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14722 …__IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14723 …__IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14724 …__IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14725 …__IO uint16_t RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14726 …__IO uint16_t RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14727 …__IO uint16_t RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14729 …__IO uint16_t RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14731 …__IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of trai…
14732 …__IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of trai…
14734 …__IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14735 …__IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14736 …__IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14737 …__IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14739 …__IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14740 …__IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14741 …__IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14742 …__IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14744 …__IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282…
14746 __IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */
14748 __IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */
14750 …__IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: …
14752 …__IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60…
14754 __IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */
14756 …__IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14757 …__IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14758 …__IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14759 …__IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Gro…
14761 …__IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14762 …__IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14763 …__IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14764 …__IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Grou…
14765 …__IO uint16_t RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14766 …__IO uint16_t RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14767 …__IO uint16_t RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14769 …__IO uint16_t RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing G…
14771 …__IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14772 …__IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14773 …__IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14774 …__IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14776 …__IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offs…
14777 …__IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offs…
14778 …__IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offs…
14779 …__IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offs…
14781 …__IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14782 …__IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14783 …__IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14784 …__IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14786 …__IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14787 …__IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14788 …__IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14789 …__IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14791 …__IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14792 …__IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14793 …__IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14794 …__IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14796 …__IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14797 …__IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14798 …__IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14799 …__IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14801 …__IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14802 …__IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14803 …__IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14804 …__IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14806 …__IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14807 …__IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14808 …__IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14809 …__IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14811 …__IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x…
14812 …__IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x…
14813 …__IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x…
14814 …__IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x…
14833 #define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
14843 #define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14854 #define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
14867 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14880 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
14891 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14898 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14908 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
14914 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
14922 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
14928 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
14934 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
14942 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
14953 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
14960 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
14970 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
14976 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
14982 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
14988 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
14999 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
15006 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
15016 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15026 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15032 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15042 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15049 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15055 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15062 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15072 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue(x) (((uint16_t)(((uint16_t)(x)) …
15078 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue(x) (((uint16_t)(((uint16_t)(x)) …
15084 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue(x) (((uint16_t)(((uint16_t)(x))…
15090 #define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue(x) (((uint16_t)(((uint16_t)(x))…
15100 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBY…
15106 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBY…
15112 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15118 #define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15131 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
15138 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15144 #define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15155 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210(x) (((uint16_t)(((uint16_t)(x))…
15166 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654(x) (((uint16_t)(((uint16_t)(x))…
15180 #define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI(x) (((uint16_t)(((uint16_t)(x)) << DW…
15190 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15196 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15202 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15212 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15222 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15232 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15242 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15253 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15264 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15275 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15286 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15296 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15306 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15316 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15326 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15336 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15346 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15356 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15366 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15376 #define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
15389 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15399 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15409 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15419 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15429 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15439 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15449 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15459 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15469 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
15475 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15481 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15487 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15493 #define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15506 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15519 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15530 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15537 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15547 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15553 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
15561 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15567 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
15573 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
15584 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
15591 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
15602 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
15609 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
15619 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15625 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15635 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15641 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15647 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
15657 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15667 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15677 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15687 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15698 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15709 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15720 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15731 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15741 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15751 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15761 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15771 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15781 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15791 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15801 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15811 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
15821 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15831 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15841 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15851 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15861 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15871 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15881 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15891 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
15904 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15917 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
15927 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15937 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15947 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15957 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
15967 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15977 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15987 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
15997 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16010 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16023 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16033 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16043 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16053 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16063 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16073 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16083 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16093 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16103 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16116 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16129 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16139 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16149 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16159 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16169 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16179 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16189 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16199 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16209 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16222 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16235 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16245 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16255 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16265 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16275 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16285 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16295 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16305 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16315 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16328 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16341 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16351 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16361 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16371 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16381 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16391 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16401 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16411 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16421 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16434 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16447 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16457 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16467 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16477 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16487 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16497 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16507 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16517 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16527 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16540 #define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16553 #define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16563 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16573 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16583 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16593 #define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16603 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16613 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16623 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16633 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16644 #define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
16655 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16662 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16672 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16678 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
16686 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
16692 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16698 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
16706 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
16717 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
16724 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
16735 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
16742 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
16752 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
16762 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16768 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16778 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16784 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
16790 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
16801 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16812 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16823 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16834 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16844 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16854 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16864 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16874 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16884 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16894 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16904 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16914 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
16924 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16934 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16944 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16954 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
16964 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16974 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16984 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
16994 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17005 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17012 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17022 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17028 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
17036 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
17042 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17048 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
17059 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
17066 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
17077 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
17084 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
17094 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17100 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17110 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17116 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17122 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17133 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17144 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17155 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17166 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17176 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17186 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17196 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17206 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17216 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17226 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17236 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17246 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17256 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17266 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17276 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17286 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17296 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17306 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17316 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17326 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17336 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17346 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17356 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17366 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17376 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17386 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17396 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17406 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17416 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17426 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17436 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17446 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17456 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17466 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17476 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17486 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17496 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17506 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17516 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17526 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17536 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17546 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17556 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17566 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17576 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17586 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17596 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17606 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17617 #define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
17628 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17635 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17645 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17651 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
17659 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
17665 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17671 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
17679 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
17690 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
17697 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
17708 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
17715 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
17725 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
17735 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17741 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17751 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17757 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
17763 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
17774 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17785 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17796 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17807 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17817 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17827 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17837 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17847 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17857 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17867 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17877 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17887 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
17897 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2(x) (((uint16_t)(((uint16_t)(x…
17907 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2(x) (((uint16_t)(((uint16_t)(x…
17917 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17927 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17937 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17947 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
17957 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17967 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17977 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17987 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
17998 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18005 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18015 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18021 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
18029 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
18035 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18041 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
18052 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
18059 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
18070 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
18077 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
18087 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18093 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18103 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18109 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18115 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18126 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18137 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18148 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18159 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18169 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18179 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18189 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18199 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18209 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18219 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18229 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18239 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18249 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18259 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18269 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18279 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18289 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18299 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18309 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18319 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18329 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18339 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18349 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18359 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18369 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18379 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18389 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18399 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18409 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18419 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18429 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18439 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18449 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18459 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18469 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18479 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18489 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18499 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18509 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18519 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18529 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18539 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18549 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18559 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18569 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18579 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18589 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18599 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18610 #define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_…
18621 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18628 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18638 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18644 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
18652 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
18658 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18664 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
18672 #define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
18683 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
18690 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
18701 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
18708 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
18718 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18728 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18734 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18744 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18750 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
18756 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
18767 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18778 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18789 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18800 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18810 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18820 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18830 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18840 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18850 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18860 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18870 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18880 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
18890 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3(x) (((uint16_t)(((uint16_t)(x…
18900 #define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3(x) (((uint16_t)(((uint16_t)(x…
18910 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18920 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18930 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18940 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
18950 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18960 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18970 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18980 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
18991 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP(x) (((uint16_t)(((uint16_t)(x)) << DWC…
18998 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
19008 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19014 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
19022 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
19028 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte(x) (((uint16_t)(((uint16_t)(x)) << DWC…
19034 #define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
19045 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP(x) (((uint16_t)(((uint16_t)(x)) << D…
19052 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN(x) (((uint16_t)(((uint16_t)(x)) << D…
19063 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP(x) (((uint16_t)(((uint16_t)(x)) <<…
19070 #define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN(x) (((uint16_t)(((uint16_t)(x)) <<…
19080 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19086 #define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19096 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
19102 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DB…
19108 #define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
19119 #define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19130 #define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19141 #define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19152 #define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19162 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19172 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19182 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19192 #define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19202 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19212 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19222 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19232 #define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << …
19242 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19252 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19262 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19272 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19282 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19292 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19302 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19312 #define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px(x) (((uint16_t)(((uint16_t)(x)) << DW…
19322 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19332 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19342 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19352 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19362 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19372 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19382 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19392 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19402 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19412 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19422 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19432 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19442 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19452 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19462 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19472 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19482 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19492 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19502 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19512 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19522 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19532 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19542 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19552 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19562 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19572 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19582 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19592 #define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
19640 __IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */
19641 __IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */
19643 …__I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0…
19644 …__I uint16_t PUBREV; /**< The hardware version of this PUB, excluding …
19664 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_D…
19671 #define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DR…
19682 #define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DR…
19692 #define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTU…
19702 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19708 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19714 #define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_…
19750 …__IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status…
19769 #define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITEN…
19804 …__IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offs…
19805 __IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */
19807 …__IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to f…
19808 …__I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offse…
19809 …__IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., o…
19811 __IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */
19812 …__IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0…
19814 __IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */
19815 …__IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19816 …__IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19817 …__IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19818 …__IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Regist…
19819 __I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */
19820 …__IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operation…
19822 __IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */
19824 …__I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offs…
19825 …__I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offs…
19826 …__IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset:…
19827 …__IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset:…
19828 …__IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces …
19829 …__IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Comm…
19830 …__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x3…
19831 …__IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for deb…
19832 …__IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 …
19834 __IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */
19836 __IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */
19837 …__IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCL…
19838 …__IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dra…
19839 …__IO uint16_t DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause …
19840 …__IO uint16_t DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read an…
19841 …__IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram devi…
19842 …__IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select…
19843 …__IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:…
19844 …__IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training,…
19846 …__IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58…
19847 …__IO uint16_t DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI…
19848 …__IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Val…
19850 …__IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x7…
19852 …__IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offse…
19854 __IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */
19856 …__IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control,…
19857 …__IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offse…
19858 …__IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control,…
19860 …__IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength contro…
19862 …__IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control …
19864 …__IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAl…
19865 …__IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAl…
19867 …__IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, off…
19869 …__IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
19870 __IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */
19871 __I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */
19872 …__IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses …
19873 …__IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE…
19875 …__IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE…
19876 __IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */
19878 …__IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, off…
19879 __IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */
19881 __IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */
19883 …__IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110…
19884 …__IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x1…
19886 __IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */
19888 __IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */
19890 …__IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Don…
19892 …__I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0…
19893 …__IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls…
19895 …__IO uint16_t CALMISC; /**< Controls for disabling the impedance calibra…
19896 __I uint16_t CALVREFS; /**< , offset: 0x136 */
19897 …__I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: …
19898 …__I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: …
19899 …__I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: …
19901 …__IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, of…
19903 …__IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset…
19905 …__IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm tim…
19907 __IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */
19909 …__IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm tim…
19910 …__I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updat…
19911 …__I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interfa…
19912 …__I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interfa…
19913 …__I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Int…
19914 …__I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Int…
19915 …__I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Upd…
19916 …__I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Inter…
19917 …__I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Inter…
19918 …__IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x…
19920 __IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */
19921 __IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */
19922 …__IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, off…
19923 __IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */
19924 …__IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, off…
19925 …__IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 …
19926 __I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */
19927 …__IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of …
19928 __IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */
19929 …__IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, off…
19930 …__I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offse…
19931 …__I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output…
19932 __I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */
19934 …__IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing th…
19935 …__I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C…
19937 …__I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0…
19938 …__I uint16_t PHYREV; /**< The hardware version of this PHY, excluding …
19939 …__IO uint16_t LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit o…
19940 …__IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset…
19941 …__IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset…
19942 …__IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset…
19943 …__IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset…
19944 …__IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset…
19945 …__IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset…
19946 …__IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset…
19947 …__IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset…
19948 …__IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 …
19949 __IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */
19950 __IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */
19951 …__IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of t…
19953 __IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */
19954 …__IO uint16_t MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the…
19955 …__IO uint16_t MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the…
19956 …__IO uint16_t MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the…
19957 …__IO uint16_t MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the…
19958 …__IO uint16_t MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the…
19959 …__IO uint16_t MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the…
19960 …__IO uint16_t MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the…
19961 …__IO uint16_t MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the…
19962 …__IO uint16_t MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the…
19963 …__IO uint16_t MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the…
19965 …__IO uint16_t MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the…
19966 …__IO uint16_t MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the…
19967 …__IO uint16_t MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the…
19968 …__IO uint16_t MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the…
19969 …__IO uint16_t MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the…
19970 …__IO uint16_t MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the…
19971 …__IO uint16_t MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the…
19972 …__IO uint16_t MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the…
19973 …__IO uint16_t MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the…
19974 …__IO uint16_t MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the…
19976 __IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */
19977 …__IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x2…
19978 __IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */
19979 __IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */
19980 __I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */
19981 …__IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, of…
19982 …__IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, of…
19983 …__IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, of…
19984 …__IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, of…
19985 …__IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, of…
19986 …__IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, of…
19987 …__IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, of…
19988 …__IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, of…
19989 …__IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, of…
19990 …__IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, of…
19991 …__IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, of…
19992 …__IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, of…
19993 …__IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, of…
19994 …__IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, of…
19995 …__IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, of…
19996 …__IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, of…
19997 …__IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, of…
19998 …__IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, of…
19999 …__IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, of…
20000 …__IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, of…
20001 …__IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, of…
20002 …__IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, of…
20003 …__IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, of…
20004 …__IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, of…
20005 …__IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, of…
20006 …__IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, of…
20007 …__IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, of…
20009 …__IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshak…
20010 …__IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshak…
20012 …__IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0…
20014 …__IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20015 …__IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20016 …__IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20017 …__IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Regist…
20019 …__IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operation…
20021 …__IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Comm…
20023 __IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */
20025 …__IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read an…
20027 …__IO uint16_t DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI…
20028 …__IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Val…
20030 …__IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control …
20032 __IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */
20034 …__IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20036 …__IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */
20038 …__IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20040 …__IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, off…
20042 …__IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, off…
20044 …__IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of …
20046 …__IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, off…
20048 __IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */
20050 …__IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0…
20052 …__IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20053 …__IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20054 …__IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20055 …__IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Regist…
20057 …__IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operation…
20059 …__IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Comm…
20061 __IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */
20063 …__IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read an…
20065 …__IO uint16_t DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI…
20066 …__IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Val…
20068 …__IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control …
20070 __IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */
20072 …__IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20074 …__IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */
20076 …__IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20078 …__IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, off…
20080 …__IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, off…
20082 …__IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of …
20084 …__IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, off…
20086 __IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */
20088 …__IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0…
20090 …__IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20091 …__IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20092 …__IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20093 …__IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Regist…
20095 …__IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operation…
20097 …__IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Comm…
20099 __IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */
20101 …__IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read an…
20103 …__IO uint16_t DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI…
20104 …__IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Val…
20106 …__IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control …
20108 __IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */
20110 …__IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20112 …__IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */
20114 …__IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm tim…
20116 …__IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, off…
20118 …__IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, off…
20120 …__IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of …
20122 …__IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, off…
20124 __IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */
20143 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20149 #define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20161 #define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20171 #define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate(x) (((uint16_t)(((uint16_t)(x)) …
20181 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20187 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20193 #define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20203 #define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20213 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20219 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20229 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20236 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20242 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref(x) (((uint16_t)(((uint16_t)(x)) << DW…
20248 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20254 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20264 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20274 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20281 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20287 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20293 #define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20304 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20315 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20326 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20337 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20347 #define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20357 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
20363 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
20373 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20379 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
20389 #define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20399 #define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20409 #define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20419 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20425 #define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20435 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20441 #define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20451 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20457 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20463 #define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
20473 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
20479 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20485 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20495 #define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20505 #define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20515 #define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20525 #define DWC_DDRPHYA_MASTER_PHYTID_PhyTID(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20536 #define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20546 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20553 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20559 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20568 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
20576 #define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20587 #define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20597 #define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20609 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
20616 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
20622 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
20629 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
20635 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
20642 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
20649 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
20659 #define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
20669 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20675 #define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
20687 #define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast(x) (((uint16_t)(((uint16_t)(x)) << D…
20697 #define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20708 #define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20718 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20728 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20738 #define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode(x) (((uint16_t)(((uint16_t)(x)) << D…
20748 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20754 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20760 #define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20770 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
20776 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20782 #define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20794 #define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20806 #define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
20817 #define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20827 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20833 #define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20846 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20854 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20864 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20870 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20884 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
20890 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20896 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
20902 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20908 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20918 #define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC…
20928 #define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
20934 #define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20944 #define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
20955 #define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
20965 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
20971 #define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
20981 #define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
20991 #define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21001 #define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21012 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21018 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21024 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21030 #define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21040 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21046 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21052 #define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21062 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase(x) (((uint16_t)(((uint16_t)…
21068 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x…
21074 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase(x) (((uint16_t)(((uint16_t)(x…
21080 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved(x) (((uint16_t)(((uint16_t)(…
21086 …HYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21092 #define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase(x) (((uint16_t)(((uint16_t)(x)…
21102 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21109 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21115 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21125 #define DWC_DDRPHYA_MASTER_CALRATE_CalInterval(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21131 #define DWC_DDRPHYA_MASTER_CALRATE_CalRun(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21137 #define DWC_DDRPHYA_MASTER_CALRATE_CalOnce(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21145 #define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates(x) (((uint16_t)(((uint16_t)(x)) << DW…
21155 #define DWC_DDRPHYA_MASTER_CALZAP_CalZap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21165 #define DWC_DDRPHYA_MASTER_PSTATE_PState(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21175 #define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21185 #define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21195 #define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21205 #define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21211 #define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21218 #define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21224 #define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21234 #define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21242 #define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21250 #define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21260 #define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21270 #define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21280 #define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21290 #define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21300 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21306 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21312 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21318 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21324 #define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21334 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21340 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21346 #define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21357 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21364 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21371 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21378 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21394 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21403 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21409 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21415 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
21426 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21433 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21440 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21447 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21457 #define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21467 #define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21477 #define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21487 #define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21497 #define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21508 #define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21519 #define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21530 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21540 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21546 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21552 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21558 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21564 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21570 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21576 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21582 #define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21592 #define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21602 #define DWC_DDRPHYA_MASTER_PLLRESET_PllReset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21612 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21622 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21628 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21634 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21641 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21647 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21653 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21659 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21665 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21671 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21677 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21683 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21689 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21695 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21701 #define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
21711 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21717 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21727 #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21733 #define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21739 #define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
21749 #define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21759 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21769 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21775 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21781 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21787 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAST…
21793 #define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21803 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
21809 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21819 #define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21829 #define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21839 #define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21849 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
21855 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
21862 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
21868 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21881 #define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
21891 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
21897 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21903 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
21909 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
21915 #define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
21925 #define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MAS…
21935 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21941 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21947 #define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER…
21957 …STER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21963 …TER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed(x) (((uint16_t)(((uint16_t)(x)) << DWC…
21973 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21979 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21985 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
21991 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22001 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22007 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22013 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22019 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22029 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22035 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRP…
22041 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22047 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22057 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22063 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22069 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22075 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22085 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22091 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22097 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22103 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22113 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22119 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22125 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22131 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22141 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22147 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22153 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22159 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22169 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22175 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22181 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22187 #define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
22198 #define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
22209 #define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22220 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22230 #define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks(x) (((uint16_t)(((uint16_t)(x)) << D…
22241 #define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22251 #define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22261 #define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22271 #define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22281 #define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22291 #define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22301 #define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22311 #define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22321 #define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22331 #define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22341 #define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22351 #define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22361 #define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22371 #define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22381 #define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22391 #define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22401 #define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22411 #define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22421 #define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22431 #define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22441 #define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
22451 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22457 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22463 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22469 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DW…
22475 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn(x) (((uint16_t)(((uint16_t)(x)) << …
22481 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn(x) (((uint16_t)(((uint16_t)(x)) << D…
22487 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn(x) (((uint16_t)(((uint16_t)(x)) << DW…
22497 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << …
22503 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW(x) (((uint16_t)(((uint16_t)(x)) << …
22509 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW(x) (((uint16_t)(((uint16_t)(x)) << D…
22515 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW(x) (((uint16_t)(((uint16_t)(x)) <<…
22525 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22531 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22537 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22543 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22549 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk(x) (((uint16_t)(((uint16_t)(x)) << D…
22555 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk(x) (((uint16_t)(((uint16_t)(x)) << DW…
22561 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22571 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22577 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22583 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22589 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DW…
22595 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr(x) (((uint16_t)(((uint16_t)(x)) << …
22601 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr(x) (((uint16_t)(((uint16_t)(x)) << D…
22607 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr(x) (((uint16_t)(((uint16_t)(x)) << DW…
22617 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22623 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22629 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
22635 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22641 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
22647 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22653 #define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
22663 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0(x) (((uint16_t)(((uint16_t)(…
22673 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1(x) (((uint16_t)(((uint16_t)(…
22683 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2(x) (((uint16_t)(((uint16_t)(…
22693 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3(x) (((uint16_t)(((uint16_t)(…
22703 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4(x) (((uint16_t)(((uint16_t)(…
22713 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5(x) (((uint16_t)(((uint16_t)(…
22723 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6(x) (((uint16_t)(((uint16_t)(…
22733 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7(x) (((uint16_t)(((uint16_t)(…
22743 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8(x) (((uint16_t)(((uint16_t)(…
22753 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9(x) (((uint16_t)(((uint16_t)(…
22763 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10(x) (((uint16_t)(((uint16_t…
22773 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11(x) (((uint16_t)(((uint16_t…
22783 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12(x) (((uint16_t)(((uint16_t…
22793 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13(x) (((uint16_t)(((uint16_t…
22803 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14(x) (((uint16_t)(((uint16_t…
22813 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15(x) (((uint16_t)(((uint16_t…
22823 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17(x) (((uint16_t)(((uint16_t…
22833 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN(x) (((uint16_t)(((uint16_t)(x)) << D…
22843 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0(x) (((uint16_t)(((uint16_t)(x)) <<…
22853 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1(x) (((uint16_t)(((uint16_t)(x)) <<…
22863 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2(x) (((uint16_t)(((uint16_t)(x)) <<…
22873 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22883 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22893 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN(x) (((uint16_t)(((uint16_t)(x)) << D…
22903 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN(x) (((uint16_t)(((uint16_t)(x)) << D…
22913 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN(x) (((uint16_t)(((uint16_t)(x)) << DWC…
22923 #define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn(x) (((uint16_t)(((uint16_t)(…
22934 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << D…
22940 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << D…
22946 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0(x) (((uint16_t)(((uint16_t)(x)) << …
22952 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0(x) (((uint16_t)(((uint16_t)(x)) << …
22963 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << D…
22969 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << D…
22975 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1(x) (((uint16_t)(((uint16_t)(x)) << …
22981 #define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1(x) (((uint16_t)(((uint16_t)(x)) << …
22991 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23002 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23013 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23024 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23035 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23045 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23051 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23061 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23067 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23073 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23084 #define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23096 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23103 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23109 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23116 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23122 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23129 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23136 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23146 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23156 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23169 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23177 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23187 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23194 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23200 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23211 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23218 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23225 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23232 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23248 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23257 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23263 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23269 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23280 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23287 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23294 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23301 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23311 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
23321 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23327 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23337 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23347 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23353 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23364 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23374 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23385 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23396 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23407 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23418 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23428 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23434 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23444 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23450 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23456 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23467 #define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23479 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23486 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23492 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23499 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23505 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23512 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23519 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23529 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23539 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23552 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23560 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23570 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23577 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23583 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23594 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23601 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23608 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23615 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23631 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23640 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23646 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23652 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23663 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23670 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23677 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23684 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23694 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
23704 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23710 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23720 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23730 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23736 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23747 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23757 #define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23768 #define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23779 #define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23790 #define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23801 #define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
23811 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval(x) (((uint16_t)(((uint16_t)(x)) <<…
23817 #define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck(x) (((uint16_t)(((uint16_t)(x)) << D…
23827 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri(x) (((uint16_t)(((uint16_t)(x)) << DWC_DD…
23833 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
23839 #define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
23850 #define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTE…
23862 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23869 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x)) << …
23875 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit(x) (((uint16_t)(((uint16_t)(x)) <<…
23882 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre(x) (((uint16_t)(((uint16_t)(x…
23888 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt(x) (((uint16_t)(((uint16_t)(x)) <<…
23895 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn(x) (((uint16_t)(((uint16_t)(x…
23902 #define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << D…
23912 #define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
23922 #define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23935 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
23943 #define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
23953 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23960 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_M…
23966 #define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
23977 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23984 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23991 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
23998 #define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24014 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
24023 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
24029 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
24035 #define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode(x) (((uint16_t)(((uint16_t)(x)) << DWC_…
24046 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24053 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24060 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24067 #define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3(x) (((uint16_t)(((uint16_t)(x)) << DWC…
24077 #define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MA…
24087 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_…
24093 #define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA…
24103 #define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDR…
24113 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHY…
24119 #define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPH…
24130 #define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3(x) (((uint16_t)(((uint16_t)(x)) << DWC_D…
33572 __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */
33574 …__IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 …
33576 __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */
33578 __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */
33580 __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */
33597 #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT…
33605 #define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)…
33617 #define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIF…
33625 #define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIF…
33634 #define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT…
33642 #define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIF…
33650 #define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIF…
33658 #define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT…
33670 #define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIF…
33681 #define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT…
33689 #define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT…
33697 #define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT…
33705 #define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT…
33713 #define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIF…
33721 #define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT…
33729 #define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIF…
44110 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */
44111 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */
46433 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46445 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46449 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46457 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
46461 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTG…
47238 …__IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enab…
47243 …__I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, arr…
47247 …__IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x…
47249 …__IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, …
47511 #define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_S…
47520 #define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_S…
47529 #define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_S…
47538 #define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_S…
47546 #define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_S…
47554 #define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_S…
47562 #define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_S…
47570 #define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_S…
47579 #define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_…
47588 #define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_…
47597 #define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_…
47606 #define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_…
47615 #define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_…
47624 #define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_…
47633 #define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_S…
47642 #define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_S…
47653 #define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SH…
47657 #define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SH…
47661 #define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SH…
47665 #define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SH…
47669 #define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SH…
47673 #define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SH…
47677 #define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SH…
47681 #define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SH…
47685 #define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_S…
47689 #define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_S…
47693 #define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_S…
47697 #define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_S…
47701 #define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_S…
47705 #define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_S…
47709 #define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SH…
47713 #define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SH…
47724 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM…
47728 #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN…
47736 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNS…
47740 #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNT…
51379 …__I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0…
51383 …__I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset:…
51646 #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCI…
51714 #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCI…
55232 __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
55233 __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
55234 …__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 …
55235 …__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset:…
55236 …__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, off…
55257 #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHI…
55265 #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIF…
55273 #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT…
55281 #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT…
55289 #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT…
55297 #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT…
55305 #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT…
55313 #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT…
55324 #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)…
55336 #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT…
55348 #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHI…
55356 #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHI…
55364 #define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIF…
55378 #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHI…
55386 #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHI…
55394 #define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIF…
55406 #define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIF…