Lines Matching +full:cc +full:- +full:include
12 ** Version: rev. 1.0, 2024-03-21
18 ** Copyright 1997-2016 Freescale Semiconductor, Inc.
19 ** Copyright 2016-2024 NXP
20 ** SPDX-License-Identifier: BSD-3-Clause
26 ** - rev. 1.0 (2024-03-21)
35 * @date 2024-03-21
51 /* ----------------------------------------------------------------------------
52 -- Interrupt vector numbers
53 ---------------------------------------------------------------------------- */
65 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
68 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
69 HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */
70 MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */
71 BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */
72 UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */
73 SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */
74 SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */
77 SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */
102 WUU0_IRQn = 22, /**< Wake-Up Unit 0 interrupt */
110 ELE_NONSECURE_IRQn = 30, /**< EdgeLock enclave non-secure interrupt */
114 LPTMR0_IRQn = 34, /**< Low-Power Timer0 interrupt */
115 LPTMR1_IRQn = 35, /**< Low-Power Timer1 interrupt */
116 …LPIT0_IRQn = 36, /**< Low-Power Periodic Interrupt Timer 0 interru…
119 …LPI2C0_IRQn = 39, /**< Low-Power Inter Integrated Circuit 0 interru…
120 …LPI2C1_IRQn = 40, /**< Low-Power Inter Integrated Circuit 1 interru…
121 …I3C0_IRQn = 41, /**< Improved Inter-Integrated Circuit 0 interrup…
122 …LPSPI0_IRQn = 42, /**< Low-Power Serial Peripheral Interface 0 inte…
123 …LPSPI1_IRQn = 43, /**< Low-Power Serial Peripheral Interface 1 inte…
124 …LPUART0_IRQn = 44, /**< Low-Power Universal Asynchronous Receiver/Tr…
125 …LPUART1_IRQn = 45, /**< Low-Power Universal Asynchronous Receiver/Tr…
133 …RF_802_15_4_IRQn = 53, /**< Radio Frequency 2.4GHz - 802.15.4 Link Layer…
134 …RF_Generic_IRQn = 54, /**< Radio Frequency 2.4 GHz - Generic Link Layer…
135 RF_BRIC_IRQn = 55, /**< Radio Frequency 2.4 GHz - BRIC interrupt */
136 …RF_LANT_SW_IRQn = 56, /**< Radio Transceiver - Radio LANT_SW interrupt …
151 ADC0_IRQn = 71, /**< Analog-to-Digital Converter 0 interrupt */
152 LPCMP0_IRQn = 72, /**< Low-Power Comparator 0 interrupt */
153 LPCMP1_IRQn = 73, /**< Low-Power Comparator 1 interrupt */
163 /* ----------------------------------------------------------------------------
164 -- Cortex M33 Core Configuration
165 ---------------------------------------------------------------------------- */
176 #define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP…
179 #include "core_cm33.h" /* Core Peripheral Access Layer */
180 #include "system_MCXW716A.h" /* Device specific configuration file */
187 /* ----------------------------------------------------------------------------
188 -- Mapping Information
189 ---------------------------------------------------------------------------- */
306 kTRDC_SlaveFlash = 0U, /**< Flash - 1MB */
307 kTRDC_SlaveFlashIFR0 = 1U, /**< Flash IFR0 - 32 KB */
308 kTRDC_SlaveFlashIFR1 = 2U, /**< Flash IFR1 - 8 KB */
309 kTRDC_SlaveROM = 3U, /**< ROM - 96KB */
319 kTRDC_SlaveCTCM0_1 = 0U, /**< CTCM0,1 - 16 KB (with ECC) */
320 kTRDC_SlaveSTCM0_1_2 = 1U, /**< STCM0,1,2 - 16,16,32 KB (with ECC) */
321 kTRDC_SlaveSTCM3_4 = 2U, /**< STCM3,4 - 32,8 KB (with ECC) */
322 kTRDC_SlaveSTCM5 = 3U, /**< STCM5 - 8 KB (with ECC) */
411 kTRGMUX_SourceAdcGp0Output0 = 59U, /**< ADC-GP0 Trigger Output 0 is selected */
412 kTRGMUX_SourceAdcGp0Output1 = 60U, /**< ADC-GP0 Trigger Output 1 is selected */
413 kTRGMUX_SourceAdcGp0Output2 = 61U, /**< ADC-GP0 Trigger Output 2 is selected */
414 kTRGMUX_SourceAdcGp0Output3 = 62U, /**< ADC-GP0 Trigger Output 3 is selected */
415 kTRGMUX_SourceCmpGp0Output = 63U, /**< CMP-GP0 Comparator Output is selected */
416 kTRGMUX_SourceCmpGp1Output = 64U, /**< CMP-GP1 Comparator Output is selected */
418 kTRGMUX_SourceRf2p4gTofTimestamp = 66U, /**< RF-2.4G TOF TIMESTAMP TRIG is selected */
419 kTRGMUX_SourceRf2p4gLantSw = 67U, /**< RF-2.4G LANT_SW is selected */
455 /* ----------------------------------------------------------------------------
456 -- Device Peripheral Access Layer
457 ---------------------------------------------------------------------------- */
484 /* ----------------------------------------------------------------------------
485 -- ADC Peripheral Access Layer
486 ---------------------------------------------------------------------------- */
493 /** ADC - Register Layout Typedef */
525 …__IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset…
526 …__IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset…
527 …__IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset…
528 …__IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset…
529 …__IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset…
530 …__IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset…
531 …__IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset…
532 …__IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset…
533 …__IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset…
534 …__IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset…
535 …__IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset…
536 …__IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset…
537 …__IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset…
538 …__IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset…
539 …__IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset…
540 …__IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset…
541 …__IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset…
542 …__IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset…
543 …__IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset…
544 …__IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset…
545 …__IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset…
546 …__IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset…
547 …__IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset…
548 …__IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset…
549 …__IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset…
550 …__IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset…
551 …__IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset…
552 …__IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset…
553 …__IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset…
554 …__IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset…
555 …__IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset…
556 …__IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset…
557 …__IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset…
559 …__IO uint32_t CAL_GBR0; /**< Calibration General B-Side Registers, offset…
560 …__IO uint32_t CAL_GBR1; /**< Calibration General B-Side Registers, offset…
561 …__IO uint32_t CAL_GBR2; /**< Calibration General B-Side Registers, offset…
562 …__IO uint32_t CAL_GBR3; /**< Calibration General B-Side Registers, offset…
563 …__IO uint32_t CAL_GBR4; /**< Calibration General B-Side Registers, offset…
564 …__IO uint32_t CAL_GBR5; /**< Calibration General B-Side Registers, offset…
565 …__IO uint32_t CAL_GBR6; /**< Calibration General B-Side Registers, offset…
566 …__IO uint32_t CAL_GBR7; /**< Calibration General B-Side Registers, offset…
567 …__IO uint32_t CAL_GBR8; /**< Calibration General B-Side Registers, offset…
568 …__IO uint32_t CAL_GBR9; /**< Calibration General B-Side Registers, offset…
569 …__IO uint32_t CAL_GBR10; /**< Calibration General B-Side Registers, offset…
570 …__IO uint32_t CAL_GBR11; /**< Calibration General B-Side Registers, offset…
571 …__IO uint32_t CAL_GBR12; /**< Calibration General B-Side Registers, offset…
572 …__IO uint32_t CAL_GBR13; /**< Calibration General B-Side Registers, offset…
573 …__IO uint32_t CAL_GBR14; /**< Calibration General B-Side Registers, offset…
574 …__IO uint32_t CAL_GBR15; /**< Calibration General B-Side Registers, offset…
575 …__IO uint32_t CAL_GBR16; /**< Calibration General B-Side Registers, offset…
576 …__IO uint32_t CAL_GBR17; /**< Calibration General B-Side Registers, offset…
577 …__IO uint32_t CAL_GBR18; /**< Calibration General B-Side Registers, offset…
578 …__IO uint32_t CAL_GBR19; /**< Calibration General B-Side Registers, offset…
579 …__IO uint32_t CAL_GBR20; /**< Calibration General B-Side Registers, offset…
580 …__IO uint32_t CAL_GBR21; /**< Calibration General B-Side Registers, offset…
581 …__IO uint32_t CAL_GBR22; /**< Calibration General B-Side Registers, offset…
582 …__IO uint32_t CAL_GBR23; /**< Calibration General B-Side Registers, offset…
583 …__IO uint32_t CAL_GBR24; /**< Calibration General B-Side Registers, offset…
584 …__IO uint32_t CAL_GBR25; /**< Calibration General B-Side Registers, offset…
585 …__IO uint32_t CAL_GBR26; /**< Calibration General B-Side Registers, offset…
586 …__IO uint32_t CAL_GBR27; /**< Calibration General B-Side Registers, offset…
587 …__IO uint32_t CAL_GBR28; /**< Calibration General B-Side Registers, offset…
588 …__IO uint32_t CAL_GBR29; /**< Calibration General B-Side Registers, offset…
589 …__IO uint32_t CAL_GBR30; /**< Calibration General B-Side Registers, offset…
590 …__IO uint32_t CAL_GBR31; /**< Calibration General B-Side Registers, offset…
591 …__IO uint32_t CAL_GBR32; /**< Calibration General B-Side Registers, offset…
594 /* ----------------------------------------------------------------------------
595 -- ADC Register Masks
596 ---------------------------------------------------------------------------- */
603 /*! @name VERID - Version ID Register */
608 /*! RES - Resolution
609 * 0b0..Up to 13-bit differential or 12-bit single-ended resolution supported.
610 …* 0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] availab…
617 /*! DIFFEN - Differential Supported
625 /*! MVI - Multiple Vref Implemented
633 /*! CSW - Channel Scale Width
635 * 0b001..Supported with one-bit CSCALE control field.
636 * 0b110..Supported with six-bit CSCALE control field.
642 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
650 /*! IADCKI - Internal ADC Clock Implemented
658 /*! CALOFSI - Calibration Function Implemented
666 /*! NUM_SEC - Number of Single-Ended Outputs Supported
674 /*! NUM_FIFO - Number of FIFOs
685 /*! MINOR - Minor Version Number */
690 /*! MAJOR - Major Version Number */
694 /*! @name PARAM - Parameter Register */
699 /*! TRIG_NUM - Trigger Number */
704 /*! FIFOSIZE - Result FIFO Depth
716 /*! CV_NUM - Compare Value Number */
721 /*! CMD_NUM - Command Buffer Number */
725 /*! @name CTRL - Control Register */
730 /*! ADCEN - ADC Enable
738 /*! RST - Software Reset
746 /*! DOZEN - Doze Enable
747 * 0b0..ADC is enabled in low-power mode.
748 * 0b1..ADC is disabled in low-power mode.
754 /*! CAL_REQ - Auto-Calibration Request
762 /*! CALOFS - Offset Calibration Request
770 /*! RSTFIFO0 - Reset FIFO 0
778 /*! RSTFIFO1 - Reset FIFO 1
786 /*! CAL_AVGS - Auto-Calibration Averages
799 /*! @name STAT - Status Register */
804 /*! RDY0 - Result FIFO 0 Ready Flag
812 /*! FOF0 - Result FIFO 0 Overflow Flag
820 /*! RDY1 - Result FIFO1 Ready Flag
828 /*! FOF1 - Result FIFO1 Overflow Flag
836 /*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception
844 /*! TCOMP_INT - Interrupt Flag For Trigger Completion
852 /*! CAL_RDY - Calibration Ready
860 /*! ADC_ACTIVE - ADC Active
862 * 0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger.
868 /*! TRGACT - Trigger Active
878 /*! CMDACT - Command Active
882 * 0b0011-0b1111..Associated command number currently being executed.
887 /*! @name IE - Interrupt Enable Register */
892 /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable
900 /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable
908 /*! FWMIE1 - FIFO1 Watermark Interrupt Enable
916 /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable
924 /*! TEXC_IE - Trigger Exception Interrupt Enable
932 /*! TCOMP_IE - Trigger Completion Interrupt Enable
936 * 0b0011-0b1110..Associated trigger completion interrupts are enabled.
942 /*! @name DE - DMA Enable Register */
947 /*! FWMDE0 - FIFO 0 Watermark DMA Enable
955 /*! FWMDE1 - FIFO1 Watermark DMA Enable
962 /*! @name CFG - Configuration Register */
967 /*! TPRICTRL - ADC Trigger Priority Control
970 …* averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is se…
971 …* 0b10..Current command is completed (averaging, looping, compare) before servicing the higher-pr…
978 /*! PWRSEL - Power Configuration Select
986 /*! REFSEL - Voltage Reference Selection
996 /*! TRES - Trigger Resume Enable
1004 /*! TCMDRES - Trigger Command Resume
1012 /*! HPT_EXDI - High-Priority Trigger Exception Disable
1020 /*! PUDLY - Power-up Delay */
1025 /*! PWREN - ADC Analog Pre-Enable
1027 …* 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delay…
1028 …* of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immedia…
1029 …* is set. No detected triggers begin ADC operation until the power-up delay time has passed.…
1030 …* initial delay expires, the analog circuits remain pre-enabled, and no additional delays ar…
1035 /*! @name PAUSE - Pause Register */
1040 /*! PAUSEDLY - Pause Delay */
1045 /*! PAUSEEN - Pause Enable
1052 /*! @name SWTRIG - Software Trigger Register */
1057 /*! SWT0 - Software Trigger 0
1065 /*! SWT1 - Software Trigger 1
1073 /*! SWT2 - Software Trigger 2
1081 /*! SWT3 - Software Trigger 3
1088 /*! @name TSTAT - Trigger Status Register */
1093 /*! TEXC_NUM - Trigger Exception Number
1094 * 0b0000..No triggers have been interrupted by a high-priority exception.
1095 * 0b0001..Trigger 0 has been interrupted by a high-priority exception.
1096 * 0b0010..Trigger 1 has been interrupted by a high-priority exception.
1097 * 0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception.
1098 * 0b1111..Every trigger sequence has been interrupted by a high-priority exception.
1104 /*! TCOMP_FLAG - Trigger Completion Flag
1108 * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts.
1114 /*! @name OFSTRIM - Offset Trim Register */
1119 /*! OFSTRIM_A - Trim for Offset */
1124 /*! OFSTRIM_B - Trim for Offset */
1128 /*! @name TCTRL - Trigger Control Register */
1133 /*! HTEN - Trigger Enable
1141 /*! FIFO_SEL_A - SAR Result Destination for Channel A
1149 /*! FIFO_SEL_B - SAR Result Destination for Channel B
1157 /*! TPRI - Trigger Priority Setting
1159 * 0b01-0b10..Set to corresponding priority level.
1166 /*! RSYNC - Trigger Resync
1174 /*! TDLY - Trigger Delay Select */
1179 /*! TCMD - Trigger Command Select
1182 * 0b0010-0b1110..Corresponding CMD is executed
1191 /*! @name FCTRL - FIFO Control Register */
1196 /*! FCOUNT - Result FIFO Counter */
1201 /*! FWMARK - Watermark Level Selection */
1208 /*! @name GCC - Gain Calibration Control */
1213 /*! GAIN_CAL - Gain Calibration Value */
1218 /*! RDY - Gain Calibration Value Valid
1228 /*! @name GCR - Gain Calculation Result */
1233 /*! GCALR - Gain Calculation Result */
1238 /*! RDY - Gain Calculation Ready
1248 /*! @name CMDL - Command Low Buffer Register */
1253 /*! ADCH - Input Channel Select
1258 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1266 /*! CTYPE - Conversion Type
1267 * 0b00..Single-Ended mode. Only A-side channel is converted.
1268 * 0b01..Single-Ended mode. Only B-side channel is converted.
1269 * 0b10..Differential mode. A-B.
1270 * 0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently.
1276 /*! MODE - Select Resolution of Conversions
1277 …* 0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2…
1278 …* 0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's c…
1286 /*! @name CMDH - Command High Buffer Register */
1291 /*! CMPEN - Compare Function Enable
1301 /*! WAIT_TRIG - Wait for Trigger Assertion Before Execution
1309 /*! LWI - Loop with Increment
1317 /*! STS - Sample Time Select
1331 /*! AVGS - Hardware Average Select
1345 /*! LOOP - Loop Count Select
1349 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times.
1356 /*! NEXT - Next Command Select
1360 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1369 /*! @name CV - Compare Value Register */
1374 /*! CVL - Compare Value Low */
1379 /*! CVH - Compare Value High */
1386 /*! @name RESFIFO - Data Result FIFO Register */
1391 /*! D - Data Result */
1396 /*! TSRC - Trigger Source
1399 * 0b10-0b10..Corresponding trigger source initiated this conversion.
1406 /*! LOOPCNT - Loop Count Value
1409 * 0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command.
1416 /*! CMDSRC - Command Buffer Source
1420 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1427 /*! VALID - FIFO Entry is Valid
1437 /*! @name CAL_GAR0 - Calibration General A-Side Registers */
1442 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1446 /*! @name CAL_GAR1 - Calibration General A-Side Registers */
1451 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1455 /*! @name CAL_GAR2 - Calibration General A-Side Registers */
1460 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1464 /*! @name CAL_GAR3 - Calibration General A-Side Registers */
1469 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1473 /*! @name CAL_GAR4 - Calibration General A-Side Registers */
1478 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1482 /*! @name CAL_GAR5 - Calibration General A-Side Registers */
1487 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1491 /*! @name CAL_GAR6 - Calibration General A-Side Registers */
1496 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1500 /*! @name CAL_GAR7 - Calibration General A-Side Registers */
1505 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1509 /*! @name CAL_GAR8 - Calibration General A-Side Registers */
1514 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1518 /*! @name CAL_GAR9 - Calibration General A-Side Registers */
1523 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1527 /*! @name CAL_GAR10 - Calibration General A-Side Registers */
1532 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1536 /*! @name CAL_GAR11 - Calibration General A-Side Registers */
1541 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1545 /*! @name CAL_GAR12 - Calibration General A-Side Registers */
1550 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1554 /*! @name CAL_GAR13 - Calibration General A-Side Registers */
1559 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1563 /*! @name CAL_GAR14 - Calibration General A-Side Registers */
1568 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1572 /*! @name CAL_GAR15 - Calibration General A-Side Registers */
1577 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1581 /*! @name CAL_GAR16 - Calibration General A-Side Registers */
1586 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1590 /*! @name CAL_GAR17 - Calibration General A-Side Registers */
1595 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1599 /*! @name CAL_GAR18 - Calibration General A-Side Registers */
1604 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1608 /*! @name CAL_GAR19 - Calibration General A-Side Registers */
1613 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1617 /*! @name CAL_GAR20 - Calibration General A-Side Registers */
1622 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1626 /*! @name CAL_GAR21 - Calibration General A-Side Registers */
1631 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1635 /*! @name CAL_GAR22 - Calibration General A-Side Registers */
1640 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1644 /*! @name CAL_GAR23 - Calibration General A-Side Registers */
1649 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1653 /*! @name CAL_GAR24 - Calibration General A-Side Registers */
1658 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1662 /*! @name CAL_GAR25 - Calibration General A-Side Registers */
1667 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1671 /*! @name CAL_GAR26 - Calibration General A-Side Registers */
1676 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1680 /*! @name CAL_GAR27 - Calibration General A-Side Registers */
1685 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1689 /*! @name CAL_GAR28 - Calibration General A-Side Registers */
1694 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1698 /*! @name CAL_GAR29 - Calibration General A-Side Registers */
1703 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1707 /*! @name CAL_GAR30 - Calibration General A-Side Registers */
1712 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1716 /*! @name CAL_GAR31 - Calibration General A-Side Registers */
1721 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1725 /*! @name CAL_GAR32 - Calibration General A-Side Registers */
1730 /*! CAL_GAR_VAL - Calibration General A Side Register Element */
1734 /*! @name CAL_GBR0 - Calibration General B-Side Registers */
1739 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1743 /*! @name CAL_GBR1 - Calibration General B-Side Registers */
1748 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1752 /*! @name CAL_GBR2 - Calibration General B-Side Registers */
1757 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1761 /*! @name CAL_GBR3 - Calibration General B-Side Registers */
1766 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1770 /*! @name CAL_GBR4 - Calibration General B-Side Registers */
1775 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1779 /*! @name CAL_GBR5 - Calibration General B-Side Registers */
1784 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1788 /*! @name CAL_GBR6 - Calibration General B-Side Registers */
1793 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1797 /*! @name CAL_GBR7 - Calibration General B-Side Registers */
1802 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1806 /*! @name CAL_GBR8 - Calibration General B-Side Registers */
1811 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1815 /*! @name CAL_GBR9 - Calibration General B-Side Registers */
1820 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1824 /*! @name CAL_GBR10 - Calibration General B-Side Registers */
1829 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1833 /*! @name CAL_GBR11 - Calibration General B-Side Registers */
1838 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1842 /*! @name CAL_GBR12 - Calibration General B-Side Registers */
1847 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1851 /*! @name CAL_GBR13 - Calibration General B-Side Registers */
1856 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1860 /*! @name CAL_GBR14 - Calibration General B-Side Registers */
1865 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1869 /*! @name CAL_GBR15 - Calibration General B-Side Registers */
1874 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1878 /*! @name CAL_GBR16 - Calibration General B-Side Registers */
1883 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1887 /*! @name CAL_GBR17 - Calibration General B-Side Registers */
1892 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1896 /*! @name CAL_GBR18 - Calibration General B-Side Registers */
1901 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1905 /*! @name CAL_GBR19 - Calibration General B-Side Registers */
1910 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1914 /*! @name CAL_GBR20 - Calibration General B-Side Registers */
1919 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1923 /*! @name CAL_GBR21 - Calibration General B-Side Registers */
1928 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1932 /*! @name CAL_GBR22 - Calibration General B-Side Registers */
1937 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1941 /*! @name CAL_GBR23 - Calibration General B-Side Registers */
1946 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1950 /*! @name CAL_GBR24 - Calibration General B-Side Registers */
1955 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1959 /*! @name CAL_GBR25 - Calibration General B-Side Registers */
1964 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1968 /*! @name CAL_GBR26 - Calibration General B-Side Registers */
1973 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1977 /*! @name CAL_GBR27 - Calibration General B-Side Registers */
1982 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1986 /*! @name CAL_GBR28 - Calibration General B-Side Registers */
1991 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
1995 /*! @name CAL_GBR29 - Calibration General B-Side Registers */
2000 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
2004 /*! @name CAL_GBR30 - Calibration General B-Side Registers */
2009 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
2013 /*! @name CAL_GBR31 - Calibration General B-Side Registers */
2018 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
2022 /*! @name CAL_GBR32 - Calibration General B-Side Registers */
2027 /*! CAL_GBR_VAL - Calibration General B Side Register Element */
2037 /* ADC - Peripheral instance base addresses */
2073 /* ----------------------------------------------------------------------------
2074 -- AXBS Peripheral Access Layer
2075 ---------------------------------------------------------------------------- */
2082 /** AXBS - Register Layout Typedef */
2129 /* ----------------------------------------------------------------------------
2130 -- AXBS Register Masks
2131 ---------------------------------------------------------------------------- */
2138 /*! @name PRS0 - Priority Slave Registers */
2143 /*! M0 - Master 0 Priority
2157 /*! M1 - Master 1 Priority
2171 /*! M2 - Master 2 Priority
2185 /*! M3 - Master 3 Priority
2199 /*! M4 - Master 4 Priority
2213 /*! M5 - Master 5 Priority
2226 /*! @name CRS0 - Control Register */
2231 /*! PARK - Park
2244 /*! PCTL - Parking Control
2254 /*! ARB - Arbitration Mode
2256 * 0b01..Round-robin(RR) or rotating priority
2264 /*! HLP - Halt Low Priority
2265 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2266 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2272 /*! RO - Read Only
2274 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2280 /*! @name PRS1 - Priority Slave Registers */
2285 /*! M0 - Master 0 Priority
2299 /*! M1 - Master 1 Priority
2313 /*! M2 - Master 2 Priority
2327 /*! M3 - Master 3 Priority
2341 /*! M4 - Master 4 Priority
2355 /*! M5 - Master 5 Priority
2368 /*! @name CRS1 - Control Register */
2373 /*! PARK - Park
2386 /*! PCTL - Parking Control
2396 /*! ARB - Arbitration Mode
2398 * 0b01..Round-robin(RR) or rotating priority
2406 /*! HLP - Halt Low Priority
2407 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2408 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2414 /*! RO - Read Only
2416 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2422 /*! @name PRS2 - Priority Slave Registers */
2427 /*! M0 - Master 0 Priority
2441 /*! M1 - Master 1 Priority
2455 /*! M2 - Master 2 Priority
2469 /*! M3 - Master 3 Priority
2483 /*! M4 - Master 4 Priority
2497 /*! M5 - Master 5 Priority
2510 /*! @name CRS2 - Control Register */
2515 /*! PARK - Park
2528 /*! PCTL - Parking Control
2538 /*! ARB - Arbitration Mode
2540 * 0b01..Round-robin(RR) or rotating priority
2548 /*! HLP - Halt Low Priority
2549 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2550 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2556 /*! RO - Read Only
2558 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2564 /*! @name PRS3 - Priority Slave Registers */
2569 /*! M0 - Master 0 Priority
2583 /*! M1 - Master 1 Priority
2597 /*! M2 - Master 2 Priority
2611 /*! M3 - Master 3 Priority
2625 /*! M4 - Master 4 Priority
2639 /*! M5 - Master 5 Priority
2652 /*! @name CRS3 - Control Register */
2657 /*! PARK - Park
2670 /*! PCTL - Parking Control
2680 /*! ARB - Arbitration Mode
2682 * 0b01..Round-robin(RR) or rotating priority
2690 /*! HLP - Halt Low Priority
2691 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2692 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2698 /*! RO - Read Only
2700 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2706 /*! @name PRS4 - Priority Slave Registers */
2711 /*! M0 - Master 0 Priority
2725 /*! M1 - Master 1 Priority
2739 /*! M2 - Master 2 Priority
2753 /*! M3 - Master 3 Priority
2767 /*! M4 - Master 4 Priority
2781 /*! M5 - Master 5 Priority
2794 /*! @name CRS4 - Control Register */
2799 /*! PARK - Park
2812 /*! PCTL - Parking Control
2822 /*! ARB - Arbitration Mode
2824 * 0b01..Round-robin(RR) or rotating priority
2832 /*! HLP - Halt Low Priority
2833 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2834 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2840 /*! RO - Read Only
2842 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2848 /*! @name PRS5 - Priority Slave Registers */
2853 /*! M0 - Master 0 Priority
2867 /*! M1 - Master 1 Priority
2881 /*! M2 - Master 2 Priority
2895 /*! M3 - Master 3 Priority
2909 /*! M4 - Master 4 Priority
2923 /*! M5 - Master 5 Priority
2936 /*! @name CRS5 - Control Register */
2941 /*! PARK - Park
2954 /*! PCTL - Parking Control
2964 /*! ARB - Arbitration Mode
2966 * 0b01..Round-robin(RR) or rotating priority
2974 /*! HLP - Halt Low Priority
2975 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
2976 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
2982 /*! RO - Read Only
2984 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
2990 /*! @name PRS6 - Priority Slave Registers */
2995 /*! M0 - Master 0 Priority
3009 /*! M1 - Master 1 Priority
3023 /*! M2 - Master 2 Priority
3037 /*! M3 - Master 3 Priority
3051 /*! M4 - Master 4 Priority
3065 /*! M5 - Master 5 Priority
3078 /*! @name CRS6 - Control Register */
3083 /*! PARK - Park
3096 /*! PCTL - Parking Control
3106 /*! ARB - Arbitration Mode
3108 * 0b01..Round-robin(RR) or rotating priority
3116 /*! HLP - Halt Low Priority
3117 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
3118 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
3124 /*! RO - Read Only
3126 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
3132 /*! @name PRS7 - Priority Slave Registers */
3137 /*! M0 - Master 0 Priority
3151 /*! M1 - Master 1 Priority
3165 /*! M2 - Master 2 Priority
3179 /*! M3 - Master 3 Priority
3193 /*! M4 - Master 4 Priority
3207 /*! M5 - Master 5 Priority
3220 /*! @name CRS7 - Control Register */
3225 /*! PARK - Park
3238 /*! PCTL - Parking Control
3248 /*! ARB - Arbitration Mode
3250 * 0b01..Round-robin(RR) or rotating priority
3258 /*! HLP - Halt Low Priority
3259 * 0b0..The low-power mode request has the highest priority for arbitration on this slave port.
3260 …* 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave p…
3266 /*! RO - Read Only
3268 …* 0b1..The slave port's registers are read-only and cannot be written. Attempted writes do not af…
3274 /*! @name MGPCR0 - Master General Purpose Control Register */
3279 /*! AULB - Arbitrates On Undefined Length Bursts
3292 /*! @name MGPCR1 - Master General Purpose Control Register */
3297 /*! AULB - Arbitrates On Undefined Length Bursts
3310 /*! @name MGPCR2 - Master General Purpose Control Register */
3315 /*! AULB - Arbitrates On Undefined Length Bursts
3328 /*! @name MGPCR3 - Master General Purpose Control Register */
3333 /*! AULB - Arbitrates On Undefined Length Bursts
3346 /*! @name MGPCR4 - Master General Purpose Control Register */
3351 /*! AULB - Arbitrates On Undefined Length Bursts
3364 /*! @name MGPCR5 - Master General Purpose Control Register */
3369 /*! AULB - Arbitrates On Undefined Length Bursts
3388 /* AXBS - Peripheral instance base addresses */
3422 /* ----------------------------------------------------------------------------
3423 -- BRIC Peripheral Access Layer
3424 ---------------------------------------------------------------------------- */
3431 /** BRIC - Register Layout Typedef */
3438 /* ----------------------------------------------------------------------------
3439 -- BRIC Register Masks
3440 ---------------------------------------------------------------------------- */
3447 /*! @name KEY0 - KEY0 Registers (PKB) */
3452 /*! KEY0_x - KEY0 written through PKB interface */
3459 /*! @name KEY1 - KEY1 Registers (PKB) */
3464 /*! KEY1_x - KEY1 written through PKB interface */
3471 /*! @name BRIC_CONFIG - BRIC CONFIG register */
3476 /*! KEY_INDEX - KEY INDEX */
3506 /* BRIC - Peripheral instance base addresses */
3540 /* ----------------------------------------------------------------------------
3541 -- CCM32K Peripheral Access Layer
3542 ---------------------------------------------------------------------------- */
3549 /** CCM32K - Register Layout Typedef */
3561 /* ----------------------------------------------------------------------------
3562 -- CCM32K Register Masks
3563 ---------------------------------------------------------------------------- */
3570 /*! @name FRO32K_CTRL - Free Running 32 kHz Oscillator Control Register */
3575 /*! FRO_EN - FRO Enable
3583 /*! LOCK_EN - Write Access Lock
3590 /*! @name FRO32K_TRIM - Free Running 32 kHz Oscillator Trim Register */
3595 /*! FREQ_TRIM - Frequency Trim
3602 /*! IFR_DIS - IFR Loading Disable Control
3610 /*! LOCK_EN - Write Access Lock
3617 /*! @name OSC32K_CTRL - 32 kHz OSC Control Register */
3622 /*! OSC_EN - Crystal Oscillator Enable
3630 /*! OSC_BYP_EN - Crystal Oscillator Bypass Enable
3638 /*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable
3646 /*! EXTAL_CAP_SEL - Crystal load capacitance selection bits
3668 /*! XTAL_CAP_SEL - Crystal load capacitance selection bits
3690 /*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external c…
3700 /*! SOX_EN - SOX Mode Enable
3708 /*! LOCK_EN - Write Access Lock bit
3715 /*! @name STATUS - Status Register */
3720 /*! OSC32K_RDY - 32 kHz Oscillator ready bit.
3728 /*! OSC32K_ACTIVE - 32 kHz Oscillator active bit
3736 /*! FRO32K_ACTIVE - 32 kHz FRO active bit
3744 /*! CLOCK_DET - Clock Detect
3751 /*! @name CLKMON_CTRL - Clock Monitor Control Register */
3756 /*! MON_EN - CLKMON Enable
3764 /*! FREQ_TRIM - Frequency trim bits
3774 /*! DIVIDE_TRIM - Divide Trim
3784 /*! LOCK_EN - Write Access Lock bit
3791 /*! @name CGC32K - 32 kHz Clock Gate Control Register */
3796 /*! CLK_OE_32K - 32 kHz clock output enable bits
3804 /*! CLK_SEL_32K - 32 kHz clock source selection bit
3812 /*! LOCK_EN - Write Access Lock bit
3825 /* CCM32K - Peripheral instance base addresses */
3859 /* ----------------------------------------------------------------------------
3860 -- CIU2 Peripheral Access Layer
3861 ---------------------------------------------------------------------------- */
3868 /** CIU2 - Register Layout Typedef */
3894 …__IO uint32_t CIU2_CLK_CP15_DIS3; /**< Clock Auto Shut-off Enable3, offset: 0x118 */
3969 /* ----------------------------------------------------------------------------
3970 -- CIU2 Register Masks
3971 ---------------------------------------------------------------------------- */
3978 /*! @name CIU2_CLK_ENABLE - Clock enable */
3983 /*! ahb2_clk_enable - Clock ahb2_clk enable signal. Ahb2_clk enable. 1: enable, 0: disable */
3988 /*! cpu1_div_clk_enable - Clock cpu1_div_clk enable signal. cpu1_div_clk enable. 1: enable, 0: disa…
3993 /*! soc_ahb_clk_sel - Clock selection for soc_ahb_clk. 0: AHB2_CLK, 1: CPU1_CLK_DIV */
3997 /*! @name CIU2_ECO_0 - ECO Register 0 */
4002 /*! spare - Eco Reserve Register */
4006 /*! @name CIU2_ECO_1 - ECO Register 1 */
4011 /*! spare - Eco Reserve Register */
4015 /*! @name CIU2_ECO_2 - ECO Register 2 */
4020 /*! spare - Eco Reserve Register */
4024 /*! @name CIU2_ECO_3 - ECO Register 3 */
4029 /*! spare - Eco Reserve Register */
4033 /*! @name CIU2_ECO_4 - ECO Register 4 */
4038 /*! spare - Eco Reserve Register */
4042 /*! @name CIU2_ECO_5 - ECO Register 5 */
4047 /*! spare - Eco Reserve Register */
4051 /*! @name CIU2_ECO_6 - ECO Register 6 */
4056 /*! spare - Eco Reserve Register */
4060 /*! @name CIU2_ECO_7 - ECO Register 7 */
4065 /*! spare - Eco Reserve Register */
4069 /*! @name CIU2_ECO_8 - ECO Register 8 */
4074 /*! spare - Eco Reserve Register */
4078 /*! @name CIU2_ECO_9 - ECO Register 9 */
4083 /*! spare - Eco Reserve Register */
4087 /*! @name CIU2_ECO_10 - ECO Register 10 */
4092 /*! spare - Eco Reserve Register */
4096 /*! @name CIU2_ECO_11 - ECO Register 11 */
4101 /*! spare - Eco Reserve Register */
4105 /*! @name CIU2_ECO_12 - ECO Register 12 */
4110 /*! spare - Eco Reserve Register */
4114 /*! @name CIU2_ECO_13 - ECO Register 13 */
4119 /*! spare - Eco Reserve Register */
4123 /*! @name CIU2_ECO_14 - ECO Register 14 */
4128 /*! spare - Eco Reserve Register */
4132 /*! @name CIU2_ECO_15 - ECO Register 15 */
4137 /*! spare - Eco Reserve Register */
4141 /*! @name CIU2_CLK_ENABLE4 - Clock Enable 4 */
4146 /*! bist_ahb2_clk_gating_en - CPU2 Redbist and Rombist Clock for ITCM/DTCM/SQU/BROM */
4151 /*! bru_ahb2_addr_mask_dis - CPU2 ROM Address Mask Selection */
4156 /*! itcm_ahb2_dyn_clk_gating_dis - CPU2 ITCM Dynamic Clock Gating Feature */
4161 /*! dtcm_ahb2_dyn_clk_gating_dis - CPU2 DTCM Dynamic Clock Gating Feature */
4166 /*! bru_ahb2_dyn_clk_gating_dis - CPU2 ROM Dynamic Clock Gating Feature */
4171 /*! smu2_dyn_clk_gating_dis - SMU2 Dynamic Clock Gating Feature */
4176 /*! ebram_bist_clk_en - EBRAM BIST Clock Enable */
4181 /*! bt_eclk_en - BTU EBC Clock Enable */
4186 /*! bt_4mclk_en - BTU 4 MHz Clock Enable */
4191 /*! btu_ahb_clk_en - BTU AHB Clock Enable */
4196 /*! siu_clk_en - BT SIU (UART) clock enable */
4201 /*! smu2_ahb_clk_en - SMU2 AHB Clock Enable */
4206 /*! hpu2_ciu_clk_en - HPU2 CIU Clock Enable */
4211 /*! ble_ahb_clk_en - BLE ARM Clock Enable */
4216 /*! ble_sys_clk_en - BLE SYS Clock Enable */
4221 /*! ble_aeu_clk_en - BT/BLE AEU Clock Enable */
4226 /*! bt_16m_clk_en - BT 16MHz Clock Enable */
4231 /*! dbus_clk_en - BLE DBUS Clock Enable */
4236 /*! siu_ahb2_clk_en - BT SIU (UART) AHB clock enable */
4241 /*! btrtu1_clk_en - BT RTU1 clock enable */
4245 /*! @name CIU2_CLK_ENABLE5 - Clock Enable 5 */
4250 /*! itcm_ahb2_clk_en - Enable CPU2 ITCM Banks 1-2 */
4255 /*! bt_adma_ahb_clk_en - BT ADMA AHB Clock Enable */
4260 /*! ciu2_reg_clk_en - CIU2 Reg Clock Enable */
4265 /*! br_ahb2_clk_en - CPU2 BROM AHB Clock Enable */
4270 /*! btu_mclk_en - BTU MCLK Enalbe */
4275 /*! smu2_bank_clk_en - SMU2 bank Clock Enable */
4280 /*! sif_clk_sel - SIF Clock Select */
4297 /*! sif_ahb2_clk_en - SIF ahb2 Clock Enalbe */
4301 /*! @name CIU2_CLK_CPU2CLK_CTRL - CPU2_AHB2 Clock Control */
4306 /*! t1_freq_sel - AHB2 Clock Frequency Select */
4310 /*! @name CIU2_CLK_UARTCLK_CTRL - UART Clock Control */
4315 /*! refclk_sel - Reference Clock Select */
4320 /*! nco_step_size - Programmable UART Clock Frequency */
4324 /*! @name CIU2_CLK_LBU2_BTRTU1_CTRL - LBU2 BT_RTU1 Clock Control */
4329 /*! lbu2_use_refclk - Static bit set by FW based on Reference Clock Frequency. If reference clock
4338 /*! btrtu1_timer1_use_slp_clk - Timer 1 BT_RTU1 Clock */
4343 /*! btrtu1_use_ref_clk - Static bit set by FW. If it is required that timers need not be programmed
4354 /*! @name CIU2_CLK_CP15_DIS3 - Clock Auto Shut-off Enable3 */
4359 /*! br_ahb2_clk - BRU_AHB2 Shut Off */
4364 /*! imem_ahb2_clk - IMEM_AHB2 Shut Off */
4369 /*! dmem_ahb2_clk - DMEM_AHB2 Shut Off */
4374 /*! arb_ahb2_clk - AHB2 Arbiter Shut Off */
4379 /*! dec_ahb2_clk - AHB2 Decoder Shut Off */
4384 /*! btu_ahb_clk - BTU Shut Off */
4389 /*! ble_ahb_clk - BLE Shut Off */
4393 /*! @name CIU2_RST_SW3 - Software Module Reset */
4398 /*! btu_ahb_clk_ - BTU (ARM_Clk) Soft Reset */
4403 /*! ble_soc_ - BLE SoC Soft Reset */
4408 /*! bt_common_ - BT Common Soft Rest */
4413 /*! cpu2_core_ - CPU2 core reset */
4418 /*! cpu2_tcm_ - CPU2 TCM/DMA/Arbiter reset */
4423 /*! arb_ahb2_clk_ - AHB2 Arbiter Soft Reset */
4428 /*! dec_ahb2_clk_ - AHB2 Decoder Mux Soft Reset */
4433 /*! bru_ahb2_clk_ - BRU_AHB2 Soft Reset */
4438 /*! bt_uart_n - BT UART soft reset */
4443 /*! siu_ahb2_clk_n - BT SIU (UART) AHB soft reset */
4448 /*! smu2_ahb_clk_ - SMU2 (AHB_Clk) Soft Reset */
4453 /*! sif_ - sif clock Soft Reset */
4458 /*! sif_ahb2_clk_ - sif ahb2 Clock Soft Reset */
4463 /*! hpu2_ - HPU2 Reset */
4468 /*! ciu2_ahb_clk_ - CIU2 AHB Soft Reset */
4473 /*! brf_pr_ - BRF_PR Reset */
4486 /*! bt_16m_clk_ - Bt 16M clock reset */
4491 /*! bt_adma_ - BT ADMA Soft Reset */
4495 /*! @name CIU2_MEM_WRTC3 - Memory WRTC Control 3 */
4500 /*! ble_rom_rtc - BLE ROM RTC */
4505 /*! ble_rom_rtc_ref - BLE ROM RTC_REF */
4509 /*! @name CIU2_MEM_WRTC4 - Memory WRTC Control 4 */
4514 /*! cpu2_itcm_rtc - CPU2 ITCM RTC */
4519 /*! cpu2_itcm_wtc - CPU2 ITCM WTC */
4524 /*! cpu2_dtcm_rtc - CPU2 DTCM RTC */
4529 /*! cpu2_dtcm_wtc - CPU2 DTCM WTC */
4534 /*! smu2_rtc - SMU2 RTC */
4539 /*! smu2_wtc - SMU2 WTC */
4544 /*! cpu2_bru_rtc - CPU2 BROM RTC */
4549 /*! cpu2_bru_rtc_ref - CPU2 BROM RTC_REF */
4554 /*! btu_rtc - BTU EBRAM RTC */
4559 /*! btu_wtc - BTU EBRAM WTC */
4564 /*! ble_rtc - ble RTC */
4569 /*! ble_wtc - ble WTC */
4573 /*! @name CIU2_MEM_PWDN3 - Memory Powerdown Control */
4578 /*! cpu2_bru_bypass_val - Firmware Bypass value for CPU2 Boot ROM Memories Power Down */
4583 /*! cpu2_dtcm_bypass_val - Firmware Bypass value for CPU2 DTCM Memories Power Down */
4588 /*! cpu2_itcm_bypass_val - Firmware Bypass value for CPU2 ITCM Memories Power Down */
4593 /*! smu2_bypass_val - Firmware Bypass value for SMU2 Memories Power Down */
4598 /*! siu_bypass_val - Firmware Bypass value for UART Memories Power Down */
4603 /*! btu_bypass_val - Firmware Bypass value for BTU Memories Power Down */
4608 /*! bt_adma_bypass_val - Firmware Bypass value for BT ADMA Memories Power Down */
4613 /*! cpu2_bru_bypass_en - Firmware Bypass Enable for CPU2 Boot ROM Memories Power Down */
4618 /*! cpu2_dtcm_bypass_en - Firmware Bypass Enable for CPU2 DTCM Memories Power Down */
4623 /*! cpu2_itcm_bypass_en - Firmware Bypass Enable for CPU2 ITCM Memories Power Down */
4628 /*! smu2_bypass_en - Firmware Bypass Enable for SMU2 Memories Power Down */
4633 /*! siu_bypass_en - Firmware Bypass Enable for UART Memories Power Down */
4638 /*! btu_bypass_en - Firmware Bypass Enable for BTU Memories Power Down */
4643 /*! bt_adma_bypass_en - Firmware Bypass Enable for BT ADMA Memories Power Down */
4647 /*! @name CIU2_BLE_CTRL - BLE Control and Status */
4652 /*! bt_aes_clk_freq_sel - btu_aes_clk Frequency Select */
4656 /*! @name CIU2_AHB2_TO_LAST_ADDR - AHB2 Timeout Last Address */
4661 /*! address - Last AHB2 Address Right Before the Current Timeout */
4665 /*! @name CIU2_AHB2_TO_CUR_ADDR - AHB2 Current Timeout Address */
4670 /*! address - Current_TO_Addr */
4674 /*! @name CIU2_AHB2_TO_CTRL - AHB2 ARB Control */
4679 /*! current_to_slave_id - Current_TO_Slave_ID */
4684 /*! last_to_slave_id - Last_TO_Slave_ID */
4689 /*! current_to_master_id - AHB2 Current_TO_Master_ID */
4694 /*! last_to_master_id - AHB2 Last_TO_Master_ID */
4699 /*! ahb2_smu1_mem_prot_dis - Disable SMU1 Memory Protection from AHB2 side */
4704 /*! ahb2_cpu2_imem_prot_dis - 1 = Disable CPU2 Imem Memory Protection from AHB2 side and allow AHB2…
4709 /*! ahb2_cpu2_dmem_prot_dis - 1 = Disable CPU2 Dmem Memory Protection from AHB2 side and allow AHB2…
4714 /*! ahb2_timeout_mode - AHB2_TimeoutMode[1:0] */
4718 /*! @name CIU2_AHB2_SMU1_ACCESS_ADDR - AHB2 to SMU1 Accessible Address */
4723 /*! ahb2_smu1_access_addr - SMU1 Accessible Memory Address from AHB2 side */
4727 /*! @name CIU2_AHB2_SMU1_ACCESS_MASK - AHB2 to SMU1 Accessible Mask */
4732 /*! ahb2_smu1_access_mask - SMU1 Accessible Memory Mask from AHB2 side */
4736 /*! @name CIU2_CPU2_FABRIC_ARB_CTRL - CPU2 fabric arbiter control */
4772 /*! @name CIU2_CPU2_ICODE_INV_ADDR_CTRL - CPU2 Icode invalid address access control */
4777 /*! last2_inv_addr_slave_id - Last2_inv_addr_Slave_ID */
4782 /*! last_inv_addr_slave_id - Last_inv_addr_Slave_ID */
4787 /*! cur_inv_addr_slave_id - Cur_inv_addr_Slave_ID */
4792 /*! haddr_icod_sel - There are 3 haddr which can be observed by selecting this: */
4796 /*! @name CIU2_CPU2_ICODE_INV_ADDR - CPU2 Icode invalid address */
4801 /*! haddr_inv_addr - based on CIU_CPU2_ICODE_INV_ADDR_CTRL[31:30], the address status is obsrved in…
4805 /*! @name CIU2_CPU2_DCODE_INV_ADDR_CTRL - CPU2 Dcode invalid address access control */
4810 /*! last2_inv_addr_slave_id - Last2_inv_addr_Slave_ID */
4815 /*! last_inv_addr_slave_id - Last_inv_addr_Slave_ID */
4820 /*! cur_inv_addr_slave_id - Cur_inv_addr_Slave_ID */
4825 /*! last2_inv_addr_master_id - Last2_inv_addr_master_ID */
4830 /*! last_inv_addr_master_id - Last_inv_addr_master_ID */
4835 /*! cur_inv_addr_master_id - Cur_inv_addr_master_ID */
4840 /*! haddr_icod_sel - There are 3 haddr which can be observed by selecting this: */
4844 /*! @name CIU2_CPU2_DCODE_INV_ADDR - CPU2 Dcode invalid address */
4849 /*! haddr_inv_addr - based on CIU_CPU2_DCODE_INV_ADDR_CTRL[31:30], the address status is obsrved in…
4853 /*! @name CIU2_CPU_CPU2_CTRL - CPU2 control register */
4874 /*! cpu2_dbg_ctrl - cpu2 debug control */
4879 /*! cpu3_reset_int - cpu2 fw resets cpu3(or cpu3 fw resets cpu2 if this register is used by cpu3) */
4884 /*! dsr_wkup_in_use - dsr wkup when dsr_wkup_in_use = 1'b1 */
4889 /*! cpu1_reset_int - cpu2 fw resets cpu1( or cpu3 fw resets cpu1 if this register is used by cpu3) …
4893 /*! @name CIU2_BRF_CTRL - BRF Control and Status */
4898 /*! ahb_slv_brf_ser_en - When set to 1, BRF serial interface will be accessed thru AHB slave memory…
4903 /*! sel_brf_to_ssu_dump_path - When set to 0, select BRF to SSU dump path */
4912 /*! ciu_brf_ref1x_clk_ctrl_bypass_val - 1. brf ref clk 1x is enabled */
4917 /*! brf_chip_rdy - BRF Chip_Rdy Status */
4921 /*! @name CIU2_BRF_EXTRA_PORT - BRF Extra Port Connection */
4926 /*! soc_brf_extra - SOC_BRF_EXTRA[3:0] */
4930 /*! @name CIU2_BRF_ECO_CTRL - BRF ECO Control */
4935 /*! eco_bits - Reserved */
4939 /*! @name CIU2_BTU_CTRL - BTU Control and Status */
4944 /*! btu_cipher_en - Bluetooth Cipher Logic */
4949 /*! dbus_high_speed_sel - Dbus High Speed Select Signal for Greater than 4 MHz */
4954 /*! bt_clk_sel - Bluetooth sys Clock Select */
4959 /*! bt_ip_ser_sel - bt_ip_ser_sel */
4964 /*! btu_mc_wakeup - BTU MC_Wakeup Status */
4968 /*! @name CIU2_BT_PS - BT Clock Power Save */
4973 /*! bt_mclk_nco_mval - BT_MCLK NCO Module Step Control (default 0x0) */
4978 /*! bt_mclk_nco_en - BT_MCLK_NCO logic to count */
4983 /*! bt_mclk_tbg_nco_sel - BT_4M_PCM_CLK */
4988 /*! bt_mclk_from_soc_sel - BT_MCLK */
4992 /*! @name CIU2_BT_PS2 - BT Clock Power Save 2 */
4997 /*! bt_pcm_clk_nco_mval - BT_PCM_CLK NCO Module Step Control (default 0x0) */
5002 /*! bt_pcm_clk_nco_en - BT_PCM_CLK_NCO logic to count */
5007 /*! bt_pcm_clk_tbg_nco_sel - BT_4M_PCM_CLK */
5011 /*! @name CIU2_BT_REF_CTRL - BT Ref Control */
5016 /*! nco_en - Bluetooth Reference Clock NCO Enable information to APU. */
5021 /*! nco_sel - Bluetooth Reference Clock NCO Select Value */
5026 /*! nco_gen - Bluetooth Reference Clock NCO Gen Value */
5031 /*! bt_clk_nco_refclk_sel - BT clk (bt sys clk) selection */
5035 /*! @name CIU2_BT_PS3 - BT Clock Power Save 3 */
5040 /*! btu_16m_clk_nco_step_ctrl - BT_16M_CLK NCO Module Step Control */
5045 /*! btu_16m_clk_nco_en - BTU 16M Clock NCO Enable */
5050 /*! btu_16m_clk_nco_sel - BTU 16M clock NCO Select Value */
5055 /*! btu_clk_nco_mode - BTU Clock source from ref clock (nco mode) */
5059 /*! @name CIU2_BTU_ECO_CTRL - BTU ECO Control */
5064 /*! eco_bits - Reserved */
5068 /*! @name CIU2_INT_MASK - CIU2 Interrupt Mask */
5073 /*! mask - Interrupt Mask for CIU2 Interrupts */
5077 /*! @name CIU2_INT_SELECT - CIU2 Interrupt Select */
5082 /*! sel - Interrupt Read/Write Clear for CIU2 Interrupts */
5086 /*! @name CIU2_INT_EVENT_MASK - CIU2 Interrupt Event Mask */
5091 /*! mask - Interrupt Event Mask for CIU2 Interrupts */
5095 /*! @name CIU2_INT_STATUS - CIU2 Interrupt Status */
5100 /*! ciu_isr - CIU2 Interrupt Status (ISR) */
5104 /*! @name CPU2_ERR_INT_MASK - CPU2 ERR Interrupt Mask */
5109 /*! mask - Interrupt Mask for CPU2 ERR Interrupts */
5113 /*! @name CPU2_ERR_INT_SELECT - CPU2 ERR Interrupt Clear Select */
5118 /*! sel - Interrupt Read/Write Clear for CPU2 ERR Interrupts */
5122 /*! @name CPU2_ERR_INT_EVENT_MASK - CPU2 ERR Interrupt Event Mask */
5127 /*! mask - Interrupt Event Mask for CPU2 ERR Interrupts */
5131 /*! @name CPU2_ERR_INT_STATUS - CPU2 ERR Interrupt Status */
5136 /*! err_isr - CPU2 ERR Interrupt Status (ISR) */
5140 /*! @name CPU2_ERR_INT2_MASK - CPU2 ERR Interrupt 2 Mask */
5145 /*! mask - Interrupt Mask for CPU2 ERR Interrupts 2 */
5149 /*! @name CPU2_ERR_INT2_SELECT - CPU2 ERR Interrupt 2 Clear Select */
5154 /*! sel - Interrupt Read/Write Clear for CPU2 ERR Interrupts 2 */
5158 /*! @name CPU2_ERR_INT2_EVENT_MASK - CPU2 ERR Interrupt 2 Event Mask */
5163 /*! mask - Interrupt Event Mask for CPU2 ERR Interrupts 2 */
5167 /*! @name CPU2_ERR_INT2_STATUS - CPU2 ERR Interrupt 2 Status */
5172 /*! err_isr - CPU1 ERR Interrupt 2 Status (ISR) */
5176 /*! @name CIU2_CPU_CPU2_MSG_CTRL - CPU2 message register */
5181 /*! cpu1_to_cpu2_msg_rdy - CPU1 Message for CPU2 is ready. This is self clearing bit. The CPU1
5189 /*! cpu3_to_cpu2_msg_rdy - CPU3 Message for CPU2 is ready. This is self clearing bit. The CPU3
5197 /*! cpu1_to_cpu2_msg_process_done - CPU1 Message for CPU2 has been read by CPU2 and executed. This
5205 /*! cpu3_to_cpu2_msg_process_done - CPU3 Message for CPU2 has been read by CPU2 and executed. This
5212 /*! @name CIU2_IMU_CPU1_WR_MSG_TO_CPU2 - CPU1 write message to CPU2 */
5217 /*! cpu1_wr_msg_cpu2 - Write CPU1 message data to CPU2 (push to FIFO) */
5221 /*! @name CIU2_IMU_CPU1_RD_MSG_FROM_CPU2 - CPU1 read message from CPU2 */
5226 /*! cpu1_rd_msg_cpu2 - CPU1 read message data from CPU2 (pop from FIFO) */
5230 /*! @name CIU2_IMU_CPU1_CPU2_MSG_FIFO_STATUS - CPU1 to CPU2 message FIFO status */
5235 /*! cpu1_to_cpu2_msg_fifo_locked - cpu1_to_cpu2_msg_fifo_locked */
5240 /*! cpu1_to_cpu2_msg_fifo_almost_full - cpu1_to_cpu2_msg_fifo_almost_full (based upon FIFO watermar…
5245 /*! cpu1_to_cpu2_msg_fifo_full - cpu1_to_cpu2_msg_fifo_full (based upon FIFO depth) */
5250 /*! cpu1_to_cpu2_msg_fifo_empty - cpu1_to_cpu2_msg_fifo_empty */
5255 /*! cpu1_to_cpu2_msg_count - cpu1_to_cpu2_msg_count */
5260 /*! cpu1_to_cpu2_msg_fifo_wr_ptr - cpu1 to cpu2 msg fifo write pointer for debug */
5265 /*! cpu1_to_cpu2_msg_fifo_rd_ptr - cpu1 to cpu2 msg fifo read pointer for debug */
5269 /*! @name CIU2_IMU_CPU1_CPU2_MSG_FIFO_CNTL - CPU1 to CPU2 message FIFO control */
5274 /*! cpu1_msg_rdy_int_clr - Writing 1 to this bit will clear message ready interrupt to CPU1 (self c…
5279 /*! cpu1_msg_sp_av_int_clr - Writing 1 to this bit will clear message space available interrupt to …
5284 /*! cpu1_to_cpu2_msg_fifo_flush - Writing 1 to this bit will flush cpu1_to_cpu2 message fifo */
5293 /*! cpu1_cpu2_msg_fifo_full_watermark - cpu1_to_cpu2 message fifo full watermark (space avail intr …
5297 /*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU1_VAL_DBG - CPU2 last message read (from cpu1) */
5302 /*! cpu2_rd_msg - CPU2 last message read (from cpu1) */
5306 /*! @name CIU2_IMU_CPU2_WR_MSG_TO_CPU1 - CPU2 write message to CPU1 */
5311 /*! cpu2_wr_msg_cpu1 - Write CPU2 message data to CPU1 (push to FIFO) */
5315 /*! @name CIU2_IMU_CPU2_RD_MSG_FROM_CPU1 - CPU2 read message from CPU1 */
5320 /*! cpu2_rd_msg_cpu1 - CPU2 read message data from CPU1 (pop from FIFO) */
5324 /*! @name CIU2_IMU_CPU2_CPU1_MSG_FIFO_STATUS - CPU2 to CPU1 message FIFO status */
5329 /*! cpu2_to_cpu1_msg_fifo_locked - cpu2_to_cpu1_msg_fifo_locked */
5334 /*! cpu2_to_cpu1_msg_fifo_almost_full - cpu2_to_cpu1_msg_fifo_almost_full (based upon FIFO watermar…
5339 /*! cpu2_to_cpu1_msg_fifo_full - cpu2_to_cpu1_msg_fifo_full (based upon FIFO depth) */
5344 /*! cpu2_to_cpu1_msg_fifo_empty - cpu2_to_cpu1_msg_fifo_empty */
5349 /*! cpu2_to_cpu1_msg_count - cpu2_to_cpu1_msg_count */
5354 /*! cpu2_to_cpu1_msg_fifo_wr_ptr - cpu1 to cpu2 msg fifo write pointer for debug */
5359 /*! cpu2_to_cpu1_msg_fifo_rd_ptr - cpu1 to cpu2 msg fifo read pointer for debug */
5363 /*! @name CIU2_IMU_CPU2_CPU1_MSG_FIFO_CNTL - CPU2 to CPU1 message FIFO control */
5368 /*! cpu2_msg_rdy_int_clr - Writing 1 to this bit will clear message ready interrupt to CPU2 (self c…
5373 /*! cpu2_msg_sp_av_int_clr - Writing 1 to this bit will clear message space available interrupt to …
5378 /*! cpu2_to_cpu1_msg_fifo_flush - Writing 1 to this bit will flush cpu2_to_cpu1 message fifo */
5387 /*! cpu2_cpu1_msg_fifo_full_watermark - cpu2_to_cpu1 message fifo full watermark (space avail intr …
5391 /*! @name CIU2_IMU_CPU1_RD_MSG_FROM_CPU2_VAL_DBG - CPU1 last message read (from cpu2) */
5396 /*! cpu1_rd_msg - CPU1 last message read (from cpu2) */
5400 /*! @name CIU2_BCA1_CPU2_INT_MASK - BCA1 to CPU2 Interrupt Mask */
5405 /*! imr - Interrupt Mask for BCA1 to CPU2 Interrupts */
5409 /*! @name CIU2_BCA1_CPU2_INT_SELECT - BCA1 to CPU2 Interrupt Select */
5414 /*! rsr - Interrupt Read/Write Clear for BCA1 to CPU2 Interrupts */
5418 /*! @name CIU2_BCA1_CPU2_INT_EVENT_MASK - BCA1 to CPU2 Interrupt Event Mask */
5423 /*! smr - Interrupt Event Mask for BCA1 to CPU2 Interrupts */
5427 /*! @name CIU2_BCA1_CPU2_INT_STATUS - BCA1 to CPU2 Interrupt Status */
5432 /*! isr - BCA1 to CPU2 Interrupt Status */
5436 /*! @name CIU2_APU_BYPASS1 - CIU2 APU Bypass Register 1 */
5441 /*! brf_clk_en_bypass_en - Firmware Bypass BRF_Clk_En */
5446 /*! brf_clk_en_bypass_val - Firmware Bypass Value for BRF_Clk_En (active high signal) */
5451 /*! bt_aes_clk_en_bypass_en - Firmware Bypass for Btu_Aes_Clk */
5456 /*! bt_aes_clk_en_bypass_val - Firmware Bypass Value for Btu_Aes_Clk */
5461 /*! soc_clk_en2_T1_bypass_en - Firmware Bypass for SoC_Clk_En2 */
5466 /*! soc_clk_en2_T1_bypass_val - Firmware Bypass Value for SoC_Clk_En2(active high signal) */
5471 /*! tbg_btu_clk_en_bypass_sel - TBG512_320_176_BTU_Clk_En_Sel to TBG512_320_176 of CAU */
5476 /*! bt_aes_clk_sel_bypass_en - Firmware Bypass for Btu_Aes_Clk_Sel */
5481 /*! bt_aes_clk_sel_bypass_val - Firmware Bypass Value for Btu_Aes_Clk_Sel */
5486 /*! tbg_btu_clk_en_bypass_val - TBG512_320_176_BTU_Clk_En Bypass Value */
5490 /*! @name CIU2_CPU2_LMU_STA_BYPASS0 - LMU static bank control byapss0 Register for CPU2 mem */
5495 /*! lmu_sta_banks_iso_en_bp_en - Firmware Bypass enable for lmu static banks iso_en */
5500 /*! lmu_sta_banks_iso_en_bp_val - Firmware Bypass value for lmu static banks iso_en */
5505 /*! lmu_sta_banks_psw_en_bp_en - Firmware Bypass enable for lmu static banks psw_en */
5510 /*! lmu_sta_banks_psw_en_bp_val - Firmware Bypass value for lmu static banks psw_en */
5514 /*! @name CIU2_CPU2_LMU_STA_BYPASS1 - LMU static bank control byapss1 Register for CPU2 */
5519 /*! lmu_sta_banks_sram_pd_bp_en - Firmware Bypass enable for lmu static banks sram_pd */
5524 /*! lmu_sta_banks_sram_pd_bp_val - Firmware Bypass value for lmu static banks sram_pd */
5529 /*! lmu_sta_banks_fnrst_bp_en - Firmware Bypass enable for lmu static banks fnrst */
5534 /*! lmu_sta_banks_fnrst_bp_val - Firmware Bypass value for lmu static banks fnrst */
5538 /*! @name CIU2_CPU2_LMU_STA_BYPASS2 - LMU static bank byapss2 Register for CPU2 */
5543 /*! lmu_sta_banks_vddmc_sw_pd_ctrl_bp_en - Firmware Bypass enable for lmu static banks vddmc_sw_pd_…
5548 /*! lmu_sta_banks_vddmc_sw_pd_ctrl_bp_val - Firmware Bypass value for lmu static banks vddmc_sw_pd_…
5552 /*! @name CIU2_CPU2_LMU_G2BIST_CTRL_BYPASS - LMU G2Bist control byapss Register for CPU2 */
5557 /*! lmu_cpu2_sta_pwrdmn_rpr_req_bp_en - Firmware Bypass enable for CPU2 static banks lmu powerdomai…
5562 /*! lmu_cpu2_sta_pwrdmn_rpr_req_bp_val - Firmware Bypass value for CPU2 static banks lmu powerdomai…
5566 /*! @name CIU2_APU_PWR_CTRL_BYPASS1 - APU power control Bypass Register 1 */
5571 /*! brf_psw_bypass_val - brf Power Switch Control */
5576 /*! brf_psw_bypass_en - brf Power Switch Control Enable */
5581 /*! brf_fwbar_bypass_val - brf Firewallbar Control */
5586 /*! brf_fwbar_bypass_en - brf Firewallbar Control Enable */
5591 /*! brf_iso_en_bypass_val - brf Isolation Cell Control */
5596 /*! brf_iso_en_bypass_en - brf Isolation Cell Control Enable */
5601 /*! brf_clk_div_rstb_bypass_val - Firmware Bypass Value for brf Clk_Div_Rstb (active low signal) */
5606 /*! brf_clk_div_rstb_bypass_en - Firmware Bypass brf Clk_Div_Rstb from APU */
5611 /*! brf_sram_pd_bypass_val - Firmware Bypass Value for SRAM_PD (active high signal) */
5616 /*! brf_sram_pd_bypass_en - Firmware Bypass SRAM_PD from APU */
5620 /*! @name CIU2_AHB2AHB_BRIDGE_CTRL - AHB2AHB Bridge Control Register */
5625 /*! prefetch_hsel_en - ahb2ahb bridge pre-fetch hsel enable */
5629 /*! @name CIU2_AHB1_AHB2_TO_CLEAR - AHB1 AHB2 timeout logic clear register */
5634 /*! ahb2_timeout_clear - After the timeout happended on AHB2 bus, the cpu will read the ERR ISR and
5642 /*! cpu2_dcode_inv_addr_clr - After the invalid address int happended on CPU2 dcode bus, the cpu2
5651 /*! cpu2_icode_inv_addr_clr - After the invalid address int happended on CPU2 icode bus, the cpu2
5659 /*! @name CIU2_CPU_CPU2_DBG_STAT - CPU2 debug register */
5664 /*! cpu2_ro_status - cpu2 debug output */
5668 /*! @name CIU2_CPU_CPU1_CTRL - CPU1 control register */
5681 /*! cpu2_reset_int - cpu1 fw reset cpu2 */
5685 /*! @name CIU2_TESTBUS_CTRL - CPU2 debug register */
5690 /*! testbus_sel - Select testbus debug output */
5694 /*! @name CIU2_LBC_CTRL - LBC Control and Status */
5699 /*! lbc_nco_en - LBC NCO Enable Signal */
5704 /*! lbc_debug_ctrl - LBC Debug Control Signal */
5709 /*! dejit_en - De-jitter Enable */
5714 /*! auto_dejit - Auto de-jitter */
5719 /*! man_sel_nco - Manual select NCO */
5724 /*! nco_lpo_ramp_dn - Status nco_lpo_ramp_dn */
5729 /*! ref_lpo_clk_good - Status ref_lpo_clk_good */
5734 /*! ref_lpo_ramp_dn - Status ref_lpo_ramp_dn */
5739 /*! lpo_clk_sel_fsm - Status lpo_clk_sel_fsm */
5744 /*! lpo_clk_3k2_cnt - Status lpo_clk_3k2_cnt, 3.2KHz Count */
5748 /*! @name CIU2_LBC_SLPCLK_NCO - LBC NCO Step for Sleep Clock */
5753 /*! step - LBC NCO step for sleep clock. Please refer to design spreadsheet for more details. */
5763 /* CIU2 - Peripheral instance base addresses */
5797 /* ----------------------------------------------------------------------------
5798 -- CMC Peripheral Access Layer
5799 ---------------------------------------------------------------------------- */
5806 /** CMC - Register Layout Typedef */
5841 /* ----------------------------------------------------------------------------
5842 -- CMC Register Masks
5843 ---------------------------------------------------------------------------- */
5850 /*! @name VERID - Version ID */
5855 /*! FEATURE - Feature Specification Number */
5860 /*! MINOR - Minor Version Number */
5865 /*! MAJOR - Major Version Number */
5869 /*! @name CKCTRL - Clock Control */
5874 /*! CKMODE - Clocking Mode
5878 * 0b0111..Core, platform, and peripheral clocks are gated, but no change in Low-Power mode
5879 * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode
5885 /*! LOCK - Lock
5892 /*! @name CKSTAT - Clock Status */
5897 /*! CKMODE - Low Power Status
5902 …* 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mo…
5908 /*! WAKEUP - Wake-up Source */
5913 /*! VALID - Clock Status Valid
5915 * 0b1..Core clock was gated due to Low-Power mode entry
5920 /*! @name PMPROT - Power Mode Protection */
5925 /*! LPMODE - Low-Power Mode
5933 /*! LOCK - Lock Register
5940 /*! @name GPMCTRL - Global Power Mode Control */
5945 /*! LPMODE - Low-Power Mode */
5949 /*! @name PMCTRL - Power Mode Control */
5954 /*! LPMODE - Low-Power Mode
5959 * 0b1111..Deep-Power Down
5967 /*! @name SRS - System Reset Status */
5972 /*! WAKEUP - Wake-up Reset
5980 /*! POR - Power-on Reset
5988 /*! LVD - Low Voltage Detect Reset
5996 /*! HVD - High Voltage Detect Reset
6004 /*! WARM - Warm Reset
6012 /*! FATAL - Fatal Reset
6020 /*! PIN - Pin Reset
6028 /*! DAP - Debug Access Port Reset
6036 /*! RSTACK - Reset Timeout
6044 /*! LPACK - Low Power Acknowledge Timeout Reset
6052 /*! SCG - System Clock Generation Reset
6060 /*! WDOG0 - Watchdog 0 Reset
6068 /*! SW - Software Reset
6076 /*! LOCKUP - Lockup Reset
6084 /*! WDOG1 - Watchdog 1 Reset
6092 /*! SECVIO - Security Violation Reset
6099 /*! @name RPC - Reset Pin Control */
6104 /*! FILTCFG - Reset Filter Configuration */
6109 /*! FILTEN - Filter Enable
6117 /*! LPFEN - Low-Power Filter Enable
6124 /*! @name SSRS - Sticky System Reset Status */
6129 /*! WAKEUP - Wake-up Reset
6137 /*! POR - Power-on Reset
6145 /*! LVD - Low Voltage Detect Reset
6153 /*! HVD - High Voltage Detect Reset
6161 /*! WARM - Warm Reset
6169 /*! FATAL - Fatal Reset
6177 /*! PIN - Pin Reset
6185 /*! DAP - DAP Reset
6193 /*! RSTACK - Reset Timeout
6201 /*! LPACK - Low Power Acknowledge Timeout Reset
6209 /*! SCG - System Clock Generation Reset
6217 /*! WDOG0 - Watchdog 0 Reset
6225 /*! SW - Software Reset
6233 /*! LOCKUP - Lockup Reset
6241 /*! WDOG1 - Watchdog 1 Reset
6249 /*! SECVIO - Security Violation Reset
6256 /*! @name SRIE - System Reset Interrupt Enable */
6261 /*! PIN - Pin Reset
6269 /*! DAP - DAP Reset
6277 /*! LPACK - Low Power Acknowledge Timeout Reset
6285 /*! WDOG0 - Watchdog 0 Reset
6293 /*! SW - Software Reset
6301 /*! LOCKUP - Lockup Reset
6309 /*! WDOG1 - Watchdog 1 Reset
6316 /*! @name SRIF - System Reset Interrupt Flag */
6321 /*! PIN - Pin Reset
6329 /*! DAP - DAP Reset
6337 /*! LPACK - Low Power Acknowledge Timeout Reset
6345 /*! WDOG0 - Watchdog 0 Reset
6353 /*! SW - Software Reset
6361 /*! LOCKUP - Lockup Reset
6369 /*! WDOG1 - Watchdog 1 Reset
6376 /*! @name RSTCNT - Reset Count Register */
6381 /*! COUNT - Count */
6385 /*! @name MR - Mode */
6390 /*! ISPMODE_n - Boot Configuration */
6397 /*! @name FM - Force Mode */
6402 /*! FORCECFG - Boot Configuration
6412 /*! @name SRAMDIS - SRAM Shut Down Register */
6417 /*! DIS - Shut Down Enable */
6424 /*! @name SRAMRET - SRAM Deep Sleep Register */
6429 /*! RET - Deep Sleep Enable */
6436 /*! @name FLASHCR - Flash Control */
6441 /*! FLASHDIS - Flash Disable
6449 /*! FLASHDOZE - Flash Doze
6457 /*! FLASHWAKE - Flash Wake
6464 /*! @name BSR - BootROM Status */
6469 /*! STAT - Provides status information written by the BootROM. */
6476 /*! @name BLR - BootROM Lock Register */
6481 /*! LOCK - Lock
6488 /*! @name CORECTL - Core Control */
6493 /*! NPIE - Non-maskable Pin Interrupt Enable
6500 /*! @name DBGCTL - Debug Control */
6505 /*! SOD - Sleep Or Debug
6518 /* CMC - Peripheral instance base addresses */
6552 /* ----------------------------------------------------------------------------
6553 -- CRC Peripheral Access Layer
6554 ---------------------------------------------------------------------------- */
6561 /** CRC - Register Layout Typedef */
6598 /* ----------------------------------------------------------------------------
6599 -- CRC Register Masks
6600 ---------------------------------------------------------------------------- */
6607 /*! @name DATALL - CRC_DATALL register */
6615 /*! @name DATALU - CRC_DATALU register */
6623 /*! @name DATAHL - CRC_DATAHL register */
6631 /*! @name DATAHU - CRC_DATAHU register */
6639 /*! @name DATAL - CRC_DATAL register */
6647 /*! @name DATAH - CRC_DATAH register */
6655 /*! @name DATA - CRC Data */
6660 /*! LL - CRC Low Lower Byte */
6665 /*! LU - CRC Low Upper Byte */
6670 /*! HL - CRC High Lower Byte */
6675 /*! HU - CRC High Upper Byte */
6679 /*! @name GPOLYLL - CRC_GPOLYLL register */
6687 /*! @name GPOLYLU - CRC_GPOLYLU register */
6695 /*! @name GPOLYHL - CRC_GPOLYHL register */
6703 /*! @name GPOLYHU - CRC_GPOLYHU register */
6711 /*! @name GPOLYL - CRC_GPOLYL register */
6719 /*! @name GPOLYH - CRC_GPOLYH register */
6727 /*! @name GPOLY - CRC Polynomial */
6732 /*! LOW - Low Polynominal Half-Word */
6737 /*! HIGH - High Polynominal Half-Word */
6741 /*! @name CTRLHU - CRC_CTRLHU register */
6746 /*! TCRC - TCRC
6747 * 0b0..16-bit
6748 * 0b1..32-bit
6754 /*! WAS - Write as Seed
6762 /*! FXOR - Complement Read of CRC Data Register
6770 /*! TOTR - Transpose Type for Read
6780 /*! TOT - Transpose Type for Writes
6789 /*! @name CTRL - CRC Control */
6794 /*! TCRC - TCRC
6795 * 0b0..16-bit
6796 * 0b1..32-bit
6802 /*! WAS - Write as Seed
6810 /*! FXOR - Complement Read of CRC Data Register
6818 /*! TOTR - Transpose Type for Read
6828 /*! TOT - Transpose Type for Writes
6843 /* CRC - Peripheral instance base addresses */
6877 /* ----------------------------------------------------------------------------
6878 -- DMA Peripheral Access Layer
6879 ---------------------------------------------------------------------------- */
6886 /** DMA - Register Layout Typedef */
6927 /* ----------------------------------------------------------------------------
6928 -- DMA Register Masks
6929 ---------------------------------------------------------------------------- */
6936 /*! @name MP_CSR - Management Page Control */
6941 /*! EDBG - Enable Debug
6949 /*! ERCA - Enable Round Robin Channel Arbitration
6950 * 0b0..Round-robin channel arbitration disabled
6951 * 0b1..Round-robin channel arbitration enabled
6957 /*! HAE - Halt After Error
6965 /*! HALT - Halt DMA Operations
6973 /*! GCLC - Global Channel Linking Control
6981 /*! GMRC - Global Master ID Replication Control
6989 /*! ECX - Cancel Transfer With Error
6997 /*! CX - Cancel Transfer
7005 /*! ACTIVE_ID - Active Channel ID */
7010 /*! ACTIVE - DMA Active Status
7017 /*! @name MP_ES - Management Page Error Status */
7022 /*! DBE - Destination Bus Error
7030 /*! SBE - Source Bus Error
7038 /*! SGE - Scatter/Gather Configuration Error
7046 /*! NCE - NBYTES/CITER Configuration Error
7054 /*! DOE - Destination Offset Error
7062 /*! DAE - Destination Address Error
7070 /*! SOE - Source Offset Error
7078 /*! SAE - Source Address Error
7086 /*! ECX - Transfer Canceled
7094 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
7099 /*! VLD - Valid
7106 /*! @name MP_INT - Management Page Interrupt Request Status */
7111 /*! INT - Interrupt Request Status */
7115 /*! @name MP_HRS - Management Page Hardware Request Status */
7120 /*! HRS - Hardware Request Status */
7124 /*! @name CH_GRPRI - Channel Arbitration Group */
7129 /*! GRPRI - Arbitration Group For Channel n */
7136 /*! @name CH_CSR - Channel Control and Status */
7141 /*! ERQ - Enable DMA Request
7149 /*! EARQ - Enable Asynchronous DMA Request
7157 /*! EEI - Enable Error Interrupt
7165 /*! EBW - Enable Buffered Writes
7173 /*! DONE - Channel Done */
7178 /*! ACTIVE - Channel Active */
7185 /*! @name CH_ES - Channel Error Status */
7190 /*! DBE - Destination Bus Error
7198 /*! SBE - Source Bus Error
7206 /*! SGE - Scatter/Gather Configuration Error
7214 /*! NCE - NBYTES/CITER Configuration Error
7222 /*! DOE - Destination Offset Error
7230 /*! DAE - Destination Address Error
7238 /*! SOE - Source Offset Error
7246 /*! SAE - Source Address Error
7254 /*! ERR - Error In Channel
7264 /*! @name CH_INT - Channel Interrupt Status */
7269 /*! INT - Interrupt Request
7279 /*! @name CH_SBR - Channel System Bus */
7284 /*! MID - Master ID */
7289 /*! SEC - Security Level
7297 /*! PAL - Privileged Access Level
7305 /*! EMI - Enable Master ID Replication
7313 /*! ATTR - Attribute Output */
7320 /*! @name CH_PRI - Channel Priority */
7325 /*! APL - Arbitration Priority Level */
7330 /*! DPA - Disable Preempt Ability
7331 * 0b0..Channel can suspend a lower-priority channel
7338 /*! ECP - Enable Channel Preemption
7339 * 0b0..Channel cannot be suspended by a higher-priority channel's service request
7340 * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request
7348 /*! @name CH_MUX - Channel Multiplexor Configuration */
7353 /*! SRC - Service Request Source */
7360 /*! @name TCD_SADDR - TCD Source Address */
7365 /*! SADDR - Source Address */
7372 /*! @name TCD_SOFF - TCD Signed Source Address Offset */
7377 /*! SOFF - Source Address Signed Offset */
7384 /*! @name TCD_ATTR - TCD Transfer Attributes */
7389 /*! DSIZE - Destination Data Transfer Size */
7394 /*! DMOD - Destination Address Modulo */
7399 /*! SSIZE - Source Data Transfer Size
7400 * 0b000..8-bit
7401 * 0b001..16-bit
7402 * 0b010..32-bit
7403 * 0b011..64-bit
7404 * 0b100..16-byte
7405 * 0b101..32-byte
7413 /*! SMOD - Source Address Modulo
7415 * 0b00001..Source address modulo feature enabled for any non-zero value [1-31]
7423 /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
7428 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
7433 /*! DMLOE - Destination Minor Loop Offset Enable
7441 /*! SMLOE - Source Minor Loop Offset Enable
7451 /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
7456 /*! NBYTES - Number of Bytes To Transfer Per Service Request */
7461 /*! MLOFF - Minor Loop Offset */
7466 /*! DMLOE - Destination Minor Loop Offset Enable
7474 /*! SMLOE - Source Minor Loop Offset Enable
7484 /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
7489 /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */
7496 /*! @name TCD_DADDR - TCD Destination Address */
7501 /*! DADDR - Destination Address */
7508 /*! @name TCD_DOFF - TCD Signed Destination Address Offset */
7513 /*! DOFF - Destination Address Signed Offset */
7520 /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
7525 /*! CITER - Current Major Iteration Count */
7530 /*! ELINK - Enable Link
7531 * 0b0..Channel-to-channel linking disabled
7532 * 0b1..Channel-to-channel linking enabled
7540 /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
7545 /*! CITER - Current Major Iteration Count */
7550 /*! LINKCH - Minor Loop Link Channel Number */
7555 /*! ELINK - Enable Link
7556 * 0b0..Channel-to-channel linking disabled
7557 * 0b1..Channel-to-channel linking enabled
7565 /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
7570 /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */
7577 /*! @name TCD_CSR - TCD Control and Status */
7582 /*! START - Channel Start
7584 * 0b1..Channel explicitly started via a software-initiated service request
7590 /*! INTMAJOR - Enable Interrupt If Major count complete
7591 * 0b0..End-of-major loop interrupt disabled
7592 * 0b1..End-of-major loop interrupt enabled
7598 /*! INTHALF - Enable Interrupt If Major Counter Half-complete
7606 /*! DREQ - Disable Request
7614 /*! ESG - Enable Scatter/Gather Processing
7622 /*! MAJORELINK - Enable Link When Major Loop Complete
7623 * 0b0..Channel-to-channel linking disabled
7624 * 0b1..Channel-to-channel linking enabled
7630 /*! EEOP - Enable End-Of-Packet Processing
7631 * 0b0..End-of-packet operation disabled
7632 * 0b1..End-of-packet hardware input signal enabled
7638 /*! ESDA - Enable Store Destination Address
7646 /*! MAJORLINKCH - Major Loop Link Channel Number */
7651 /*! BWC - Bandwidth Control
7663 /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) …
7668 /*! BITER - Starting Major Iteration Count */
7673 /*! ELINK - Enables Link
7674 * 0b0..Channel-to-channel linking disabled
7675 * 0b1..Channel-to-channel linking enabled
7683 /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) …
7688 /*! BITER - Starting Major Iteration Count */
7693 /*! LINKCH - Link Channel Number */
7698 /*! ELINK - Enable Link
7699 * 0b0..Channel-to-channel linking disabled
7700 * 0b1..Channel-to-channel linking enabled
7714 /* DMA - Peripheral instance base addresses */
7751 /* ----------------------------------------------------------------------------
7752 -- DSB Peripheral Access Layer
7753 ---------------------------------------------------------------------------- */
7760 /** DSB - Register Layout Typedef */
7770 /* ----------------------------------------------------------------------------
7771 -- DSB Register Masks
7772 ---------------------------------------------------------------------------- */
7779 /*! @name CSR - Control Register */
7784 /*! SFTRST - Soft Reset
7792 /*! DSB_EN - Data Stream Buffer Enable
7800 /*! DMA_EN - DMA Transfer Enable
7808 /*! INT_EN - Interrupt Request Enable
7816 /*! ERR_EN - Error Interrupt Request Enable
7824 /*! CBT_EN - Continuous Burst Transfer Enable
7831 /*! @name INT - Interrupt Request Status Register */
7836 /*! DRDY - Data Ready
7844 /*! OVRF - Overflow Error
7852 /*! UNDR - Underrun Error
7860 /*! DBE - Destination Bus Error
7868 /*! DONE - DMA Packet Transfer Complete
7870 * 0b1..Packet transfer is done; TCNT 32-bit words transferred
7875 /*! @name WMC - Watermark Configuration Register */
7880 /*! WMRK - Watermark */
7885 /*! CNT - FIFO Count */
7890 /*! SIZE - FIFO size */
7894 /*! @name RDATA - FIFO Read Data Register */
7899 /*! DATA - FIFO Data */
7903 /*! @name DADDR - DMA Destination Address Register */
7908 /*! DADDR - Destination Address */
7912 /*! @name XCR - DMA Transfer Count Register */
7917 /*! TCNT - Total Transfer Count */
7922 /*! CCNT - Current Transfer Count */
7932 /* DSB - Peripheral instance base addresses */
7966 /* ----------------------------------------------------------------------------
7967 -- ELEMU Peripheral Access Layer
7968 ---------------------------------------------------------------------------- */
7975 /** ELEMU - Register Layout Typedef */
8003 /* ----------------------------------------------------------------------------
8004 -- ELEMU Register Masks
8005 ---------------------------------------------------------------------------- */
8012 /*! @name VER - Version ID Register */
8017 /*! FEATURE - Feature Set Number
8024 /*! MINOR - Minor Version Number (0x00 ) */
8029 /*! MAJOR - Major Version Number (0x01 ) */
8033 /*! @name PAR - Parameter Register */
8038 /*! TR_NUM - Number of Transmit (TRn) registers (8'd16) */
8043 /*! RR_NUM - Number of Receive (RRn) registers (8'd2) */
8047 /*! @name SR - Status Register */
8052 /*! TEP - Transmit Empty Pending */
8057 /*! RFP - Receive Full Pending Flag
8064 /*! @name TCR - Transmit Control Register */
8069 /*! TEIEn - Transmit Register n Empty Interrupt Enable */
8073 /*! @name TSR - Transmit Status Register */
8078 /*! TEn - Transmit Register n Empty */
8082 /*! @name RSR - Receive Status Register */
8087 /*! RFn - Receive Register n Full */
8091 /*! @name UNUSED1 - Unused Register 1 */
8096 /*! DATA16 - Unused 16-bit Register */
8100 /*! @name TR - Transmit Register */
8105 /*! TR_DATA - Transmit Data */
8112 /*! @name RR - Receive Register */
8117 /*! RR_DATA - Receive Data */
8124 /*! @name SEMA4_SR - Semaphore Status Register */
8129 /*! OWNR16 - Semaphore Owner */
8134 /*! SSS_CIP2 - Security SubSystem (ELE) command group 2 in progress
8142 /*! SSS_CIP1 - Security SubSystem (ELE) command group 1 in progress
8150 /*! SSS_LCK - Security SubSystem (ELE) lockup
8158 /*! MISC_BSY - Miscellaneous ELE Busy Indicators */
8163 /*! SSS_BSY - Security SubSystem (ELE) Busy
8170 /*! @name SEMA4_OWNR - Semaphore Ownership Register */
8175 /*! OWNR32 - Semaphore Owner */
8179 /*! @name SEMA4_ACQ - Semaphore Acquire Register */
8184 /*! OWNR32 - Semaphore Owner */
8188 /*! @name SEMA4_REL - Semaphore Release Register */
8193 /*! OWNR32 - Semaphore Owner */
8197 /*! @name SEMA4_FREL - Semaphore Forced Release Register */
8202 /*! OWNR32 - Semaphore Owner */
8212 /* ELEMU - Peripheral instance base addresses */
8246 /* ----------------------------------------------------------------------------
8247 -- EWM Peripheral Access Layer
8248 ---------------------------------------------------------------------------- */
8255 /** EWM - Register Layout Typedef */
8265 /* ----------------------------------------------------------------------------
8266 -- EWM Register Masks
8267 ---------------------------------------------------------------------------- */
8274 /*! @name CTRL - Control */
8279 /*! EWMEN - EWM Enable
8287 /*! ASSIN - Assertion State Select
8295 /*! INEN - Input Enable
8303 /*! INTEN - Interrupt Enable
8310 /*! @name SERV - Service */
8315 /*! SERVICE - Service */
8319 /*! @name CMPL - Compare Low */
8324 /*! COMPAREL - Compare Low */
8328 /*! @name CMPH - Compare High */
8333 /*! COMPAREH - Compare High */
8337 /*! @name CLKPRESCALER - Clock Prescaler */
8342 /*! CLK_DIV - Clock Divider */
8352 /* EWM - Peripheral instance base addresses */
8388 /* ----------------------------------------------------------------------------
8389 -- FLEXIO Peripheral Access Layer
8390 ---------------------------------------------------------------------------- */
8397 /** FLEXIO - Register Layout Typedef */
8461 /* ----------------------------------------------------------------------------
8462 -- FLEXIO Register Masks
8463 ---------------------------------------------------------------------------- */
8470 /*! @name VERID - Version ID Register */
8475 /*! FEATURE - Feature Specification Number
8485 /*! MINOR - Minor Version Number */
8490 /*! MAJOR - Major Version Number */
8494 /*! @name PARAM - Parameter Register */
8499 /*! SHIFTER - Shifter Number */
8504 /*! TIMER - Timer Number */
8509 /*! PIN - Pin Number */
8514 /*! TRIGGER - Trigger Number */
8518 /*! @name CTRL - FlexIO Control Register */
8523 /*! FLEXEN - FlexIO Enable
8531 /*! SWRST - Software Reset
8539 /*! FASTACC - Fast Access
8547 /*! DBGE - Debug Enable
8555 /*! DOZEN - Doze Enable
8562 /*! @name PIN - Pin State Register */
8567 /*! PDI - Pin Data Input */
8571 /*! @name SHIFTSTAT - Shifter Status Register */
8576 /*! SSF - Shifter Status Flag */
8580 /*! @name SHIFTERR - Shifter Error Register */
8585 /*! SEF - Shifter Error Flags */
8589 /*! @name TIMSTAT - Timer Status Register */
8594 /*! TSF - Timer Status Flags */
8598 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
8603 /*! SSIE - Shifter Status Interrupt Enable */
8607 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
8612 /*! SEIE - Shifter Error Interrupt Enable */
8616 /*! @name TIMIEN - Timer Interrupt Enable Register */
8621 /*! TEIE - Timer Status Interrupt Enable */
8625 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
8630 /*! SSDE - Shifter Status DMA Enable */
8634 /*! @name TIMERSDEN - Timer Status DMA Enable */
8639 /*! TSDE - Timer Status DMA Enable */
8643 /*! @name SHIFTSTATE - Shifter State Register */
8648 /*! STATE - Current State Pointer */
8652 /*! @name TRGSTAT - Trigger Status Register */
8657 /*! ETSF - External Trigger Status Flags */
8661 /*! @name TRIGIEN - External Trigger Interrupt Enable Register */
8666 /*! TRIE - External Trigger Interrupt Enable */
8670 /*! @name PINSTAT - Pin Status Register */
8675 /*! PSF - Pin Status Flags */
8679 /*! @name PINIEN - Pin Interrupt Enable Register */
8684 /*! PSIE - Pin Status Interrupt Enable */
8688 /*! @name PINREN - Pin Rising Edge Enable Register */
8693 /*! PRE - Pin Rising Edge */
8697 /*! @name PINFEN - Pin Falling Edge Enable Register */
8702 /*! PFE - Pin Falling Edge */
8706 /*! @name PINOUTD - Pin Output Data Register */
8711 /*! OUTD - Output Data */
8715 /*! @name PINOUTE - Pin Output Enable Register */
8720 /*! OUTE - Output Enable */
8724 /*! @name PINOUTDIS - Pin Output Disable Register */
8729 /*! OUTDIS - Output Disable */
8733 /*! @name PINOUTCLR - Pin Output Clear Register */
8738 /*! OUTCLR - Output Clear */
8742 /*! @name PINOUTSET - Pin Output Set Register */
8747 /*! OUTSET - Output Set */
8751 /*! @name PINOUTTOG - Pin Output Toggle Register */
8756 /*! OUTTOG - Output Toggle */
8760 /*! @name SHIFTCTL - Shifter Control N Register */
8765 /*! SMOD - Shifter Mode
8779 /*! PINPOL - Shifter Pin Polarity
8787 /*! PINSEL - Shifter Pin Select */
8792 /*! PINCFG - Shifter Pin Configuration
8802 /*! TIMPOL - Timer Polarity
8810 /*! TIMSEL - Timer Select */
8817 /*! @name SHIFTCFG - Shifter Configuration N Register */
8822 /*! SSTART - Shifter Start bit
8832 /*! SSTOP - Shifter Stop bit
8847 /*! INSRC - Input Source
8855 /*! LATST - Late Store
8856 * 0b0..Shift register stores the pre-shift register state.
8857 * 0b1..Shift register stores the post-shift register state.
8863 /*! SSIZE - Shifter Size
8864 * 0b0..Shift register is 32-bit.
8865 * 0b1..Shift register is 24-bit.
8871 /*! PWIDTH - Parallel Width */
8878 /*! @name SHIFTBUF - Shifter Buffer N Register */
8883 /*! SHIFTBUF - Shift Buffer */
8890 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
8895 /*! SHIFTBUFBIS - Shift Buffer */
8902 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
8907 /*! SHIFTBUFBYS - Shift Buffer */
8914 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
8919 /*! SHIFTBUFBBS - Shift Buffer */
8926 /*! @name TIMCTL - Timer Control N Register */
8931 /*! TIMOD - Timer Mode
8933 * 0b001..Dual 8-bit counters baud mode.
8934 * 0b010..Dual 8-bit counters PWM high mode.
8935 * 0b011..Single 16-bit counter mode.
8936 * 0b100..Single 16-bit counter disable mode.
8937 * 0b101..Dual 8-bit counters word mode.
8938 * 0b110..Dual 8-bit counters PWM low mode.
8939 * 0b111..Single 16-bit input capture mode.
8945 /*! ONETIM - Timer One Time Operation
8953 /*! PININS - Timer Pin Input Select
8961 /*! PINPOL - Timer Pin Polarity
8969 /*! PINSEL - Timer Pin Select */
8974 /*! PINCFG - Timer Pin Configuration
8984 /*! TRGSRC - Trigger Source
8992 /*! TRGPOL - Trigger Polarity
9000 /*! TRGSEL - Trigger Select */
9007 /*! @name TIMCFG - Timer Configuration N Register */
9012 /*! TSTART - Timer Start Bit
9020 /*! TSTOP - Timer Stop Bit
9030 /*! TIMENA - Timer Enable
9032 * 0b001..Timer enabled on Timer N-1 enable
9044 /*! TIMDIS - Timer Disable
9046 * 0b001..Timer disabled on Timer N-1 disable
9047 * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
9048 * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
9058 /*! TIMRST - Timer Reset
9072 /*! TIMDEC - Timer Decrement
9086 /*! TIMOUT - Timer Output
9098 /*! @name TIMCMP - Timer Compare N Register */
9103 /*! CMP - Timer Compare Value */
9110 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
9115 /*! SHIFTBUFNBS - Shift Buffer */
9122 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
9127 /*! SHIFTBUFHWS - Shift Buffer */
9134 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
9139 /*! SHIFTBUFNIS - Shift Buffer */
9146 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
9151 /*! SHIFTBUFOES - Shift Buffer */
9158 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
9163 /*! SHIFTBUFEOS - Shift Buffer */
9170 /*! @name SHIFTBUFHBS - Shifter Buffer N Halfword Byte Swapped Register */
9175 /*! SHIFTBUFHBS - Shift Buffer */
9188 /* FLEXIO - Peripheral instance base addresses */
9224 /* ----------------------------------------------------------------------------
9225 -- FMU Peripheral Access Layer
9226 ---------------------------------------------------------------------------- */
9233 /** FMU - Register Layout Typedef */
9242 /* ----------------------------------------------------------------------------
9243 -- FMU Register Masks
9244 ---------------------------------------------------------------------------- */
9251 /*! @name FSTAT - Flash Status Register */
9256 /*! FAIL - Command Fail Flag
9264 /*! CMDABT - Command Abort Flag
9272 /*! PVIOL - Command Protection Violation Flag
9280 /*! ACCERR - Command Access Error Flag
9288 /*! CWSABT - Command Write Sequence Abort Flag
9296 /*! CCIF - Command Complete Interrupt Flag
9304 /*! CMDPRT - Command protection level
9314 /*! CMDP - Command protection status flag
9322 /*! CMDDID - Command domain ID */
9327 /*! DFDIF - Double Bit Fault Detect Interrupt Flag
9335 /*! SALV_USED - Salvage Used for Erase operation
9343 /*! PEWEN - Program-Erase Write Enable Control
9353 /*! PERDY - Program-Erase Ready Control/Status Flag
9360 /*! @name FCNFG - Flash Configuration Register */
9365 /*! CCIE - Command Complete Interrupt Enable
9373 /*! ERSREQ - Mass Erase Request
9381 /*! DFDIE - Double Bit Fault Detect Interrupt Enable
9389 /*! ERSIEN0 - Erase IFR Sector Enable - Block 0
9397 /*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs)
9404 /*! @name FCTRL - Flash Control Register */
9409 /*! RWSC - Read Wait-State Control */
9414 /*! LSACTIVE - Low speed active mode
9422 /*! FDFD - Force Double Bit Fault Detect
9431 /*! ABTREQ - Abort Request
9438 /*! @name FCCOB - Flash Common Command Object Registers */
9443 /*! CCOBn - CCOBn */
9456 /* FMU - Peripheral instance base addresses */
9502 /* ----------------------------------------------------------------------------
9503 -- FRO192M Peripheral Access Layer
9504 ---------------------------------------------------------------------------- */
9511 /** FRO192M - Register Layout Typedef */
9517 /* ----------------------------------------------------------------------------
9518 -- FRO192M Register Masks
9519 ---------------------------------------------------------------------------- */
9526 /*! @name FROCCSR - FRO192 Clock Control Status Register */
9531 /*! FRODIV - FRO Clock Divide
9541 /*! POSTDIV_SEL - Post Divider Clock Select
9555 /*! VALID - Clock Valid Flag
9562 /*! @name FRODIV - FRO192 Divide Register */
9567 /*! FRODIV - FRO Clock Divide
9582 /* FRO192M - Peripheral instance base addresses */
9616 /* ----------------------------------------------------------------------------
9617 -- GEN4PHY Peripheral Access Layer
9618 ---------------------------------------------------------------------------- */
9625 /** GEN4PHY - Register Layout Typedef */
9661 …__I uint32_t RTT_STAT; /**< High resolution Time-Of-Flight calculation S…
9666 /* ----------------------------------------------------------------------------
9667 -- GEN4PHY Register Masks
9668 ---------------------------------------------------------------------------- */
9675 /*! @name FSK_PD_CFG0 - PHY Uncoded Preamble Detect Config 0 */
9680 /*! PREAMBLE_T_SCALE - Scaling factor used for fractional time estimation during preamble search. */
9685 /*! PD_IIR_ALPHA - Forgetting factor used by the complex correlations smoothing leaky integrator. */
9689 /*! @name FSK_PD_CFG1 - PHY Uncoded Preamble Detect Config 1 */
9694 /*! PREAMBLE_PATTERN - 8-bit preamble pattern used in FM-domain preamble detector. */
9698 /*! @name FSK_PD_CFG2 - PHY Uncoded Preamble Detect Config 2 */
9703 /*! PD_THRESH_ACQ_1_3_1M - Preamble detect threshold for acq mode 1 and 3 at data rate 1Mbps */
9708 /*! PD_THRESH_ACQ_1_3_2M - Preamble detect threshold for acq mode 1 and 3 at data rate 2Mbps */
9712 /*! @name FSK_PD_PH - */
9717 /*! REF0 - Uncoded preamble reference waveform sample 4 (sfix6en5) */
9722 /*! REF1 - Uncoded preamble reference waveform sample 5 (sfix6en5) */
9727 /*! REF2 - Uncoded preamble reference waveform sample 6 (sfix6en5) */
9732 /*! REF3 - Uncoded preamble reference waveform sample 7 (sfix6en5) */
9739 /*! @name FSK_PD_RO_PH - */
9744 /*! REF0 - Uncoded preamble reference waveform sample 28 (sfix6en5) */
9749 /*! REF1 - Uncoded preamble reference waveform sample 29 (sfix6en5) */
9754 /*! REF2 - Uncoded preamble reference waveform sample 30 (sfix6en5) */
9759 /*! REF3 - Uncoded preamble reference waveform sample 31 (sfix6en5) */
9766 /*! @name FSK_CFG0 - PHY Uncoded Config 0 */
9771 /*! AA_OUT_SEL - Specifies which AA bits to be played-back to the LL:
9779 /*! FSK_BIT_INVERT - This applies at the demodulator, so it affects both AA and the data portions o…
9787 /*! MSK_EN - Configures PHY for MSK decoding. */
9792 /*! MSK2FSK_SEED - Last bit of preamble. */
9797 /*! AA_ACQ_1_2_3_THRESH_1M - For 1Mbps data rate, Correlation threshold applicable to AA detection;…
9802 /*! HAMMING_AA_LOW_PWR - Maximum hamming distance from the given AA pattern that may still be
9809 /*! BLE_NTW_ADR_THR - Maximum hamming distance from the given AA pattern that may still be accepted
9816 /*! AA_ACQ_1_2_3_THRESH_2M - For 2Mbps data rate, correlation threshold applicable to AA detection;…
9820 /*! @name FSK_CFG1 - PHY Uncoded Config 1 */
9825 /*! OVERH - Modulation index; represented in ufix9_En6 format. */
9830 /*! OVERH_INV - Reciprocal of modulation index; represented in ufix9_En7 format. */
9835 /*! SYNCTSCALE - Scaling factor used for fractional time estimation during AA search; represented i…
9839 /*! @name FSK_CFG2 - PHY Uncoded Config 2 */
9844 /*! MAG_WIN - Indicates the forgetting factor used in received signal level measurement; */
9848 /*! @name FSK_PT - PHY Uncoded Power Threshold Config */
9853 /*! AGC_TIMEOUT - Time-out, applicable to special conditioning of signal power detection in the
9860 /*! COND_SIG_PRST_EN - Enables special conditioning of signal detection;
9868 /*! COND_AA_BUFF_EN - Enables special condition for enabling AA detector buffer;
9876 /*! BYPASS_WITH_RSSI - Bypass signal power measurement with RSSI measurement;
9883 /*! @name FSK_FAD_CTRL - PHY Uncoded FAD Control */
9888 /*! FAD_EN - Enables FAD;
9895 /*! @name FSK_FAD_CFG - PHY Uncoded FAD Config */
9900 /*! WIN_FAD_WAIT_SYNCH - Time-window to wait for clean samples, before transitioning to AA search
9901 * PHY state, if PD was found after antenna switch (refered to as T3 in the PHY state-machine
9908 /*! WIN_FAD_WAIT_PD - Time-window to wait for clean samples if PD was not found after antenna switch
9909 * (refered to as T2 in the PHY state-machine section).
9915 /*! WIN_FAD_SEARCH_PD - Time-window to match preamble pattern on samples coming from the previously
9916 * selected antenna (refered to as T1 in the PHY state-machine section).
9922 /*! WIN_SEARCH_PD - Time-window to match preamble pattern on samples coming from the currently
9923 * selected antenna (refered to as T0 in the PHY state-machine section).
9928 /*! @name FSK_STAT - PHY Uncoded Status */
9933 /*! EXT_TO_MODES_13 - Reserved */
9938 /*! AA_FOUND - Indicates that a uncoded AA detect is active. */
9943 /*! LAST_AA_BIT - reserved */
9948 /*! AA_MATCH - Indicates which non-coded AA has matched. This will clear when the PHY is re-initial…
9953 /*! HAMM_DIST - Indicates the hamming distance witnessed when AA match occurred. */
9958 /*! CORR_MAX - Indicates the correlation witnessed when AA match occurred */
9963 /*! TOF_OFF - Timing offset for use in time-of-flight calculation. */
9967 /*! @name LR_PD_CFG - PHY Long Range Preamble Detect Config */
9972 /*! CORR_TH - Correlation threshold applicable to preamble detection; uses (0,8,8) fixed-point form…
9977 /*! FREQ_TH - Threshold used to compare CFO estimates in the LR preamble detector; uses ufix5_En5 f…
9982 /*! NO_PEAKS - Number of consecutive correlation values that have to exceed the PD correlation
9992 /*! @name LR_PD_PH - */
9997 /*! REF0 - Long range preamble reference waveform sample 12 (sfix6en5) */
10002 /*! REF1 - Long range preamble reference waveform sample 13 (sfix6en5) */
10007 /*! REF2 - Long range preamble reference waveform sample 14 (sfix6en5) */
10012 /*! REF3 - Long range preamble reference waveform sample 15 (sfix6en5) */
10019 /*! @name LR_PD_RO_PH - */
10024 /*! REF0 - Long range preamble reference waveform sample 64 (sfix6en5) */
10029 /*! REF1 - Long range preamble reference waveform sample 65 (sfix6en5) */
10034 /*! REF2 - Long range preamble reference waveform sample 66 (sfix6en5) */
10039 /*! REF3 - Long range preamble reference waveform sample 67 (sfix6en5) */
10046 /*! @name LR_AA_CFG - PHY Long Range AA Config */
10051 /*! AA_COR_THRESH - Threshold use to compare the correlation magnitude in the long-range AA correla…
10056 /*! AA_HAM_THRESH - Threshold use to compare the Hamming distance, between reference coded sequence
10057 * and received coded sequence, in the long-range AA correlator.
10063 /*! ACCESS_ADDR_HAM - Threshold use to compare the Hamming distance, between the reference AA
10070 /*! AA_LR_CORR_GAIN - AA correlator gain. Format ufix6en3. This gain is applied to soft bits from
10076 /*! @name LR_STAT - PHY Long Range Status */
10081 /*! DECODED_HAMM_DIST - Hamming distance between the reference sequence and the Viterbi decoded rec…
10086 /*! AA_FOUND - Indicates that a AA detect is active for both LR and uncoded. */
10091 /*! CI - CI received. */
10096 /*! CODED_HAMM_DIST - Hamming distance between the coded reference sequence and the coded received …
10101 /*! AA_CORR_MAX - Indicates the AA correlation magnitude witnessed when AA match occurred */
10106 /*! CMAG_MAX - Indicates the maximum preamble correlation magnitude during preamble found */
10110 /*! @name SM_CFG - PHY State Machine Config */
10115 /*! ACQ_MODE - Acquisition mode for non-coded reception
10126 /*! EN_PHY_SM_EXT_RST - Enable PHY state-machine reset on the external reset port; Reserved, should…
10134 /*! AGC_FRZ_ON_PD_FOUND_ACQ1_LR - Specfies AGC freeze condition for non-coded acq.1 and Bluetooth L…
10142 /*! PH_BUFF_PTR_SYM - Phase buffer size to demodulator, long range only. */
10147 /*! EARLY_PD_TIMEOUT - Time-out used to reset the AGC state-machine for the eventuality that an "PD
10154 /*! AA_TIMEOUT_UNCODED - Time-out value for access address search for uncoded packets */
10158 /*! @name MISC - PHY Misc Config */
10163 /*! RSSI_CORR_TH - Threshold use to compare a correlation magnitude value, computed in the
10171 /*! DMA_PAGE_SEL - Select which DMA page is send out
10174 * 0b010..Select DMA PAGE 2 for un-coded;
10182 /*! ECO1_RSVD - Reserved. Must be programed as reset value 0. */
10187 /*! PHY_CLK_CTRL - Enables various clock gating features. Bits are individually decoded, so any com…
10192 /*! ECO2_RSVD - Reserved */
10197 /*! DTEST_MUX_EN - Reserved. Should be programed as reset value 0. */
10202 /*! PHY_CLK_ON - Force PHY clock ON */
10206 /*! @name STAT0 - PHY Status 0 */
10211 /*! PD_FOUND - PD_FOUND for LR or uncoded */
10216 /*! LR_DET_FLAG - Indicates Bluetooth LE long range was detected */
10221 /*! AA_MATCHED - Indicates AA was matched for LR or uncoded */
10226 /*! AA_FOUND_ID - Indicates which AA was matched for LR and uncode
10237 /*! DATA_RATE - Indicates the data rate of received bit
10247 /*! FRAC - Indicates the fractional timing estimate determined in the acquisition block. Format is
10254 /*! CFO_EST - Indicates the currently estimated CFO. Format is sfix10_en9(sign extend form sfix8_en…
10258 /*! @name STAT1 - PHY Status 1 */
10263 /*! AA_BITS - AA bits either received or programed */
10267 /*! @name STAT2 - PHY Status 2 */
10272 /*! CNT_ANT_SW - Count of uncoded ANT switch event when FAD was enabled. */
10277 /*! CNT_UNCAA_TIMEOUT - Count of uncoded AA search timeout event */
10282 /*! CNT_LRAA_TIMEOUT - Count of lang range AA search timeout event */
10287 /*! CNT_AACI_TIMEOUT - Count of long range AACI detect timeout event */
10292 /*! CNT_AGC_RST - Count of AGC soft reset event */
10296 /*! @name PREPHY_MISC - PHY PrePHY Misc Config */
10301 /*! BUFF_PTR_LR - Pointer to the PrePHY IQ buffer for the reception of the long-range packets. */
10306 /*! BUFF_PTR_GFSK - Pointer to the PrePHY IQ buffer for the reception of the uncoded packets. */
10310 /*! @name DMD_CTRL0 - PHY Demodulator Control 0 */
10315 /*! TED_ACT_WIN - Active window size for the time tracking mechanism, expressed in symbols. */
10320 /*! FED_ACT_WIN - Active window size for the frequency tracking mechanism, expressed in symbols. */
10325 /*! DREP_SCALE_FREQ - Frequency domain signal scaling factor used by the de-repeater. */
10330 /*! REPEAT_FACTOR - Repetition factor used by the de-repeater. */
10335 /*! FED_ERR_SCALE - Scaling factor used by the freqency tracking loop. */
10340 /*! TERR_TRK_EN - Enables time tracking in the demodulator. */
10345 /*! FERR_TRK_EN - Enables frequency tracking in the demodulator. */
10350 /*! DREP_SINE_EN - Flag used to enable the non-linear operation in the de-repeater. */
10355 /*! DEMOD_MOD - Determines the number of taps used by the demodulator correlators;
10364 /*! @name DMD_CTRL1 - PHY Dmodulator Control 1 */
10369 /*! FED_IDLE_WIN - Idle window size for the frequency tracking mechanism, expressed in symbols. */
10374 /*! TED_ERR_SCALE - Scaling factor used by the time tracking loop. */
10379 /*! FED_IMM_MEAS_EN - Specifies whether the frequency tracking starts with an active window;
10387 /*! TED_IDLE_WIN - Idle window size for the time tracking mechanism, expressed in symbols. */
10392 /*! TTRK_INT_RANGE - Timing error correction interpolation range, expressed in samples. The value m…
10397 /*! TED_IMM_MEAS_EN - Specifies whether the time tracking starts with an active window;
10404 /*! @name DMD_CTRL2 - PHY Demodulator Control 2 */
10409 /*! WAIT_DMD_LR_ADJ - Reserved. Must be programed as reset value 1. */
10414 /*! WAIT_VIA_AFTER_AA_ADJ - Reserved. Must be programed as reset value 1. */
10419 /*! WAIT_DMD_CLKEN_ADJ - Reserved. Must be programed as reset value 1. */
10423 /*! @name DMD_WAVE_REG0 - */
10428 /*! SMPL0 - Demodulator waveform 7 sample 0 (sfix6en5) */
10433 /*! SMPL1 - Demodulator waveform 7 sample 1 (sfix6en5) */
10438 /*! SMPL2 - Demodulator waveform 7 sample 2 (sfix6en5) */
10443 /*! SMPL3 - Demodulator waveform 7 sample 3 (sfix6en5) */
10448 /*! SMPL4 - Demodulator waveform 7 sample 4 (sfix6en5) */
10455 /*! @name DMD_WAVE_REG1 - */
10460 /*! SMPL5 - Demodulator waveform 7 sample 5 (sfix6en5) */
10465 /*! SMPL6 - Demodulator waveform 7 sample 6 (sfix6en5) */
10470 /*! SMPL7 - Demodulator waveform 7 sample 7 (sfix6en5) */
10475 /*! SMPL8 - Demodulator waveform 7 sample 8 (sfix6en5) */
10480 /*! SMPL9 - Demodulator waveform 7 sample 9 (sfix6en5) */
10487 /*! @name DMD_WAVE_REG2 - */
10492 /*! SMPL10 - Demodulator waveform 7 sample 10 (sfix6en5) */
10497 /*! SMPL11 - Demodulator waveform 7 sample 11 (sfix6en5) */
10502 /*! SMPL12 - Demodulator waveform 7 sample 12 (sfix6en5) */
10509 /*! @name DMDAA_CTRL - PHY Demodulator Based SFD Confirmation control register. */
10514 /*! DMDAA_HAMM_LP - Maximum hamming distance from the given AA pattern that may still be accepted as
10521 /*! DMDAA_HAMM_HP - Maximum hamming distance from the given AA pattern that may still be accepted as
10528 /*! HIPOW_DIS_OVRD - Override the feature: disable DMDAA when power sensitivity is higher;
10536 /*! DMDAA_EN - Enables Demodulator Based SFD Confirmation;
10543 /*! @name RTT_STAT - High resolution Time-Of-Flight calculation Status. */
10548 /*! RTT_CFO - The high accuracy CFO computed by the HARTT block through the CORDIC algorithm. */
10553 /*! RTT_P_DELTA - Difference between the squared correlation magnitude values, pm-pp provided by th…
10558 /*! RTT_DIST_SAT - Computed Hamming distance saturated to 2 bits, format is ufix2. */
10563 /*! RTT_INT_ADJ - An integer adjustment of the timing which takes a value different of 0 when the
10564 * early-late mechanism in the HARTT block chooses a peak different of the one chosen in the
10565 * acquisition module (possible values are {-1,0,+1}).
10571 /*! RTT_FOUND - Flag that indicates that the HARTT operation is done and a valid PN pattern was det…
10575 /*! @name RTT_CTRL - PHY RTT control register. */
10580 /*! HA_RTT_THRESHOLD - threshold used to validate a HA RTT result. */
10585 /*! FIRST_PDU_BIT - is programmed by software - used for regular packets high accuracy RTT; */
10590 /*! RTT_SEQ_LEN - can be either 32 (when 0) or 64 bits (when 1) depending on the RTT configuration;…
10595 /*! OVERRD_PROGR_AA - Enables overriding the programmed AA bits with the PN sequence used by RTT; */
10600 /*! EN_HIGH_ACC_RTT - enables the use of the HA RTT block; */
10604 /*! @name RTT_REF - PHY RTT reference register. */
10609 /*! FM_REF_010 - Contextual values used to derive the FM reference ha_rtt_threshold . */
10614 /*! FM_REF_110 - Contextual values used to derive the FM reference ha_rtt_threshold . */
10619 /*! FM_REF_111 - Contextual values used to derive the FM reference ha_rtt_threshold . */
10629 /* GEN4PHY - Peripheral instance base addresses */
10663 /* ----------------------------------------------------------------------------
10664 -- GENFSK Peripheral Access Layer
10665 ---------------------------------------------------------------------------- */
10672 /** GENFSK - Register Layout Typedef */
10734 …__IO uint32_t GTM_IPD; /**< GTM MODE INTER-PACKET DURATION, offset: 0xB0…
10772 /* ----------------------------------------------------------------------------
10773 -- GENFSK Register Masks
10774 ---------------------------------------------------------------------------- */
10781 /*! @name IRQ_CTRL - IRQ CONTROL */
10786 /*! SEQ_END_IRQ - Sequence End Interrupt
10794 /*! TX_IRQ - TX Interrupt
10802 /*! RX_IRQ - RX Interrupt
10810 /*! NTW_ADR_IRQ - Network Address Match Interrupt
10818 /*! T1_IRQ - Timer1 (T1) Compare Interrupt
10826 /*! T2_IRQ - Timer2 (T2) Compare Interrupt
10834 /*! PLL_UNLOCK_IRQ - PLL Unlock Interrupt
10842 /*! WAKE_IRQ - Wake Interrrupt
10850 /*! RX_WATERMARK_IRQ - RX Watermark Interrupt
10858 /*! TSM_IRQ - TSM Interrupt
10866 /*! CRC_VALID - CRC Valid */
10871 /*! ACK_IRQ - Auto ACK Interrupt
10879 /*! PHRFFAIL_IRQ - Received Frame PHR Fail Interrupt
10887 /*! FILTERFAIL_IRQ - Received Frame Filter Fail Interrupt
10895 /*! CCA_IRQ - CCA Interrupt
10903 /*! MS_IRQ - Mode Switch Interrupt
10911 /*! SEQ_END_IRQ_EN - SEQ_END_IRQ Enable
10919 /*! TX_IRQ_EN - TX_IRQ Enable
10927 /*! RX_IRQ_EN - RX_IRQ Enable
10935 /*! NTW_ADR_IRQ_EN - NTW_ADR_IRQ Enable
10943 /*! T1_IRQ_EN - T1_IRQ Enable
10951 /*! T2_IRQ_EN - T2_IRQ Enable
10959 /*! PLL_UNLOCK_IRQ_EN - PLL_UNLOCK_IRQ Enable
10967 /*! WAKE_IRQ_EN - WAKE_IRQ Enable
10975 /*! RX_WATERMARK_IRQ_EN - RX_WATERMARK_IRQ Enable
10983 /*! TSM_IRQ_EN - TSM_IRQ Enable
10991 /*! GENERIC_FSK_IRQ_EN - GENERIC_FSK_IRQ Master Enable
10999 /*! ACK_IRQ_EN - ACK_IRQ Enable
11007 /*! PHRFAIL_IRQ_EN - PHRFAIL_IRQ Enable
11015 /*! FILTERFAIL_IRQ_EN - FILTERFAIL_IRQ Enable
11023 /*! CCA_IRQ_EN - CCA_IRQ Enable
11031 /*! MS_IRQ_EN - MS_IRQ Enable
11038 /*! @name EVENT_TMR - EVENT TIMER */
11043 /*! EVENT_TMR - Event Timer */
11047 /*! @name T1_CMP - T1 COMPARE */
11052 /*! T1_CMP - Timer1 (T1) Compare Value */
11056 /*! @name T2_CMP - T2 COMPARE */
11061 /*! T2_CMP - Timer2 (T2) Compare Value */
11065 /*! @name TIMESTAMP - TIMESTAMP */
11070 /*! TIMESTAMP - Received Packet Timestamp */
11074 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
11079 /*! SEQCMD - Sequence Commands, also named as "XCVSEQ(Transceiver Sequence)"
11084 * 0b00100..TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress
11090 * 0b01010..RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress
11091 * 0b01011..Abort All - Cancels all pending events and abort any sequence-in-progress
11095 * 0b01111..TR Cancel -- Cancels pending TR events but do not abort a TR-in-progress
11099 * 0b10011..CCA Cancel -- Cancels pending CCA events but do not abort a CCA-in-progress
11105 /*! LENGTH_EXT - Extracted Length Field */
11110 /*! CMDDEC_CS - Command Decode */
11115 /*! XCVR_BUSY - Transceiver Busy
11122 /*! @name XCVR_STS - TRANSCEIVER STATUS */
11127 /*! LQI - Link Quality Indicator */
11132 /*! LQI_VALID - LQI Valid Indicator
11140 /*! RSSI - RSSI Value */
11144 /*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
11149 /*! TX_WHITEN_DIS - TX Whitening Disable */
11154 /*! RX_DEWHITEN_DIS - RX De-Whitening Disable */
11159 /*! SW_CRC_EN - Software CRC Enable */
11164 /*! STOP_POSTPONE_ON_AA - Postpone Stop Command Timeout On Access Address Match Enable
11173 /*! PREAMBLE_SZ - Preamble Size */
11178 /*! GEN_PREAMBLE - Preamble pattern */
11183 /*! PREAMBLE_SEL - Preamble Select
11195 /*! T1_CMP_EN - Timer1 (T1) Compare Enable */
11200 /*! T2_CMP_EN - Timer2 (T2) Compare Enable */
11204 /*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
11209 /*! CHANNEL_NUM0 - Channel Number for PAN0 */
11213 /*! @name TX_POWER - TRANSMIT POWER */
11218 /*! TX_POWER - Transmit Power */
11222 /*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
11227 /*! NTW_ADR_EN - Network Address Enable
11237 /*! NTW_ADR_MCH - Network Address Match
11247 /*! NTW_ADR_SZ - Network Address Size
11248 * 0b00..Network Address 0/1/2/3 requires a 8-bit correlation
11249 * 0b01..Network Address 0/1/2/3 requires a 16-bit correlation
11250 * 0b10..Network Address 0/1/2/3 requires a 24-bit correlation
11251 * 0b11..Network Address 0/1/2/3 requires a 32-bit correlation
11257 /*! NTW_ADR_THR - Network Address Threshold */
11261 /*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
11266 /*! NTW_ADR_0 - Network Address 0 */
11270 /*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
11275 /*! NTW_ADR_1 - Network Address 1 */
11279 /*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
11284 /*! NTW_ADR_2 - Network Address 2 */
11288 /*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
11293 /*! NTW_ADR_3 - Network Address 2 */
11297 /*! @name RX_WATERMARK - RECEIVE WATERMARK */
11302 /*! RX_WATERMARK - Receive Watermark */
11307 /*! BYTE_COUNTER - Byte Counter */
11311 /*! @name DSM_CTRL - DSM CONTROL */
11316 /*! GEN_SLEEP_REQUEST - GENERIC_FSK Deep Sleep Mode Request */
11320 /*! @name PART_ID - PART ID */
11325 /*! PART_ID - Part ID */
11329 /*! @name SLOT_PRELOAD - SLOT PRELOAD */
11334 /*! SLOT_PRELOAD - Slotted Mode Preload */
11338 /*! @name SLOT_TIME - SLOT TIME */
11343 /*! SLOT_TIME - Duration of the Backoff Slot */
11347 /*! @name TURNAROUND_TIME - TURNAROUND TIME */
11352 /*! TURNAROUND_TIME - RX-to-TX or TX-to-RX turnaround time */
11356 /*! @name ACKDELAY - ACK DELAY */
11361 /*! ACKDELAY - ACK Delay */
11365 /*! @name RXDELAY - RX DELAY */
11370 /*! RXDELAY - RX Delay */
11374 /*! @name TXDELAY - TX DELAY */
11379 /*! TXDELAY - TX Delay */
11383 /*! @name PACKET_CFG - PACKET CONFIGURATION */
11388 /*! LENGTH_SZ - LENGTH Size */
11393 /*! LENGTH_BIT_ORD - LENGTH Bit Order
11401 /*! SYNC_ADDR_SZ - Sync Address Size */
11406 /*! H0_SZ - H0 Size */
11411 /*! AA_PLAYBACK_CNT - AA PLAYBACK COUNT
11419 /*! LL_FETCH_AA - Link layer fetches AA from PHY
11427 /*! H1_SZ - H1 Size */
11432 /*! H1_FAIL - H1 Violated Status Bit */
11437 /*! H0_FAIL - H0 Violated Status Bit */
11442 /*! LENGTH_FAIL - Maximum Length Violated Status Bit */
11446 /*! @name H0_CFG - H0 CONFIGURATION */
11451 /*! H0_MATCH - H0 Match Register */
11456 /*! H0_MASK - H0 Mask Register */
11460 /*! @name H1_CFG - H1 CONFIGURATION */
11465 /*! H1_MATCH - H1 Match Register */
11470 /*! H1_MASK - H1 Mask Register */
11474 /*! @name CRC_CFG - CRC CONFIGURATION */
11479 /*! CRC_IGNORE - CRC Ignore
11487 /*! CRC_VALID - CRC Valid
11494 /*! @name LENGTH_ADJ - LENGTH ADJUSTMENT */
11499 /*! LENGTH_ADJ - Length Adjustment */
11503 /*! @name TIMESTAMP_RX_DONE - TIMESTAMP_RX_DONE */
11508 /*! TIMESTAMP_RX_DONE - Received Packet Timestamp. Captured at Rx done. */
11512 /*! @name TIMESTAMP_TX_DONE - TIMESTAMP_TX_DONE */
11517 /*! TIMESTAMP_TX_DONE - Received Packet Timestamp. Captured at Tx done. */
11521 /*! @name MULT_PKT_CTRL - MULT_PKT_CTRL */
11526 /*! SEG_SZ - RAM Segment Size */
11531 /*! PKT_INDEX - Packet Index */
11536 /*! SEG_BASE_ADDR - Segment Offset Address */
11541 /*! RESET_PKT_IDX - Reset the PKT_INDEX to zero */
11546 /*! MULT_PKT_EN - Enable to send or receive multiple packets
11553 /*! @name RPA_WL_STATUS - RPA AND WHITE LIST STATUS */
11558 /*! WL_MATCH_INDEX - The matched white list index of the identity address resolved(RPA is enabled)
11565 /*! PEER_RESOLVED_INDEX - The matched RPA index of peer address */
11570 /*! LOCAL_RESOLVED_INDEX - The matched RPA index of local address */
11575 /*! SEARCH_WL - Search Identity Address in White List */
11579 /*! @name LENGTH_MAX - MAXIMUM LENGTH */
11584 /*! LENGTH_MAX - Maximum Length for Received Packets */
11589 /*! REC_BAD_PKT - Receive Bad Packets
11596 /*! @name EVENT_TMR_LD - EVENT TIMER LOAD */
11601 /*! EVENT_TMR_LD - Event Timer Load */
11605 /*! @name EVENT_TMR_ADD - EVENT TIMER ADD */
11610 /*! EVENT_TMR_ADD - Event Timer Add */
11614 /*! @name ENH_FEATURE - ENHANCED FEATURES */
11619 /*! GENLL_MODE - Linklayer Mode Select
11641 /*! SEL_RXIRQ - Select the RX IRQ assert time
11644 * in Bluetooth LE-LR and CTE bits as needed.
11650 /*! DATARATE_CONFIG_SEL - Select the data rate configuration bank
11658 /*! STAY_IN_RX - Stay in receive
11666 /*! PHR_TYPE - PHR Type
11676 /*! SW_BUILD_ACK - Software builds the ACK packet in RAM
11684 /*! ACKBUF_SEL - ACK frame is in 64-byte dedicated RAM or TX buffer RAM
11685 * 0b0..ACK frame is in 64-byte dedicated RAM
11692 /*! AUTOACK - Auto Acknowledge Enable
11695 …* 0b1..sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack f…
11701 /*! RXACKRQD - Receive Acknowledge Frame required
11703 * 0b1..A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).
11709 /*! SLOTTED - Slotted Mode */
11714 /*! LENGTH_ACK - Length of the ACK frame(or part of the ACK frame) in RAM */
11719 /*! BLE_V5P1_CTE_EN - Bluetooth LE version 5.1 CTE feature enable
11727 /*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
11732 /*! BEACON_FT - Beacon Frame Type Enable
11740 /*! DATA_FT - Data Frame Type Enable
11748 /*! ACK_FT - Ack Frame Type Enable
11756 /*! CMD_FT - MAC Command Frame Type Enable
11764 /*! LLDN_FT - LLDN Frame Type Enable
11772 /*! MULTIPURPOSE_FT - Multipurpose Frame Type Enable
11780 /*! FRAGMENT_FT - Fragment Frame Type Enable
11788 /*! EXTENDED_FT - Extended Frame Type Enable
11796 /*! NS_FT - "Not Specified" Frame Type Enable
11798 …* 0b1..Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering …
11806 /*! FRM_VER_FILTER - Frame Version selector. */
11811 /*! EXTENDED_FCS_CHK - Verify FCS on Frame Type Extended
11813 …* 0b1..Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, …
11819 /*! FV2_BEACON_RECD - Frame Version 2 Beacon Packet Received
11827 /*! FV2_DATA_RECD - Frame Version 2 Data Packet Received
11835 /*! FV2_ACK_RECD - Frame Version 2 Acknowledge Packet Received
11843 /*! FV2_CMD_RECD - Frame Version 2 MAC Command Packet Received
11851 /*! LLDN_RECD - LLDN Packet Received
11859 /*! MULTIPURPOSE_RECD - Multipurpose Packet Received
11867 /*! FRAGMENT_RECD - Fragment Packet Received
11875 /*! EXTENDED_RECD - Extended Packet Received
11883 /*! RXCYC_SEL - Rx Recycle Time Select
11891 /*! FILTER_FAIL_IGNORE - Filter Fail Ignore
11899 /*! PROMISCUOUS - Promiscuous Mode Enable
11907 /*! ENH_PKT_STATUS - Enhanced Packet Status
11908 * 0b0..The last packet received was not 2015-compliant
11909 …* 0b1..The last packet received was 2015-compliant (RX_FRAME_FILTER register should be queried fo…
11914 /*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
11919 /*! FILTERFAIL_CODE_PAN - Filter Fail Code When in PAN Mode */
11924 /*! FILTERFAIL_CODE_FAN - Filter Fail Code When in FAN Mode */
11929 /*! FILTERFAIL_PAN_SEL - PAN Selector for Filter Fail Code
11937 /*! FILTERFAIL_FLAG_SEL - Consolidated Filter Fail Flag */
11941 /*! @name LENIENCY_LSB - LENIENCY LSB */
11946 /*! LENIENCY_LSB - Leniency LSB Register */
11950 /*! @name RPA_CTRL - RPA CONTROL */
11994 /*! @name LENIENCY_MSB - LENIENCY MSB */
11999 /*! LENIENCY_MSB - Leniency MSB Register */
12003 /*! @name WL_CTRL - WHITE LIST CONTROL */
12031 /*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
12036 /*! ACTIVE_NETWORK - Active Network Selector
12044 /*! DUAL_PAN_AUTO - Activates automatic Dual PAN operating mode */
12049 /*! CURRENT_NETWORK - Indicates which PAN is currently selected by hardware
12057 /*! DUAL_PAN_DWELL - Dual PAN Channel Frequency Dwell Time */
12062 /*! DUAL_PAN_REMAIN - Time Remaining before next PAN switch in auto Dual PAN mode */
12067 /*! MODE_PAN0 - PAN0 Mode Select
12075 /*! MODE_PAN1 - PAN1 Mode Select
12083 /*! DP_CHAN_OVRD_EN - Dual PAN Channel Override Enable */
12088 /*! DP_CHAN_OVRD_SEL - Dual PAN Channel Override Selector */
12093 /*! PANCORDNTR0 - Device is a PAN Coordinator on PAN0 */
12098 /*! PANCORDNTR1 - Device is a PAN Coordinator on PAN1 */
12103 /*! RECD_ON_PAN0 - Last Packet was Received on PAN0 */
12108 /*! RECD_ON_PAN1 - Last Packet was Received on PAN1 */
12112 /*! @name GTM_PDU - GTM MODE PDU */
12117 /*! GTM_PDU - GTM MODE PDU */
12121 /*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
12126 /*! MACPANID1 - MAC PAN ID for PAN1 */
12131 /*! MACSHORTADDRS1 - MAC SHORT ADDRESS for PAN1 */
12135 /*! @name WL_VALID_ENTRY1 - VALID ENTRY OF WHITE LIST 1 */
12143 /*! @name DIRECT_PEER_ADDR_LSB - DIRECT_PEER_ADDR[31:0] */
12151 /*! @name GTM_CFG - GTM MODE CONFIGURATION */
12156 /*! GTM_PKT_NUM - GTM MODE PACKET NUMBER */
12161 /*! GTM_PDU_TYPE - GTM MODE PDU TYPE SELECTION
12163 * 0b0001..Programmable 8-bit Pattern (from register GTM_PDU[7:0], reused from MACSHORTADDRS1[7:0])
12164 * 0b0010..PRBS-13 Sequence
12165 * 0b0011..PRBS-15 Sequence
12166 …* 0b0100..Programmable 32-bit Pattern (from register GTM_PDU[31:0], reused from {MACSHORTADDRS1,M…
12173 /*! GTM_IPD_CHECK_DIS - GTM MODE INTER-PACKET DURATION CHECK DISABLE */
12178 /*! GTM_PKT_COUNT_CHECK_DIS - GTM MODE PACKET NUMBER CHECK DISABLE */
12182 /*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
12187 /*! MACLONGADDRS1_LSB - MAC LONG ADDRESS for PAN1 LSB */
12191 /*! @name DIRECT_PEER_ADDR_MSB - DIRECT_PEER_ADDR[47:32] */
12207 /*! @name GTM_IPD - GTM MODE INTER-PACKET DURATION */
12212 /*! GTM_IPD - GTM MODE INTER-PACKET DURATION */
12216 /*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
12221 /*! MACLONGADDRS1_MSB - MAC LONG ADDRESS for PAN1 MSB */
12225 /*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
12230 /*! CHANNEL_NUM1 - Channel Number for PAN1 */
12234 /*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
12239 /*! MACPANID0 - MAC PAN ID for PAN0 */
12244 /*! MACSHORTADDRS0 - MAC SHORT ADDRESS FOR PAN0 */
12248 /*! @name WL_VALID_ENTRY0 - VALID ENTRY OF WHITE LIST 0 */
12256 /*! @name GTM_FIRST_SFD2WD - GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN */
12261 /*! GTM_FIRST_SFD2WD - GTM MODE TIME OF FIRST SFD FOUND TO FORCE RX WARMDOWN */
12265 /*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
12270 /*! MACLONGADDRS0_LSB - MAC LONG ADDRESS for PAN0 LSB */
12274 /*! @name WL_SEARCH_ADDR_LSB - WL_SEARCH_ADDR[31:0] */
12282 /*! @name GTM_RX_RECYCLE_TIME - GTM MODE RX RECYCLE TIME */
12287 /*! GTM_RX_RECYCLE_TIME - GTM MODE RX RECYCLE TIME */
12291 /*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
12296 /*! MACLONGADDRS0_MSB - MAC LONG ADDRESS for PAN0 MSB */
12300 /*! @name WL_SEARCH_ADDR_MSB - WL_SEARCH_ADDR[47:32] */
12316 /*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
12321 /*! CCABFRTX - CCA Before TX
12329 /*! SIMUL_CCA_RX - Simultaneous CCA and Receive Enable
12337 /*! CCA - CCA Status
12345 /*! CCA1_THRESH - CCA Mode 1 Threshold */
12350 /*! CCA1_ED_FNL - Final Result for CCA Mode 1 and Energy Detect */
12354 /*! @name WARMUP_TIME - TX/RX WARMUP TIME */
12359 /*! RX_WARMUP - Receive Warmup Time */
12364 /*! TX_WARMUP - Transmit Warmup Time */
12368 /*! @name RXEN_DLY - RX_EN Delay Time */
12378 …* 0b0..For Bluetooth LE case, RX_EN signal will delay to de-assert accroding to the length of TER…
12380 …* 0b1..For all receive case, RX_EN signal will delay to de-assert accroding to register RXEN_DLY[…
12385 /*! @name SAM_CTRL - SAM CONTROL */
12390 /*! SAP0_EN - Enables SAP0 Partition of the SAM Table
12398 /*! SAA0_EN - Enables SAA0 Partition of the SAM Table
12406 /*! SAP1_EN - Enables SAP1 Partition of the SAM Table
12414 /*! SAA1_EN - Enables SAA1 Partition of the SAM Table
12422 /*! SAA0_START - First Index of SAA0 partition */
12427 /*! SAP1_START - First Index of SAP1 partition */
12432 /*! SAA1_START - First Index of SAA1 partition */
12436 /*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
12441 /*! SAM_INDEX - Contains the SAM table index to be enabled or invalidated */
12446 /*! SAM_INDEX_WR - Enables SAM Table Contents to be updated */
12451 /*! SAM_CHECKSUM - Software-computed source address checksum, to be installed into a table index */
12456 /*! SAM_INDEX_INV - Invalidate the SAM table index selected by SAM_INDEX */
12461 /*! SAM_INDEX_EN - Enable the SAM table index selected by SAM_INDEX */
12466 /*! ACK_FRM_PND - State of AutoTxAck FramePending field when SAM Accelleration is Disabled */
12471 /*! ACK_FRM_PND_CTRL - Manual Control for AutoTxAck FramePending field
12479 /*! FIND_FREE_IDX - Find First Free Index */
12484 /*! INVALIDATE_ALL - Invalidate Entire SAM Table */
12489 /*! SRCADDR - Source Address Match Status */
12494 /*! SAM_BUSY - SAM Table Update Status Bit */
12498 /*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
12503 /*! SAP0_MATCH - Index in the SAP0 Partition of the SAM Table corresponding to the first checksum m…
12508 /*! SAP0_ADDR_PRESENT - A Checksum Match is Present in the SAP0 Partition of the SAM Table */
12513 /*! SAA0_MATCH - Index in the SAA0 Partition of the SAM Table corresponding to the first checksum m…
12518 /*! SAA0_ADDR_ABSENT - A Checksum Match is Absent in the SAA0 Partition of the SAM Table */
12523 /*! SAP1_MATCH - Index in the SAP1 Partition of the SAM Table corresponding to the first checksum m…
12528 /*! SAP1_ADDR_PRESENT - A Checksum Match is Present in the SAP1 Partition of the SAM Table */
12533 /*! SAA1_MATCH - Index in the SAA1 Partition of the SAM Table corresponding to the first checksum m…
12538 /*! SAA1_ADDR_ABSENT - A Checksum Match is Absent in the SAP1 Partition of the SAM Table */
12542 /*! @name SAM_FREE_IDX - SAM FREE INDEX */
12547 /*! SAP0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP0 partition */
12552 /*! SAA0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA0 partition */
12557 /*! SAP1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP1 partition */
12562 /*! SAA1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA1 partition */
12566 /*! @name MISC1 - MISCELLANEOUS(1) */
12571 /*! SRC_ADDR_CHECKSUM - Hardware-computed received source address checksum */
12576 /*! SW_ABORTED - Autosequence has terminated due to a Software abort. */
12581 /*! PLL_ABORTED - Autosequence has terminated due to an PLL unlock event. */
12586 /*! EXT_ABORTED - Autosequence has terminated due to a Wake-On-Radio command */
12591 /*! ARB_GRANT_DEASSERTION_ABORTED - Autosequence has terminated due to an arb_grant deassertion eve…
12596 /*! FAST_TX_WU_OVRD - FAST_TX_WU override
12604 /*! FAST_RX_WU_OVRD - FAST_RX_WU override
12612 /*! PI - Poll Indication
12621 /*! RX_FRM_PEND - RX Frame Pending */
12625 /*! @name SEQ_STS - SEQUENCE STATUS */
12630 /*! TX_START_T1_PEND - TX T1 Start Pending Status */
12635 /*! TX_START_T2_PEND - TX T2 Start Pending Status */
12640 /*! TX_IN_WARMUP - TX Warmup Status */
12645 /*! TX_IN_PROGRESS - TX in Progress Status */
12650 /*! TX_IN_WARMDN - TX Warmdown Status */
12655 /*! RX_START_T1_PEND - RX T1 Start Pending Status */
12660 /*! RX_START_T2_PEND - RX T2 Start Pending Status */
12665 /*! RX_STOP_T1_PEND - RX T1 Stop Pending Status */
12670 /*! RX_STOP_T2_PEND - RX T2 Start Pending Status */
12675 /*! RX_IN_WARMUP - RX Warmup Status */
12680 /*! RX_IN_SEARCH - RX Search Status */
12685 /*! RX_IN_PROGRESS - RX in Progress Status */
12690 /*! RX_IN_WARMDN - RX Warmdown Status */
12695 /*! TR_START_T1_PEND - TR T1 Start Pending Status */
12700 /*! TR_START_T2_PEND - TR T2 Start Pending Status */
12705 /*! CCA_START_T1_PEND - CCA T1 Start Pending Status */
12710 /*! CCA_START_T2_PEND - CCA T2 Start Pending Status */
12715 /*! SEQ_T_STATUS - Status of the just-completed or ongoing Sequence T or Sequence TR */
12719 /*! @name PHR_MISC - PHR MISCELLANEOUS */
12724 /*! SUNFSK_MS - Mode Switch Bit */
12729 /*! SUNFSK_MSP - Mode Switch Parameter Bit */
12734 /*! SUNFSK_FEC - New Mode FEC Bit */
12739 /*! SUNFSK_NM - New Mode Bit */
12744 /*! PHR_FAIL_IGNORE - Ignore PHR Fail */
12748 /*! @name GTM_CTRL - GTM CONTROL */
12753 /*! GTM_IN_RX - Enable GTM Receive Mode
12761 /*! GTM_IN_TX - Enable GTM Transmit Mode
12768 /*! @name GTM_BAD_CNT - GTM BAD PACKET COUNTER */
12773 /*! GTM_BAD_PKT_COUNT - GTM Bad Packet Counter */
12777 /*! @name GTM_GOOD_CNT - GTM GOOD PACKET COUNTER */
12782 /*! GTM_GOOD_PKT_COUNT - GTM Good Packet Counter */
12786 /*! @name GTM_PKT_CNT - GTM PACKET COUNTER */
12791 /*! GTM_PKT_COUNT - GTM Packet Counter */
12795 /*! @name COEX_CTRL - COEXISTENCE CONTROL */
12800 /*! COEX_EN - Coexistence Enable
12808 /*! COEX_REQ_DELAY_EN - Coexistence Request Delay Enable
12816 /*! COEX_REQ_ON_PD - Coexistence Request on Preamble detected
12824 /*! COEX_TIMEOUT - Coexistence timeout value */
12828 /*! @name COEX_PRIORITY - COEXISTENCE PRIORITY */
12833 /*! PRIORITY_T - PRIORITY_T */
12838 /*! PRIORITY_R_PRE - PRIORITY_R_PRE */
12843 /*! PRIORITY_R_PKT - PRIORITY_R_PKT */
12848 /*! PRIORITY_TACK - PRIORITY_TACK */
12853 /*! PRIORITY_CCA - PRIORITY_CCA */
12858 /*! PRIORITY_CTX - PRIORITY_CT */
12863 /*! PRIORITY_RACK_PRE - PRIORITY_RACK_PRE */
12868 /*! PRIORITY_RACK_PKT - PRIORITY_RACK_PKT */
12873 /*! PRIORITY_OVRD - PRIORITY_OVRD */
12878 /*! PRIORITY_OVRD_EN - PRIORITY_OVRD_EN
12885 /*! @name IRQ_CTRL2 - IRQ CONTROL 2 */
12890 /*! ARB_GRANT_DEASSERTION_IRQ - arb_grant Deassertion IRQ
12898 /*! COEX_TIMEOUT_IRQ - Coexistence Timeout Interrupt */
12903 /*! EVENT_TIMER_OVER_FLOW_IRQ - Event Timer Overflow Interrupt */
12908 /*! WL_FAIL_IRQ - White List Check Fail Interrupt */
12913 /*! DIRECT_ID_FAIL_IRQ - Direct Case Check Fail Interrupt */
12918 /*! PEER_RPA_FAIL_IRQ - Peer RPA Check Fail Interrupt */
12923 /*! LOCAL_RPA_FAIL_IRQ - Local RPA Check Fail Interrupt */
12928 /*! ARB_GRANT_DEASSERTION_IRQ_EN - arb_grant Deassertion Interrupt enable
12936 /*! COEX_TIMEOUT_IRQ_EN - Coexistence Timeout Interrupt enable bit
12944 /*! EVENT_TIMER_OVER_FLOW_IRQ_EN - Event Timer Overflow Interrupt enable bit
12989 /* GENFSK - Peripheral instance base addresses */
13023 /* ----------------------------------------------------------------------------
13024 -- GPIO Peripheral Access Layer
13025 ---------------------------------------------------------------------------- */
13032 /** GPIO - Register Layout Typedef */
13038 __IO uint32_t PCNS; /**< Pin Control Non-Secure, offset: 0x10 */
13039 …__IO uint32_t ICNS; /**< Interrupt Control Non-Secure, offset: 0x14 */
13040 __IO uint32_t PCNP; /**< Pin Control Non-Privilege, offset: 0x18 */
13041 …__IO uint32_t ICNP; /**< Interrupt Control Non-Privilege, offset: 0x1…
13059 /* ----------------------------------------------------------------------------
13060 -- GPIO Register Masks
13061 ---------------------------------------------------------------------------- */
13068 /*! @name VERID - Version ID */
13073 /*! FEATURE - Feature Specification Number
13081 /*! MINOR - Minor Version Number */
13086 /*! MAJOR - Major Version Number */
13090 /*! @name PARAM - Parameter */
13095 /*! IRQNUM - Interrupt Number */
13099 /*! @name LOCK - Lock */
13104 /*! PCNS - Lock PCNS
13105 * 0b0..PCNS register is writable by software in Secure-Privilege state.
13112 /*! ICNS - Lock ICNS
13113 * 0b0..ICNS register is writable by software in Secure-Privilege state.
13120 /*! PCNP - Lock PCNP
13121 * 0b0..PCNP register is writable by software in Secure-Privilege state.
13128 /*! ICNP - Lock ICNP
13129 * 0b0..ICNP register is writable by software in Secure-Privilege state.
13135 /*! @name PCNS - Pin Control Non-Secure */
13140 /*! NSE0 - Non-Secure Enable
13143 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13145 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13146 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13154 /*! NSE1 - Non-Secure Enable
13157 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13159 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13160 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13168 /*! NSE2 - Non-Secure Enable
13171 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13173 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13174 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13182 /*! NSE3 - Non-Secure Enable
13185 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13187 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13188 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13196 /*! NSE4 - Non-Secure Enable
13199 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13201 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13202 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13210 /*! NSE5 - Non-Secure Enable
13213 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13215 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13216 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13224 /*! NSE6 - Non-Secure Enable
13227 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13229 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13230 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13238 /*! NSE7 - Non-Secure Enable
13241 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13243 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13244 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13252 /*! NSE8 - Non-Secure Enable
13255 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13257 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13258 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13266 /*! NSE9 - Non-Secure Enable
13269 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13271 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13272 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13280 /*! NSE10 - Non-Secure Enable
13283 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13285 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13286 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13294 /*! NSE11 - Non-Secure Enable
13297 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13299 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13300 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13308 /*! NSE12 - Non-Secure Enable
13311 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13313 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13314 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13322 /*! NSE13 - Non-Secure Enable
13325 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13327 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13328 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13336 /*! NSE14 - Non-Secure Enable
13339 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13341 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13342 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13350 /*! NSE15 - Non-Secure Enable
13353 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13355 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13356 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13364 /*! NSE16 - Non-Secure Enable
13367 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13369 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13370 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13378 /*! NSE17 - Non-Secure Enable
13381 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13383 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13384 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13392 /*! NSE18 - Non-Secure Enable
13395 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13397 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13398 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13406 /*! NSE19 - Non-Secure Enable
13409 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13411 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13412 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13420 /*! NSE20 - Non-Secure Enable
13423 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13425 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13426 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13434 /*! NSE21 - Non-Secure Enable
13437 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13439 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13440 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13448 /*! NSE22 - Non-Secure Enable
13451 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13453 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13454 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13462 /*! NSE23 - Non-Secure Enable
13465 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13467 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13468 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13476 /*! NSE24 - Non-Secure Enable
13479 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13481 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13482 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13490 /*! NSE25 - Non-Secure Enable
13493 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13495 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13496 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13504 /*! NSE26 - Non-Secure Enable
13507 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13509 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13510 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13518 /*! NSE27 - Non-Secure Enable
13521 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13523 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13524 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13532 /*! NSE28 - Non-Secure Enable
13535 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13537 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13538 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13546 /*! NSE29 - Non-Secure Enable
13549 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13551 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13552 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13560 /*! NSE30 - Non-Secure Enable
13563 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13565 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13566 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13574 /*! NSE31 - Non-Secure Enable
13577 …* by software in Non-Secure state, all bits in the registers related to that pin are read ze…
13579 …* 0b1..The pin is configured for Non-Secure access. Read or write access to the corresponding pin…
13580 …* and bit fields is only allowed by software in Non-Secure state. When the corresponding pin…
13587 /*! @name ICNS - Interrupt Control Non-Secure */
13592 /*! NSE0 - Non-Secure Enable
13596 …* 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only sof…
13597 …* Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or…
13604 /*! NSE1 - Non-Secure Enable
13608 …* 0b1..The interrupt, output trigger or DMA request is configured for Non-Secure access. Only sof…
13609 …* Non-Secure state can configure a pin to use the corresponding interrupt, output trigger or…
13615 /*! @name PCNP - Pin Control Non-Privilege */
13620 /*! NPE0 - Non-Privilege Enable
13623 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13625 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13626 * is allowed by software in both Privilege or Non-Privilege state.
13632 /*! NPE1 - Non-Privilege Enable
13635 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13637 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13638 * is allowed by software in both Privilege or Non-Privilege state.
13644 /*! NPE2 - Non-Privilege Enable
13647 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13649 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13650 * is allowed by software in both Privilege or Non-Privilege state.
13656 /*! NPE3 - Non-Privilege Enable
13659 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13661 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13662 * is allowed by software in both Privilege or Non-Privilege state.
13668 /*! NPE4 - Non-Privilege Enable
13671 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13673 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13674 * is allowed by software in both Privilege or Non-Privilege state.
13680 /*! NPE5 - Non-Privilege Enable
13683 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13685 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13686 * is allowed by software in both Privilege or Non-Privilege state.
13692 /*! NPE6 - Non-Privilege Enable
13695 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13697 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13698 * is allowed by software in both Privilege or Non-Privilege state.
13704 /*! NPE7 - Non-Privilege Enable
13707 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13709 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13710 * is allowed by software in both Privilege or Non-Privilege state.
13716 /*! NPE8 - Non-Privilege Enable
13719 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13721 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13722 * is allowed by software in both Privilege or Non-Privilege state.
13728 /*! NPE9 - Non-Privilege Enable
13731 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13733 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13734 * is allowed by software in both Privilege or Non-Privilege state.
13740 /*! NPE10 - Non-Privilege Enable
13743 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13745 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13746 * is allowed by software in both Privilege or Non-Privilege state.
13752 /*! NPE11 - Non-Privilege Enable
13755 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13757 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13758 * is allowed by software in both Privilege or Non-Privilege state.
13764 /*! NPE12 - Non-Privilege Enable
13767 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13769 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13770 * is allowed by software in both Privilege or Non-Privilege state.
13776 /*! NPE13 - Non-Privilege Enable
13779 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13781 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13782 * is allowed by software in both Privilege or Non-Privilege state.
13788 /*! NPE14 - Non-Privilege Enable
13791 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13793 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13794 * is allowed by software in both Privilege or Non-Privilege state.
13800 /*! NPE15 - Non-Privilege Enable
13803 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13805 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13806 * is allowed by software in both Privilege or Non-Privilege state.
13812 /*! NPE16 - Non-Privilege Enable
13815 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13817 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13818 * is allowed by software in both Privilege or Non-Privilege state.
13824 /*! NPE17 - Non-Privilege Enable
13827 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13829 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13830 * is allowed by software in both Privilege or Non-Privilege state.
13836 /*! NPE18 - Non-Privilege Enable
13839 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13841 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13842 * is allowed by software in both Privilege or Non-Privilege state.
13848 /*! NPE19 - Non-Privilege Enable
13851 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13853 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13854 * is allowed by software in both Privilege or Non-Privilege state.
13860 /*! NPE20 - Non-Privilege Enable
13863 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13865 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13866 * is allowed by software in both Privilege or Non-Privilege state.
13872 /*! NPE21 - Non-Privilege Enable
13875 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13877 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13878 * is allowed by software in both Privilege or Non-Privilege state.
13884 /*! NPE22 - Non-Privilege Enable
13887 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13889 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13890 * is allowed by software in both Privilege or Non-Privilege state.
13896 /*! NPE23 - Non-Privilege Enable
13899 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13901 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13902 * is allowed by software in both Privilege or Non-Privilege state.
13908 /*! NPE24 - Non-Privilege Enable
13911 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13913 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13914 * is allowed by software in both Privilege or Non-Privilege state.
13920 /*! NPE25 - Non-Privilege Enable
13923 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13925 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13926 * is allowed by software in both Privilege or Non-Privilege state.
13932 /*! NPE26 - Non-Privilege Enable
13935 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13937 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13938 * is allowed by software in both Privilege or Non-Privilege state.
13944 /*! NPE27 - Non-Privilege Enable
13947 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13949 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13950 * is allowed by software in both Privilege or Non-Privilege state.
13956 /*! NPE28 - Non-Privilege Enable
13959 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13961 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13962 * is allowed by software in both Privilege or Non-Privilege state.
13968 /*! NPE29 - Non-Privilege Enable
13971 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13973 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13974 * is allowed by software in both Privilege or Non-Privilege state.
13980 /*! NPE30 - Non-Privilege Enable
13983 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13985 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13986 * is allowed by software in both Privilege or Non-Privilege state.
13992 /*! NPE31 - Non-Privilege Enable
13995 …* are accessed by software in Non-Privilege state, all bits related to that pin in this GPIO…
13997 …* 0b1..The pin is configured for Non-Privilege access, Read or write access to the corresponding …
13998 * is allowed by software in both Privilege or Non-Privilege state.
14003 /*! @name ICNP - Interrupt Control Non-Privilege */
14008 /*! NPE0 - Non-Privilege Enable
14012 …* 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privil…
14020 /*! NPE1 - Non-Privilege Enable
14024 …* 0b1..The pin is configured for Non-Privilege access. Software in either Privilege or Non-Privil…
14031 /*! @name PDOR - Port Data Output Register */
14036 /*! PDO0 - Port Data Output
14037 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14038 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14044 /*! PDO1 - Port Data Output
14045 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14046 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14052 /*! PDO2 - Port Data Output
14053 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14054 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14060 /*! PDO3 - Port Data Output
14061 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14062 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14068 /*! PDO4 - Port Data Output
14069 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14070 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14076 /*! PDO5 - Port Data Output
14077 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14078 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14084 /*! PDO6 - Port Data Output
14085 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14086 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14092 /*! PDO7 - Port Data Output
14093 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14094 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14100 /*! PDO8 - Port Data Output
14101 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14102 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14108 /*! PDO9 - Port Data Output
14109 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14110 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14116 /*! PDO10 - Port Data Output
14117 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14118 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14124 /*! PDO11 - Port Data Output
14125 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14126 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14132 /*! PDO12 - Port Data Output
14133 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14134 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14140 /*! PDO13 - Port Data Output
14141 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14142 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14148 /*! PDO14 - Port Data Output
14149 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14150 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14156 /*! PDO15 - Port Data Output
14157 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14158 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14164 /*! PDO16 - Port Data Output
14165 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14166 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14172 /*! PDO17 - Port Data Output
14173 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14174 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14180 /*! PDO18 - Port Data Output
14181 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14182 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14188 /*! PDO19 - Port Data Output
14189 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14190 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14196 /*! PDO20 - Port Data Output
14197 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14198 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14204 /*! PDO21 - Port Data Output
14205 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14206 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14212 /*! PDO22 - Port Data Output
14213 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14214 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14220 /*! PDO23 - Port Data Output
14221 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14222 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14228 /*! PDO24 - Port Data Output
14229 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14230 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14236 /*! PDO25 - Port Data Output
14237 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14238 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14244 /*! PDO26 - Port Data Output
14245 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14246 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14252 /*! PDO27 - Port Data Output
14253 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14254 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14260 /*! PDO28 - Port Data Output
14261 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14262 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14268 /*! PDO29 - Port Data Output
14269 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14270 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14276 /*! PDO30 - Port Data Output
14277 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14278 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14284 /*! PDO31 - Port Data Output
14285 * 0b0..Logic level 0 is driven on pin, if the pin is configured for general-purpose output.
14286 * 0b1..Logic level 1 is driven on pin, if the pin is configured for general-purpose output.
14291 /*! @name PSOR - Port Set Output Register */
14296 /*! PTSO0 - Port Set Output
14304 /*! PTSO1 - Port Set Output
14312 /*! PTSO2 - Port Set Output
14320 /*! PTSO3 - Port Set Output
14328 /*! PTSO4 - Port Set Output
14336 /*! PTSO5 - Port Set Output
14344 /*! PTSO6 - Port Set Output
14352 /*! PTSO7 - Port Set Output
14360 /*! PTSO8 - Port Set Output
14368 /*! PTSO9 - Port Set Output
14376 /*! PTSO10 - Port Set Output
14384 /*! PTSO11 - Port Set Output
14392 /*! PTSO12 - Port Set Output
14400 /*! PTSO13 - Port Set Output
14408 /*! PTSO14 - Port Set Output
14416 /*! PTSO15 - Port Set Output
14424 /*! PTSO16 - Port Set Output
14432 /*! PTSO17 - Port Set Output
14440 /*! PTSO18 - Port Set Output
14448 /*! PTSO19 - Port Set Output
14456 /*! PTSO20 - Port Set Output
14464 /*! PTSO21 - Port Set Output
14472 /*! PTSO22 - Port Set Output
14480 /*! PTSO23 - Port Set Output
14488 /*! PTSO24 - Port Set Output
14496 /*! PTSO25 - Port Set Output
14504 /*! PTSO26 - Port Set Output
14512 /*! PTSO27 - Port Set Output
14520 /*! PTSO28 - Port Set Output
14528 /*! PTSO29 - Port Set Output
14536 /*! PTSO30 - Port Set Output
14544 /*! PTSO31 - Port Set Output
14551 /*! @name PCOR - Port Clear Output Register */
14556 /*! PTCO0 - Port Clear Output
14564 /*! PTCO1 - Port Clear Output
14572 /*! PTCO2 - Port Clear Output
14580 /*! PTCO3 - Port Clear Output
14588 /*! PTCO4 - Port Clear Output
14596 /*! PTCO5 - Port Clear Output
14604 /*! PTCO6 - Port Clear Output
14612 /*! PTCO7 - Port Clear Output
14620 /*! PTCO8 - Port Clear Output
14628 /*! PTCO9 - Port Clear Output
14636 /*! PTCO10 - Port Clear Output
14644 /*! PTCO11 - Port Clear Output
14652 /*! PTCO12 - Port Clear Output
14660 /*! PTCO13 - Port Clear Output
14668 /*! PTCO14 - Port Clear Output
14676 /*! PTCO15 - Port Clear Output
14684 /*! PTCO16 - Port Clear Output
14692 /*! PTCO17 - Port Clear Output
14700 /*! PTCO18 - Port Clear Output
14708 /*! PTCO19 - Port Clear Output
14716 /*! PTCO20 - Port Clear Output
14724 /*! PTCO21 - Port Clear Output
14732 /*! PTCO22 - Port Clear Output
14740 /*! PTCO23 - Port Clear Output
14748 /*! PTCO24 - Port Clear Output
14756 /*! PTCO25 - Port Clear Output
14764 /*! PTCO26 - Port Clear Output
14772 /*! PTCO27 - Port Clear Output
14780 /*! PTCO28 - Port Clear Output
14788 /*! PTCO29 - Port Clear Output
14796 /*! PTCO30 - Port Clear Output
14804 /*! PTCO31 - Port Clear Output
14811 /*! @name PTOR - Port Toggle Output Register */
14816 /*! PTTO0 - Port Toggle Output
14824 /*! PTTO1 - Port Toggle Output
14832 /*! PTTO2 - Port Toggle Output
14840 /*! PTTO3 - Port Toggle Output
14848 /*! PTTO4 - Port Toggle Output
14856 /*! PTTO5 - Port Toggle Output
14864 /*! PTTO6 - Port Toggle Output
14872 /*! PTTO7 - Port Toggle Output
14880 /*! PTTO8 - Port Toggle Output
14888 /*! PTTO9 - Port Toggle Output
14896 /*! PTTO10 - Port Toggle Output
14904 /*! PTTO11 - Port Toggle Output
14912 /*! PTTO12 - Port Toggle Output
14920 /*! PTTO13 - Port Toggle Output
14928 /*! PTTO14 - Port Toggle Output
14936 /*! PTTO15 - Port Toggle Output
14944 /*! PTTO16 - Port Toggle Output
14952 /*! PTTO17 - Port Toggle Output
14960 /*! PTTO18 - Port Toggle Output
14968 /*! PTTO19 - Port Toggle Output
14976 /*! PTTO20 - Port Toggle Output
14984 /*! PTTO21 - Port Toggle Output
14992 /*! PTTO22 - Port Toggle Output
15000 /*! PTTO23 - Port Toggle Output
15008 /*! PTTO24 - Port Toggle Output
15016 /*! PTTO25 - Port Toggle Output
15024 /*! PTTO26 - Port Toggle Output
15032 /*! PTTO27 - Port Toggle Output
15040 /*! PTTO28 - Port Toggle Output
15048 /*! PTTO29 - Port Toggle Output
15056 /*! PTTO30 - Port Toggle Output
15064 /*! PTTO31 - Port Toggle Output
15071 /*! @name PDIR - Port Data Input Register */
15076 /*! PDI0 - Port Data Input
15084 /*! PDI1 - Port Data Input
15092 /*! PDI2 - Port Data Input
15100 /*! PDI3 - Port Data Input
15108 /*! PDI4 - Port Data Input
15116 /*! PDI5 - Port Data Input
15124 /*! PDI6 - Port Data Input
15132 /*! PDI7 - Port Data Input
15140 /*! PDI8 - Port Data Input
15148 /*! PDI9 - Port Data Input
15156 /*! PDI10 - Port Data Input
15164 /*! PDI11 - Port Data Input
15172 /*! PDI12 - Port Data Input
15180 /*! PDI13 - Port Data Input
15188 /*! PDI14 - Port Data Input
15196 /*! PDI15 - Port Data Input
15204 /*! PDI16 - Port Data Input
15212 /*! PDI17 - Port Data Input
15220 /*! PDI18 - Port Data Input
15228 /*! PDI19 - Port Data Input
15236 /*! PDI20 - Port Data Input
15244 /*! PDI21 - Port Data Input
15252 /*! PDI22 - Port Data Input
15260 /*! PDI23 - Port Data Input
15268 /*! PDI24 - Port Data Input
15276 /*! PDI25 - Port Data Input
15284 /*! PDI26 - Port Data Input
15292 /*! PDI27 - Port Data Input
15300 /*! PDI28 - Port Data Input
15308 /*! PDI29 - Port Data Input
15316 /*! PDI30 - Port Data Input
15324 /*! PDI31 - Port Data Input
15331 /*! @name PDDR - Port Data Direction Register */
15336 /*! PDD0 - Port Data Direction
15337 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15338 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15344 /*! PDD1 - Port Data Direction
15345 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15346 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15352 /*! PDD2 - Port Data Direction
15353 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15354 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15360 /*! PDD3 - Port Data Direction
15361 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15362 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15368 /*! PDD4 - Port Data Direction
15369 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15370 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15376 /*! PDD5 - Port Data Direction
15377 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15378 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15384 /*! PDD6 - Port Data Direction
15385 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15386 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15392 /*! PDD7 - Port Data Direction
15393 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15394 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15400 /*! PDD8 - Port Data Direction
15401 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15402 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15408 /*! PDD9 - Port Data Direction
15409 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15410 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15416 /*! PDD10 - Port Data Direction
15417 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15418 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15424 /*! PDD11 - Port Data Direction
15425 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15426 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15432 /*! PDD12 - Port Data Direction
15433 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15434 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15440 /*! PDD13 - Port Data Direction
15441 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15442 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15448 /*! PDD14 - Port Data Direction
15449 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15450 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15456 /*! PDD15 - Port Data Direction
15457 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15458 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15464 /*! PDD16 - Port Data Direction
15465 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15466 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15472 /*! PDD17 - Port Data Direction
15473 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15474 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15480 /*! PDD18 - Port Data Direction
15481 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15482 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15488 /*! PDD19 - Port Data Direction
15489 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15490 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15496 /*! PDD20 - Port Data Direction
15497 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15498 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15504 /*! PDD21 - Port Data Direction
15505 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15506 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15512 /*! PDD22 - Port Data Direction
15513 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15514 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15520 /*! PDD23 - Port Data Direction
15521 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15522 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15528 /*! PDD24 - Port Data Direction
15529 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15530 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15536 /*! PDD25 - Port Data Direction
15537 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15538 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15544 /*! PDD26 - Port Data Direction
15545 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15546 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15552 /*! PDD27 - Port Data Direction
15553 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15554 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15560 /*! PDD28 - Port Data Direction
15561 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15562 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15568 /*! PDD29 - Port Data Direction
15569 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15570 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15576 /*! PDD30 - Port Data Direction
15577 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15578 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15584 /*! PDD31 - Port Data Direction
15585 * 0b0..Pin is configured as general-purpose input for the GPIO function.
15586 * 0b1..Pin is configured as general-purpose output for the GPIO function.
15591 /*! @name PIDR - Port Input Disable Register */
15596 /*! PID0 - Port Input Disable
15597 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15598 * 0b1..Pin is disabled for general-purpose input.
15604 /*! PID1 - Port Input Disable
15605 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15606 * 0b1..Pin is disabled for general-purpose input.
15612 /*! PID2 - Port Input Disable
15613 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15614 * 0b1..Pin is disabled for general-purpose input.
15620 /*! PID3 - Port Input Disable
15621 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15622 * 0b1..Pin is disabled for general-purpose input.
15628 /*! PID4 - Port Input Disable
15629 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15630 * 0b1..Pin is disabled for general-purpose input.
15636 /*! PID5 - Port Input Disable
15637 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15638 * 0b1..Pin is disabled for general-purpose input.
15644 /*! PID6 - Port Input Disable
15645 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15646 * 0b1..Pin is disabled for general-purpose input.
15652 /*! PID7 - Port Input Disable
15653 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15654 * 0b1..Pin is disabled for general-purpose input.
15660 /*! PID8 - Port Input Disable
15661 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15662 * 0b1..Pin is disabled for general-purpose input.
15668 /*! PID9 - Port Input Disable
15669 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15670 * 0b1..Pin is disabled for general-purpose input.
15676 /*! PID10 - Port Input Disable
15677 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15678 * 0b1..Pin is disabled for general-purpose input.
15684 /*! PID11 - Port Input Disable
15685 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15686 * 0b1..Pin is disabled for general-purpose input.
15692 /*! PID12 - Port Input Disable
15693 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15694 * 0b1..Pin is disabled for general-purpose input.
15700 /*! PID13 - Port Input Disable
15701 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15702 * 0b1..Pin is disabled for general-purpose input.
15708 /*! PID14 - Port Input Disable
15709 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15710 * 0b1..Pin is disabled for general-purpose input.
15716 /*! PID15 - Port Input Disable
15717 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15718 * 0b1..Pin is disabled for general-purpose input.
15724 /*! PID16 - Port Input Disable
15725 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15726 * 0b1..Pin is disabled for general-purpose input.
15732 /*! PID17 - Port Input Disable
15733 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15734 * 0b1..Pin is disabled for general-purpose input.
15740 /*! PID18 - Port Input Disable
15741 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15742 * 0b1..Pin is disabled for general-purpose input.
15748 /*! PID19 - Port Input Disable
15749 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15750 * 0b1..Pin is disabled for general-purpose input.
15756 /*! PID20 - Port Input Disable
15757 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15758 * 0b1..Pin is disabled for general-purpose input.
15764 /*! PID21 - Port Input Disable
15765 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15766 * 0b1..Pin is disabled for general-purpose input.
15772 /*! PID22 - Port Input Disable
15773 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15774 * 0b1..Pin is disabled for general-purpose input.
15780 /*! PID23 - Port Input Disable
15781 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15782 * 0b1..Pin is disabled for general-purpose input.
15788 /*! PID24 - Port Input Disable
15789 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15790 * 0b1..Pin is disabled for general-purpose input.
15796 /*! PID25 - Port Input Disable
15797 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15798 * 0b1..Pin is disabled for general-purpose input.
15804 /*! PID26 - Port Input Disable
15805 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15806 * 0b1..Pin is disabled for general-purpose input.
15812 /*! PID27 - Port Input Disable
15813 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15814 * 0b1..Pin is disabled for general-purpose input.
15820 /*! PID28 - Port Input Disable
15821 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15822 * 0b1..Pin is disabled for general-purpose input.
15828 /*! PID29 - Port Input Disable
15829 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15830 * 0b1..Pin is disabled for general-purpose input.
15836 /*! PID30 - Port Input Disable
15837 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15838 * 0b1..Pin is disabled for general-purpose input.
15844 /*! PID31 - Port Input Disable
15845 …* 0b0..Pin is configured for general-purpose input provided, the pin is configured for any digita…
15846 * 0b1..Pin is disabled for general-purpose input.
15851 /*! @name PDR - Pin Data Register a */
15856 /*! PD - Pin Data (input and output)
15866 /*! @name ICR - Interrupt Control Register 0..Interrupt Control Register 31 */
15871 /*! IRQC - Interrupt Configuration
15881 * 0b1001..ISF flag and Interrupt on rising-edge.
15882 * 0b1010..ISF flag and Interrupt on falling-edge.
15895 /*! IRQS - Interrupt Select
15903 /*! LK - Lock Register
15911 /*! ISF - Interrupt Status Flag
15924 /*! @name GICLR - Global Interrupt Control Low Register */
15929 /*! GIWE0 - Global Interrupt Write Enable
15930 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15931 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15937 /*! GIWE1 - Global Interrupt Write Enable
15938 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15939 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15945 /*! GIWE2 - Global Interrupt Write Enable
15946 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15947 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15953 /*! GIWE3 - Global Interrupt Write Enable
15954 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15955 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15961 /*! GIWE4 - Global Interrupt Write Enable
15962 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15963 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15969 /*! GIWE5 - Global Interrupt Write Enable
15970 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15971 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15977 /*! GIWE6 - Global Interrupt Write Enable
15978 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15979 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15985 /*! GIWE7 - Global Interrupt Write Enable
15986 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15987 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
15993 /*! GIWE8 - Global Interrupt Write Enable
15994 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
15995 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16001 /*! GIWE9 - Global Interrupt Write Enable
16002 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16003 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16009 /*! GIWE10 - Global Interrupt Write Enable
16010 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16011 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16017 /*! GIWE11 - Global Interrupt Write Enable
16018 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16019 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16025 /*! GIWE12 - Global Interrupt Write Enable
16026 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16027 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16033 /*! GIWE13 - Global Interrupt Write Enable
16034 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16035 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16041 /*! GIWE14 - Global Interrupt Write Enable
16042 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16043 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16049 /*! GIWE15 - Global Interrupt Write Enable
16050 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16051 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16057 /*! GIWD - Global Interrupt Write Data */
16061 /*! @name GICHR - Global Interrupt Control High Register */
16066 /*! GIWE16 - Global Interrupt Write Enable
16067 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16068 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16074 /*! GIWE17 - Global Interrupt Write Enable
16075 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16076 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16082 /*! GIWE18 - Global Interrupt Write Enable
16083 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16084 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16090 /*! GIWE19 - Global Interrupt Write Enable
16091 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16092 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16098 /*! GIWE20 - Global Interrupt Write Enable
16099 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16100 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16106 /*! GIWE21 - Global Interrupt Write Enable
16107 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16108 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16114 /*! GIWE22 - Global Interrupt Write Enable
16115 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16116 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16122 /*! GIWE23 - Global Interrupt Write Enable
16123 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16124 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16130 /*! GIWE24 - Global Interrupt Write Enable
16131 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16132 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16138 /*! GIWE25 - Global Interrupt Write Enable
16139 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16140 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16146 /*! GIWE26 - Global Interrupt Write Enable
16147 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16148 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16154 /*! GIWE27 - Global Interrupt Write Enable
16155 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16156 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16162 /*! GIWE28 - Global Interrupt Write Enable
16163 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16164 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16170 /*! GIWE29 - Global Interrupt Write Enable
16171 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16172 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16178 /*! GIWE30 - Global Interrupt Write Enable
16179 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16180 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16186 /*! GIWE31 - Global Interrupt Write Enable
16187 …* 0b0..Upper 16-bit of corresponding Interrupt Control Register is not updated with the value in …
16188 * 0b1..Upper 16-bit of corresponding Interrupt Control Register is updated with the value in GIWD.
16194 /*! GIWD - Global Interrupt Write Data */
16198 /*! @name ISFR - Interrupt Status Flag Register */
16203 /*! ISF0 - Interrupt Status Flag
16215 /*! ISF1 - Interrupt Status Flag
16227 /*! ISF2 - Interrupt Status Flag
16239 /*! ISF3 - Interrupt Status Flag
16251 /*! ISF4 - Interrupt Status Flag
16263 /*! ISF5 - Interrupt Status Flag
16275 /*! ISF6 - Interrupt Status Flag
16287 /*! ISF7 - Interrupt Status Flag
16299 /*! ISF8 - Interrupt Status Flag
16311 /*! ISF9 - Interrupt Status Flag
16323 /*! ISF10 - Interrupt Status Flag
16335 /*! ISF11 - Interrupt Status Flag
16347 /*! ISF12 - Interrupt Status Flag
16359 /*! ISF13 - Interrupt Status Flag
16371 /*! ISF14 - Interrupt Status Flag
16383 /*! ISF15 - Interrupt Status Flag
16395 /*! ISF16 - Interrupt Status Flag
16407 /*! ISF17 - Interrupt Status Flag
16419 /*! ISF18 - Interrupt Status Flag
16431 /*! ISF19 - Interrupt Status Flag
16443 /*! ISF20 - Interrupt Status Flag
16455 /*! ISF21 - Interrupt Status Flag
16467 /*! ISF22 - Interrupt Status Flag
16479 /*! ISF23 - Interrupt Status Flag
16491 /*! ISF24 - Interrupt Status Flag
16503 /*! ISF25 - Interrupt Status Flag
16515 /*! ISF26 - Interrupt Status Flag
16527 /*! ISF27 - Interrupt Status Flag
16539 /*! ISF28 - Interrupt Status Flag
16551 /*! ISF29 - Interrupt Status Flag
16563 /*! ISF30 - Interrupt Status Flag
16575 /*! ISF31 - Interrupt Status Flag
16595 /* GPIO - Peripheral instance base addresses */
16670 /* ----------------------------------------------------------------------------
16671 -- I3C Peripheral Access Layer
16672 ---------------------------------------------------------------------------- */
16679 /** I3C - Register Layout Typedef */
16694 …__O uint32_t SWDATAH; /**< Slave Write Data Half-word Register, offset:…
16695 …__O uint32_t SWDATAHE; /**< Slave Write Data Half-word End Register, off…
16698 …__I uint32_t SRDATAH; /**< Slave Read Data Half-word Register, offset: …
16707 …__I uint32_t SMSGMAPADDR; /**< Slave Message-Mapped Address Register, offse…
16711 …__IO uint32_t MIBIRULES; /**< Master In-band Interrupt Registry and Rules …
16721 …__O uint32_t MWDATAH; /**< Master Write Data Half-word Register, offset…
16725 …__I uint32_t MRDATAH; /**< Master Read Data Half-word Register, offset:…
16743 /* ----------------------------------------------------------------------------
16744 -- I3C Register Masks
16745 ---------------------------------------------------------------------------- */
16752 /*! @name MCONFIG - Master Configuration Register */
16757 /*! MSTENA - Master enable
16767 /*! DISTO - Disable Timeout */
16772 /*! HKEEP - High-Keeper
16782 /*! ODSTOP - Open drain stop */
16787 /*! PPBAUD - Push-pull baud rate */
16792 /*! PPLOW - Push-Pull low */
16797 /*! ODBAUD - Open drain baud rate */
16802 /*! ODHPP - Open drain high push-pull */
16807 /*! SKEW - Skew */
16812 /*! I2CBAUD - I2C baud rate */
16816 /*! @name SCONFIG - Slave Configuration Register */
16821 /*! SLVENA - Slave enable */
16826 /*! NACK - Not acknowledge */
16831 /*! MATCHSS - Match START or STOP */
16836 /*! S0IGNORE - S0/S1 errors ignore */
16841 /*! DDROK - Double Data Rate OK */
16846 /*! IDRAND - ID random */
16851 /*! OFFLINE - Offline */
16856 /*! BAMATCH - Bus available match */
16861 /*! SADDR - Static address */
16865 /*! @name SSTATUS - Slave Status Register */
16870 /*! STNOTSTOP - Status not stop */
16875 /*! STMSG - Status message */
16880 /*! STCCCH - Status Common Command Code Handler */
16885 /*! STREQRD - Status required */
16890 /*! STREQWR - Status request write */
16895 /*! STDAA - Status Dynamic Address Assignment */
16900 /*! STHDR - Status High Data Rate */
16905 /*! START - Start */
16910 /*! MATCHED - Matched */
16915 /*! STOP - Stop */
16920 /*! RX_PEND - Received message pending */
16925 /*! TXNOTFULL - Transmit buffer is not full */
16930 /*! DACHG - DACHG */
16935 /*! CCC - Common Command Code */
16940 /*! ERRWARN - Error warning */
16945 /*! HDRMATCH - High Data Rate command match */
16950 /*! CHANDLED - Common-Command-Code handled */
16955 /*! EVENT - Event */
16960 /*! EVDET - Event details
16970 /*! IBIDIS - In-Band Interrupts are disabled */
16975 /*! MRDIS - Master requests are disabled */
16980 /*! HJDIS - Hot-Join is disabled */
16985 /*! ACTSTATE - Activity state from Common Command Codes (CCC)
16995 /*! TIMECTRL - Time control
17004 /*! @name SCTRL - Slave Control Register */
17009 /*! EVENT - EVENT
17019 /*! IBIDATA - In-Band Interrupt Data */
17024 /*! PENDINT - Pending interrupt */
17029 /*! ACTSTATE - Activity state (of slave) */
17034 /*! VENDINFO - Vendor information */
17038 /*! @name SINTSET - Slave Interrupt Set Register */
17043 /*! START - Start interrupt enable */
17048 /*! MATCHED - Match interrupt enable */
17053 /*! STOP - Stop interrupt enable */
17058 /*! RXPEND - Receive interrupt enable */
17063 /*! TXSEND - Transmit interrupt enable */
17068 /*! DACHG - Dynamic address change interrupt enable */
17073 /*! CCC - Common Command Code (CCC) (that was not handled by I3C module) interrupt enable */
17078 /*! ERRWARN - Error/warning interrupt enable */
17083 /*! DDRMATCHED - Double Data Rate (DDR) interrupt enable */
17088 /*! CHANDLED - Common Command Code (CCC) (that was handled by I3C module) interrupt enable */
17093 /*! EVENT - Event interrupt enable */
17097 /*! @name SINTCLR - Slave Interrupt Clear Register */
17102 /*! START - START interrupt enable clear */
17107 /*! MATCHED - MATCHED interrupt enable clear */
17112 /*! STOP - STOP interrupt enable clear */
17117 /*! RXPEND - RXPEND interrupt enable clear */
17122 /*! TXSEND - TXSEND interrupt enable clear */
17127 /*! DACHG - DACHG interrupt enable clear */
17132 /*! CCC - CCC interrupt enable clear */
17137 /*! ERRWARN - ERRWARN interrupt enable clear */
17142 /*! DDRMATCHED - DDRMATCHED interrupt enable clear */
17147 /*! CHANDLED - CHANDLED interrupt enable clear */
17152 /*! EVENT - EVENT interrupt enable clear */
17156 /*! @name SINTMASKED - Slave Interrupt Mask Register */
17161 /*! START - START interrupt mask */
17166 /*! MATCHED - MATCHED interrupt mask */
17171 /*! STOP - STOP interrupt mask */
17176 /*! RXPEND - RXPEND interrupt mask */
17181 /*! TXSEND - TXSEND interrupt mask */
17186 /*! DACHG - DACHG interrupt mask */
17191 /*! CCC - CCC interrupt mask */
17196 /*! ERRWARN - ERRWARN interrupt mask */
17201 /*! DDRMATCHED - DDRMATCHED interrupt mask */
17206 /*! CHANDLED - CHANDLED interrupt mask */
17211 /*! EVENT - EVENT interrupt mask */
17215 /*! @name SERRWARN - Slave Errors and Warnings Register */
17220 /*! ORUN - Overrun error */
17225 /*! URUN - Underrun error */
17230 /*! URUNNACK - Underrun and Not Acknowledged (NACKed) error */
17235 /*! TERM - Terminated error */
17240 /*! INVSTART - Invalid start error */
17245 /*! SPAR - SDR parity error */
17250 /*! HPAR - HDR parity error */
17255 /*! HCRC - HDR-DDR CRC error */
17260 /*! S0S1 - S0 or S1 error */
17265 /*! OREAD - Over-read error */
17270 /*! OWRITE - Over-write error */
17274 /*! @name SDMACTRL - Slave DMA Control Register */
17279 /*! DMAFB - DMA Read (From-bus) trigger
17288 /*! DMATB - DMA Write (To-bus) trigger
17297 /*! DMAWIDTH - Width of DMA operations
17306 /*! @name SDATACTRL - Slave Data Control Register */
17311 /*! FLUSHTB - Flush the to-bus buffer/FIFO */
17316 /*! FLUSHFB - Flushes the from-bus buffer/FIFO */
17321 /*! UNLOCK - Unlock */
17326 /*! TXTRIG - Trigger level for TX FIFO emptiness
17336 /*! RXTRIG - Trigger level for RX FIFO fullness
17346 /*! TXCOUNT - Count of bytes in TX */
17351 /*! RXCOUNT - Count of bytes in RX */
17356 /*! TXFULL - TX is full
17364 /*! RXEMPTY - RX is empty
17371 /*! @name SWDATAB - Slave Write Data Byte Register */
17376 /*! DATA - The data byte to send to the master */
17381 /*! END - End */
17386 /*! END_ALSO - End also */
17390 /*! @name SWDATABE - Slave Write Data Byte End */
17395 /*! DATA - The data byte to send to the master */
17399 /*! @name SWDATAH - Slave Write Data Half-word Register */
17404 /*! DATA0 - The 1st byte to send to the master */
17409 /*! DATA1 - The 2nd byte to send to the master */
17414 /*! END - End of message */
17418 /*! @name SWDATAHE - Slave Write Data Half-word End Register */
17423 /*! DATA0 - The 1st byte to send to the master */
17428 /*! DATA1 - The 2nd byte to send to the master */
17432 /*! @name SRDATAB - Slave Read Data Byte Register */
17437 /*! DATA0 - Byte read from the master */
17441 /*! @name SRDATAH - Slave Read Data Half-word Register */
17446 /*! LSB - The 1st byte read from the slave */
17451 /*! MSB - The 2nd byte read from the slave */
17455 /*! @name SCAPABILITIES - Slave Capabilities Register */
17460 /*! IDENA - ID 48b handler
17470 /*! IDREG - ID register */
17475 /*! HDRSUPP - HDR support */
17480 /*! MASTER - Master
17488 /*! SADDR - Static address
17498 /*! CCCHANDLE - Common Command Codes (CCC) handling */
17503 /*! IBI_MR_HJ - In-Band Interrupts, Master Requests, Hot Join events */
17508 /*! TIMECTRL - Time control
17516 /*! EXTFIFO - External FIFO
17526 /*! FIFOTX - FIFO transmit
17536 /*! FIFORX - FIFO receive
17546 /*! INT - Interrupt
17554 /*! DMA - DMA
17561 /*! @name SDYNADDR - Slave Dynamic Address Register */
17566 /*! DAVALID - DAVALID
17574 /*! DADDR - Dynamic address */
17579 /*! MAPIDX - Mapped Dynamic Address */
17584 /*! MAPSA - Map a Static Address */
17589 /*! KEY - Key */
17593 /*! @name SMAXLIMITS - Slave Maximum Limits Register */
17598 /*! MAXRD - Maximum read length */
17603 /*! MAXWR - Maximum write length */
17607 /*! @name SIDPARTNO - Slave ID Part Number Register */
17612 /*! PARTNO - Part number */
17616 /*! @name SIDEXT - Slave ID Extension Register */
17621 /*! DCR - Device Characteristic Register */
17626 /*! BCR - Bus Characteristics Register */
17630 /*! @name SVENDORID - Slave Vendor ID Register */
17635 /*! VID - Vendor ID */
17639 /*! @name STCCLOCK - Slave Time Control Clock Register */
17644 /*! ACCURACY - Clock accuracy */
17649 /*! FREQ - Clock frequency */
17653 /*! @name SMSGMAPADDR - Slave Message-Mapped Address Register */
17658 /*! MAPLAST - Matched address index */
17663 /*! MAPLASTM1 - Previous match index 1 */
17668 /*! MAPLASTM2 - Previous match index 2 */
17672 /*! @name MCTRL - Master Main Control Register */
17677 /*! REQUEST - Request
17691 /*! TYPE - Bus type with START
17701 /*! IBIRESP - In-Band Interrupt (IBI) response
17711 /*! DIR - DIR
17719 /*! ADDR - ADDR */
17724 /*! RDTERM - Read terminate */
17728 /*! @name MSTATUS - Master Status Register */
17733 /*! STATE - State of the master
17747 /*! BETWEEN - Between
17755 /*! NACKED - Not acknowledged */
17760 /*! IBITYPE - In-Band Interrupt (IBI) type
17770 /*! SLVSTART - Slave start */
17775 /*! MCTRLDONE - Master control done */
17780 /*! COMPLETE - COMPLETE */
17785 /*! RXPEND - RXPEND */
17790 /*! TXNOTFULL - TX buffer/FIFO not yet full */
17795 /*! IBIWON - In-Band Interrupt (IBI) won */
17800 /*! ERRWARN - Error or warning */
17805 /*! NOWMASTER - Now master (now this module is a master) */
17810 /*! IBIADDR - IBI address */
17814 /*! @name MIBIRULES - Master In-band Interrupt Registry and Rules Register */
17819 /*! ADDR0 - ADDR0 */
17824 /*! ADDR1 - ADDR1 */
17829 /*! ADDR2 - ADDR2 */
17834 /*! ADDR3 - ADDR3 */
17839 /*! ADDR4 - ADDR4 */
17844 /*! MSB0 - Set Most Significant address Bit to 0 */
17849 /*! NOBYTE - No IBI byte */
17853 /*! @name MINTSET - Master Interrupt Set Register */
17858 /*! SLVSTART - Slave start interrupt enable */
17863 /*! MCTRLDONE - Master control done interrupt enable */
17868 /*! COMPLETE - Completed message interrupt enable */
17873 /*! RXPEND - RX pending interrupt enable */
17878 /*! TXNOTFULL - TX buffer/FIFO is not full interrupt enable */
17883 /*! IBIWON - In-Band Interrupt (IBI) won interrupt enable */
17888 /*! ERRWARN - Error or warning (ERRWARN) interrupt enable */
17893 /*! NOWMASTER - Now master (now this I3C module is a master) interrupt enable */
17897 /*! @name MINTCLR - Master Interrupt Clear Register */
17902 /*! SLVSTART - SLVSTART interrupt enable clear */
17907 /*! MCTRLDONE - MCTRLDONE interrupt enable clear */
17912 /*! COMPLETE - COMPLETE interrupt enable clear */
17917 /*! RXPEND - RXPEND interrupt enable clear */
17922 /*! TXNOTFULL - TXNOTFULL interrupt enable clear */
17927 /*! IBIWON - IBIWON interrupt enable clear */
17932 /*! ERRWARN - ERRWARN interrupt enable clear */
17937 /*! NOWMASTER - NOWMASTER interrupt enable clear */
17941 /*! @name MINTMASKED - Master Interrupt Mask Register */
17946 /*! SLVSTART - SLVSTART interrupt mask */
17951 /*! MCTRLDONE - MCTRLDONE interrupt mask */
17956 /*! COMPLETE - COMPLETE interrupt mask */
17961 /*! RXPEND - RXPEND interrupt mask */
17966 /*! TXNOTFULL - TXNOTFULL interrupt mask */
17971 /*! IBIWON - IBIWON interrupt mask */
17976 /*! ERRWARN - ERRWARN interrupt mask */
17981 /*! NOWMASTER - NOWMASTER interrupt mask */
17985 /*! @name MERRWARN - Master Errors and Warnings Register */
17990 /*! NACK - Not acknowledge (NACK) error */
17995 /*! WRABT - WRABT (Write abort) error */
18000 /*! TERM - Terminate error */
18005 /*! HPAR - High data rate parity */
18010 /*! HCRC - High data rate CRC error */
18015 /*! OREAD - Over-read error */
18020 /*! OWRITE - Over-write error */
18025 /*! MSGERR - Message error */
18030 /*! INVREQ - Invalid request error */
18035 /*! TIMEOUT - TIMEOUT error */
18039 /*! @name MDMACTRL - Master DMA Control Register */
18044 /*! DMAFB - DMA from bus
18053 /*! DMATB - DMA to bus
18062 /*! DMAWIDTH - DMA width
18071 /*! @name MDATACTRL - Master Data Control Register */
18076 /*! FLUSHTB - Flush to-bus buffer/FIFO */
18081 /*! FLUSHFB - Flush from-bus buffer/FIFO */
18086 /*! UNLOCK - Unlock */
18091 /*! TXTRIG - TX trigger level */
18096 /*! RXTRIG - RX trigger level */
18101 /*! TXCOUNT - TX byte count */
18106 /*! RXCOUNT - RX byte count */
18111 /*! TXFULL - TX is full */
18116 /*! RXEMPTY - RX is empty */
18120 /*! @name MWDATAB - Master Write Data Byte Register */
18125 /*! VALUE - Data byte */
18130 /*! END - End of message */
18135 /*! END_ALSO - End of message also */
18139 /*! @name MWDATABE - Master Write Data Byte End Register */
18144 /*! VALUE - Data */
18148 /*! @name MWDATAH - Master Write Data Half-word Register */
18153 /*! DATA0 - Data byte 0 */
18158 /*! DATA1 - Data byte 1 */
18163 /*! END - End of message */
18167 /*! @name MWDATAHE - Master Write Data Byte End Register */
18172 /*! DATA0 - DATA 0 */
18177 /*! DATA1 - DATA 1 */
18181 /*! @name MRDATAB - Master Read Data Byte Register */
18186 /*! VALUE - VALUE */
18190 /*! @name MRDATAH - Master Read Data Half-word Register */
18195 /*! LSB - LSB */
18200 /*! MSB - MSB */
18204 /*! @name MWDATAB1 - Write Byte Data 1 (to bus) */
18209 /*! VALUE - Value */
18213 /*! @name MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
18218 /*! DIR - Direction
18226 /*! ADDR - Address to be written to */
18231 /*! END - End of SDR message */
18236 /*! I2C - I2C
18244 /*! LEN - Length */
18248 /*! @name MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
18253 /*! DATA16B - Data */
18258 /*! END - End of message */
18262 /*! @name MRMSG_SDR - Master Read Message in SDR mode */
18267 /*! DATA - Data */
18271 /*! @name MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
18276 /*! LEN - Length of message */
18281 /*! END - End of message */
18285 /*! @name MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
18290 /*! DATA16B - Data */
18295 /*! END - End of message */
18299 /*! @name MRMSG_DDR - Master Read Message in DDR mode */
18304 /*! DATA - Data */
18309 /*! CLEN - Current length */
18313 /*! @name MDYNADDR - Master Dynamic Address Register */
18318 /*! DAVALID - Dynamic address valid */
18323 /*! DADDR - Dynamic address */
18327 /*! @name SID - Slave Module ID */
18332 /*! ID - ID */
18342 /* I3C - Peripheral instance base addresses */
18378 /* ----------------------------------------------------------------------------
18379 -- LPCMP Peripheral Access Layer
18380 ---------------------------------------------------------------------------- */
18387 /** LPCMP - Register Layout Typedef */
18400 /* ----------------------------------------------------------------------------
18401 -- LPCMP Register Masks
18402 ---------------------------------------------------------------------------- */
18409 /*! @name VERID - Version ID */
18414 /*! FEATURE - Feature Specification Number
18421 /*! MINOR - Minor Version Number */
18426 /*! MAJOR - Major Version Number */
18430 /*! @name PARAM - Parameter */
18435 /*! DAC_RES - DAC Resolution
18436 * 0b0000..4-bit DAC
18437 * 0b0001..6-bit DAC
18438 * 0b0010..8-bit DAC
18439 * 0b0011..10-bit DAC
18440 * 0b0100..12-bit DAC
18441 * 0b0101..14-bit DAC
18442 * 0b0110..16-bit DAC
18447 /*! @name CCR0 - Comparator Control Register 0 */
18452 /*! CMP_EN - Comparator Enable
18460 /*! CMP_STOP_EN - Comparator Sleep Mode Enable
18467 /*! @name CCR1 - Comparator Control Register 1 */
18472 /*! WINDOW_EN - Windowing Enable
18480 /*! SAMPLE_EN - Sampling Enable
18488 /*! DMA_EN - DMA Enable
18496 /*! COUT_INV - Comparator Invert
18504 /*! COUT_SEL - Comparator Output Select
18512 /*! COUT_PEN - Comparator Output Pin Enable
18520 /*! COUTA_OWEN - COUTA_OW Enable
18528 /*! COUTA_OW - COUTA Output Level for Closed Window
18536 /*! WINDOW_INV - WINDOW/SAMPLE Signal Invert
18544 /*! WINDOW_CLS - CMPO Event Window Close
18552 /*! EVT_SEL - CMPO Event Select
18561 /*! FILT_CNT - Filter Sample Count
18575 /*! FILT_PER - Filter Sample Period */
18579 /*! @name CCR2 - Comparator Control Register 2 */
18584 /*! CMP_HPMD - CMP High Power Mode Select
18592 /*! CMP_NPMD - CMP Nano Power Mode Select
18600 /*! HYSTCTR - Comparator Hysteresis Control
18610 /*! PSEL - Plus Input MUX Select
18624 /*! MSEL - Minus Input MUX Select
18637 /*! @name DCR - DAC Control */
18642 /*! DAC_EN - DAC Enable
18650 /*! DAC_HPMD - DAC High Power Mode Select
18658 /*! VRSEL - DAC Reference High Voltage Source Select
18666 /*! DAC_DATA - DAC Output Voltage Select */
18670 /*! @name IER - Interrupt Enable */
18675 /*! CFR_IE - Comparator Flag Rising Interrupt Enable
18683 /*! CFF_IE - Comparator Flag Falling Interrupt Enable
18690 /*! @name CSR - Comparator Status */
18695 /*! CFR - Analog Comparator Flag Rising
18703 /*! CFF - Analog Comparator Flag Falling
18711 /*! COUT - Analog Comparator Output */
18721 /* LPCMP - Peripheral instance base addresses */
18767 /* ----------------------------------------------------------------------------
18768 -- LPI2C Peripheral Access Layer
18769 ---------------------------------------------------------------------------- */
18776 /** LPI2C - Register Layout Typedef */
18824 /* ----------------------------------------------------------------------------
18825 -- LPI2C Register Masks
18826 ---------------------------------------------------------------------------- */
18833 /*! @name VERID - Version ID */
18838 /*! FEATURE - Feature Specification Number
18846 /*! MINOR - Minor Version Number */
18851 /*! MAJOR - Major Version Number */
18855 /*! @name PARAM - Parameter */
18860 /*! MTXFIFO - Controller Transmit FIFO Size */
18865 /*! MRXFIFO - Controller Receive FIFO Size */
18869 /*! @name MCR - Controller Control */
18874 /*! MEN - Controller Enable
18882 /*! RST - Software Reset
18890 /*! DOZEN - Doze mode enable
18898 /*! DBGEN - Debug Enable
18906 /*! RTF - Reset Transmit FIFO
18914 /*! RRF - Reset Receive FIFO
18921 /*! @name MSR - Controller Status */
18926 /*! TDF - Transmit Data Flag
18934 /*! RDF - Receive Data Flag
18942 /*! EPF - End Packet Flag
18950 /*! SDF - STOP Detect Flag
18958 /*! NDF - NACK Detect Flag
18966 /*! ALF - Arbitration Lost Flag
18974 /*! FEF - FIFO Error Flag
18982 /*! PLTF - Pin Low Timeout Flag
18990 /*! DMF - Data Match Flag
18998 /*! STF - START Flag
19006 /*! MBF - Controller Busy Flag
19014 /*! BBF - Bus Busy Flag
19021 /*! @name MIER - Controller Interrupt Enable */
19026 /*! TDIE - Transmit Data Interrupt Enable
19034 /*! RDIE - Receive Data Interrupt Enable
19042 /*! EPIE - End Packet Interrupt Enable
19050 /*! SDIE - STOP Detect Interrupt Enable
19058 /*! NDIE - NACK Detect Interrupt Enable
19066 /*! ALIE - Arbitration Lost Interrupt Enable
19074 /*! FEIE - FIFO Error Interrupt Enable
19082 /*! PLTIE - Pin Low Timeout Interrupt Enable
19090 /*! DMIE - Data Match Interrupt Enable
19098 /*! STIE - START Interrupt Enable
19105 /*! @name MDER - Controller DMA Enable */
19110 /*! TDDE - Transmit Data DMA Enable
19118 /*! RDDE - Receive Data DMA Enable
19125 /*! @name MCFGR0 - Controller Configuration 0 */
19130 /*! HREN - Host request enable
19138 /*! HRPOL - Host request polarity
19146 /*! HRSEL - Host request select
19154 /*! CIRFIFO - Circular FIFO enable
19162 /*! RDMO - Receive data match only
19170 /*! RELAX - Relaxed Mode
19178 /*! ABORT - Abort Transfer
19185 /*! @name MCFGR1 - Controller Configuration 1 */
19190 /*! PRESCALE - Prescaler
19204 /*! AUTOSTOP - Automatic STOP Generation
19212 /*! IGNACK - Ignore NACK
19220 /*! TIMECFG - Timeout Configuration
19228 /*! STOPCFG - STOP Configuration
19237 /*! STARTCFG - START Configuration
19239 …* non-repeated START condition initiated by any other controller on the bus but not the LPI2…
19240 …* 0b1..MSR[STF] asserts on START condition provided I2C bus is idle (that is, any non-repeated ST…
19247 /*! MATCFG - Match Configuration
19261 /*! PINCFG - Pin Configuration
19262 * 0b000..Two-pin open drain mode
19263 * 0b001..Two-pin output only mode (ultra-fast mode)
19264 * 0b010..Two-pin push-pull mode
19265 * 0b011..Four-pin push-pull mode
19266 * 0b100..Two-pin open drain mode with separate LPI2C target
19267 * 0b101..Two-pin output only mode (ultra-fast mode) with separate LPI2C target
19268 * 0b110..Two-pin push-pull mode with separate LPI2C target
19269 * 0b111..Four-pin push-pull mode (inverted outputs)
19275 /*! FRCHS - Force HS mode
19282 /*! @name MCFGR2 - Controller Configuration 2 */
19287 /*! BUSIDLE - Bus Idle Timeout */
19292 /*! FILTSCL - Glitch Filter SCL */
19297 /*! FILTSDA - Glitch Filter SDA */
19301 /*! @name MCFGR3 - Controller Configuration 3 */
19306 /*! PINLOW - Pin low timeout */
19310 /*! @name MDMR - Controller Data Match */
19315 /*! MATCH0 - Match 0 Value */
19320 /*! MATCH1 - Match 1 Value */
19324 /*! @name MCCR0 - Controller Clock Configuration 0 */
19329 /*! CLKLO - Clock Low Period */
19334 /*! CLKHI - Clock High Period */
19339 /*! SETHOLD - Setup Hold Delay */
19344 /*! DATAVD - Data Valid Delay */
19348 /*! @name MCCR1 - Controller Clock Configuration 1 */
19353 /*! CLKLO - Clock Low Period */
19358 /*! CLKHI - Clock High Period */
19363 /*! SETHOLD - Setup Hold Delay */
19368 /*! DATAVD - Data Valid Delay */
19372 /*! @name MFCR - Controller FIFO Control */
19377 /*! TXWATER - Transmit FIFO Watermark */
19382 /*! RXWATER - Receive FIFO Watermark */
19386 /*! @name MFSR - Controller FIFO Status */
19391 /*! TXCOUNT - Transmit FIFO Count */
19396 /*! RXCOUNT - Receive FIFO Count */
19400 /*! @name MTDR - Controller Transmit Data */
19405 /*! DATA - Transmit Data */
19410 /*! CMD - Command Data
19417 * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode
19418 …* 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high-speed mode. This …
19423 /*! @name MRDR - Controller Receive Data */
19428 /*! DATA - Receive Data */
19433 /*! RXEMPTY - Receive Empty
19440 /*! @name MRDROR - Controller Receive Data Read Only */
19445 /*! DATA - Receive Data */
19450 /*! RXEMPTY - RX Empty
19457 /*! @name SCR - Target Control */
19462 /*! SEN - Target Enable
19470 /*! RST - Software reset
19478 /*! FILTEN - Filter enable
19486 /*! FILTDZ - Filter doze enable
19494 /*! RTF - Reset transmit FIFO
19502 /*! RRF - Reset Receive FIFO
19509 /*! @name SSR - Target Status */
19514 /*! TDF - Transmit data flag
19522 /*! RDF - Receive data flag
19530 /*! AVF - Address valid flag
19538 /*! TAF - Transmit ACK flag
19546 /*! RSF - Repeated start flag
19554 /*! SDF - STOP detect flag
19562 /*! BEF - Bit error flag
19570 /*! FEF - FIFO error flag
19578 /*! AM0F - Address match 0 flag
19586 /*! AM1F - Address match 1 flag
19594 /*! GCF - General call flag
19602 /*! SARF - SMBus alert response flag
19610 /*! SBF - Target busy flag
19618 /*! BBF - Bus busy flag
19625 /*! @name SIER - Target interrupt enable */
19630 /*! TDIE - Transmit data interrupt enable
19638 /*! RDIE - Receive data interrupt enable
19646 /*! AVIE - Address valid interrupt enable
19654 /*! TAIE - Transmit ACK interrupt enable
19662 /*! RSIE - Repeated start interrupt enable
19670 /*! SDIE - STOP detect interrupt enable
19678 /*! BEIE - Bit error interrupt enable
19686 /*! FEIE - FIFO error interrupt enable
19694 /*! AM0IE - Address match 0 interrupt enable
19702 /*! AM1IE - Address match 1 interrupt enable
19710 /*! GCIE - General call interrupt enable
19718 /*! SARIE - SMBus alert response interrupt enable
19725 /*! @name SDER - Target DMA Enable */
19730 /*! TDDE - Transmit data DMA enable
19738 /*! RDDE - Receive data DMA enable
19746 /*! AVDE - Address valid DMA enable
19754 /*! RSDE - Repeated start DMA enable
19762 /*! SDDE - Stop detect DMA enable
19769 /*! @name SCFGR0 - Target Configuration 0 */
19774 /*! RDREQ - Read Request
19782 /*! RDACK - Read Acknowledge
19789 /*! @name SCFGR1 - Target Configuration 1 */
19794 /*! ADRSTALL - Address SCL stall
19802 /*! RXSTALL - RX SCL stall
19810 /*! TXDSTALL - Transmit data SCL stall
19818 /*! ACKSTALL - ACK SCL stall
19826 /*! RXNACK - Receive NACK
19834 /*! GCEN - General call enable
19842 /*! SAEN - SMBus alert enable
19850 /*! TXCFG - Transmit flag configuration
19851 …* 0b0..MSR[TDF] becomes 1 only during a target-transmit transfer when the Transmit Data register …
19858 /*! RXCFG - Receive Data Configuration
19868 /*! IGNACK - Ignore NACK
19876 /*! HSMEN - High-speed mode enable
19884 /*! ADDRCFG - Address configuration
19885 * 0b000..Address match 0 (7-bit)
19886 * 0b001..Address match 0 (10-bit)
19887 * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
19888 * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
19889 * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
19890 * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
19891 * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
19892 * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
19898 /*! RXALL - Receive all
19906 /*! RSCFG - Repeated start configuration
19914 /*! SDCFG - Stop Detect Configuration
19921 /*! @name SCFGR2 - Target Configuration 2 */
19926 /*! CLKHOLD - Clock hold time */
19931 /*! DATAVD - Data valid delay */
19936 /*! FILTSCL - Glitch filter SCL */
19941 /*! FILTSDA - Glitch filter SDA */
19945 /*! @name SAMR - Target Address Match */
19950 /*! ADDR0 - Address 0 value */
19955 /*! ADDR1 - Address 1 value */
19959 /*! @name SASR - Target Address Status */
19964 /*! RADDR - Received Address */
19969 /*! ANV - Address not valid
19976 /*! @name STAR - Target Transmit ACK */
19981 /*! TXNACK - Transmit NACK
19988 /*! @name STDR - Target Transmit Data */
19993 /*! DATA - Transmit data */
19997 /*! @name SRDR - Target Receive Data */
20002 /*! DATA - Receive data */
20007 /*! RADDR - Received address */
20012 /*! RXEMPTY - Receive empty
20020 /*! SOF - Start of frame
20027 /*! @name SRDROR - Target Receive Data Read Only */
20032 /*! DATA - Receive data */
20037 /*! RADDR - Received address */
20042 /*! RXEMPTY - Receive empty
20050 /*! SOF - Start of frame
20063 /* LPI2C - Peripheral instance base addresses */
20111 /* ----------------------------------------------------------------------------
20112 -- LPIT Peripheral Access Layer
20113 ---------------------------------------------------------------------------- */
20120 /** LPIT - Register Layout Typedef */
20138 /* ----------------------------------------------------------------------------
20139 -- LPIT Register Masks
20140 ---------------------------------------------------------------------------- */
20147 /*! @name VERID - Version ID */
20152 /*! FEATURE - Feature Number */
20157 /*! MINOR - Minor Version Number */
20162 /*! MAJOR - Major Version Number */
20166 /*! @name PARAM - Parameter */
20171 /*! CHANNEL - Number of Timer Channels */
20176 /*! EXT_TRIG - Number of External Trigger Inputs */
20180 /*! @name MCR - Module Control */
20185 /*! M_CEN - Module Clock Enable
20193 /*! SW_RST - Software Reset
20201 /*! DOZE_EN - DOZE Mode Enable
20209 /*! DBG_EN - Debug Mode Enable
20216 /*! @name MSR - Module Status */
20221 /*! TIF0 - Channel 0 Timer Interrupt Flag
20229 /*! TIF1 - Channel 1 Timer Interrupt Flag
20237 /*! TIF2 - Channel 2 Timer Interrupt Flag
20245 /*! TIF3 - Channel 3 Timer Interrupt Flag
20252 /*! @name MIER - Module Interrupt Enable */
20257 /*! TIE0 - Channel 0 Timer Interrupt Enable
20265 /*! TIE1 - Channel 1 Timer Interrupt Enable
20273 /*! TIE2 - Channel 2 Timer Interrupt Enable
20281 /*! TIE3 - Channel 3 Timer Interrupt Enable
20288 /*! @name SETTEN - Set Timer Enable */
20293 /*! SET_T_EN_0 - Set Timer 0 Enable
20301 /*! SET_T_EN_1 - Set Timer 1 Enable
20309 /*! SET_T_EN_2 - Set Timer 2 Enable
20317 /*! SET_T_EN_3 - Set Timer 3 Enable
20324 /*! @name CLRTEN - Clear Timer Enable */
20329 /*! CLR_T_EN_0 - Clear Timer 0 Enable
20337 /*! CLR_T_EN_1 - Clear Timer 1 Enable
20345 /*! CLR_T_EN_2 - Clear Timer 2 Enable
20353 /*! CLR_T_EN_3 - Clear Timer 3 Enable
20360 /*! @name TVAL - Timer Value */
20365 /*! TMR_VAL - Timer Value
20367 …* 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In compare mode: the val…
20375 /*! @name CVAL - Current Timer Value */
20380 /*! TMR_CUR_VAL - Current Timer Value */
20387 /*! @name TCTRL - Timer Control */
20392 /*! T_EN - Timer Enable
20400 /*! CHAIN - Chain Channel
20408 /*! MODE - Timer Operation Mode
20409 * 0b00..32-bit Periodic Counter
20410 * 0b01..Dual 16-bit Periodic Counter
20411 * 0b10..32-bit Trigger Accumulator
20412 * 0b11..32-bit Trigger Input Capture
20418 /*! TSOT - Timer Start On Trigger
20426 /*! TSOI - Timer Stop On Interrupt
20437 /*! TROT - Timer Reload On Trigger
20445 /*! TRG_SRC - Trigger Source
20453 /*! TRG_SEL - Trigger Select
20454 * 0b0000-0b0011..Timer channel 0 - 3 trigger source is selected
20455 * 0b0100-0b1111..Reserved
20469 /* LPIT - Peripheral instance base addresses */
20505 /* ----------------------------------------------------------------------------
20506 -- LPSPI Peripheral Access Layer
20507 ---------------------------------------------------------------------------- */
20514 /** LPSPI - Register Layout Typedef */
20546 /* ----------------------------------------------------------------------------
20547 -- LPSPI Register Masks
20548 ---------------------------------------------------------------------------- */
20555 /*! @name VERID - Version ID */
20560 /*! FEATURE - Module Identification Number
20561 * 0b0000000000000100..Standard feature set supporting a 32-bit shift register.
20568 /*! MINOR - Minor Version Number */
20573 /*! MAJOR - Major Version Number */
20577 /*! @name PARAM - Parameter */
20582 /*! TXFIFO - Transmit FIFO Size */
20587 /*! RXFIFO - Receive FIFO Size */
20592 /*! PCSNUM - PCS Number */
20596 /*! @name CR - Control */
20601 /*! MEN - Module Enable
20609 /*! RST - Software Reset
20617 /*! DOZEN - Doze Mode Enable
20625 /*! DBGEN - Debug Enable
20633 /*! RTF - Reset Transmit FIFO
20641 /*! RRF - Reset Receive FIFO
20648 /*! @name SR - Status */
20653 /*! TDF - Transmit Data Flag
20661 /*! RDF - Receive Data Flag
20669 /*! WCF - Word Complete Flag
20677 /*! FCF - Frame Complete Flag
20685 /*! TCF - Transfer Complete Flag
20693 /*! TEF - Transmit Error Flag
20701 /*! REF - Receive Error Flag
20709 /*! DMF - Data Match Flag
20717 /*! MBF - Module Busy Flag
20724 /*! @name IER - Interrupt Enable */
20729 /*! TDIE - Transmit Data Interrupt Enable
20737 /*! RDIE - Receive Data Interrupt Enable
20745 /*! WCIE - Word Complete Interrupt Enable
20753 /*! FCIE - Frame Complete Interrupt Enable
20761 /*! TCIE - Transfer Complete Interrupt Enable
20769 /*! TEIE - Transmit Error Interrupt Enable
20777 /*! REIE - Receive Error Interrupt Enable
20785 /*! DMIE - Data Match Interrupt Enable
20792 /*! @name DER - DMA Enable */
20797 /*! TDDE - Transmit Data DMA Enable
20805 /*! RDDE - Receive Data DMA Enable
20813 /*! FCDE - Frame Complete DMA Enable
20820 /*! @name CFGR0 - Configuration 0 */
20825 /*! HREN - Host Request Enable
20833 /*! HRPOL - Host Request Polarity
20841 /*! HRSEL - Host Request Select
20849 /*! HRDIR - Host Request Direction
20857 /*! CIRFIFO - Circular FIFO Enable
20865 /*! RDMO - Receive Data Match Only
20872 /*! @name CFGR1 - Configuration 1 */
20877 /*! MASTER - Master Mode
20885 /*! SAMPLE - Sample Point
20893 /*! AUTOPCS - Automatic PCS
20901 /*! NOSTALL - No Stall
20909 /*! PARTIAL - Partial Enable
20917 /*! PCSPOL - Peripheral Chip Select Polarity */
20922 /*! MATCFG - Match Configuration
20936 /*! PINCFG - Pin Configuration
20938 …* 0b01..SIN is used for both input and output data. Only half-duplex serial transfers are support…
20939 …* 0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are suppor…
20946 /*! OUTCFG - Output Configuration
20948 * 0b1..Output data is 3-stated.
20954 /*! PCSCFG - Peripheral Chip Select Configuration
20956 * 0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
20961 /*! @name DMR0 - Data Match 0 */
20966 /*! MATCH0 - Match 0 Value */
20970 /*! @name DMR1 - Data Match 1 */
20975 /*! MATCH1 - Match 1 Value */
20979 /*! @name CCR - Clock Configuration */
20984 /*! SCKDIV - SCK Divider */
20989 /*! DBT - Delay Between Transfers */
20994 /*! PCSSCK - PCS-to-SCK Delay */
20999 /*! SCKPCS - SCK-to-PCS Delay */
21003 /*! @name CCR1 - Clock Configuration 1 */
21008 /*! SCKSET - SCK Setup */
21013 /*! SCKHLD - SCK Hold */
21018 /*! PCSPCS - PCS to PCS delay */
21023 /*! SCKSCK - SCK Inter-Frame Delay */
21027 /*! @name FCR - FIFO Control */
21032 /*! TXWATER - Transmit FIFO Watermark */
21037 /*! RXWATER - Receive FIFO Watermark */
21041 /*! @name FSR - FIFO Status */
21046 /*! TXCOUNT - Transmit FIFO Count */
21051 /*! RXCOUNT - Receive FIFO Count */
21055 /*! @name TCR - Transmit Command */
21060 /*! FRAMESZ - Frame Size */
21065 /*! WIDTH - Transfer Width
21066 * 0b00..1-bit transfer
21067 * 0b01..2-bit transfer
21068 * 0b10..4-bit transfer
21075 /*! TXMSK - Transmit Data Mask
21083 /*! RXMSK - Receive Data Mask
21091 /*! CONTC - Continuing Command
21099 /*! CONT - Continuous Transfer
21107 /*! BYSW - Byte Swap
21115 /*! LSBF - LSB First
21123 /*! PCS - Peripheral Chip Select
21133 /*! PRESCALE - Prescaler Value
21147 /*! CPHA - Clock Phase
21155 /*! CPOL - Clock Polarity
21162 /*! @name TDR - Transmit Data */
21167 /*! DATA - Transmit Data */
21171 /*! @name RSR - Receive Status */
21176 /*! SOF - Start Of Frame
21184 /*! RXEMPTY - RX FIFO Empty
21191 /*! @name RDR - Receive Data */
21196 /*! DATA - Receive Data */
21200 /*! @name RDROR - Receive Data Read Only */
21205 /*! DATA - Receive Data */
21209 /*! @name TCBR - Transmit Command Burst */
21214 /*! DATA - Command Data */
21218 /*! @name TDBR - Transmit Data Burst */
21223 /*! DATA - Data */
21230 /*! @name RDBR - Receive Data Burst */
21235 /*! DATA - Data */
21248 /* LPSPI - Peripheral instance base addresses */
21296 /* ----------------------------------------------------------------------------
21297 -- LPTMR Peripheral Access Layer
21298 ---------------------------------------------------------------------------- */
21305 /** LPTMR - Register Layout Typedef */
21313 /* ----------------------------------------------------------------------------
21314 -- LPTMR Register Masks
21315 ---------------------------------------------------------------------------- */
21322 /*! @name CSR - Control Status */
21327 /*! TEN - Timer Enable
21335 /*! TMS - Timer Mode Select
21343 /*! TFC - Timer Free-Running Counter
21351 /*! TPP - Timer Pin Polarity
21352 * 0b0..Active-high
21353 * 0b1..Active-low
21359 /*! TPS - Timer Pin Select
21369 /*! TIE - Timer Interrupt Enable
21377 /*! TCF - Timer Compare Flag
21385 /*! TDRE - Timer DMA Request Enable
21392 /*! @name PSR - Prescale and Glitch Filter */
21397 /*! PCS - Prescaler/Glitch Filter Clock Select
21407 /*! PBYP - Prescaler/Glitch Filter Bypass
21415 /*! PRESCALE - Prescale/Glitch Filter Value
21436 /*! @name CMR - Compare */
21441 /*! COMPARE - Compare Value */
21445 /*! @name CNR - Counter */
21450 /*! COUNTER - Counter Value */
21460 /* LPTMR - Peripheral instance base addresses */
21508 /* ----------------------------------------------------------------------------
21509 -- LPUART Peripheral Access Layer
21510 ---------------------------------------------------------------------------- */
21517 /** LPUART - Register Layout Typedef */
21531 __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */
21534 /* ----------------------------------------------------------------------------
21535 -- LPUART Register Masks
21536 ---------------------------------------------------------------------------- */
21543 /*! @name VERID - Version ID */
21548 /*! FEATURE - Feature Identification Number
21556 /*! MINOR - Minor Version Number */
21561 /*! MAJOR - Major Version Number */
21565 /*! @name PARAM - Parameter */
21570 /*! TXFIFO - Transmit FIFO Size */
21575 /*! RXFIFO - Receive FIFO Size */
21579 /*! @name GLOBAL - Global */
21584 /*! RST - Software Reset
21591 /*! @name PINCFG - Pin Configuration */
21596 /*! TRGSEL - Trigger Select
21605 /*! @name BAUD - Baud Rate */
21610 /*! SBR - Baud Rate Modulo Divisor */
21615 /*! SBNS - Stop Bit Number Select
21623 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
21631 /*! LBKDIE - LIN Break Detect Interrupt Enable
21639 /*! RESYNCDIS - Resynchronization Disable
21647 /*! BOTHEDGE - Both Edge Sampling
21655 /*! MATCFG - Match Configuration
21665 /*! RIDMAE - Receiver Idle DMA Enable
21673 /*! RDMAE - Receiver Full DMA Enable
21681 /*! TDMAE - Transmitter DMA Enable
21689 /*! OSR - Oversampling Ratio (OSR)
21727 /*! M10 - 10-Bit Mode Select
21728 * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters
21729 * 0b1..Receiver and transmitter use 10-bit data characters
21735 /*! MAEN2 - Match Address Mode Enable 2
21743 /*! MAEN1 - Match Address Mode Enable 1
21750 /*! @name STAT - Status */
21755 /*! LBKFE - LIN Break Flag Enable
21763 /*! AME - Address Mark Enable
21771 /*! MA2F - Match 2 Flag
21779 /*! MA1F - Match 1 Flag
21787 /*! PF - Parity Error Flag (PF)
21795 /*! FE - Framing Error Flag (FE)
21803 /*! NF - Noise Flag (NF)
21811 /*! OR - Receiver Overrun Flag
21819 /*! IDLE - Idle Line Flag
21827 /*! RDRF - Receive Data Register Full Flag
21835 /*! TC - Transmission Complete Flag
21843 /*! TDRE - Transmit Data Register Empty Flag
21851 /*! RAF - Receiver Active Flag
21859 /*! LBKDE - LIN Break Detection Enable
21867 /*! BRK13 - Break Character Generation Length
21875 /*! RWUID - Receive Wake Up Idle Detect
21883 /*! RXINV - Receive Data Inversion
21891 /*! MSBF - MSB First
21899 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
21907 /*! LBKDIF - LIN Break Detect Interrupt Flag
21914 /*! @name CTRL - Control */
21919 /*! PT - Parity Type
21927 /*! PE - Parity Enable
21935 /*! ILT - Idle Line Type Select
21943 /*! WAKE - Receiver Wakeup Method Select
21944 * 0b0..Configures CTRL[RWU] for idle-line wakeup
21945 * 0b1..Configures CTRL[RWU] with address-mark wakeup
21951 /*! M - 9-Bit Or 8-Bit Mode Select
21952 * 0b0..8-bit data characters
21953 * 0b1..9-bit data characters
21959 /*! RSRC - Receiver Source Select
21961 * 0b1..Single-wire mode
21967 /*! DOZEEN - Enables LPUART in Doze mode. If this field is 1, LPUART remains active when not in Doz…
21975 /*! LOOPS - Loop Mode Select
21977 * 0b1..Loop mode or Single-Wire mode
21983 /*! IDLECFG - Idle Configuration
21997 /*! M7 - 7-Bit Mode Select
21998 * 0b0..8-bit to 10-bit data characters
21999 * 0b1..7-bit data characters
22005 /*! MA2IE - Match 2 (MA2F) Interrupt Enable
22013 /*! MA1IE - Match 1 (MA1F) Interrupt Enable
22021 /*! SBK - Send Break
22029 /*! RWU - Receiver Wakeup Control
22037 /*! RE - Receiver Enable
22045 /*! TE - Transmitter Enable
22053 /*! ILIE - Idle Line Interrupt Enable
22061 /*! RIE - Receiver Interrupt Enable
22069 /*! TCIE - Transmission Complete Interrupt Enable
22077 /*! TIE - Transmit Interrupt Enable
22085 /*! PEIE - Parity Error Interrupt Enable
22093 /*! FEIE - Framing Error Interrupt Enable
22101 /*! NEIE - Noise Error Interrupt Enable
22109 /*! ORIE - Overrun Interrupt Enable
22117 /*! TXINV - Transmit Data Inversion
22125 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
22126 * 0b0..TXD pin is an input in Single-Wire mode
22127 * 0b1..TXD pin is an output in Single-Wire mode
22133 /*! R9T8 - Receive Bit 9 Transmit Bit 8 */
22138 /*! R8T9 - Receive Bit 8 Transmit Bit 9 */
22142 /*! @name DATA - Data */
22147 /*! R0T0 - Read Receive FIFO Bit 0 Or Write Transmit FIFO Bit 0 */
22152 /*! R1T1 - Read Receive FIFO Bit 1 Or Write Transmit FIFO Bit 1 */
22157 /*! R2T2 - Read Receive FIFO Bit 2 Or Write Transmit FIFO Bit 2 */
22162 /*! R3T3 - Read Receive FIFO Bit 3 Or Write Transmit FIFO Bit 3 */
22167 /*! R4T4 - Read Receive FIFO Bit 4 Or Write Transmit FIFO Bit 4 */
22172 /*! R5T5 - Read Receive FIFO Bit 5 Or Write Transmit FIFO Bit 5 */
22177 /*! R6T6 - Read Receive FIFO Bit 6 Or Write Transmit FIFO Bit 6 */
22182 /*! R7T7 - Read Receive FIFO Bit 7 Or Write Transmit FIFO Bit 7 */
22187 /*! R8T8 - Read Receive FIFO Bit 8 Or Write Transmit FIFO Bit 8 */
22192 /*! R9T9 - Read Receive FIFO Bit 9 Or Write Transmit FIFO Bit 9 */
22197 /*! LINBRK - LIN Break
22205 /*! IDLINE - Idle Line
22213 /*! RXEMPT - Receive Buffer Empty
22221 /*! FRETSC - Frame Error Transmit Special Character
22229 /*! PARITYE - Parity Error
22237 /*! NOISY - Noisy Data Received
22244 /*! @name MATCH - Match Address */
22249 /*! MA1 - Match Address 1 */
22254 /*! MA2 - Match Address 2 */
22258 /*! @name MODIR - MODEM IrDA */
22263 /*! TXCTSE - Transmitter CTS Enable
22271 /*! TXRTSE - Transmitter RTS Enable
22279 /*! TXRTSPOL - Transmitter RTS Polarity
22287 /*! RXRTSE - Receiver RTS Enable
22295 /*! TXCTSC - Transmit CTS Configuration
22303 /*! TXCTSSRC - Transmit CTS Source
22311 /*! RTSWATER - Receive RTS Configuration */
22316 /*! TNP - Transmitter Narrow Pulse
22326 /*! IREN - IR Enable
22333 /*! @name FIFO - FIFO */
22338 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
22352 /*! RXFE - Receive FIFO Enable
22360 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
22374 /*! TXFE - Transmit FIFO Enable
22382 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
22390 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
22398 /*! RXIDEN - Receiver Idle Empty Enable
22412 /*! RXFLUSH - Receive FIFO Flush
22420 /*! TXFLUSH - Transmit FIFO Flush
22428 /*! RXUF - Receiver FIFO Underflow Flag
22436 /*! TXOF - Transmitter FIFO Overflow Flag
22444 /*! RXEMPT - Receive FIFO Or Buffer Empty
22452 /*! TXEMPT - Transmit FIFO Or Buffer Empty
22459 /*! @name WATER - Watermark */
22464 /*! TXWATER - Transmit Watermark */
22469 /*! TXCOUNT - Transmit Counter */
22474 /*! RXWATER - Receive Watermark */
22479 /*! RXCOUNT - Receive Counter */
22483 /*! @name DATARO - Data Read-Only */
22488 /*! DATA - Receive Data */
22498 /* LPUART - Peripheral instance base addresses */
22547 /* ----------------------------------------------------------------------------
22548 -- LTC Peripheral Access Layer
22549 ---------------------------------------------------------------------------- */
22556 /** LTC - Register Layout Typedef */
22591 /* ----------------------------------------------------------------------------
22592 -- LTC Register Masks
22593 ---------------------------------------------------------------------------- */
22600 /*! @name MD - Mode Register */
22605 /*! ENC - Encrypt/Decrypt.
22613 /*! ICV_TEST - ICV Checking / Test AES fault detection. */
22618 /*! AS - Algorithm State
22628 /*! AAI - Additional Algorithm information */
22633 /*! ALG - Algorithm
22639 /*! @name KS - Key Size Register */
22644 /*! KS - Key Size */
22648 /*! @name DS - Data Size Register */
22653 /*! DS - Data Size */
22657 /*! @name ICVS - ICV Size Register */
22662 /*! ICVS - ICV Size, in Bytes */
22666 /*! @name COM - Command Register */
22671 /*! ALL - Reset All Internal Logic
22679 /*! AES - Reset AESA
22686 /*! @name CTL - Control Register */
22691 /*! IM - Interrupt Mask
22699 /*! IFE - Input FIFO DMA Enable
22707 /*! IFR - Input FIFO DMA Request Size
22715 /*! OFE - Output FIFO DMA Enable
22723 /*! OFR - Output FIFO DMA Request Size
22731 /*! IFS - Input FIFO Byte Swap
22739 /*! OFS - Output FIFO Byte Swap
22747 /*! KIS - Key Register Input Byte Swap
22755 /*! KOS - Key Register Output Byte Swap
22763 /*! CIS - Context Register Input Byte Swap
22771 /*! COS - Context Register Output Byte Swap
22779 /*! KAL - Key Register Access Lock
22786 /*! @name CW - Clear Written Register */
22791 /*! CM - Clear the Mode Register */
22796 /*! CDS - Clear the Data Size Register */
22801 /*! CICV - Clear the ICV Size Register */
22806 /*! CCR - Clear the Context Register */
22811 /*! CKR - Clear the Key Register */
22816 /*! COF - Clear Output FIFO */
22821 /*! CIF - Clear Input FIFO */
22825 /*! @name STA - Status Register */
22830 /*! AB - AESA Busy
22838 /*! DI - Done Interrupt */
22843 /*! EI - Error Interrupt
22850 /*! @name ESTA - Error Status Register */
22855 /*! ERRID1 - Error ID 1
22863 …* AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based…
22870 /*! CL1 - algorithms
22877 /*! @name AADSZ - AAD Size Register */
22882 /*! AADSZ - AAD size in Bytes, mod 16 */
22887 /*! AL - AAD Last */
22891 /*! @name CTX - Context Register */
22896 /*! CTX - CTX */
22903 /*! @name KEY - Key Registers */
22908 /*! KEY - KEY */
22915 /*! @name VID1 - Version ID Register */
22920 /*! MIN_REV - Minor revision number. */
22925 /*! MAJ_REV - Major revision number. */
22933 /*! @name VID2 - Version ID 2 Register */
22938 /*! ECO_REV - ECO revision number. */
22943 /*! ARCH_ERA - Architectural ERA. */
22947 /*! @name CHAVID - CHA Version ID Register */
22952 /*! AESREV - AES Revision Number */
22957 /*! AESVID - AES Version ID */
22961 /*! @name FIFOSTA - FIFO Status Register */
22966 /*! IFL - Input FIFO Level */
22971 /*! IFF - Input FIFO Full */
22976 /*! OFL - Output FIFO Level */
22981 /*! OFF - Output FIFO Full */
22985 /*! @name IFIFO - Input Data FIFO */
22990 /*! IFIFO - IFIFO */
22994 /*! @name OFIFO - Output Data FIFO */
22999 /*! OFIFO - Output FIFO */
23009 /* LTC - Peripheral instance base addresses */
23043 /* ----------------------------------------------------------------------------
23044 -- MCM Peripheral Access Layer
23045 ---------------------------------------------------------------------------- */
23052 /** MCM - Register Layout Typedef */
23077 /* ----------------------------------------------------------------------------
23078 -- MCM Register Masks
23079 ---------------------------------------------------------------------------- */
23086 /*! @name CPCR - Core Platform Control */
23091 /*! CBRR - Crossbar Round-robin Arbitration Enable
23092 * 0b0..Fixed-priority arbitration
23093 * 0b1..Round-robin arbitration
23099 /*! PFLEXSTALL - Flash Stall Enable
23106 /*! @name ISCR - Interrupt Status and Control */
23111 /*! CWBER - Cache Write Buffer Error Status
23119 /*! CPES - Cache Parity Error Status
23127 /*! FIOC - FPU Invalid Operation Interrupt Status
23135 /*! FDZC - FPU Divide-by-zero Interrupt Status
23143 /*! FOFC - FPU Overflow Interrupt Status
23151 /*! FUFC - FPU Underflow Interrupt status
23159 /*! FIXC - FPU Inexact Interrupt Status
23167 /*! FIDC - FPU Input Denormal Interrupt Status
23175 /*! CWBEE - Cache Write Buffer Error Enable
23183 /*! CPEE - Cache Parity Error Enable
23191 /*! FIOCE - FPU Invalid Operation Interrupt Enable
23199 /*! FDZCE - FPU Divide-by-zero Interrupt Enable
23207 /*! FOFCE - FPU Overflow Interrupt Enable
23215 /*! FUFCE - FPU Underflow Interrupt Enable
23223 /*! FIXCE - FPU Inexact Interrupt Enable
23231 /*! FIDCE - FPU Input Denormal Interrupt Enable
23238 /*! @name FADR - Write Buffer Fault Address */
23243 /*! ADDRESS - Fault address */
23247 /*! @name FATR - Store Buffer Fault Attributes */
23252 /*! BEDA - Bus Error Data Access Type
23260 /*! BEMD - Bus Error Privilege level
23268 /*! BESZ - Bus Error Size
23269 * 0b00..8-bit access
23270 * 0b01..16-bit access
23271 * 0b10..32-bit access
23278 /*! BEWT - Bus Error Write
23286 /*! BEMN - Bus Error Master Number */
23291 /*! BEOVR - Bus Error Overrun
23298 /*! @name FDR - Store Buffer Fault Data */
23303 /*! DATA - Fault Data */
23307 /*! @name CPCR2 - Core Platform Control 2 */
23312 /*! CCBC - Clear Code Bus Cache
23320 /*! DCCWB - Disable Code Cache Write Buffer
23328 /*! FCCNA - Force Code Cache to No Allocation
23336 /*! DCBC - Disable Code Bus cache
23344 /*! CBCS - Code Bus Cache Size
23357 /*! PCCMCTRL - Bypass Fixed Code Cache Map
23365 /*! LCCPWB - Limit Code Cache Peripheral Write Buffering
23372 /*! @name LMDR2 - Local Memory Descriptor 2 */
23377 /*! PCPME - PC Parity Enable
23385 /*! PCPFE - PC Parity Fault Report Enable
23393 /*! MT - Memory Type
23403 /*! RO - Read-Only
23411 /*! DPW - LMEM Data Path Width
23412 * 0b000-0b001..Reserved
23413 * 0b010..LMEMn 32-bit wide
23414 * 0b011..LMEMn 64-bit wide
23415 * 0b100-0b111..Reserved
23421 /*! WY - Level 1 Cache Ways
23423 * 0b0010..2-Way Set Associative
23424 * 0b0100..4-Way Set Associative
23425 * 0b1000..8-Way Set Associative
23431 /*! LMSZ - LMEM Size
23453 /*! LMSZH - LMEM Size Hole
23454 * 0b0..LMEMn is a power-of-2 capacity.
23461 /*! V - Valid
23468 /*! @name LMPECR - LMEM Parity Control */
23473 /*! ECPR - Enable Cache Parity Reporting
23480 /*! @name LMPEIR - LMEM Parity Interrupt */
23485 /*! PE - Parity Error */
23490 /*! PEELOC - Error Location */
23495 /*! V - Valid bit */
23499 /*! @name LMFAR - LMEM Fault Address */
23504 /*! EFADD - Fault Address */
23508 /*! @name LMFATR - LMEM Fault Attribute */
23513 /*! PEFPRT - Parity Fault Protection Signal */
23518 /*! PEFSIZE - PEFSIZE
23519 * 0b000..8-bit access
23520 * 0b001..16-bit access
23521 * 0b010..32-bit access
23522 * 0b011..64-bit access
23532 /*! PEFW - Parity Fault Write
23540 /*! BKD - Backdoor Access
23548 /*! PEFSYN - Parity Fault Syndrome */
23553 /*! OVR - Overrun
23560 /*! @name LMFDHR - LMEM Fault Data High */
23565 /*! PEFDH - PEFDH */
23569 /*! @name LMFDLR - LMEM Fault Data Low */
23574 /*! PEFDL - PEFDL */
23584 /* MCM - Peripheral instance base addresses */
23601 /* ----------------------------------------------------------------------------
23602 -- MRCC Peripheral Access Layer
23603 ---------------------------------------------------------------------------- */
23610 /** MRCC - Register Layout Typedef */
23655 …__IO uint32_t MRCC_PFLEXNVM; /**< FMC-NPX Reset and Clock Control, offset: 0x4…
23663 /* ----------------------------------------------------------------------------
23664 -- MRCC Register Masks
23665 ---------------------------------------------------------------------------- */
23672 /*! @name MRCC_EWM0 - EWM0 Reset and Clock Control */
23677 /*! CC - Clock Configuration
23687 /*! RSTB - Reset Negation
23695 /*! PR - Peripheral Present
23702 /*! @name MRCC_SYSPM0 - SYSPM0 Reset and Clock Control */
23707 /*! CC - Clock Configuration
23716 /*! @name MRCC_WDOG0 - WDOG0 Reset and Clock Control */
23721 /*! CC - Clock Configuration
23730 /*! @name MRCC_WDOG1 - WDOG1 Reset and Clock Control */
23735 /*! CC - Clock Configuration
23744 /*! @name MRCC_SFA0 - SFA0 Reset and Clock Control */
23749 /*! CC - Clock Configuration
23759 /*! RSTB - Reset Negation
23767 /*! PR - Peripheral Present
23774 /*! @name MRCC_CRC0 - CRC0 Reset and Clock Control */
23779 /*! CC - Clock Configuration
23789 /*! RSTB - Reset Negation
23797 /*! PR - Peripheral Present
23804 /*! @name MRCC_SECSUBSYS - ELE Reset and Clock Control */
23809 /*! CC - Clock Configuration
23819 /*! RSTB - Reset Negation
23827 /*! PR - Peripheral Present
23834 /*! @name MRCC_LPIT0 - LPIT0 Reset and Clock Control */
23839 /*! CC - Clock Configuration
23849 /*! MUX - Functional Clock Mux Select
23850 * 0b100..SOSC-CLK
23851 * 0b011..FRO-192M
23852 * 0b010..FRO-6M
23859 /*! DIV - Functional Clock Divider */
23864 /*! RSTB - Reset Negation
23872 /*! PR - Peripheral Present
23879 /*! @name MRCC_TSTMR0 - TSTMR0 Reset and Clock Control */
23884 /*! CC - Clock Configuration
23893 /*! @name MRCC_TPM0 - TPM0 Reset and Clock Control */
23898 /*! CC - Clock Configuration
23908 /*! MUX - Functional Clock Mux Select
23909 * 0b101..32K-CLK
23910 * 0b100..SOSC-CLK
23911 * 0b011..FRO-192M
23912 * 0b010..FRO-6M
23919 /*! DIV - Functional Clock Divider */
23924 /*! RSTB - Reset Negation
23932 /*! PR - Peripheral Present
23939 /*! @name MRCC_TPM1 - TPM1 Reset and Clock Control */
23944 /*! CC - Clock Configuration
23954 /*! MUX - Functional Clock Mux Select
23955 * 0b101..32K-CLK
23956 * 0b100..SOSC-CLK
23957 * 0b011..FRO-192M
23958 * 0b010..FRO-6M
23965 /*! DIV - Functional Clock Divider */
23970 /*! RSTB - Reset Negation
23978 /*! PR - Peripheral Present
23985 /*! @name MRCC_LPI2C0 - LPI2C0 Reset and Clock Control */
23990 /*! CC - Clock Configuration
24000 /*! MUX - Functional Clock Mux Select
24001 * 0b100..SOSC-CLK
24002 * 0b011..FRO-192M
24003 * 0b010..FRO-6M
24010 /*! DIV - Functional Clock Divider */
24015 /*! RSTB - Reset Negation
24023 /*! PR - Peripheral Present
24030 /*! @name MRCC_LPI2C1 - LPI2C1 Reset and Clock Control */
24035 /*! CC - Clock Configuration
24045 /*! MUX - Functional Clock Mux Select
24046 * 0b100..SOSC-CLK
24047 * 0b011..FRO-192M
24048 * 0b010..FRO-6M
24055 /*! DIV - Functional Clock Divider */
24060 /*! RSTB - Reset Negation
24068 /*! PR - Peripheral Present
24075 /*! @name MRCC_I3C0 - I3C0 Reset and Clock Control */
24080 /*! CC - Clock Configuration
24090 /*! MUX - Functional Clock Mux Select
24091 * 0b100..SOSC-CLK
24092 * 0b011..FRO-192M
24093 * 0b010..FRO-6M
24100 /*! DIV - Functional Clock Divider */
24105 /*! RSTB - Reset Negation
24113 /*! PR - Peripheral Present
24120 /*! @name MRCC_LPSPI0 - LPSPI0 Reset and Clock Control */
24125 /*! CC - Clock Configuration
24135 /*! MUX - Functional Clock Mux Select
24136 * 0b100..SOSC-CLK
24137 * 0b011..FRO-192M
24138 * 0b010..FRO-6M
24145 /*! DIV - Functional Clock Divider */
24150 /*! RSTB - Reset Negation
24158 /*! PR - Peripheral Present
24165 /*! @name MRCC_LPSPI1 - LPSPI1 Reset and Clock Control */
24170 /*! CC - Clock Configuration
24180 /*! MUX - Functional Clock Mux Select
24181 * 0b100..SOSC-CLK
24182 * 0b011..FRO-192M
24183 * 0b010..FRO-6M
24190 /*! DIV - Functional Clock Divider */
24195 /*! RSTB - Reset Negation
24203 /*! PR - Peripheral Present
24210 /*! @name MRCC_LPUART0 - LPUART0 Reset and Clock Control */
24215 /*! CC - Clock Configuration
24225 /*! MUX - Functional Clock Mux Select
24226 * 0b101..32K-CLK
24227 * 0b100..SOSC-CLK
24228 * 0b011..FRO-192M
24229 * 0b010..FRO-6M
24236 /*! DIV - Functional Clock Divider */
24241 /*! RSTB - Reset Negation
24249 /*! PR - Peripheral Present
24256 /*! @name MRCC_LPUART1 - LPUART1 Reset and Clock Control */
24261 /*! CC - Clock Configuration
24271 /*! MUX - Functional Clock Mux Select
24272 * 0b101..32K-CLK
24273 * 0b100..SOSC-CLK
24274 * 0b011..FRO-192M
24275 * 0b010..FRO-6M
24282 /*! DIV - Functional Clock Divider */
24287 /*! RSTB - Reset Negation
24295 /*! PR - Peripheral Present
24302 /*! @name MRCC_FLEXIO0 - FLEXIO0 Reset and Clock Control */
24307 /*! CC - Clock Configuration
24317 /*! MUX - Functional Clock Mux Select
24318 * 0b100..SOSC-CLK
24319 * 0b011..FRO-192M
24320 * 0b010..FRO-6M
24327 /*! DIV - Functional Clock Divider */
24332 /*! RSTB - Reset Negation
24340 /*! PR - Peripheral Present
24347 /*! @name MRCC_CAN0 - CAN0 Reset and Clock Control */
24352 /*! CC - Clock Configuration
24362 /*! MUX - Functional Clock Mux Select
24363 * 0b100..SOSC-CLK
24364 * 0b011..FRO-192M
24371 /*! DIV - Functional Clock Divider */
24376 /*! RSTB - Reset Negation
24384 /*! PR - Peripheral Present
24391 /*! @name MRCC_SEMA0 - SEMA42 Reset and Clock Control */
24396 /*! CC - Clock Configuration
24406 /*! RSTB - Reset Negation
24414 /*! PR - Peripheral Present
24421 /*! @name MRCC_DATA_STREAM_2P4 - DSB Reset and Clock Control */
24426 /*! CC - Clock Configuration
24436 /*! RSTB - Reset Negation
24444 /*! PR - Peripheral Present
24451 /*! @name MRCC_PORTA - PORTA Reset and Clock Control */
24456 /*! CC - Clock Configuration
24466 /*! RSTB - Reset Negation
24474 /*! PR - Peripheral Present
24481 /*! @name MRCC_PORTB - PORTB Reset and Clock Control */
24486 /*! CC - Clock Configuration
24496 /*! RSTB - Reset Negation
24504 /*! PR - Peripheral Present
24511 /*! @name MRCC_PORTC - PORTC Reset and Clock Control */
24516 /*! CC - Clock Configuration
24526 /*! RSTB - Reset Negation
24534 /*! PR - Peripheral Present
24541 /*! @name MRCC_LPADC0 - ADC0 Reset and Clock Control */
24546 /*! CC - Clock Configuration
24556 /*! MUX - Functional Clock Mux Select
24557 * 0b100..SOSC-CLK
24558 * 0b011..FRO-192M
24559 * 0b010..FRO-6M
24566 /*! DIV - Functional Clock Divider */
24571 /*! RSTB - Reset Negation
24579 /*! PR - Peripheral Present
24586 /*! @name MRCC_LPCMP0 - LPCMP0 Reset and Clock Control */
24591 /*! CC - Clock Configuration
24601 /*! RSTB - Reset Negation
24609 /*! PR - Peripheral Present
24616 /*! @name MRCC_LPCMP1 - LPCMP1 Reset and Clock Control */
24621 /*! CC - Clock Configuration
24631 /*! RSTB - Reset Negation
24639 /*! PR - Peripheral Present
24646 /*! @name MRCC_VREF0 - VREF0 Reset and Clock Control */
24651 /*! CC - Clock Configuration
24661 /*! RSTB - Reset Negation
24669 /*! PR - Peripheral Present
24676 /*! @name MRCC_GPIOA - GPIOA Reset and Clock Control */
24681 /*! CC - Clock Configuration
24691 /*! RSTB - Reset Negation
24699 /*! PR - Peripheral Present
24706 /*! @name MRCC_GPIOB - GPIOB Reset and Clock Control */
24711 /*! CC - Clock Configuration
24721 /*! RSTB - Reset Negation
24729 /*! PR - Peripheral Present
24736 /*! @name MRCC_GPIOC - GPIOC Reset and Clock Control */
24741 /*! CC - Clock Configuration
24751 /*! RSTB - Reset Negation
24759 /*! PR - Peripheral Present
24766 /*! @name MRCC_DMA0 - DMA0 Reset and Clock Control */
24771 /*! CC - Clock Configuration
24781 /*! RSTB - Reset Negation
24789 /*! PR - Peripheral Present
24796 /*! @name MRCC_PFLEXNVM - FMC-NPX Reset and Clock Control */
24801 /*! CC - Clock Configuration
24810 /*! @name MRCC_SRAM0 - CTCM Reset and Clock Control */
24815 /*! CC - Clock Configuration
24824 /*! @name MRCC_SRAM1 - STCM0 Reset and Clock Control */
24829 /*! CC - Clock Configuration
24838 /*! @name MRCC_SRAM2 - STCM1 Reset and Clock Control */
24843 /*! CC - Clock Configuration
24852 /*! @name MRCC_SRAM3 - STCM2 Reset and Clock Control */
24857 /*! CC - Clock Configuration
24872 /* MRCC - Peripheral instance base addresses */
24923 /* ----------------------------------------------------------------------------
24924 -- MSCM Peripheral Access Layer
24925 ---------------------------------------------------------------------------- */
24932 /** MSCM - Register Layout Typedef */
24951 …__I uint32_t OCMDR0; /**< On-Chip Memory Descriptor Register, offset: …
24952 …__I uint32_t OCMDR1; /**< On-Chip Memory Descriptor Register, offset: …
24953 …__I uint32_t OCMDR2; /**< On-Chip Memory Descriptor Register, offset: …
24954 …__I uint32_t OCMDR3; /**< On-Chip Memory Descriptor Register, offset: …
24955 …__I uint32_t OCMDR4; /**< On-Chip Memory Descriptor Register, offset: …
24956 …__I uint32_t OCMDR5; /**< On-Chip Memory Descriptor Register, offset: …
24964 /* ----------------------------------------------------------------------------
24965 -- MSCM Register Masks
24966 ---------------------------------------------------------------------------- */
24973 /*! @name CPXTYPE - Processor X Type Register */
24978 /*! RYPZ - Processor x Revision */
24983 /*! PERSONALITY - Processor x Personality */
24987 /*! @name CPXNUM - Processor X Number Register */
24992 /*! CPN - Processor x Number */
24996 /*! @name CPXMASTER - Processor X Master Register */
25001 /*! PPMN - Processor x Physical Master Number */
25005 /*! @name CPXCOUNT - Processor X Count Register */
25010 /*! PCNT - Processor Count */
25014 /*! @name CPXCFG0 - Processor X Configuration Register 0 */
25019 /*! DCWY - Level 1 Data Cache Ways */
25024 /*! DCSZ - Level 1 Data Cache Size */
25029 /*! ICWY - Level 1 Instruction Cache Ways */
25034 /*! ICSZ - Level 1 Instruction Cache Size */
25038 /*! @name CPXCFG1 - Processor X Configuration Register 1 */
25043 /*! L2WY - Level 2 Instruction Cache Ways */
25048 /*! L2SZ - Level 2 Instruction Cache Size */
25052 /*! @name CPXCFG2 - Processor X Configuration Register 2 */
25057 /*! TMUSZ - Tightly-coupled Memory Upper Size */
25062 /*! TMLSZ - Tightly-coupled Memory Lower Size */
25066 /*! @name CPXCFG3 - Processor X Configuration Register 3 */
25071 /*! FPU - Floating Point Unit
25079 /*! SIMD - SIMD/NEON instruction support
25087 /*! JAZ - Jazelle support
25095 /*! MMU - Memory Management Unit
25103 /*! TZ - Trust Zone
25111 /*! CMP - Core Memory Protection unit
25119 /*! BB - Bit Banding
25127 /*! SBP - System Bus Ports */
25131 /*! @name CP0TYPE - Processor 0 Type Register */
25136 /*! RYPZ - Processor 0 Revision */
25141 /*! PERSONALITY - Processor 0 Personality */
25145 /*! @name CP0NUM - Processor 0 Number Register */
25150 /*! CPN - Processor 0 Number */
25154 /*! @name CP0MASTER - Processor 0 Master Register */
25159 /*! PPMN - Processor 0 Physical Master Number */
25163 /*! @name CP0COUNT - Processor 0 Count Register */
25168 /*! PCNT - Processor Count */
25172 /*! @name CP0CFG0 - Processor 0 Configuration Register 0 */
25177 /*! DCWY - Level 1 Data Cache Ways */
25182 /*! DCSZ - Level 1 Data Cache Size */
25187 /*! ICWY - Level 1 Instruction Cache Ways */
25192 /*! ICSZ - Level 1 Instruction Cache Size */
25196 /*! @name CP0CFG1 - Processor 0 Configuration Register 1 */
25201 /*! L2WY - Level 2 Instruction Cache Ways */
25206 /*! L2SZ - Level 2 Instruction Cache Size */
25210 /*! @name CP0CFG2 - Processor 0 Configuration Register 2 */
25215 /*! TMUSZ - Tightly-coupled Memory Upper Size */
25220 /*! TMLSZ - Tightly-coupled Memory Lower Size */
25224 /*! @name CP0CFG3 - Processor 0 Configuration Register 3 */
25229 /*! FPU - Floating Point Unit
25237 /*! SIMD - SIMD/NEON instruction support
25245 /*! JAZ - Jazelle support
25253 /*! MMU - Memory Management Unit
25261 /*! TZ - Trust Zone
25269 /*! CMP - Core Memory Protection unit
25277 /*! BB - Bit Banding
25285 /*! SBP - System Bus Ports */
25289 /*! @name OCMDR0 - On-Chip Memory Descriptor Register */
25294 /*! OCMPU - OCMPU */
25299 /*! OCMT - OCMT
25313 /*! OCMW - OCMW
25314 * 0b000-0b001..Reserved
25315 * 0b010..OCMEMn 32-bits wide
25316 * 0b011..OCMEMn 64-bits wide
25317 * 0b100..OCMEMn 128-bits wide
25318 * 0b101..OCMEMn 256-bits wide
25319 * 0b110-0b111..Reserved
25325 /*! OCMSZ - OCMSZ
25347 /*! OCMSZH - OCMSZH
25348 * 0b0..OCMEMn is a power-of-2 capacity.
25349 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25355 /*! OCMECC - OCMECC
25363 /*! V - V
25370 /*! @name OCMDR1 - On-Chip Memory Descriptor Register */
25375 /*! OCMPU - OCMPU */
25380 /*! OCMT - OCMT
25394 /*! OCMW - OCMW
25395 * 0b000-0b001..Reserved
25396 * 0b010..OCMEMn 32-bits wide
25397 * 0b011..OCMEMn 64-bits wide
25398 * 0b100..OCMEMn 128-bits wide
25399 * 0b101..OCMEMn 256-bits wide
25400 * 0b110-0b111..Reserved
25406 /*! OCMSZ - OCMSZ
25428 /*! OCMSZH - OCMSZH
25429 * 0b0..OCMEMn is a power-of-2 capacity.
25430 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25436 /*! OCMECC - OCMECC
25444 /*! V - V
25451 /*! @name OCMDR2 - On-Chip Memory Descriptor Register */
25456 /*! OCMPU - OCMPU */
25461 /*! OCMT - OCMT
25475 /*! OCMW - OCMW
25476 * 0b000-0b001..Reserved
25477 * 0b010..OCMEMn 32-bits wide
25478 * 0b011..OCMEMn 64-bits wide
25479 * 0b100..OCMEMn 128-bits wide
25480 * 0b101..OCMEMn 256-bits wide
25481 * 0b110-0b111..Reserved
25487 /*! OCMSZ - OCMSZ
25509 /*! OCMSZH - OCMSZH
25510 * 0b0..OCMEMn is a power-of-2 capacity.
25511 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25517 /*! OCMECC - OCMECC
25525 /*! V - V
25532 /*! @name OCMDR3 - On-Chip Memory Descriptor Register */
25537 /*! OCMPU - OCMPU */
25542 /*! OCMT - OCMT
25556 /*! OCMW - OCMW
25557 * 0b000-0b001..Reserved
25558 * 0b010..OCMEMn 32-bits wide
25559 * 0b011..OCMEMn 64-bits wide
25560 * 0b100..OCMEMn 128-bits wide
25561 * 0b101..OCMEMn 256-bits wide
25562 * 0b110-0b111..Reserved
25568 /*! OCMSZ - OCMSZ
25590 /*! OCMSZH - OCMSZH
25591 * 0b0..OCMEMn is a power-of-2 capacity.
25592 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25598 /*! OCMECC - OCMECC
25606 /*! V - V
25613 /*! @name OCMDR4 - On-Chip Memory Descriptor Register */
25618 /*! OCMPU - OCMPU */
25623 /*! OCMT - OCMT
25637 /*! OCMW - OCMW
25638 * 0b000-0b001..Reserved
25639 * 0b010..OCMEMn 32-bits wide
25640 * 0b011..OCMEMn 64-bits wide
25641 * 0b100..OCMEMn 128-bits wide
25642 * 0b101..OCMEMn 256-bits wide
25643 * 0b110-0b111..Reserved
25649 /*! OCMSZ - OCMSZ
25671 /*! OCMSZH - OCMSZH
25672 * 0b0..OCMEMn is a power-of-2 capacity.
25673 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25679 /*! OCMECC - OCMECC
25687 /*! V - V
25694 /*! @name OCMDR5 - On-Chip Memory Descriptor Register */
25699 /*! OCMPU - OCMPU */
25704 /*! OCMT - OCMT
25718 /*! OCMW - OCMW
25719 * 0b000-0b001..Reserved
25720 * 0b010..OCMEMn 32-bits wide
25721 * 0b011..OCMEMn 64-bits wide
25722 * 0b100..OCMEMn 128-bits wide
25723 * 0b101..OCMEMn 256-bits wide
25724 * 0b110-0b111..Reserved
25730 /*! OCMSZ - OCMSZ
25752 /*! OCMSZH - OCMSZH
25753 * 0b0..OCMEMn is a power-of-2 capacity.
25754 * 0b1..OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
25760 /*! OCMECC - OCMECC
25768 /*! V - V
25775 /*! @name SECURE_IRQ - Secure Interrupt Request */
25780 /*! SEC_IRQ_ARG - Secure Interrupt Argument */
25784 /*! @name UID - Unique ID 0..Unique ID 3 */
25789 /*! UID0 - Unique ID 0 */
25794 /*! UID1 - Unique ID 1 */
25799 /*! UID2 - Unique ID 2 */
25804 /*! UID3 - Unique ID 3 */
25811 /*! @name SID - System ID */
25816 /*! QI - Qual Info
25826 /*! SIREV - Silicon Revision
25836 /*! PINID - Pin Identification
25845 /*! CMP - CMP Presence
25853 /*! FLXIO - FlexIO Presence
25861 /*! VREF - VREF Presence
25869 /*! I3C - I3C Presence
25877 /*! CAN - CAN Presence
25885 /*! SEC - Secure Enclave Presence
25893 /*! RAMSZ - RAM Size
25901 /*! FLSZ - Flash Size
25909 /*! BLEF - Bluetooth LE Feature
25917 /*! RADIOF - Radio Feature
25926 /*! FAMID - Family ID */
25936 /* MSCM - Peripheral instance base addresses */
25970 /* ----------------------------------------------------------------------------
25971 -- PORT Peripheral Access Layer
25972 ---------------------------------------------------------------------------- */
25979 /** PORT - Register Layout Typedef */
25995 /* ----------------------------------------------------------------------------
25996 -- PORT Register Masks
25997 ---------------------------------------------------------------------------- */
26004 /*! @name VERID - Version ID */
26009 /*! FEATURE - Feature Specification Number
26016 /*! MINOR - Minor Version Number */
26021 /*! MAJOR - Major Version Number */
26025 /*! @name GPCLR - Global Pin Control Low */
26030 /*! GPWD - Global Pin Write Data */
26035 /*! GPWE0 - Global Pin Write Enable
26043 /*! GPWE1 - Global Pin Write Enable
26051 /*! GPWE2 - Global Pin Write Enable
26059 /*! GPWE3 - Global Pin Write Enable
26067 /*! GPWE4 - Global Pin Write Enable
26075 /*! GPWE5 - Global Pin Write Enable
26083 /*! GPWE6 - Global Pin Write Enable
26091 /*! GPWE7 - Global Pin Write Enable
26099 /*! GPWE8 - Global Pin Write Enable
26107 /*! GPWE9 - Global Pin Write Enable
26115 /*! GPWE10 - Global Pin Write Enable
26123 /*! GPWE11 - Global Pin Write Enable
26131 /*! GPWE12 - Global Pin Write Enable
26139 /*! GPWE13 - Global Pin Write Enable
26147 /*! GPWE14 - Global Pin Write Enable
26155 /*! GPWE15 - Global Pin Write Enable
26162 /*! @name GPCHR - Global Pin Control High */
26167 /*! GPWD - Global Pin Write Data */
26172 /*! GPWE16 - Global Pin Write Enable
26180 /*! GPWE17 - Global Pin Write Enable
26188 /*! GPWE18 - Global Pin Write Enable
26196 /*! GPWE19 - Global Pin Write Enable
26204 /*! GPWE20 - Global Pin Write Enable
26212 /*! GPWE21 - Global Pin Write Enable
26220 /*! GPWE22 - Global Pin Write Enable
26228 /*! GPWE23 - Global Pin Write Enable
26236 /*! GPWE24 - Global Pin Write Enable
26244 /*! GPWE25 - Global Pin Write Enable
26252 /*! GPWE26 - Global Pin Write Enable
26260 /*! GPWE27 - Global Pin Write Enable
26268 /*! GPWE28 - Global Pin Write Enable
26276 /*! GPWE29 - Global Pin Write Enable
26284 /*! GPWE30 - Global Pin Write Enable
26292 /*! GPWE31 - Global Pin Write Enable
26299 /*! @name CONFIG - Configuration */
26304 /*! RANGE - Port Voltage Range
26305 * 0b0..1.71 V-3.6 V
26306 * 0b1..2.70 V-3.6 V
26311 /*! @name EDFR - EFT Detect Flag */
26316 /*! EDF0 - EFT Detect Flag
26324 /*! EDF1 - EFT Detect Flag
26332 /*! EDF2 - EFT Detect Flag
26340 /*! EDF3 - EFT Detect Flag
26348 /*! EDF4 - EFT Detect Flag
26356 /*! EDF5 - EFT Detect Flag
26364 /*! EDF6 - EFT Detect Flag
26372 /*! Reserved6 - Reserved
26380 /*! Reserved7 - Reserved
26388 /*! EDF8 - EFT Detect Flag
26396 /*! Reserved8 - Reserved
26404 /*! EDF9 - EFT Detect Flag
26412 /*! Reserved9 - Reserved
26420 /*! Reserved10 - Reserved
26428 /*! Reserved11 - Reserved
26436 /*! Reserved12 - Reserved
26444 /*! Reserved13 - Reserved
26452 /*! Reserved14 - Reserved
26460 /*! Reserved15 - Reserved
26468 /*! EDF16 - EFT Detect Flag
26476 /*! Reserved16 - Reserved
26484 /*! EDF17 - EFT Detect Flag
26492 /*! Reserved17 - Reserved
26500 /*! EDF18 - EFT Detect Flag
26508 /*! Reserved18 - Reserved
26516 /*! EDF19 - EFT Detect Flag
26524 /*! Reserved19 - Reserved
26532 /*! EDF20 - EFT Detect Flag
26540 /*! Reserved20 - Reserved
26548 /*! EDF21 - EFT Detect Flag
26556 /*! Reserved21 - Reserved
26564 /*! EDF22 - EFT Detect Flag
26572 /*! Reserved22 - Reserved
26580 /*! Reserved23 - Reserved
26588 /*! Reserved24 - Reserved
26596 /*! Reserved25 - Reserved
26604 /*! Reserved26 - Reserved
26612 /*! Reserved27 - Reserved
26620 /*! Reserved28 - Reserved
26628 /*! Reserved29 - Reserved
26636 /*! Reserved30 - Reserved
26644 /*! Reserved31 - Reserved
26651 /*! @name EDIER - EFT Detect Interrupt Enable */
26656 /*! EDIE0 - EFT Detect Interrupt Enable
26664 /*! EDIE1 - EFT Detect Interrupt Enable
26672 /*! EDIE2 - EFT Detect Interrupt Enable
26680 /*! EDIE3 - EFT Detect Interrupt Enable
26688 /*! EDIE4 - EFT Detect Interrupt Enable
26696 /*! EDIE5 - EFT Detect Interrupt Enable
26704 /*! EDIE6 - EFT Detect Interrupt Enable
26712 /*! Reserved6 - Reserved
26720 /*! Reserved7 - Reserved
26728 /*! EDIE8 - EFT Detect Interrupt Enable
26736 /*! Reserved8 - Reserved
26744 /*! EDIE9 - EFT Detect Interrupt Enable
26752 /*! Reserved9 - Reserved
26760 /*! Reserved10 - Reserved
26768 /*! Reserved11 - Reserved
26776 /*! Reserved12 - Reserved
26784 /*! Reserved13 - Reserved
26792 /*! Reserved14 - Reserved
26800 /*! Reserved15 - Reserved
26808 /*! EDIE16 - EFT Detect Interrupt Enable
26816 /*! Reserved16 - Reserved
26824 /*! EDIE17 - EFT Detect Interrupt Enable
26832 /*! Reserved17 - Reserved
26840 /*! EDIE18 - EFT Detect Interrupt Enable
26848 /*! Reserved18 - Reserved
26856 /*! EDIE19 - EFT Detect Interrupt Enable
26864 /*! Reserved19 - Reserved
26872 /*! EDIE20 - EFT Detect Interrupt Enable
26880 /*! Reserved20 - Reserved
26888 /*! EDIE21 - EFT Detect Interrupt Enable
26896 /*! Reserved21 - Reserved
26904 /*! EDIE22 - EFT Detect Interrupt Enable
26912 /*! Reserved22 - Reserved
26920 /*! Reserved23 - Reserved
26928 /*! Reserved24 - Reserved
26936 /*! Reserved25 - Reserved
26944 /*! Reserved26 - Reserved
26952 /*! Reserved27 - Reserved
26960 /*! Reserved28 - Reserved
26968 /*! Reserved29 - Reserved
26976 /*! Reserved30 - Reserved
26984 /*! Reserved31 - Reserved
26991 /*! @name EDCR - EFT Detect Clear */
26996 /*! EDHC - EFT Detect High Clear
27004 /*! EDLC - EFT Detect Low Clear
27011 /*! @name PCR - Pin Control 0..Pin Control 22 */
27016 /*! PS - Pull Select
27024 /*! PE - Pull Enable
27032 /*! PV - Pull Value
27040 /*! SRE - Slew Rate Enable
27048 /*! PFE - Passive Filter Enable
27056 /*! ODE - Open Drain Enable
27064 /*! DSE - Drive Strength Enable
27072 /*! DSE1 - Drive Strength Enable
27080 /*! MUX - Pin Multiplex Control
27083 * 0b0010..Alternative 2 (chip-specific)
27084 * 0b0011..Alternative 3 (chip-specific)
27085 * 0b0100..Alternative 4 (chip-specific)
27086 * 0b0101..Alternative 5 (chip-specific)
27087 * 0b0110..Alternative 6 (chip-specific)
27088 * 0b0111..Alternative 7 (chip-specific)
27089 * 0b1000..Alternative 8 (chip-specific)
27090 * 0b1001..Alternative 9 (chip-specific)
27091 * 0b1010..Alternative 10 (chip-specific)
27092 * 0b1011..Alternative 11 (chip-specific)
27098 /*! LK - Lock Register
27114 /* PORT - Peripheral instance base addresses */
27186 /* ----------------------------------------------------------------------------
27187 -- RADIO_CTRL Peripheral Access Layer
27188 ---------------------------------------------------------------------------- */
27195 /** RADIO_CTRL - Register Layout Typedef */
27211 /* ----------------------------------------------------------------------------
27212 -- RADIO_CTRL Register Masks
27213 ---------------------------------------------------------------------------- */
27220 /*! @name LL_CTRL - LL Control Register */
27225 /*! ACTIVE_LL - link layer control register
27234 /*! @name RF_CTRL - Radio Control Register */
27239 /*! RBME_MODE_OVRD_EN - RBME Mode Override Enable
27247 /*! RBME_MODE_OVRD - RBME Mode Override */
27252 /*! RX_CON_EN_OVRD_EN - rx_con_en Override Enable
27260 /*! RX_CON_EN_OVRD - rx_con_en Override */
27265 /*! BLE_LR_EN_OVRD_EN - ble_lr_en Override Enable
27273 /*! BLE_LR_EN_OVRD - ble_lr_en Override */
27278 /*! RIF_SEL_2MBPS_OVRD_EN - rif_sel_2mbps Override Enable
27286 /*! RIF_SEL_2MBPS_OVRD - rif_sel_2mbps Override */
27291 /*! WOR_RX_FAIL_WAKEUP_EN - WOR RX Fail Wakeup Enable
27299 /*! BRIC_WAKEUP_EN - BRIC Wakeup Enable
27307 /*! GENERIC_WAKEUP_EN - Generic LL Wakeup Enable
27315 /*! ZIGBEE_WAKEUP_EN - Zigbee LL Wakeup Enable
27322 /*! @name RF_CLK_CTRL - Radio Clock Control Register */
27327 /*! ZBLL_CLK_EN_OVRD - ZBLL Clock Enable Override
27335 /*! GENLL_CLK_EN_OVRD - GENLL Clock Enable Override
27343 /*! BTLL_CLK_EN_OVRD - BTLL Clock Enable Override
27351 /*! BTU_EBRAM_CLK_ON_OVRD - BTU EBRAM Clock Enable Override
27359 /*! BT_ECLK_DIV - BE_ECLK Divider
27367 /*! NBU_HCLK_EN - NBU HCLK Enable
27375 /*! CM3_HCLK_EN - CM3 HCLK Enable
27383 /*! BLE_AHB_CLK_EN - BLE_AHB CLOCK Enable
27391 /*! NBU_PKB_CLK_EN - NBU PKB Clock Enable
27399 /*! BT_16M_CLK_EN - BT 16M Clock Enable
27407 /*! RTU_CLK_EN - RTU Clock Enable
27415 /*! BT_4M_CLK_EN - BT 4M Clock Enable
27423 /*! BT_REF_4M_CLK_EN - BT REF 4M Clock Enable
27431 /*! BT_XCVR_4M_CLK_EN - BT XCVR 4M Clock Enable
27439 /*! BT_XCVR_32M_CLK_EN - BT XCVR 32M Clock Enable
27447 /*! BT_ECLK_EN - BT_ECLK Enable
27455 /*! BLE_AES_CLK_EN - BLE_AES_CLK Enable
27463 /*! UART_CLK_EN - UART Clock Enable
27471 /*! MAN_DS_EN - Manual deep sleep control enable
27479 /*! WOR_DS_EN - WOR deep sleep control enable
27487 /*! BT_CLK_REQ_EN - BT_CLK_REQ control enable
27494 /*! @name COEX_CTRL - COEXISTENCE CONTROL */
27499 /*! RF_NOT_ALLOWED_EN - RF_NOT_ALLOWED PER-LINK-LAYER ENABLE */
27504 /*! RF_NOT_ALLOWED_ASSERTED - RF_NOT_ALLOWED_ASSERTED
27512 /*! RF_NOT_ALLOWED - RF_NOT_ALLOWED */
27517 /*! RF_NOT_ALLOWED_OVRD - RF_NOT_ALLOWED Override */
27522 /*! RF_NOT_ALLOWED_OVRD_EN - RF_NOT_ALLOWED Override Enable
27530 /*! RF_NALLOWED_INV - RF_NALLOWED Invert
27538 /*! RF_ACTIVE_INV - RF_ACTIVE Invert
27546 /*! RF_PRIORITY_INV - RF_PRIORITY Invert
27556 /*! RF_STATUS_INV - RF_STATUS Invert
27564 /*! COEX_SEL - COEX_SEL
27571 /*! @name UID_MSB - Radio Control Register */
27576 /*! RADIO_UID_MSB - The most signficant 8bits of the 40bit Radio UID. */
27580 /*! @name UID_LSB - Radio Control Register */
27585 /*! RADIO_UID_LSB - The least signficant 32bits of the 40bit Radio UID. */
27589 /*! @name PACKET_RAM_CTRL - PACKET RAM Control Register */
27594 /*! PB_PROTECT - PB_PROTECT
27601 /*! @name BLE_PHY_CTRL - BLE PHY Interface Control Register */
27606 /*! CTE_AVG_SAMP_SEL - Sampling select */
27611 /*! READ_START_OFFSET_1M - Start sending Rx data to NBU after a programmable number of symbols are …
27616 /*! READ_START_OFFSET_2M - Start sending Rx data to NBU after a programmable number of symbols are …
27621 /*! READ_START_OFFSET_LR - Start sending Rx data to NBU after a programmable number of symbols are …
27626 /*! GUARD_TIME_1M - Guard time offset for 1M */
27631 /*! GUARD_TIME_2M - Guard time offset for 2M */
27636 /*! AVG_IQ_DISABLE - Disable IQ sample averaging */
27641 /*! CTE_SINGLE_BUF - Config for using single buffer for Rx data and CTE samples */
27645 /*! @name DTEST_CTRL - DTEST Control register */
27650 /*! DTEST_PAGE - DTEST PAGE Number */
27655 /*! DTEST_EN - DTEST_EN control
27663 /*! DTEST_OUT_REG_EN - Enable/Disable register dtest signal
27671 /*! RAW_MODE_I - Select rx_dig_i as DTEST RX_IQ page */
27676 /*! RAW_MODE_Q - Select rx_dig_q as DTEST RX_IQ page */
27681 /*! DTEST_SHIFT - DTEST shift control */
27685 /*! @name DTEST_PIN_CTRL2 - DTEST PIN Control 2 register */
27690 /*! DTEST_PIN8_MUX_SEL - DTEST_PIN8_MUX_SEL */
27695 /*! DTEST_PIN8_OVRD_SEL - DTEST_PIN8_OVRD_SEL
27707 * 0b1011-0b1111..reserved
27713 /*! DTEST_PIN9_MUX_SEL - DTEST_PIN9_MUX_SEL */
27718 /*! DTEST_PIN9_OVRD_SEL - DTEST_PIN9_OVRD_SEL
27730 * 0b1011-0b1111..reserved
27736 /*! DTEST_PIN10_MUX_SEL - DTEST_PIN10_MUX_SEL */
27741 /*! DTEST_PIN10_OVRD_SEL - DTEST_PIN10_OVRD_SEL
27753 * 0b1011-0b1111..reserved
27759 /*! DTEST_PIN11_MUX_SEL - DTEST_PIN11_MUX_SEL */
27764 /*! DTEST_PIN11_OVRD_SEL - DTEST_PIN11_OVRD_SEL
27776 * 0b1011-0b1111..reserved
27787 /* RADIO_CTRL - Peripheral instance base addresses */
27821 /* ----------------------------------------------------------------------------
27822 -- RBME Peripheral Access Layer
27823 ---------------------------------------------------------------------------- */
27830 /** RBME - Register Layout Typedef */
27862 /* ----------------------------------------------------------------------------
27863 -- RBME Register Masks
27864 ---------------------------------------------------------------------------- */
27871 /*! @name CRCW_CFG - CRC/WHITENER CONFIG REGISTER */
27876 /*! CRCW_EN - CRC calculation enable */
27881 /*! CRCW_EC_EN - CRC Error Correction Enable */
27886 /*! CRC_ZERO - CRC zero */
27891 /*! CRC_EARLY_FAIL - CRC error correction fail */
27896 /*! CRC_RES_OUT_VLD - CRC result output valid */
27901 /*! CRC_EC_OFFSET - CRC error correction offset */
27906 /*! CRC_EC_DONE - CRC error correction done */
27911 /*! CRC_EC_FAIL - CRC error correction fail */
27915 /*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */
27920 /*! CRC_EC_MASK - CRC error correction mask */
27924 /*! @name CRC_RES_OUT - CRC RESULT */
27929 /*! CRC_RES_OUT - CRC result output */
27933 /*! @name CRCW_CFG2 - CRC/WHITENER CONFIG 2 REGISTER */
27938 /*! CRC_EC_SPKT_BYTES - Error Correction Short Packet Bytes */
27943 /*! CRC_EC_SPKT_WND - Error correction short packet burst error window */
27948 /*! CRC_EC_LPKT_WND - Error correction long packet burst error window */
27952 /*! @name CRCW_CFG3 - CRC CONFIGURATION */
27957 /*! CRC_SZ - CRC Size (in octets) */
27962 /*! CRC_START_BYTE - Configure CRC Start Point */
27967 /*! CRC_REF_IN - CRC Reflect In
27975 /*! CRC_REF_OUT - CRC Reflect Out
27983 /*! CRC_BYTE_ORD - CRC Byte Order
27990 /*! @name CRC_INIT - CRC INITIALIZATION */
27995 /*! CRC_SEED - CRC Seed Value */
27999 /*! @name CRC_POLY - CRC POLYNOMIAL */
28004 /*! CRC_POLY - CRC Polynomial. */
28008 /*! @name CRC_XOR_OUT - CRC XOR OUT */
28013 /*! CRC_XOR_OUT - CRC XOR OUT Register */
28017 /*! @name WHITEN_CFG - WHITENER CONFIGURATION */
28022 /*! WHITEN_START - Configure Whitener Start Point
28024 * 0b01..start whitening at start-of-H0
28025 * 0b10..start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR
28026 * 0b11..start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR
28032 /*! WHITEN_END - Configure end-of-whitening
28033 * 0b0..end whiten at end-of-payload
28034 * 0b1..end whiten at end-of-crc
28040 /*! WHITEN_B4_CRC - Congifure for Whitening-before-CRC
28041 * 0b0..CRC before whiten/de-whiten
28042 * 0b1..Whiten/de-whiten before CRC
28048 /*! WHITEN_POLY_TYPE - Whiten Polynomial Type */
28053 /*! WHITEN_REF_IN - Whiten Reflect Input */
28058 /*! WHITEN_PAYLOAD_REINIT - Configure for Whitener re-initialization
28059 * 0b0..Does not re-initialize Whitener LFSR at start-of-payload
28060 * 0b1..Re-initialize Whitener LFSR at start-of-payload
28066 /*! WHITEN_SIZE - Length of Whitener LFSR */
28071 /*! WHITEN_INIT - Initialization value for whitening/de-whitening */
28075 /*! @name WHITEN_POLY - WHITENER POLYNOMIAL */
28080 /*! WHITEN_POLY - Whitener Polynomial */
28084 /*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */
28089 /*! WHITEN_SZ_THR - Whitener Size Threshold */
28093 /*! @name FEC_CFG1 - FEC CONFIG REGISTER 1 */
28098 /*! FEC_EN - FEC enable
28106 /*! FEC_SWAP - FEC output swap */
28111 /*! FECOV_EN - Enable dynamic overide of FEC
28119 /*! INTV_EN - Enable interleaver reigster */
28124 /*! FEC_START_BYTE - FEC Start Byte */
28129 /*! NTERM - Number of term bits */
28133 /*! @name RBME_RST - RBME SOFT RESET REGISTER */
28138 /*! RBME_RST - RBME reset signal
28147 /*! RBME_CLK_EN_OVRD - RBME Clock Enable override */
28151 /*! @name FEC_CFG2 - FEC CONFIG REGISTER 2 */
28156 /*! TB_LENGTH - Trace-back length */
28161 /*! SAT_VL - Saturation value for PM */
28166 /*! LARGE_VL - Large value used at startup phase, assigned to the initial PMs. */
28171 /*! SDIDX - Index of startup state. PM(startStIdx)=0 */
28175 /*! @name SPREAD_CFG - SPREADER CONFIG REGISTER */
28180 /*! SP_EN - Spreader Enable bit
28188 /*! SPOV_EN - Spreader Override Enable
28196 /*! CI_TX - Bluetooth LE
28204 /*! SP_START_BYTE - Spread Start Byte */
28209 /*! SP_FACTOR - Spreading Factor
28220 /*! SP_SEQ - Spreading Bit Sequence */
28224 /*! @name WHT_CFG - WHITEN CONFIG REGISTER */
28229 /*! W1_EN - Enable first whitener */
28234 /*! WFIRST - Whitens before CRC */
28239 /*! WTOV_EN - Allows overwrite of the whitening */
28244 /*! WT_OUT_SEL - Selected Output */
28249 /*! WT_TPOGY - Whiten 1 Polynomial Type */
28253 /*! @name PKT_SZ - PACKET SIZE REGISTER */
28258 /*! MAX_PKT_SZ - Maximum Packet Size In Bits */
28263 /*! DEF_PKT_SZ - Default Packet Size */
28267 /*! @name CRC_PHR_SZ - LENGTH OF PHR CONFIG REGISTER */
28272 /*! PHR_SZ - PHR Size Config */
28276 /*! @name FCP_CFG - FCP SUPPORT CONFIG REGISTER */
28281 /*! FCP_SUPPORT - FCP Suppport
28288 /*! @name FRAME_OVER_SZ - FRAME OVERRIDE SIZE REGISTER */
28293 /*! STD_FRM_OV_EN - Overrides actvie STD frame length from link layer enable bit
28301 /*! STD_FRM_OV - Value to overide the STD frame length (bits) */
28305 /*! @name FEC_BSZ_OV_B4SP - OVERRIDE OF FEC BLOCK SIZE REGISTER */
28310 /*! FEC_BSZ_OV_B4SP_EN - Override of the FEC block size for data
28318 /*! FEC_BSZ_OV - Value of the override in bits. It is for test purpose. */
28322 /*! @name LEG0_CFG - LEG0 CONFIG REGISTER */
28327 /*! LEG0_INV_EN - Whiten invert enable bit
28335 /*! LEG0_SUP - LEG0 support register
28343 /*! LEG0_XOR_BYTE - LEG0 whitening masking byte */
28348 /*! LEG0_XOR_RP_BYTE - LEG0 repeat bytes masking */
28353 /*! LEG0_XOR_FST_BYTE - FEC first byte masking */
28357 /*! @name NPAYL_OVER_SZ - OVERRIDE PAYLOAD LENGTH REGISTER */
28362 /*! NPAYL_OV_EN - Override the internal payload length computation
28370 /*! FT_FEC_FLUSH - Value to overide the payload length (bits) */
28378 /*! @name RAM_S_ADDR - PACKET RAM SOURCE ADDRESS */
28383 /*! RAM_S_ADDR - Packet RAM source address. This address is ram physical address. */
28387 /*! @name RAM_D_ADDR - PACKET RAM DESTINATION ADDRESS */
28392 /*! RAM_D_ADDR - Packet RAM destination address, this address is ram physical address. */
28396 /*! @name RAM_IF_CFG - PACKET RAM INTERFACE CONFIG REGISTER */
28401 /*! RAM_IF_TX_EN - RAM interface TX enable bit
28409 /*! RAM_IF_RX_EN - RAM interface RX enable
28417 /*! RAM_IF_IE - RAM interface interrupt enable bit
28425 /*! RAM_IF_IC - RAM interface interrupt clear
28433 /*! H2S_EN - Hard bit convert to soft bit enable
28441 /*! SOFT_HD_SEL_RD - Soft and hard bit selection of write operation
28449 /*! SOFT_HD_SEL_WR - Soft and hard bit selection of read operation
28457 /*! WR_IRQ - Write to RAM complete flag
28465 /*! RD_IRQ - Read to RAM complete flag
28478 /* RBME - Peripheral instance base addresses */
28512 /* ----------------------------------------------------------------------------
28513 -- REGFILE Peripheral Access Layer
28514 ---------------------------------------------------------------------------- */
28521 /** REGFILE - Register Layout Typedef */
28529 /* ----------------------------------------------------------------------------
28530 -- REGFILE Register Masks
28531 ---------------------------------------------------------------------------- */
28538 /*! @name REG - Register File Register 0..Register File Register 7 */
28543 /*! REG - Register File */
28550 /*! @name WAR - Write Access Register */
28555 /*! WAR0 - REG0 Register Write Access
28563 /*! WAR1 - REG1 Register Write Access
28571 /*! WAR2 - REG2 Register Write Access
28579 /*! WAR3 - REG3 Register Write Access
28587 /*! WAR4 - REG4 Register Write Access
28595 /*! WAR5 - REG5 Register Write Access
28603 /*! WAR6 - REG6 Register Write Access
28611 /*! WAR7 - REG7 Register Write Access
28618 /*! @name RAR - Read Access Register */
28623 /*! RAR0 - REG0 Register Read Access
28631 /*! RAR1 - REG1 Register Read Access
28639 /*! RAR2 - REG2 Register Read Access
28647 /*! RAR3 - REG3 Register Read Access
28655 /*! RAR4 - REG4 Register Read Access
28663 /*! RAR5 - REG5 Register Read Access
28671 /*! RAR6 - REG6 Register Read Access
28679 /*! RAR7 - REG7 Register Read Access
28692 /* REGFILE - Peripheral instance base addresses */
28738 /* ----------------------------------------------------------------------------
28739 -- RFMC Peripheral Access Layer
28740 ---------------------------------------------------------------------------- */
28747 /** RFMC - Register Layout Typedef */
28767 /* ----------------------------------------------------------------------------
28768 -- RFMC Register Masks
28769 ---------------------------------------------------------------------------- */
28776 /*! @name VERID - RFMC Version ID Register */
28781 /*! RADIO_ID - Radio Identification Number */
28786 /*! MINOR - Minor RFMC Version Number */
28791 /*! MAJOR - Major RFMC Version Number */
28795 /*! @name PARAM - RFMC Parameter Register */
28807 /*! @name CTRL - RFMC Control Register */
28812 /*! RST_MSK - Reset Mask */
28817 /*! RFMC_RST - S/W System Reset for RFMC
28824 /*! @name XO_CTRL - XO Control Register */
28829 /*! RDY_IE - XTAL Ready Interrupt Enable
28837 /*! INT_IE - XO Internal Request Interrupt Enable
28845 /*! EXT_IE - XO External Request Interrupt Enable
28853 /*! XTAL_OUT_EN - XTAL_OUT Output Pin Enable
28861 /*! XTAL_REQ_OBE - XTAL_REQ Output Pin Enable
28869 /*! XTAL_EN_IBE - XTAL_OUT_EN Input Pin Enable
28877 /*! WKUP_OFFSET - XO Wakeup Offset */
28882 /*! RDY_CNT - XTAL Ready Count
28892 /*! RDY_CNT_OFF - XTAL Ready Count Disable
28900 /*! XTAL_OUT_INV - XO Clock Output Invert
28908 /*! LDO_BYPASS - XO LDO Bypass */
28913 /*! EXT_MODE - External Clock Mode
28921 /*! XTAL_RDY_OVR_EN - XTAL Ready Override Enable */
28926 /*! XTAL_RDY_OVR - XTAL Ready Override */
28931 /*! SPARE - XO Spare Registers */
28936 /*! XO_LDO_OVR - XO LDO Enable Override
28944 /*! XO_LDO_EN - XO LDO Enable
28952 /*! XO_ANA_OVR - XO Analog Enable Override
28960 /*! XO_ANA_EN - XO Analog Enable
28967 /*! @name XO_STAT - XO Status Register */
28972 /*! RDY_FLAG - XTAL Ready Flag */
28977 /*! INT_FLAG - XO Internal Request Flag */
28982 /*! EXT_FLAG - XO External Request Flag */
28987 /*! XTAL_RDY - XTAL Ready */
28992 /*! XO_EN - XO_EN */
28996 /*! @name XO_TEST - XO Test Register */
29001 /*! ISEL - XO Amplifier Current Select
29011 /*! CDAC - XO On-chip Load Capacitor Trim
29019 /*! CAP_OFF - XO Load Capacitor Disable */
29024 /*! AUX_PD - XO CLK_AUX_DRV Powerdown */
29029 /*! AMP_FORCE - XO Amplifier Force PTAT Startup */
29034 /*! DYN_ISEL - XO Amplifier: enable current switching during startup */
29039 /*! DYN_CAP - XO On-chip Load Capacitor: enable switching during startup */
29044 /*! LDO_TRIM - XO LDO Output Voltage Trim
29054 /*! LDO_BUMP - XO LDO PTAT Current Bump
29062 /*! LDO_FORCE - XO LDO Force PTAT Startup */
29066 /*! @name RF2P4GHZ_CTRL - 2.4GHz Radio Control Register */
29071 /*! WOR_WKUP_IE - WOR Wakeup Interrupt Enable
29079 /*! MAN_WKUP_IE - MAN Wakeup Interrupt Enable
29087 /*! BLE_WKUP_IE - Bluetooth LE Wakeup Interrupt Enable
29095 /*! RFACT_IE - RF_ACTIVE Interrupt Enable
29103 /*! LP_WKUP_IE - Low Power Wakeup Interrupt Enable
29111 /*! BLE_WKUP - Bluetooth LE Wakeup
29119 /*! BLE_LP_EN - Bluetooth LE Low Power Enable
29127 /*! LP_ENTER - S/W Low Power Entry Request
29135 /*! LP_MODE - Radio Low Power Mode
29146 /*! LP_WKUP_DLY - LP Wakeup Delay */
29151 /*! SFA_TRIG_EN - SFA Trigger Enable
29163 /*! LP_STOP_REQ_GLITCH_DIS - LP_STOP_REQ Glitch Disable for 2.4GHz Radio */
29168 /*! XO_EN_GLITCH_DIS - XO_EN Glitch Disable for 2.4GHz Radio */
29173 /*! XO_EN - XO Enable for 2.4GHz Radio
29181 /*! CLK_OVR - Clock Gating Override
29195 /*! CPU_RST_LOCK - LOCK for CPU_RST
29203 /*! CPU_RST - S/W Reset for 2.4GHz Radio CPU
29211 /*! RF_POR - S/W Power-on-Reset for 2.4GHz Radio
29212 * 0b0..Release the 2.4GHz radio from power-on-reset
29213 * 0b1..Hold the 2.4GHz radio in power-on-reset
29219 /*! RST - S/W Reset for 2.4GHz Radio
29226 /*! @name RF2P4GHZ_STAT - 2.4GHz Radio Status Register */
29231 /*! WOR_WKUP_FLAG - WOR Wakeup Flag */
29236 /*! MAN_WKUP_FLAG - MAN Wakeup Flag */
29241 /*! BLE_WKUP_FLAG - Bluetooth LE Wakeup Flag */
29246 /*! RFACT_FLAG - RF_ACTIVE Flag */
29251 /*! LP_WKUP_FLAG - Low Power Wakeup Flag */
29256 /*! SLP_RDY_STAT - RF_CMC Sleep Ready Status */
29261 /*! RST_STAT - Reset Status
29269 /*! FRO_CLK_VLD_STAT - FRO Clock Valid Status */
29274 /*! LP_REQ_STAT - Low Power Request Status */
29279 /*! LP_ACK_STAT - Low Power Acknowledge Status */
29284 /*! BLE_WKUP_STAT - Bluetooth LE Wakeup Status */
29289 /*! WOR_STATE - WOR Low Power State
29299 /*! MAN_STATE - MAN Low Power State
29309 /*! BLE_STATE - Bluetooth LE Low Power State
29318 /*! @name RF2P4GHZ_COEXT - 2.4GHz Radio Coexistence Register */
29323 /*! RFGPO_OBE - RF_GPO Output Buffer Enable */
29328 /*! RFGPO_SRC - RF_GPO Source
29340 /*! PORTA_PWR - PORTA Power
29348 /*! RFACT_SRC - RF_ACTIVE Source
29358 /*! RFACT_IDIS - RF_ACTIVE Idle Disable
29366 /*! RFACT_EN - S/W Enable of RF_ACTIVE pin
29374 /*! RFACT_WKUP_DLY - RF_ACTIVE Wakeup Delay */
29379 /*! QREQ_SRC - QUIET_REQ Source
29387 /*! QREQ_SOC_EN - QUIET_REQ Enable for SOC Core Flash
29395 /*! QREQ_RF_EN - QUIET_REQ Enable for Radio CPU Flash
29403 /*! RFNA_IBE - RF_NOT_ALLOWED Input Buffer Enables
29414 /*! @name RF2P4GHZ_TIMER - 2.4GHz TIMER Register */
29419 /*! TIME - Timer Count */
29424 /*! TIM_CLR - Timer Clear
29432 /*! TIM_EN - Timer Enable
29439 /*! @name RF2P4GHZ_WOR1 - 2.4GHz WOR Register 1 */
29444 /*! DURATION_TGT - WOR Low Power Duration Target */
29449 /*! ENTER_REQ - WOR Low Power Entry Request
29456 /*! @name RF2P4GHZ_WOR2 - 2.4GHz WOR Register 2 */
29461 /*! DURATION - WOR Low Power Duration */
29466 /*! WOR_WKUP - WOR Wakeup
29474 /*! WOR_EN - WOR Enable
29481 /*! @name RF2P4GHZ_MAN1 - 2.4GHz MAN Register 1 */
29486 /*! ENTER_TIME - MAN Low Power Entry Time Stamp */
29491 /*! ENTER_REQ - MAN Low Power Entry Request
29498 /*! @name RF2P4GHZ_MAN2 - 2.4GHz MAN Register 2 */
29503 /*! WKUP_TIME - MAN Low Power Wakeup Time Stamp */
29508 /*! MAN_WKUP - MAN Wakeup
29516 /*! MAN_EN - MAN Enable
29523 /*! @name RF2P4GHZ_MAN3 - 2.4GHz MAN Register 3 */
29528 /*! ENTER_TIME_CAPT - MAN Low Power Entry Time Captured */
29532 /*! @name RF2P4GHZ_MAN4 - 2.4GHz MAN Register 4 */
29537 /*! WKUP_TIME_CAPT - MAN Low Power Wakeup Time Captured */
29547 /* RFMC - Peripheral instance base addresses */
29581 /* ----------------------------------------------------------------------------
29582 -- RF_CMC1 Peripheral Access Layer
29583 ---------------------------------------------------------------------------- */
29590 /** RF_CMC1 - Register Layout Typedef */
29600 /* ----------------------------------------------------------------------------
29601 -- RF_CMC1 Register Masks
29602 ---------------------------------------------------------------------------- */
29609 /*! @name RADIO_LP - Radio Low Power Control Register */
29614 /*! SLEEP_EN - Sleep Enable */
29619 /*! BLE_WKUP - Bluetooth Wakeup */
29624 /*! CK - Clock Control
29641 /*! @name SOC_LP - SOC Low Power Control and Status Register */
29646 /*! BUS_REQ - Bus Access Request */
29651 /*! BUS_AWAKE - Bus Awake */
29655 /*! @name IRQ_CTRL - Interrupt Control Register */
29660 /*! RDY_FLAG - XTAL Ready Flag */
29665 /*! RDY_IE - XTAL Ready Interrupt Enable */
29670 /*! XTAL_RDY - XTAL Ready */
29674 /*! @name TPM2_CFG - TPM2 Configuration Register */
29679 /*! CH0_MUX_SEL - Channel0 Input Mux Select
29687 /*! CH1_MUX_SEL - Channel1 Input Mux Select
29709 /*! CGC - Clock Gate Control
29717 /*! CLK_MUX_SEL - Clock Mux Select
29726 /*! @name RADIO_TRIM - Radio Trim Register */
29731 /*! BG_TRIM - Bandgap Trim
29745 /*! CM3_PHANTOM - CM3 Phantom
29752 /*! @name RAM_PWR - RAM Power Control register */
29757 /*! SD_EN - Shut Down Enable */
29762 /*! DS_EN - Deep Sleep Enable */
29772 /* RF_CMC1 - Peripheral instance base addresses */
29806 /* ----------------------------------------------------------------------------
29807 -- RF_FMCCFG Peripheral Access Layer
29808 ---------------------------------------------------------------------------- */
29815 /** RF_FMCCFG - Register Layout Typedef */
29820 /* ----------------------------------------------------------------------------
29821 -- RF_FMCCFG Register Masks
29822 ---------------------------------------------------------------------------- */
29829 /*! @name RFMCCFG - Radio Flash Memory Controller Configuration Register */
29834 /*! RFCF0 - Radio Flash Control Field 0 */
29839 /*! RFCF1 - Radio Flash Control Field 1 */
29844 /*! RFCF2 - Radio Flash Control Field 2 */
29849 /*! RFCF3 - Radio Flash Control Field 3 */
29859 /* RF_FMCCFG - Peripheral instance base addresses */
29893 /* ----------------------------------------------------------------------------
29894 -- RTC Peripheral Access Layer
29895 ---------------------------------------------------------------------------- */
29902 /** RTC - Register Layout Typedef */
29926 /* ----------------------------------------------------------------------------
29927 -- RTC Register Masks
29928 ---------------------------------------------------------------------------- */
29935 /*! @name TSR - RTC Time Seconds Register */
29940 /*! TSR - Time Seconds Register */
29944 /*! @name TPR - RTC Time Prescaler Register */
29949 /*! TPR - Time Prescaler Register */
29953 /*! @name TAR - RTC Time Alarm Register */
29958 /*! TAR - Time Alarm Register */
29962 /*! @name TCR - RTC Time Compensation Register */
29967 /*! TCR - Time Compensation Register
29980 /*! CIR - Compensation Interval Register */
29985 /*! TCV - Time Compensation Value */
29990 /*! CIC - Compensation Interval Counter */
29994 /*! @name CR - RTC Control Register */
29999 /*! SWR - Software Reset
30008 /*! WPE - Wakeup Pin Enable
30016 /*! UM - Update Mode
30024 /*! CPS - Clock Pin Select
30032 /*! CLKO - Clock Output
30040 /*! CPE - Clock Pin Enable
30049 /*! @name SR - RTC Status Register */
30054 /*! TIF - Time Invalid Flag
30062 /*! TOF - Time Overflow Flag
30070 /*! TAF - Time Alarm Flag
30078 /*! MOF - Monotonic Overflow Flag
30086 /*! TCE - Time Counter Enable
30094 /*! TIDF - Tamper Interrupt Detect Flag
30101 /*! @name LR - RTC Lock Register */
30106 /*! TCL - Time Compensation Lock
30114 /*! CRL - Control Register Lock
30122 /*! SRL - Status Register Lock
30130 /*! LRL - Lock Register Lock
30138 /*! TTSL - Tamper Time Seconds Lock
30146 /*! MEL - Monotonic Enable Lock
30154 /*! MCLL - Monotonic Counter Low Lock
30162 /*! MCHL - Monotonic Counter High Lock
30170 /*! TDL - Tamper Detect Lock
30178 /*! TIL - Tamper Interrupt Lock
30186 /*! PCL - Pin Configuration Lock */
30190 /*! @name IER - RTC Interrupt Enable Register */
30195 /*! TIIE - Time Invalid Interrupt Enable
30203 /*! TOIE - Time Overflow Interrupt Enable
30211 /*! TAIE - Time Alarm Interrupt Enable
30219 /*! MOIE - Monotonic Overflow Interrupt Enable
30227 /*! TSIE - Time Seconds Interrupt Enable
30235 /*! WPON - Wakeup Pin On
30243 /*! TSIC - Timer Seconds Interrupt Configuration
30256 /*! @name TTSR - RTC Tamper Time Seconds Register */
30261 /*! TTS - Tamper Time Seconds */
30265 /*! @name MER - RTC Monotonic Enable Register */
30270 /*! MCE - Monotonic Counter Enable
30277 /*! @name MCLR - RTC Monotonic Counter Low Register */
30282 /*! MCL - Monotonic Counter Low */
30286 /*! @name MCHR - RTC Monotonic Counter High Register */
30291 /*! MCH - Monotonic Counter High */
30295 /*! @name TDR - RTC Tamper Detect Register */
30300 /*! LCTF - Loss of Clock Tamper Flag
30308 /*! STF - Security Tamper Flag
30316 /*! FSF - Flash Security Flag
30324 /*! TMF - Test Mode Flag
30332 /*! TPF - Tamper Pin Flag */
30336 /*! @name TIR - RTC Tamper Interrupt Register */
30341 /*! LCIE - Loss of Clock Interrupt Enable
30349 /*! SIE - Security Module Interrupt Enable
30357 /*! FSIE - Flash Security Interrupt Enable
30365 /*! TMIE - Test Mode Interrupt Enable
30373 /*! TPIE - Tamper Pin Interrupt Enable
30380 /*! @name PCR - RTC Pin Configuration Register */
30385 /*! TPE - Tamper Pull Enable
30393 /*! TPS - Tamper Pull Select
30401 /*! TFE - Tamper Filter Enable
30409 /*! TPP - Tamper Pin Polarity
30417 /*! TPID - Tamper Pin Input Data
30427 /*! @name WAR - RTC Write Access Register */
30432 /*! TSRW - Time Seconds Register Write
30440 /*! TPRW - Time Prescaler Register Write
30448 /*! TARW - Time Alarm Register Write
30456 /*! TCRW - Time Compensation Register Write
30464 /*! CRW - Control Register Write
30472 /*! SRW - Status Register Write
30480 /*! LRW - Lock Register Write
30488 /*! IERW - Interrupt Enable Register Write
30496 /*! TTSW - Tamper Time Seconds Write
30504 /*! MERW - Monotonic Enable Register Write
30512 /*! MCLW - Monotonic Counter Low Write
30520 /*! MCHW - Monotonic Counter High Write
30528 /*! TDRW - Tamper Detect Register Write
30536 /*! TIRW - Tamper Interrupt Register Write
30544 /*! PCRW - Pin Configuration Register Write */
30548 /*! @name RAR - RTC Read Access Register */
30553 /*! TSRR - Time Seconds Register Read
30561 /*! TPRR - Time Prescaler Register Read
30569 /*! TARR - Time Alarm Register Read
30577 /*! TCRR - Time Compensation Register Read
30585 /*! CRR - Control Register Read
30593 /*! SRR - Status Register Read
30601 /*! LRR - Lock Register Read
30609 /*! IERR - Interrupt Enable Register Read
30617 /*! TTSR - Tamper Time Seconds Read
30625 /*! MERR - Monotonic Enable Register Read
30633 /*! MCLR - Monotonic Counter Low Read
30641 /*! MCHR - Monotonic Counter High Read
30649 /*! TDRR - Tamper Detect Register Read
30657 /*! TIRR - Tamper Interrupt Register Read
30665 /*! PCRR - Pin Configuration Register Read */
30675 /* RTC - Peripheral instance base addresses */
30712 /* ----------------------------------------------------------------------------
30713 -- RX_PACKET_RAM Peripheral Access Layer
30714 ---------------------------------------------------------------------------- */
30721 /** RX_PACKET_RAM - Register Layout Typedef */
30726 /* ----------------------------------------------------------------------------
30727 -- RX_PACKET_RAM Register Masks
30728 ---------------------------------------------------------------------------- */
30735 /*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */
30740 /*! RAM - One entry in the packet RAM */
30753 /* RX_PACKET_RAM - Peripheral instance base addresses */
30787 /* ----------------------------------------------------------------------------
30788 -- SCG Peripheral Access Layer
30789 ---------------------------------------------------------------------------- */
30796 /** SCG - Register Layout Typedef */
30820 /* ----------------------------------------------------------------------------
30821 -- SCG Register Masks
30822 ---------------------------------------------------------------------------- */
30829 /*! @name VERID - Version ID Register */
30834 /*! VERSION - SCG Version Number */
30838 /*! @name PARAM - Parameter Register */
30843 /*! CLKPRES - Clock Present
30844 * 0b00000000-0b00000001..Reserved
30854 /*! DIVPRES - Divider Present
30862 /*! @name CSR - Clock Status Register */
30867 /*! DIVSLOW - Slow Clock Divide Ratio
30868 * 0b0000..Divide-by-1
30869 * 0b0001..Divide-by-2
30870 * 0b0010..Divide-by-3
30871 * 0b0011..Divide-by-4
30872 * 0b0100..Divide-by-5
30873 * 0b0101..Divide-by-6
30874 * 0b0110..Divide-by-7
30875 * 0b0111..Divide-by-8
30876 * 0b1000..Divide-by-9
30877 * 0b1001..Divide-by-10
30878 * 0b1010..Divide-by-11
30879 * 0b1011..Divide-by-12
30880 * 0b1100..Divide-by-13
30881 * 0b1101..Divide-by-14
30882 * 0b1110..Divide-by-15
30883 * 0b1111..Divide-by-16
30889 /*! DIVBUS - Bus Clock Divide Ratio
30890 * 0b0000..Divide-by-1
30891 * 0b0001..Divide-by-2
30892 * 0b0010..Divide-by-3
30893 * 0b0011..Divide-by-4
30894 * 0b0100..Divide-by-5
30895 * 0b0101..Divide-by-6
30896 * 0b0110..Divide-by-7
30897 * 0b0111..Divide-by-8
30898 * 0b1000..Divide-by-9
30899 * 0b1001..Divide-by-10
30900 * 0b1010..Divide-by-11
30901 * 0b1011..Divide-by-12
30902 * 0b1100..Divide-by-13
30903 * 0b1101..Divide-by-14
30904 * 0b1110..Divide-by-15
30905 * 0b1111..Divide-by-16
30911 /*! DIVCORE - Core Clock Divide Ratio
30912 * 0b0000..Divide-by-1
30913 * 0b0001..Divide-by-2
30914 * 0b0010..Divide-by-3
30915 * 0b0011..Divide-by-4
30916 * 0b0100..Divide-by-5
30917 * 0b0101..Divide-by-6
30918 * 0b0110..Divide-by-7
30919 * 0b0111..Divide-by-8
30920 * 0b1000..Divide-by-9
30921 * 0b1001..Divide-by-10
30922 * 0b1010..Divide-by-11
30923 * 0b1011..Divide-by-12
30924 * 0b1100..Divide-by-13
30925 * 0b1101..Divide-by-14
30926 * 0b1110..Divide-by-15
30927 * 0b1111..Divide-by-16
30933 /*! SCS - System Clock Source
30946 /*! @name RCCR - Run Clock Control Register */
30951 /*! DIVSLOW - Slow Clock Divide Ratio
30952 * 0b0000..Divide-by-1
30953 * 0b0001..Divide-by-2
30954 * 0b0010..Divide-by-3
30955 * 0b0011..Divide-by-4
30956 * 0b0100..Divide-by-5
30957 * 0b0101..Divide-by-6
30958 * 0b0110..Divide-by-7
30959 * 0b0111..Divide-by-8
30960 * 0b1000..Divide-by-9
30961 * 0b1001..Divide-by-10
30962 * 0b1010..Divide-by-11
30963 * 0b1011..Divide-by-12
30964 * 0b1100..Divide-by-13
30965 * 0b1101..Divide-by-14
30966 * 0b1110..Divide-by-15
30967 * 0b1111..Divide-by-16
30973 /*! DIVBUS - Bus Clock Divide Ratio
30974 * 0b0000..Divide-by-1
30975 * 0b0001..Divide-by-2
30976 * 0b0010..Divide-by-3
30977 * 0b0011..Divide-by-4
30978 * 0b0100..Divide-by-5
30979 * 0b0101..Divide-by-6
30980 * 0b0110..Divide-by-7
30981 * 0b0111..Divide-by-8
30982 * 0b1000..Divide-by-9
30983 * 0b1001..Divide-by-10
30984 * 0b1010..Divide-by-11
30985 * 0b1011..Divide-by-12
30986 * 0b1100..Divide-by-13
30987 * 0b1101..Divide-by-14
30988 * 0b1110..Divide-by-15
30989 * 0b1111..Divide-by-16
30995 /*! DIVCORE - Core Clock Divide Ratio
30996 * 0b0000..Divide-by-1
30997 * 0b0001..Divide-by-2
30998 * 0b0010..Divide-by-3
30999 * 0b0011..Divide-by-4
31000 * 0b0100..Divide-by-5
31001 * 0b0101..Divide-by-6
31002 * 0b0110..Divide-by-7
31003 * 0b0111..Divide-by-8
31004 * 0b1000..Divide-by-9
31005 * 0b1001..Divide-by-10
31006 * 0b1010..Divide-by-11
31007 * 0b1011..Divide-by-12
31008 * 0b1100..Divide-by-13
31009 * 0b1101..Divide-by-14
31010 * 0b1110..Divide-by-15
31011 * 0b1111..Divide-by-16
31017 /*! SCS - System Clock Source
31030 /*! @name CLKOUTCNFG - SCG CLKOUT Configuration Register */
31035 /*! CLKOUTSEL - SCG Clkout Select
31049 /*! @name SOSCCSR - System OSC Control Status Register */
31054 /*! SOSCEN - System OSC Enable
31062 /*! SOSCSTEN - System OSC Stop Enable
31071 /*! SOSCCM - System OSC Clock Monitor Enable
31079 /*! SOSCCMRE - System OSC Clock Monitor Reset Enable
31087 /*! LK - Lock Register
31095 /*! SOSCVLD - System OSC Valid
31103 /*! SOSCSEL - System OSC Selected
31111 /*! SOSCERR - System OSC Clock Error
31118 /*! @name SIRCCSR - Slow IRC Control Status Register */
31123 /*! SIRCSTEN - Slow IRC Stop Enable
31131 /*! LK - Lock Register
31139 /*! SIRCVLD - Slow IRC Valid
31147 /*! SIRCSEL - Slow IRC Selected
31154 /*! @name FIRCCSR - Fast IRC Control Status Register */
31159 /*! FIRCEN - Fast IRC Enable
31167 /*! FIRCSTEN - Fast IRC Stop Enable
31175 /*! FIRCTREN - Fast IRC Trim Enable
31183 /*! FIRCTRUP - Fast IRC Trim Update
31191 /*! TRIM_LOCK - Fast IRC TRIM LOCK
31199 /*! COARSE_TRIM_BYPASS - Fast Coarse Auto Trim Bypass
31207 /*! LK - Lock Register
31215 /*! FIRCVLD - Fast IRC Valid status
31223 /*! FIRCSEL - Fast IRC Selected status
31231 /*! FIRCERR - Fast IRC Clock Error
31238 /*! @name FIRCCFG - Fast IRC Configuration Register */
31243 /*! RANGE - Frequency Range
31252 /*! @name FIRCTCFG - Fast IRC Trim Configuration Register */
31257 /*! TRIMSRC - Trim Source
31267 /*! TRIMDIV - Fast IRC Trim Predivide */
31271 /*! @name FIRCSTAT - Fast IRC Status Register */
31276 /*! TRIMFINE - Trim Fine */
31281 /*! TRIMCOAR - Trim Coarse */
31285 /*! @name ROSCCSR - RTC OSC Control Status Register */
31290 /*! ROSCCM - RTC OSC Clock Monitor
31298 /*! ROSCCMRE - RTC OSC Clock Monitor Reset Enable
31306 /*! LK - Lock Register
31314 /*! ROSCVLD - RTC OSC Valid
31322 /*! ROSCSEL - RTC OSC Selected
31330 /*! ROSCERR - RTC OSC Clock Error
31343 /* SCG - Peripheral instance base addresses */
31377 /* ----------------------------------------------------------------------------
31378 -- SEMA42 Peripheral Access Layer
31379 ---------------------------------------------------------------------------- */
31386 /** SEMA42 - Register Layout Typedef */
31411 /* ----------------------------------------------------------------------------
31412 -- SEMA42 Register Masks
31413 ---------------------------------------------------------------------------- */
31420 /*! @name GATE3 - Gate */
31425 /*! GTFSM - Gate Finite State Machine
31446 /*! @name GATE2 - Gate */
31451 /*! GTFSM - Gate Finite State Machine
31472 /*! @name GATE1 - Gate */
31477 /*! GTFSM - Gate Finite State Machine
31498 /*! @name GATE0 - Gate */
31503 /*! GTFSM - Gate Finite State Machine
31524 /*! @name GATE7 - Gate */
31529 /*! GTFSM - Gate Finite State Machine
31550 /*! @name GATE6 - Gate */
31555 /*! GTFSM - Gate Finite State Machine
31576 /*! @name GATE5 - Gate */
31581 /*! GTFSM - Gate Finite State Machine
31602 /*! @name GATE4 - Gate */
31607 /*! GTFSM - Gate Finite State Machine
31628 /*! @name GATE11 - Gate */
31633 /*! GTFSM - Gate Finite State Machine
31654 /*! @name GATE10 - Gate */
31659 /*! GTFSM - Gate Finite State Machine
31680 /*! @name GATE9 - Gate */
31685 /*! GTFSM - Gate Finite State Machine
31706 /*! @name GATE8 - Gate */
31711 /*! GTFSM - Gate Finite State Machine
31732 /*! @name GATE15 - Gate */
31737 /*! GTFSM - Gate Finite State Machine
31758 /*! @name GATE14 - Gate */
31763 /*! GTFSM - Gate Finite State Machine
31784 /*! @name GATE13 - Gate */
31789 /*! GTFSM - Gate Finite State Machine
31810 /*! @name GATE12 - Gate */
31815 /*! GTFSM - Gate Finite State Machine
31836 /*! @name RSTGT_R - Reset Gate Read */
31841 /*! RSTGTN - Reset Gate Number */
31846 /*! RSTGMS - Reset Gate Domain */
31851 /*! RSTGSM - Reset Gate Finite State Machine
31854 …* 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset…
31861 /*! @name RSTGT_W - Reset Gate Write */
31866 /*! RSTGTN - Reset Gate Number */
31871 /*! RSTGDP - Reset Gate Data Pattern */
31881 /* SEMA42 - Peripheral instance base addresses */
31915 /* ----------------------------------------------------------------------------
31916 -- SFA Peripheral Access Layer
31917 ---------------------------------------------------------------------------- */
31924 /** SFA - Register Layout Typedef */
31942 /* ----------------------------------------------------------------------------
31943 -- SFA Register Masks
31944 ---------------------------------------------------------------------------- */
31951 /*! @name CTRL - Signal Frequency Analyser (SFA) Control */
31956 /*! MODE - MEASUREMENT MODE
31966 /*! TRIG_START_POL - Trigger Start Polarity
31974 /*! TRIG_END_POL - Trigger End Polarity
31982 /*! SFA_TRIG_MEAS_EN - SFA Triggered Measurement Enable
31991 /*! SFA_IRQ_EN - SFA Interrupt Enable
31999 /*! SFA_EN - SFA Enable
32007 /*! TRIG_START_SEL - Signal MUX For Trigger Based Measurement Start */
32012 /*! TRIG_END_SEL - Signal MUX For Trigger Based Measurement End */
32017 /*! CUT_PREDIV - CUT_PREDIV
32028 * 0b00001010-0b11111101..Divide by CUT_PREDIV - CUT_PREDIV%2
32036 /*! CUT_SEL - CUT_SEL */
32041 /*! CUT_PIN_EN - CUT_PIN_EN */
32045 /*! @name CTRL_EXT - Signal Frequency Analyser (SFA) Control Extended */
32050 /*! CUT_CLK_EN - CUT_CLK_EN */
32054 /*! @name CNT_STAT - Signal Frequency Analyser Count Status Register */
32059 /*! REF_STOPPED - REF_STOPPED */
32064 /*! CUT_STOPPED - CUT_STOPPED */
32069 /*! MEAS_STARTED - Measurement Started Flag */
32074 /*! REF_CNT_TIMEOUT - Reference Counter Time Out */
32079 /*! SFA_IRQ - SFA Interrupt Request */
32084 /*! FREQ_GT_MAX_IRQ - FREQ_GT_MAX interrupt flag */
32089 /*! FREQ_LT_MIN_IRQ - FREQ_LT_MIN interrupt flag */
32093 /*! @name CUT_CNT - Signal Frequency Analyser Clock Under Test Counter */
32098 /*! CUT_CNT - CUT_CNT */
32102 /*! @name REF_CNT - Signal Frequency Analyser Reference Clock Counter */
32107 /*! REF_CNT - REF_CNT */
32111 /*! @name CUT_TARGET - Signal Frequency Analyser Clock Under Test Target Count */
32116 /*! CUT_TARGET - CUT_TARGET */
32120 /*! @name REF_TARGET - Signal Frequency Analyser Reference Clock Target Count */
32125 /*! REF_TARGET - REF_TARGET */
32129 /*! @name REF_CNT_ST_SAVED - Signal Frequency Analyser Reference Clock Count Start Saved Register */
32134 /*! REF_CNT_ST_SAVED - REF_CNT_ST_SAVED */
32138 /*! @name REF_CNT_END_SAVED - Signal Frequency Analyser Reference Clock Count End Saved Register */
32143 /*! REF_CNT_END_SAVED - REF_CNT_END_SAVED */
32147 /*! @name CTRL2 - Extended control register for SFA */
32152 /*! REF_CLK_SEL - Reference clock select */
32157 /*! FREQ_GT_MAX_IRQ_EN - FREQ_GT_MAX interrupt enable */
32162 /*! FREQ_LT_MIN_IRQ_EN - FREQ_LT_MIN interrupt enable */
32166 /*! @name REF_LOW_LIMIT_CNT - Record the low limit reference clock count */
32171 /*! REF_LOW_LIMIT_CNT - Low limit reference clock count value */
32175 /*! @name REF_HIGH_LIMIT_CNT - This register record the low limit of ref clk counter */
32180 /*! REF_HIGH_LIMIT_CNT - High limit reference clock count value */
32184 /*! @name CUT_LOW_LIMIT_CNT - Record the CUT clock low limit counter */
32189 /*! cut_low_limit_cnt - Low limit cut clock count value */
32193 /*! @name CUT_HIGH_LIMIT_CNT - Record high limit count of cut clock */
32198 /*! cut_high_limit_cnt - High limit cut clock count value */
32208 /* SFA - Peripheral instance base addresses */
32254 /* ----------------------------------------------------------------------------
32255 -- SMSCM Peripheral Access Layer
32256 ---------------------------------------------------------------------------- */
32263 /** SMSCM - Register Layout Typedef */
32285 …__IO uint32_t OCMDR0; /**< On-Chip Memory Descriptor Register, offset: …
32287 …__IO uint32_t OCMDR2; /**< On-Chip Memory Descriptor Register, offset: …
32288 …__IO uint32_t OCMDR3; /**< On-Chip Memory Descriptor Register, offset: …
32290 …__IO uint32_t OCMDR5; /**< On-Chip Memory Descriptor Register, offset: …
32292 …__IO uint32_t OCMECR; /**< On-Chip Memory ECC Control Register, offset:…
32294 …__IO uint32_t OCMEIR; /**< On-Chip Memory ECC Interrupt Register, offse…
32296 …__I uint32_t OCMFAR; /**< On-Chip Memory Fault Address Register, offse…
32297 …__I uint32_t OCMFTR; /**< On-Chip Memory Fault Attribute Register, off…
32298 …__I uint32_t OCMFDRH; /**< On-Chip Memory ECC Fault Data High Register,…
32299 …__I uint32_t OCMFDRL; /**< On-Chip Memory ECC Fault Data Low Register, …
32304 /* ----------------------------------------------------------------------------
32305 -- SMSCM Register Masks
32306 ---------------------------------------------------------------------------- */
32313 /*! @name DBGEN - Debug Enable */
32318 /*! DBGEN - Invasive Debug Enable (DFF3 bitfield)
32319 * 0b101..W5C - Disable Invasive Debug.
32320 * 0b010..W2S - Enable Invasive Debug.
32328 /*! SPIDEN - Secure Invasive Debug Enable (DFF3 bitfield)
32329 * 0b101..W5C - Disable Secure Invasive Debug.
32330 * 0b010..W2S - Enable Secure Invasive Debug.
32338 /*! NIDEN - Non-Invasive Debug Enable (DFF3 bitfield)
32339 * 0b101..W5C - Disable Non-Invasive Debug.
32340 * 0b010..W2S - Enable Non-Invasive Debug.
32341 * 0b000..Non-Invasive Debug Disabled.
32342 * 0b010..Non-Invasive Debug Enabled.
32348 /*! SPNIDEN - Secure Non-Invasive Debug Enable (DFF3 bitfield)
32349 * 0b101..W5C - Disable Secure Non-Invasive Debug.
32350 * 0b010..W2S - Enable Secure Non-Invasive Debug.
32351 * 0b000..Secure Non-Invasive Debug Disabled.
32352 * 0b010..Secure Non-Invasive Debug Enabled.
32358 /*! ALTDBGEN - Alternate Invasive Debug Enable (DFF3 bitfield)
32359 * 0b101..W5C - Disable Alternate Invasive Debug.
32360 * 0b010..W2S - Enable Alternate Invasive Debug.
32368 /*! ALTEN - Alternate Enable (DFF3 bitfield)
32369 * 0b101..W5C - Disable Alternate.
32370 * 0b010..W2S - Enable Alternate.
32377 /*! @name DBGEN_B - Debug Enable Complement */
32382 /*! DBGEN_B - Invasive Debug Enable Complement (DFF3 bitfield)
32383 * 0b101..W5C - Enable Invasive Debug.
32384 * 0b010..W2S - Disable Invasive Debug.
32392 /*! SPIDEN_B - Secure Invasive Debug Enable - Complement (DFF3 bitfield)
32393 * 0b101..W5C - Enable Secure Invasive Debug.
32394 * 0b010..W2S - Disable Secure Invasive Debug.
32402 /*! NIDEN_B - Non-Invasive Debug Enable Complement (DFF3 bitfield)
32403 * 0b101..W5C - Enable Non-Invasive Debug.
32404 * 0b010..W2S - Disable Non-Invasive Debug.
32405 * 0b000..Non-Invasive Debug Enabled.
32406 * 0b010..Non-Invasive Debug Disabled.
32412 /*! SPNIDEN_B - Secure Non-Invasive Debug Enable Complement (DFF3 bitfield)
32413 * 0b101..W5C - Enable Secure Non-Invasive Debug.
32414 * 0b010..W2S - Disable Secure Non-Invasive Debug.
32415 * 0b000..Secure Non-Invasive Debug Enabled.
32416 * 0b010..Secure Non-Invasive Debug Disabled.
32422 /*! ALTDBGEN_B - Alternate Invasive Debug Enable Complement (DFF3 bitfield)
32423 * 0b101..W5C - Alternate Enable Invasive Debug.
32424 * 0b010..W2S - Alternate Disable Invasive Debug.
32432 /*! ALTEN_B - Alternate Enable Complement (DFF3 bitfield)
32433 * 0b101..W5C - Enable Alternate.
32434 * 0b010..W2S - Disable Alternate.
32441 /*! @name DBGEN_LOCK - Debug Enable Lock */
32446 /*! LOCK - Lock (DFF3 bitfield)
32459 /*! ALT_DBGEN_LOCK - Alternate Lock (DFF3 bitfield)
32471 /*! ALT_EN_LOCK - Alternate Lock (DFF3 bitfield)
32482 /*! @name DBG_AUTH_BEACON - Debug Authentication Beacon */
32487 /*! AUTH_BEACON - Authentication Beacon */
32492 /*! CREDENTIAL_BEACON - Credential Beacon */
32496 /*! @name LIFECYCLE - Lifecycle Fuse Word */
32501 /*! CLC - Converged Lifecycle
32517 /*! DBG_EN_LOCK - Debug Enable Lock
32519 * 0b1..The debug access control registers are write-locked before jumping to customer code.
32525 /*! DBG_AUTH_DIS - Debug Authentication Disabled
32533 /*! TZM_EN - Trust Zone Mode Enable
32534 * 0b0..TZ-M is disabled by default, can be enabled by software.
32535 * 0b1..TZ-M is enabled.
32541 /*! DICE_EN - DICE Enable
32549 /*! SERIAL_DIS - Serial Download Disabled
32557 /*! WAKEUP_DIS - Wakeup Disabled
32558 * 0b0..Boot-ROM LP wakup is enabled.
32559 * 0b1..Boot-ROM LP wakup is disabled.
32565 /*! CTRK_REVOKE - Revocation indicator from OEM Firmware Authentication Public Key */
32570 /*! SWD_ID - Serial Wire Debug Instance ID */
32574 /*! @name LIFECYCLE_B - Lifecycle Fuse Word Complement */
32579 /*! CLC_B - Converged Lifecycle Complement
32595 /*! DBG_EN_LOCK_B - Debug Enable Lock Complement
32596 * 0b0..The debug access control registers are write-locked before jumping to customer code.
32603 /*! DBG_AUTH_DIS_B - Debug Authentication Disabled Complement
32611 /*! TZM_EN_B - Trust Zone Mode Enable Complement
32612 * 0b0..TZ-M is enabled.
32613 * 0b1..TZ-M is disabled by default, can be enabled by software.
32619 /*! DICE_EN_B - DICE Enable Complement
32627 /*! SERIAL_DIS_B - Serial Download Disabled Complement
32635 /*! WAKEUP_DIS_B - Wakeup Disabled Complement
32636 * 0b1..Boot-ROM LP wakup is enabled.
32637 * 0b0..Boot-ROM LP wakup is disabled.
32643 /*! CTRK_REVOKE_B - Revocation indicator from OEM Firmware Authentication Public Key Complement */
32648 /*! SWD_ID_B - Serial Wire Debug Instance ID Complement */
32652 /*! @name ROM_LOCKOUT - ROM Lockout Register */
32657 /*! ROMWA - ROM Watermark Address */
32662 /*! REGLOCK - ROM_LOCKOUT Register Lock (DFF3 bitfield)
32671 /*! @name SCTR - Security Counter Register */
32676 /*! DATA32 - Data, 32 bits */
32680 /*! @name SCTRP1 - Security Counter Plus 1 Register */
32685 /*! DONTCARE32 - Don't Care Data, 32 bits */
32689 /*! @name SCTRM1 - Security Counter Minus 1 Register */
32694 /*! DONTCARE32 - Don't Care Data, 32 bits */
32698 /*! @name SCTRPX - Security Counter Plus X Register */
32703 /*! DATA32 - Data, 32 bits */
32707 /*! @name SCTRMX - Security Counter Minus X Register */
32712 /*! DATA32 - Data, 32 bits */
32716 /*! @name OCMDR0 - On-Chip Memory Descriptor Register */
32721 /*! OCMCF0 - OCMEM Control Field 0 */
32726 /*! OCMCF1 - OCMEM Control Field 1 */
32731 /*! OCMCF2 - OCMEM Control Field 2 */
32736 /*! RO - Read-Only
32743 /*! @name OCMDR2 - On-Chip Memory Descriptor Register */
32748 /*! OCMCF0 - OCMEM Control Field 0 */
32753 /*! RO - Read-Only
32760 /*! @name OCMDR3 - On-Chip Memory Descriptor Register */
32765 /*! OCMCF0 - OCMEM Control Field 0 */
32770 /*! RO - Read-Only
32777 /*! @name OCMDR5 - On-Chip Memory Descriptor Register */
32782 /*! OCMCF0 - OCMEM Control Field 0 */
32787 /*! RO - Read-Only
32794 /*! @name OCMECR - On-Chip Memory ECC Control Register */
32799 /*! ENCR - Enable RAM ECC Non-correctable Reporting
32800 * 0b0..Non-correctable reporting disabled
32801 * 0b1..Non-correctable reporting enabled
32807 /*! E1BR - Enable RAM ECC 1 Bit Reporting
32808 * 0b0..1-bit reporting disabled
32809 * 0b1..1-bit reporting enabled
32814 /*! @name OCMEIR - On-Chip Memory ECC Interrupt Register */
32819 /*! ENCERRN - ECC Non-correctable Error OCRAMn */
32824 /*! E1BERRN - ECC 1-bit Error OCRAMn */
32829 /*! EELOC - ECC Error Location
32830 * 0b0000..non-correctable on OCRAM0
32831 * 0b0001..non-correctable on OCRAM1
32832 * 0b0010..non-correctable on OCRAM2
32833 * 0b0011..non-correctable on OCRAM3
32834 * 0b0100..non-correctable on OCRAM4
32835 * 0b0101..non-correctable on OCRAM5
32836 * 0b0110..non-correctable on OCRAM6
32837 * 0b0111..non-correctable on OCRAM7
32838 * 0b1000..1-bit correctable on OCRAM0
32839 * 0b1001..1-bit correctable on OCRAM1
32840 * 0b1010..1-bit correctable on OCRAM2
32841 * 0b1011..1-bit correctable on OCRAM3
32842 * 0b1100..1-bit correctable on OCRAM4
32843 * 0b1101..1-bit correctable on OCRAM5
32844 * 0b1110..1-bit correctable on OCRAM6
32845 * 0b1111..1-bit correctable on OCRAM7
32851 /*! VALID - Valid ECC Error Location field
32858 /*! @name OCMFAR - On-Chip Memory Fault Address Register */
32863 /*! EFADD - ECC Fault Address */
32867 /*! @name OCMFTR - On-Chip Memory Fault Attribute Register */
32872 /*! EFPRT - On-Chip Memory ECC Fault Protection */
32877 /*! EFMS - On-Chip Memory ECC Fault Master Size
32878 * 0b000..8-bit size
32879 * 0b001..16-bit size
32880 * 0b010..32-bit size
32881 * 0b011..64-bit size
32891 /*! EFW - On-Chip Memory ECC Fault Write
32899 /*! EFMST - On-Chip Memory ECC Fault Master Number */
32904 /*! EFSYN - On-Chip Memory ECC Fault Syndrome */
32908 /*! @name OCMFDRH - On-Chip Memory ECC Fault Data High Register */
32913 /*! EFDH - On-Chip Memory ECC Fault Data High */
32917 /*! @name OCMFDRL - On-Chip Memory ECC Fault Data Low Register */
32922 /*! EFDL - On-Chip Memory ECC Fault Data Low */
32926 /*! @name CPCR - Core Platform Control Register */
32931 /*! AXBS0_RREN - AXBS0 Round Robin Enable
32944 /* SMSCM - Peripheral instance base addresses */
32978 /* ----------------------------------------------------------------------------
32979 -- SPC Peripheral Access Layer
32980 ---------------------------------------------------------------------------- */
32987 /** SPC - Register Layout Typedef */
32994 …__IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1…
33001 __IO uint32_t WAKEUP; /**< General Purpose Wake-up, offset: 0xE0 */
33004 …__IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x104 …
33006 __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */
33024 /* ----------------------------------------------------------------------------
33025 -- SPC Register Masks
33026 ---------------------------------------------------------------------------- */
33033 /*! @name VERID - Version ID */
33038 /*! FEATURE - Feature Specification Number
33045 /*! MINOR - Minor Version Number */
33050 /*! MAJOR - Major Version Number */
33054 /*! @name SC - Status Control */
33059 /*! BUSY - SPC Busy Status Flag
33067 /*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag
33069 …* 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode conf…
33077 /*! SPC_LP_MODE - Power Domain Low-Power Mode Request
33088 /*! ISO_CLR - Isolation Clear Flags */
33093 /*! SWITCH_STATE - Power Switch State
33100 /*! @name CNTRL - SPC Regulator Control */
33105 /*! CORELDO_EN - LDO_CORE Regulator Enable
33113 /*! SYSLDO_EN - LDO_SYS Regulator Enable
33121 /*! DCDC_EN - DCDC_CORE Regulator Enable
33128 /*! @name LPREQ_CFG - Low-Power Request Configuration */
33133 /*! LPREQOE - Low-Power Request Output Enable
33141 /*! LPREQPOL - Low-Power Request Output Pin Polarity Control
33149 /*! LPREQOV - Low-Power Request Output Override
33158 /*! @name CFG - SPC Configuration */
33163 /*! INTG_PWSWTCH_SLEEP_EN - Integrated Power Switch Sleep Enable
33171 /*! INTG_PWSWTCH_WKUP_EN - Integrated Power Switch Wake-up Enable
33179 /*! INTG_PWSWTCH_SLEEP_ACTIVE_EN - Integrated Power Switch Active Enable
33187 /*! INTG_PWSWTCH_WKUP_ACTIVE_EN - Integrated Power Switch Wake-up Enable
33194 /*! @name PD_STATUS - SPC Power Domain Mode Status */
33199 /*! PWR_REQ_STATUS - Power Request Status Flag
33207 /*! PD_LP_REQ - Power Domain Low Power Request Flag
33215 /*! LP_MODE - Power Domain Low Power Mode Request
33228 /*! @name SRAMCTL - SRAM Control */
33233 /*! VSM - Voltage Select Margin
33243 /*! REQ - SRAM Voltage Update Request
33251 /*! ACK - SRAM Voltage Update Request Acknowledge
33258 /*! @name WAKEUP - General Purpose Wake-up */
33263 /*! WAKEUP - Wake-up */
33267 /*! @name ACTIVE_CFG - Active Power Mode Configuration */
33272 /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
33280 /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
33284 * 0b11..Regulate to safe-mode voltage (1.15 V)
33290 /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
33298 /*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level
33306 /*! DCDC_VDD_DS - DCDC VDD Drive Strength
33315 /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
33319 * 0b11..Safe-mode voltage (1.8 V)
33325 /*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable
33333 /*! LPBUFF_EN - CMP Bandgap Buffer Enable
33341 /*! BGMODE - Bandgap Mode
33351 /*! CORE_LVDE - Core Low-Voltage Detection Enable
33359 /*! SYS_LVDE - System Low-Voltage Detection Enable
33367 /*! IO_LVDE - IO Low-Voltage Detection Enable
33375 /*! CORE_HVDE - Core High-Voltage Detection Enable
33383 /*! SYS_HVDE - System High-Voltage Detection Enable
33391 /*! IO_HVDE - IO High-Voltage Detection Enable
33398 /*! @name LP_CFG - Low-Power Mode Configuration */
33403 /*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength
33411 /*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level
33415 * 0b11..Safe-mode voltage (1.15 V)
33422 /*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength
33430 /*! DCDC_VDD_DS - DCDC VDD Drive Strength
33440 /*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level
33444 * 0b11..Safe-mode voltage (1.8 V)
33450 /*! GLITCH_DETECT_DISABLE - VDD Core Glitch Detect Disable
33458 /*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable
33466 /*! LPBUFF_EN - CMP Bandgap Buffer Enable
33474 /*! BGMODE - Bandgap Mode
33484 /*! LP_IREFEN - Low-Power IREF Enable
33492 /*! CORE_LVDE - Core Low Voltage Detect Enable
33500 /*! SYS_LVDE - System Low Voltage Detect Enable
33508 /*! IO_LVDE - IO Low Voltage Detect Enable
33516 /*! CORE_HVDE - Core High Voltage Detect Enable
33524 /*! SYS_HVDE - System High Voltage Detect Enable
33532 /*! IO_HVDE - IO High Voltage Detect Enable
33539 /*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */
33544 /*! LPWKUP_DELAY - Low-Power Wake-Up Delay */
33548 /*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */
33553 /*! ACTIVE_VDELAY - Active Voltage Delay */
33557 /*! @name VD_STAT - Voltage Detect Status Register */
33562 /*! COREVDD_LVDF - Core VDD Low-Voltage Detect Flag
33563 * 0b0..Low-voltage event not detected
33564 * 0b1..Low-voltage event detected
33570 /*! SYSVDD_LVDF - System VDD Low-Voltage Detect Flag
33571 * 0b0..Low-voltage event not detected
33572 * 0b1..Low-voltage event detected
33578 /*! IOVDD_LVDF - IO VDD Low-Voltage Detect Flag
33579 * 0b0..Low-voltage event not detected
33580 * 0b1..Low-voltage event detected
33586 /*! COREVDD_HVDF - Core VDD High-Voltage Detect Flag
33587 * 0b0..High-voltage event not detected
33588 * 0b1..High-voltage event detected
33594 /*! SYSVDD_HVDF - System VDD High-Voltage Detect Flag
33595 * 0b0..High-voltage event not detected
33596 * 0b1..High-voltage event detected
33602 /*! IOVDD_HVDF - IO VDD High-Voltage Detect Flag
33603 * 0b0..High-voltage event not detected
33604 * 0b1..High-voltage event detected
33609 /*! @name VD_CORE_CFG - Core Voltage Detect Configuration Register */
33614 /*! LVDRE - Core VDD Low-Voltage Detect Reset Enable
33622 /*! LVDIE - Core VDD Low-Voltage Detect Interrupt Enable
33630 /*! HVDRE - Core VDD High-Voltage Detect Reset Enable
33638 /*! HVDIE - Core VDD High-Voltage Detect Interrupt Enable
33646 /*! LOCK - CORE Voltage Detect Reset Enable Lock Bit
33653 /*! @name VD_SYS_CFG - System Voltage Detect Configuration Register */
33658 /*! LVDRE - System VDD Low-Voltage Detect Reset Enable
33666 /*! LVDIE - System VDD Low-Voltage Detect Interrupt Enable
33674 /*! HVDRE - System VDD High-Voltage Detect Reset Enable
33682 /*! HVDIE - System VDD High-Voltage Detect Interrupt Enable
33690 /*! LVSEL - System VDD Low-Voltage Level Select
33698 /*! LOCK - System Voltage Detect Reset Enable Lock Bit
33705 /*! @name VD_IO_CFG - IO Voltage Detect Configuration Register */
33710 /*! LVDRE - IO VDD Low-Voltage Detect Reset Enable
33718 /*! LVDIE - IO VDD Low-Voltage Detect Interrupt Enable
33726 /*! HVDRE - IO VDD High-Voltage Detect Reset Enable
33734 /*! HVDIE - IO VDD High-Voltage Detect Interrupt Enable
33742 /*! LVSEL - IO VDD Low-Voltage Level Select
33750 /*! LOCK - IO Voltage Detect Reset Enable Lock Bit
33757 /*! @name EVD_CFG - External Voltage Domain Configuration Register */
33762 /*! EVDISO - External Voltage Domain Isolation */
33767 /*! EVDLPISO - External Voltage Domain Low Power Isolation */
33772 /*! EVDSTAT - External Voltage Domain Status */
33776 /*! @name VDD_CORE_GLITCH_DETECT_SC - VDD Core Glitch Detect Status Control Register */
33781 /*! CNT_SELECT - CNT_SELECT
33782 * 0b00..Select bit-0 of 4-bit Ripple Counter to detect glitch on VDD Core
33783 * 0b01..Select bit-1 of 4-bit Ripple Counter to detect glitch on VDD Core
33784 * 0b10..Select bit-2 of 4-bit Ripple Counter to detect glitch on VDD Core
33785 * 0b11..Select bit-3 of 4-bit Ripple Counter to detect glitch on VDD Core
33791 /*! TIMEOUT - TIMEOUT */
33796 /*! RE - Core VDD Glitch Detect Reset Enable
33804 /*! IE - Core VDD Glitch Detect Interrupt Enable
33812 /*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */
33817 /*! LOCK - VDD Core Voltage Glitch Detect Reset Enable Lock Bit
33824 /*! @name CORELDO_CFG - LDO_CORE Configuration Register */
33829 /*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable
33836 /*! @name SYSLDO_CFG - LDO_SYS Configuration Register */
33841 /*! ISINKEN - Current Sink Enable
33848 /*! @name DCDC_CFG - DCDC Configuration Register */
33853 /*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable */
33858 /*! FREQ_CNTRL - DCDC Burst Frequency Control Register */
33863 /*! VOUT2P5_SEL - VOUT2P5_SEL
33870 /*! @name DCDC_BURST_CFG - DCDC BURST Configuration Register */
33875 /*! BURST_REQ - Software Burst Request Register
33883 /*! EXT_BURST_EN - DCDC External Burst Request Enable Register
33891 /*! BURST_ACK - DCDC Burst Acknowledge Flag
33899 /*! PULSE_REFRESH_CNT - DCDC 16-bit refresh count value */
33909 /* SPC - Peripheral instance base addresses */
33943 /* ----------------------------------------------------------------------------
33944 -- SYSPM Peripheral Access Layer
33945 ---------------------------------------------------------------------------- */
33952 /** SYSPM - Register Layout Typedef */
33968 /* ----------------------------------------------------------------------------
33969 -- SYSPM Register Masks
33970 ---------------------------------------------------------------------------- */
33977 /*! @name CFGSS - Configuration 0..Configuration 3 */
33982 /*! ID - Identifier */
33987 /*! HRL - Hardware revision level */
33992 /*! NCTRS - Number of Counters */
33997 /*! MSC - Miscellaneous */
34004 /*! @name PMCR - Performance Monitor Control Register */
34009 /*! MENB - Module is Enabled
34017 /*! SSC - Start/Stop Control
34031 /*! CMODE - Count Mode
34041 /*! DCIFSH - Disable Counters if Stopped or Halted
34049 /*! RICTR - Resets the Instruction Counter
34057 /*! RECTR1 - Reset Event Counter 1 */
34062 /*! RECTR2 - Reset Event Counter 2 */
34067 /*! RECTR3 - Reset Event Counter 3
34075 /*! SELEVT1 - Select Event 1 */
34080 /*! SELEVT2 - Select Event 2 */
34085 /*! SELEVT3 - Select Event 3 */
34092 /*! @name HI - Performance Monitor Event Counter */
34097 /*! ECTR - Event Counter */
34107 /*! @name LO - Performance Monitor Event Counter */
34112 /*! ECTR - Event Counter */
34128 /* SYSPM - Peripheral instance base addresses */
34162 /* ----------------------------------------------------------------------------
34163 -- TPM Peripheral Access Layer
34164 ---------------------------------------------------------------------------- */
34171 /** TPM - Register Layout Typedef */
34197 /* ----------------------------------------------------------------------------
34198 -- TPM Register Masks
34199 ---------------------------------------------------------------------------- */
34206 /*! @name VERID - Version ID */
34211 /*! FEATURE - Feature Identification Number
34221 /*! MINOR - Minor Version Number */
34226 /*! MAJOR - Major Version Number */
34230 /*! @name PARAM - Parameter */
34235 /*! CHAN - Channel Count */
34240 /*! TRIG - Trigger Count */
34245 /*! WIDTH - Counter Width */
34249 /*! @name GLOBAL - TPM Global */
34254 /*! NOUPDATE - No Update
34262 /*! RST - Software Reset
34269 /*! @name SC - Status and Control */
34274 /*! PS - Prescale Factor Selection
34288 /*! CMOD - Clock Mode Selection
34298 /*! CPWMS - Center-Aligned PWM Select
34300 * 0b1..TPM counter operates in up-down counting mode.
34306 /*! TOIE - Timer Overflow Interrupt Enable
34314 /*! TOF - Timer Overflow Flag
34322 /*! DMA - DMA Enable
34329 /*! @name CNT - Counter */
34334 /*! COUNT - Counter value */
34338 /*! @name MOD - Modulo */
34343 /*! MOD - Modulo value */
34347 /*! @name STATUS - Capture and Compare Status */
34352 /*! CH0F - Channel 0 Flag
34360 /*! CH1F - Channel 1 Flag
34368 /*! CH2F - Channel 2 Flag
34376 /*! CH3F - Channel 3 Flag
34384 /*! CH4F - Channel 4 Flag
34392 /*! CH5F - Channel 5 Flag
34400 /*! TOF - Timer Overflow Flag
34407 /*! @name CnSC - Channel (n) Status and Control */
34412 /*! DMA - DMA Enable
34420 /*! ELSA - Edge or Level Select */
34425 /*! ELSB - Edge or Level Select */
34430 /*! MSA - Channel Mode Select */
34435 /*! MSB - Channel Mode Select */
34440 /*! CHIE - Channel Interrupt Enable
34448 /*! CHF - Channel Flag
34458 /*! @name CnV - Channel (n) Value */
34463 /*! VAL - Channel Value */
34470 /*! @name COMBINE - Combine Channel Register */
34475 /*! COMBINE0 - Combine Channels 0 and 1
34483 /*! COMSWAP0 - Combine Channel 0 and 1 Swap
34491 /*! COMBINE1 - Combine Channels 2 and 3
34499 /*! COMSWAP1 - Combine Channels 2 and 3 Swap
34507 /*! COMBINE2 - Combine Channels 4 and 5
34515 /*! COMSWAP2 - Combine Channels 4 and 5 Swap
34522 /*! @name TRIG - Channel Trigger */
34527 /*! TRIG0 - Channel 0 Trigger
34535 /*! TRIG1 - Channel 1 Trigger
34543 /*! TRIG2 - Channel 2 Trigger
34551 /*! TRIG3 - Channel 3 Trigger
34559 /*! TRIG4 - Channel 4 Trigger
34567 /*! TRIG5 - Channel 5 Trigger
34574 /*! @name POL - Channel Polarity */
34579 /*! POL0 - Channel 0 Polarity
34587 /*! POL1 - Channel 1 Polarity
34595 /*! POL2 - Channel 2 Polarity
34603 /*! POL3 - Channel 3 Polarity
34611 /*! POL4 - Channel 4 Polarity
34619 /*! POL5 - Channel 5 Polarity
34626 /*! @name FILTER - Filter Control */
34631 /*! CH0FVAL - Channel 0 Filter Value */
34636 /*! CH1FVAL - Channel 1 Filter Value */
34641 /*! CH2FVAL - Channel 2 Filter Value */
34646 /*! CH3FVAL - Channel 3 Filter Value */
34651 /*! CH4FVAL - Channel 4 Filter Value */
34656 /*! CH5FVAL - Channel 5 Filter Value */
34660 /*! @name QDCTRL - Quadrature Decoder Control and Status */
34665 /*! QUADEN - QUADEN
34673 /*! TOFDIR - TOFDIR
34683 /*! QUADIR - Counter Direction in Quadrature Decode Mode
34691 /*! QUADMODE - Quadrature Decoder Mode
34698 /*! @name CONF - Configuration */
34703 /*! DOZEEN - Doze Enable
34712 /*! DBGMODE - Debug Mode
34721 /*! GTBSYNC - Global Time Base Synchronization
34729 /*! GTBEEN - Global time base enable
34737 /*! CSOT - Counter Start on Trigger
34746 /*! CSOO - Counter Stop On Overflow
34754 /*! CROT - Counter Reload On Trigger
34762 /*! CPOT - Counter Pause On Trigger
34770 /*! TRGPOL - Trigger Polarity
34778 /*! TRGSRC - Trigger Source
34786 /*! TRGSEL - Trigger Select
34800 /* TPM - Peripheral instance base addresses */
34860 /* ----------------------------------------------------------------------------
34861 -- TRDC Peripheral Access Layer
34862 ---------------------------------------------------------------------------- */
34869 /** TRDC - Register Layout Typedef */
34919 … offset: 0x1040, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0-9] */
34921 …rray offset: 0x1140, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1], [2][2]…
34927 …ord, array offset: 0x11A8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
34931 …ord, array offset: 0x11D0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0], [0][1] */
34933 …Enable Word, array offset: 0x11F0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0] */
34935 … offset: 0x1240, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0-9] */
34937 …rray offset: 0x1340, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1], [2][2]…
34943 …ord, array offset: 0x13A8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
34947 …ord, array offset: 0x13D0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0], [0][1] */
34949 …Enable Word, array offset: 0x13F0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0] */
34951 … offset: 0x1440, array step: index*0x1000, index2*0x4, valid indices: [0][0-3], [1][0], [2][0-9] */
34953 …rray offset: 0x1540, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1], [2][2]…
34959 …ord, array offset: 0x15A8, array step: index*0x1000, index2*0x4, valid indices: [0-2][0], [2][1] */
34963 …ord, array offset: 0x15D0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0], [0][1] */
34965 …Enable Word, array offset: 0x15F0, array step: index*0x1000, index2*0x4, valid indices: [0-1][0] */
34990 /* ----------------------------------------------------------------------------
34991 -- TRDC Register Masks
34992 ---------------------------------------------------------------------------- */
34999 /*! @name TRDC_CR - TRDC Register */
35004 /*! GVLDM - Global Valid for Domain Assignment Controllers
35012 /*! HRL - Hardware Revision Level */
35017 /*! GVLDB - Global Valid for Memory Block Checkers
35025 /*! GVLDR - Global Valid for Memory Region Checkers
35033 /*! LK1 - Lock Status
35035 * 0b1..The CR is locked (read-only) until the next reset.
35040 /*! @name TRDC_HWCFG0 - Hardware Configuration Register 0 */
35045 /*! NDID - Number of domains */
35050 /*! NMSTR - Number of bus masters */
35055 /*! NMBC - Number of MBCs */
35060 /*! NMRC - Number of MRCs */
35065 /*! MID - Module ID */
35069 /*! @name TRDC_HWCFG1 - TRDC Hardware Configuration Register 1 */
35074 /*! DID - Domain identifier number */
35078 /*! @name DACFG - Domain Assignment Configuration Register */
35083 /*! NMDAR - Number of master domain assignment registers for bus master m */
35088 /*! NCM - Non-CPU Master
35090 * 0b1..Bus master is a non-processor.
35098 /*! @name CFG - Memory Block Configuration Register */
35103 /*! SLV0_NMBLK - Number of blocks in slave 0. */
35108 /*! SLV2_NMBLK - Number of blocks in slave 2. */
35113 /*! SLV0_BLKSZL2 - Block size log2 in slave 0. */
35118 /*! SLV2_BLKSZL2 - Block size log2 in slave 2. */
35123 /*! SLV1_NMBLK - Number of blocks in slave 1. */
35128 /*! SLV3_NMBLK - Number of blocks in slave 3. */
35133 /*! SLV1_BLKSZL2 - Block size log2 in slave 1. */
35138 /*! SLV3_BLKSZL2 - Block size log2 in slave 3. */
35148 /*! @name MRCFG - Memory Region Configuration Register */
35153 /*! NMRGD - Number of memory region descriptors for memory region checker n */
35160 /*! @name TRDC_IDAU_CR - TRDC IDAU Control Register */
35165 /*! VLD - Valid */
35170 /*! CFGSECEXT - Configure Security Extension
35172 * 0b1..ARMv8-M Security Extension is enabled
35178 /*! MPUSDIS - Secure Memory Protection Unit Disabled
35186 /*! MPUNSDIS - NonSecure Memory Protection Unit Disabled
35194 /*! SAUDIS - Security Attribution Unit Disable
35202 /*! LKSVTAIRCR - Lock Secure VTOR, Application interrupt and Reset Control Registers
35210 /*! LKNSVTOR - Lock Nonsecure Vector Table Offset Register
35218 /*! LKSMPU - Lock Secure MPU
35227 /*! LKNSMPU - Lock Nonsecure MPU
35236 /*! LKSAU - Lock SAU
35244 /*! PCURRNS - Processor current security
35251 /*! @name TRDC_FLW_CTL - TRDC FLW Control */
35256 /*! LK - Lock bit
35264 /*! V - Valid bit
35271 /*! @name TRDC_FLW_PBASE - TRDC FLW Physical Base */
35276 /*! PBASE - Physical base address */
35280 /*! @name TRDC_FLW_ABASE - TRDC FLW Array Base */
35285 /*! ABASE_L - Array base address low */
35290 /*! ABASE_H - Array base address high */
35294 /*! @name TRDC_FLW_BCNT - TRDC FLW Block Count */
35299 /*! BCNT - Block Count */
35303 /*! @name TRDC_FDID - TRDC Fault Domain ID */
35308 /*! FDID - Domain ID of Faulted Access */
35312 /*! @name TRDC_DERRLOC - TRDC Domain Error Location Register */
35317 /*! mbc0_err_slv - MBC0 ERROR SLAVE */
35322 /*! mbc1_err_slv - MBC1 ERROR SLAVE */
35327 /*! mbc2_err_slv - MBC2 ERROR SLAVE */
35332 /*! mbc3_err_slv - MBC3 ERROR SLAVE */
35337 /*! MRCINST - MRC instance */
35344 /*! @name W0 - MBC Domain Error Word0 Register */
35349 /*! EADDR - Error address */
35356 /*! @name W1 - MBC Domain Error Word1 Register */
35361 /*! EDID - Error domain identifier */
35366 /*! EATR - Error attributes
35380 /*! ERW - Error read/write
35388 /*! EPORT - Error port
35398 /*! EST - Error state
35411 /*! @name W3 - MBC Domain Error Word3 Register */
35416 /*! RECR - Rearm Error Capture Registers */
35423 /*! @name W0 - MRC Domain Error Word0 Register */
35428 /*! EADDR - Error address */
35435 /*! @name W1 - MRC Domain Error Word1 Register */
35440 /*! EDID - Error domain identifier */
35445 /*! EATR - Error attributes
35459 /*! ERW - Error read/write
35467 /*! EPORT - Error port */
35472 /*! EST - Error state
35485 /*! @name W3 - MRC Domain Error Word3 Register */
35490 /*! RECR - Rearm Error Capture Registers */
35497 /*! @name MDA_W0_0_DFMT0 - DAC Master Domain Assignment Register */
35502 /*! DID - Domain identifier */
35507 /*! DIDS - DID Select
35510 …* 0b10..Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as th…
35517 /*! DFMT - Domain format
35518 * 0b0..Processor-core domain assignment
35519 * 0b1..Non-processor domain assignment
35525 /*! LK1 - 1-bit Lock
35527 * 0b1..Register is locked (read-only) until the next reset.
35533 /*! VLD - Valid
35540 /*! @name MDA_W0_x_DFMT1 - DAC Master Domain Assignment Register */
35545 /*! DID - Domain identifier */
35550 /*! PA - Privileged attribute
35560 /*! SA - Secure attribute
35570 /*! DIDB - DID Bypass
35578 /*! DFMT - Domain format
35579 * 0b0..Processor-core domain assignment
35580 * 0b1..Non-processor domain assignment
35586 /*! LK1 - 1-bit Lock
35588 * 0b1..Register is locked (read-only) until the next reset.
35594 /*! VLD - Valid
35604 /*! @name MBC_MEM_GLBCFG - MBC Global Configuration Register */
35609 /*! NBLKS - Number of blocks in this memory */
35614 /*! SIZE_LOG2 - Log2 size per block */
35624 /*! @name MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */
35629 /*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX det…
35634 /*! MEM_SEL - Memory Select */
35639 /*! DID_SEL0 - DID Select
35647 /*! DID_SEL1 - DID Select
35655 /*! DID_SEL2 - DID Select
35663 /*! AI - Auto Increment
35673 /*! @name MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */
35678 /*! W1SET - Write-1 Set */
35685 /*! @name MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */
35690 /*! W1CLR - Write-1 Clear */
35697 /*! @name MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */
35702 /*! MEMSEL - Memory Select */
35707 /*! DID_SEL - DID Select
35717 /*! @name MBC_MEMN_GLBAC - MBC Global Access Control */
35722 /*! NUX - NonsecureUser Execute
35730 /*! NUW - NonsecureUser Write
35738 /*! NUR - NonsecureUser Read
35746 /*! NPX - NonsecurePriv Execute
35754 /*! NPW - NonsecurePriv Write
35762 /*! NPR - NonsecurePriv Read
35770 /*! SUX - SecureUser Execute
35778 /*! SUW - SecureUser Write
35786 /*! SUR - SecureUser Read
35794 /*! SPX - SecurePriv Execute
35802 /*! SPW - SecurePriv Write
35810 /*! SPR - SecurePriv Read
35818 /*! LK - LOCK
35831 /*! @name MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
35836 /*! MBACSEL0 - Memory Block Access Control Select for block B
35850 /*! NSE0 - NonSecure Enable for block B
35860 /*! MBACSEL1 - Memory Block Access Control Select for block B
35874 /*! NSE1 - NonSecure Enable for block B
35884 /*! MBACSEL2 - Memory Block Access Control Select for block B
35898 /*! NSE2 - NonSecure Enable for block B
35908 /*! MBACSEL3 - Memory Block Access Control Select for block B
35922 /*! NSE3 - NonSecure Enable for block B
35932 /*! MBACSEL4 - Memory Block Access Control Select for block B
35946 /*! NSE4 - NonSecure Enable for block B
35956 /*! MBACSEL5 - Memory Block Access Control Select for block B
35970 /*! NSE5 - NonSecure Enable for block B
35980 /*! MBACSEL6 - Memory Block Access Control Select for block B
35994 /*! NSE6 - NonSecure Enable for block B
36004 /*! MBACSEL7 - Memory Block Access Control Select for block B
36018 /*! NSE7 - NonSecure Enable for block B
36033 /*! @name MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
36038 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
36048 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
36058 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
36068 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
36078 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
36088 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
36098 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
36108 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
36118 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
36128 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
36138 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
36148 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
36158 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
36168 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
36178 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
36188 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
36198 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
36208 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
36218 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
36228 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
36238 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
36248 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
36258 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
36268 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
36278 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
36288 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
36298 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
36308 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
36318 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
36328 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
36338 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
36348 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
36363 /*! @name MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
36368 /*! MBACSEL0 - Memory Block Access Control Select for block B
36382 /*! NSE0 - NonSecure Enable for block B
36392 /*! MBACSEL1 - Memory Block Access Control Select for block B
36406 /*! NSE1 - NonSecure Enable for block B
36416 /*! MBACSEL2 - Memory Block Access Control Select for block B
36430 /*! NSE2 - NonSecure Enable for block B
36440 /*! MBACSEL3 - Memory Block Access Control Select for block B
36454 /*! NSE3 - NonSecure Enable for block B
36464 /*! MBACSEL4 - Memory Block Access Control Select for block B
36478 /*! NSE4 - NonSecure Enable for block B
36488 /*! MBACSEL5 - Memory Block Access Control Select for block B
36502 /*! NSE5 - NonSecure Enable for block B
36512 /*! MBACSEL6 - Memory Block Access Control Select for block B
36526 /*! NSE6 - NonSecure Enable for block B
36536 /*! MBACSEL7 - Memory Block Access Control Select for block B
36550 /*! NSE7 - NonSecure Enable for block B
36565 /*! @name MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
36570 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
36580 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
36590 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
36600 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
36610 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
36620 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
36630 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
36640 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
36650 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
36660 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
36670 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
36680 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
36690 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
36700 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
36710 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
36720 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
36730 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
36740 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
36750 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
36760 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
36770 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
36780 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
36790 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
36800 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
36810 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
36820 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
36830 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
36840 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
36850 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
36860 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
36870 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
36880 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
36895 /*! @name MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
36900 /*! MBACSEL0 - Memory Block Access Control Select for block B
36914 /*! NSE0 - NonSecure Enable for block B
36924 /*! MBACSEL1 - Memory Block Access Control Select for block B
36938 /*! NSE1 - NonSecure Enable for block B
36948 /*! MBACSEL2 - Memory Block Access Control Select for block B
36962 /*! NSE2 - NonSecure Enable for block B
36972 /*! MBACSEL3 - Memory Block Access Control Select for block B
36986 /*! NSE3 - NonSecure Enable for block B
36996 /*! MBACSEL4 - Memory Block Access Control Select for block B
37010 /*! NSE4 - NonSecure Enable for block B
37020 /*! MBACSEL5 - Memory Block Access Control Select for block B
37034 /*! NSE5 - NonSecure Enable for block B
37044 /*! MBACSEL6 - Memory Block Access Control Select for block B
37058 /*! NSE6 - NonSecure Enable for block B
37068 /*! MBACSEL7 - Memory Block Access Control Select for block B
37082 /*! NSE7 - NonSecure Enable for block B
37097 /*! @name MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
37102 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
37112 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
37122 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
37132 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
37142 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
37152 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
37162 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
37172 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
37182 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
37192 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
37202 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
37212 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
37222 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
37232 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
37242 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
37252 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
37262 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
37272 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
37282 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
37292 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
37302 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
37312 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
37322 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
37332 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
37342 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
37352 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
37362 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
37372 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
37382 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
37392 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
37402 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
37412 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
37427 /*! @name MBC_DOM0_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
37432 /*! MBACSEL0 - Memory Block Access Control Select for block B
37446 /*! NSE0 - NonSecure Enable for block B
37456 /*! MBACSEL1 - Memory Block Access Control Select for block B
37470 /*! NSE1 - NonSecure Enable for block B
37480 /*! MBACSEL2 - Memory Block Access Control Select for block B
37494 /*! NSE2 - NonSecure Enable for block B
37504 /*! MBACSEL3 - Memory Block Access Control Select for block B
37518 /*! NSE3 - NonSecure Enable for block B
37528 /*! MBACSEL4 - Memory Block Access Control Select for block B
37542 /*! NSE4 - NonSecure Enable for block B
37552 /*! MBACSEL5 - Memory Block Access Control Select for block B
37566 /*! NSE5 - NonSecure Enable for block B
37576 /*! MBACSEL6 - Memory Block Access Control Select for block B
37590 /*! NSE6 - NonSecure Enable for block B
37600 /*! MBACSEL7 - Memory Block Access Control Select for block B
37614 /*! NSE7 - NonSecure Enable for block B
37629 /*! @name MBC_DOM0_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
37634 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
37644 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
37654 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
37664 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
37674 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
37684 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
37694 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
37704 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
37714 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
37724 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
37734 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
37744 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
37754 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
37764 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
37774 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
37784 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
37794 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
37804 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
37814 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
37824 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
37834 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
37844 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
37854 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
37864 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
37874 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
37884 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
37894 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
37904 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
37914 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
37924 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
37934 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
37944 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
37959 /*! @name MBC_DOM1_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
37964 /*! MBACSEL0 - Memory Block Access Control Select for block B
37978 /*! NSE0 - NonSecure Enable for block B
37988 /*! MBACSEL1 - Memory Block Access Control Select for block B
38002 /*! NSE1 - NonSecure Enable for block B
38012 /*! MBACSEL2 - Memory Block Access Control Select for block B
38026 /*! NSE2 - NonSecure Enable for block B
38036 /*! MBACSEL3 - Memory Block Access Control Select for block B
38050 /*! NSE3 - NonSecure Enable for block B
38060 /*! MBACSEL4 - Memory Block Access Control Select for block B
38074 /*! NSE4 - NonSecure Enable for block B
38084 /*! MBACSEL5 - Memory Block Access Control Select for block B
38098 /*! NSE5 - NonSecure Enable for block B
38108 /*! MBACSEL6 - Memory Block Access Control Select for block B
38122 /*! NSE6 - NonSecure Enable for block B
38132 /*! MBACSEL7 - Memory Block Access Control Select for block B
38146 /*! NSE7 - NonSecure Enable for block B
38161 /*! @name MBC_DOM1_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
38166 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
38176 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
38186 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
38196 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
38206 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
38216 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
38226 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
38236 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
38246 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
38256 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
38266 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
38276 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
38286 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
38296 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
38306 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
38316 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
38326 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
38336 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
38346 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
38356 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
38366 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
38376 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
38386 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
38396 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
38406 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
38416 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
38426 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
38436 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
38446 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
38456 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
38466 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
38476 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
38491 /*! @name MBC_DOM1_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
38496 /*! MBACSEL0 - Memory Block Access Control Select for block B
38510 /*! NSE0 - NonSecure Enable for block B
38520 /*! MBACSEL1 - Memory Block Access Control Select for block B
38534 /*! NSE1 - NonSecure Enable for block B
38544 /*! MBACSEL2 - Memory Block Access Control Select for block B
38558 /*! NSE2 - NonSecure Enable for block B
38568 /*! MBACSEL3 - Memory Block Access Control Select for block B
38582 /*! NSE3 - NonSecure Enable for block B
38592 /*! MBACSEL4 - Memory Block Access Control Select for block B
38606 /*! NSE4 - NonSecure Enable for block B
38616 /*! MBACSEL5 - Memory Block Access Control Select for block B
38630 /*! NSE5 - NonSecure Enable for block B
38640 /*! MBACSEL6 - Memory Block Access Control Select for block B
38654 /*! NSE6 - NonSecure Enable for block B
38664 /*! MBACSEL7 - Memory Block Access Control Select for block B
38678 /*! NSE7 - NonSecure Enable for block B
38693 /*! @name MBC_DOM1_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
38698 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
38708 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
38718 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
38728 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
38738 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
38748 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
38758 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
38768 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
38778 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
38788 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
38798 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
38808 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
38818 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
38828 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
38838 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
38848 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
38858 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
38868 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
38878 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
38888 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
38898 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
38908 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
38918 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
38928 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
38938 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
38948 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
38958 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
38968 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
38978 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
38988 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
38998 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
39008 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
39023 /*! @name MBC_DOM1_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
39028 /*! MBACSEL0 - Memory Block Access Control Select for block B
39042 /*! NSE0 - NonSecure Enable for block B
39052 /*! MBACSEL1 - Memory Block Access Control Select for block B
39066 /*! NSE1 - NonSecure Enable for block B
39076 /*! MBACSEL2 - Memory Block Access Control Select for block B
39090 /*! NSE2 - NonSecure Enable for block B
39100 /*! MBACSEL3 - Memory Block Access Control Select for block B
39114 /*! NSE3 - NonSecure Enable for block B
39124 /*! MBACSEL4 - Memory Block Access Control Select for block B
39138 /*! NSE4 - NonSecure Enable for block B
39148 /*! MBACSEL5 - Memory Block Access Control Select for block B
39162 /*! NSE5 - NonSecure Enable for block B
39172 /*! MBACSEL6 - Memory Block Access Control Select for block B
39186 /*! NSE6 - NonSecure Enable for block B
39196 /*! MBACSEL7 - Memory Block Access Control Select for block B
39210 /*! NSE7 - NonSecure Enable for block B
39225 /*! @name MBC_DOM1_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
39230 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
39240 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
39250 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
39260 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
39270 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
39280 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
39290 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
39300 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
39310 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
39320 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
39330 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
39340 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
39350 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
39360 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
39370 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
39380 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
39390 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
39400 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
39410 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
39420 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
39430 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
39440 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
39450 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
39460 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
39470 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
39480 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
39490 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
39500 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
39510 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
39520 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
39530 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
39540 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
39555 /*! @name MBC_DOM1_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
39560 /*! MBACSEL0 - Memory Block Access Control Select for block B
39574 /*! NSE0 - NonSecure Enable for block B
39584 /*! MBACSEL1 - Memory Block Access Control Select for block B
39598 /*! NSE1 - NonSecure Enable for block B
39608 /*! MBACSEL2 - Memory Block Access Control Select for block B
39622 /*! NSE2 - NonSecure Enable for block B
39632 /*! MBACSEL3 - Memory Block Access Control Select for block B
39646 /*! NSE3 - NonSecure Enable for block B
39656 /*! MBACSEL4 - Memory Block Access Control Select for block B
39670 /*! NSE4 - NonSecure Enable for block B
39680 /*! MBACSEL5 - Memory Block Access Control Select for block B
39694 /*! NSE5 - NonSecure Enable for block B
39704 /*! MBACSEL6 - Memory Block Access Control Select for block B
39718 /*! NSE6 - NonSecure Enable for block B
39728 /*! MBACSEL7 - Memory Block Access Control Select for block B
39742 /*! NSE7 - NonSecure Enable for block B
39757 /*! @name MBC_DOM1_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
39762 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
39772 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
39782 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
39792 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
39802 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
39812 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
39822 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
39832 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
39842 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
39852 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
39862 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
39872 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
39882 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
39892 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
39902 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
39912 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
39922 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
39932 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
39942 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
39952 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
39962 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
39972 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
39982 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
39992 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
40002 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
40012 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
40022 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
40032 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
40042 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
40052 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
40062 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
40072 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
40087 /*! @name MBC_DOM2_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */
40092 /*! MBACSEL0 - Memory Block Access Control Select for block B
40106 /*! NSE0 - NonSecure Enable for block B
40116 /*! MBACSEL1 - Memory Block Access Control Select for block B
40130 /*! NSE1 - NonSecure Enable for block B
40140 /*! MBACSEL2 - Memory Block Access Control Select for block B
40154 /*! NSE2 - NonSecure Enable for block B
40164 /*! MBACSEL3 - Memory Block Access Control Select for block B
40178 /*! NSE3 - NonSecure Enable for block B
40188 /*! MBACSEL4 - Memory Block Access Control Select for block B
40202 /*! NSE4 - NonSecure Enable for block B
40212 /*! MBACSEL5 - Memory Block Access Control Select for block B
40226 /*! NSE5 - NonSecure Enable for block B
40236 /*! MBACSEL6 - Memory Block Access Control Select for block B
40250 /*! NSE6 - NonSecure Enable for block B
40260 /*! MBACSEL7 - Memory Block Access Control Select for block B
40274 /*! NSE7 - NonSecure Enable for block B
40289 /*! @name MBC_DOM2_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
40294 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
40304 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
40314 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
40324 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
40334 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
40344 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
40354 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
40364 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
40374 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
40384 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
40394 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
40404 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
40414 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
40424 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
40434 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
40444 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
40454 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
40464 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
40474 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
40484 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
40494 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
40504 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
40514 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
40524 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
40534 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
40544 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
40554 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
40564 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
40574 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
40584 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
40594 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
40604 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
40619 /*! @name MBC_DOM2_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */
40624 /*! MBACSEL0 - Memory Block Access Control Select for block B
40638 /*! NSE0 - NonSecure Enable for block B
40648 /*! MBACSEL1 - Memory Block Access Control Select for block B
40662 /*! NSE1 - NonSecure Enable for block B
40672 /*! MBACSEL2 - Memory Block Access Control Select for block B
40686 /*! NSE2 - NonSecure Enable for block B
40696 /*! MBACSEL3 - Memory Block Access Control Select for block B
40710 /*! NSE3 - NonSecure Enable for block B
40720 /*! MBACSEL4 - Memory Block Access Control Select for block B
40734 /*! NSE4 - NonSecure Enable for block B
40744 /*! MBACSEL5 - Memory Block Access Control Select for block B
40758 /*! NSE5 - NonSecure Enable for block B
40768 /*! MBACSEL6 - Memory Block Access Control Select for block B
40782 /*! NSE6 - NonSecure Enable for block B
40792 /*! MBACSEL7 - Memory Block Access Control Select for block B
40806 /*! NSE7 - NonSecure Enable for block B
40821 /*! @name MBC_DOM2_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
40826 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
40836 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
40846 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
40856 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
40866 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
40876 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
40886 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
40896 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
40906 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
40916 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
40926 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
40936 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
40946 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
40956 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
40966 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
40976 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
40986 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
40996 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
41006 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
41016 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
41026 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
41036 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
41046 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
41056 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
41066 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
41076 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
41086 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
41096 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
41106 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
41116 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
41126 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
41136 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
41151 /*! @name MBC_DOM2_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */
41156 /*! MBACSEL0 - Memory Block Access Control Select for block B
41170 /*! NSE0 - NonSecure Enable for block B
41180 /*! MBACSEL1 - Memory Block Access Control Select for block B
41194 /*! NSE1 - NonSecure Enable for block B
41204 /*! MBACSEL2 - Memory Block Access Control Select for block B
41218 /*! NSE2 - NonSecure Enable for block B
41228 /*! MBACSEL3 - Memory Block Access Control Select for block B
41242 /*! NSE3 - NonSecure Enable for block B
41252 /*! MBACSEL4 - Memory Block Access Control Select for block B
41266 /*! NSE4 - NonSecure Enable for block B
41276 /*! MBACSEL5 - Memory Block Access Control Select for block B
41290 /*! NSE5 - NonSecure Enable for block B
41300 /*! MBACSEL6 - Memory Block Access Control Select for block B
41314 /*! NSE6 - NonSecure Enable for block B
41324 /*! MBACSEL7 - Memory Block Access Control Select for block B
41338 /*! NSE7 - NonSecure Enable for block B
41353 /*! @name MBC_DOM2_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
41358 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
41368 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
41378 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
41388 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
41398 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
41408 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
41418 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
41428 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
41438 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
41448 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
41458 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
41468 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
41478 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
41488 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
41498 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
41508 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
41518 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
41528 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
41538 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
41548 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
41558 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
41568 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
41578 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
41588 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
41598 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
41608 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
41618 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
41628 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
41638 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
41648 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
41658 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
41668 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
41683 /*! @name MBC_DOM2_MEM3_BLK_CFG_W - MBC Memory Block Configuration Word */
41688 /*! MBACSEL0 - Memory Block Access Control Select for block B
41702 /*! NSE0 - NonSecure Enable for block B
41712 /*! MBACSEL1 - Memory Block Access Control Select for block B
41726 /*! NSE1 - NonSecure Enable for block B
41736 /*! MBACSEL2 - Memory Block Access Control Select for block B
41750 /*! NSE2 - NonSecure Enable for block B
41760 /*! MBACSEL3 - Memory Block Access Control Select for block B
41774 /*! NSE3 - NonSecure Enable for block B
41784 /*! MBACSEL4 - Memory Block Access Control Select for block B
41798 /*! NSE4 - NonSecure Enable for block B
41808 /*! MBACSEL5 - Memory Block Access Control Select for block B
41822 /*! NSE5 - NonSecure Enable for block B
41832 /*! MBACSEL6 - Memory Block Access Control Select for block B
41846 /*! NSE6 - NonSecure Enable for block B
41856 /*! MBACSEL7 - Memory Block Access Control Select for block B
41870 /*! NSE7 - NonSecure Enable for block B
41885 /*! @name MBC_DOM2_MEM3_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */
41890 /*! BIT0 - Bit b NonSecure Enable [b = 0 - 31]
41900 /*! BIT1 - Bit b NonSecure Enable [b = 0 - 31]
41910 /*! BIT2 - Bit b NonSecure Enable [b = 0 - 31]
41920 /*! BIT3 - Bit b NonSecure Enable [b = 0 - 31]
41930 /*! BIT4 - Bit b NonSecure Enable [b = 0 - 31]
41940 /*! BIT5 - Bit b NonSecure Enable [b = 0 - 31]
41950 /*! BIT6 - Bit b NonSecure Enable [b = 0 - 31]
41960 /*! BIT7 - Bit b NonSecure Enable [b = 0 - 31]
41970 /*! BIT8 - Bit b NonSecure Enable [b = 0 - 31]
41980 /*! BIT9 - Bit b NonSecure Enable [b = 0 - 31]
41990 /*! BIT10 - Bit b NonSecure Enable [b = 0 - 31]
42000 /*! BIT11 - Bit b NonSecure Enable [b = 0 - 31]
42010 /*! BIT12 - Bit b NonSecure Enable [b = 0 - 31]
42020 /*! BIT13 - Bit b NonSecure Enable [b = 0 - 31]
42030 /*! BIT14 - Bit b NonSecure Enable [b = 0 - 31]
42040 /*! BIT15 - Bit b NonSecure Enable [b = 0 - 31]
42050 /*! BIT16 - Bit b NonSecure Enable [b = 0 - 31]
42060 /*! BIT17 - Bit b NonSecure Enable [b = 0 - 31]
42070 /*! BIT18 - Bit b NonSecure Enable [b = 0 - 31]
42080 /*! BIT19 - Bit b NonSecure Enable [b = 0 - 31]
42090 /*! BIT20 - Bit b NonSecure Enable [b = 0 - 31]
42100 /*! BIT21 - Bit b NonSecure Enable [b = 0 - 31]
42110 /*! BIT22 - Bit b NonSecure Enable [b = 0 - 31]
42120 /*! BIT23 - Bit b NonSecure Enable [b = 0 - 31]
42130 /*! BIT24 - Bit b NonSecure Enable [b = 0 - 31]
42140 /*! BIT25 - Bit b NonSecure Enable [b = 0 - 31]
42150 /*! BIT26 - Bit b NonSecure Enable [b = 0 - 31]
42160 /*! BIT27 - Bit b NonSecure Enable [b = 0 - 31]
42170 /*! BIT28 - Bit b NonSecure Enable [b = 0 - 31]
42180 /*! BIT29 - Bit b NonSecure Enable [b = 0 - 31]
42190 /*! BIT30 - Bit b NonSecure Enable [b = 0 - 31]
42200 /*! BIT31 - Bit b NonSecure Enable [b = 0 - 31]
42215 /*! @name MRC_GLBCFG - MRC Global Configuration Register */
42220 /*! NRGNS - Number of regions [1-16] */
42227 /*! @name MRC_NSE_RGN_INDIRECT - MRC NonSecure Enable Region Indirect */
42232 /*! DID_SEL - DID Select */
42239 /*! @name MRC_NSE_RGN_SET - MRC NonSecure Enable Region Set */
42244 /*! W1SET - Write-1 Set */
42251 /*! @name MRC_NSE_RGN_CLR - MRC NonSecure Enable Region Clear */
42256 /*! W1CLR - Write-1 Clear */
42263 /*! @name MRC_NSE_RGN_CLR_ALL - MRC NonSecure Enable Region Clear All */
42268 /*! DID_SEL - DID Select */
42275 /*! @name MRC_GLBAC - MRC Global Access Control */
42280 /*! NUX - NonsecureUser Execute
42288 /*! NUW - NonsecureUser Write
42296 /*! NUR - NonsecureUser Read
42304 /*! NPX - NonsecurePriv Execute
42312 /*! NPW - NonsecurePriv Write
42320 /*! NPR - NonsecurePriv Read
42328 /*! SUX - SecureUser Execute
42336 /*! SUW - SecureUser Write
42344 /*! SUR - SecureUser Read
42352 /*! SPX - SecurePriv Execute
42360 /*! SPW - SecurePriv Write
42368 /*! SPR - SecurePriv Read
42376 /*! LK - LOCK
42378 * 0b1..This register is locked (read-only) and cannot be altered.
42389 /*! @name MRC_DOM0_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
42394 /*! MRACSEL - Memory Region Access Control Select
42408 /*! VLD - Valid */
42413 /*! NSE - NonSecure Enable
42423 /*! END_ADDR - End Address */
42428 /*! STRT_ADDR - Start Address */
42441 /*! @name MRC_DOM0_RGD_NSE - MRC Region Descriptor NonSecure Enable */
42446 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
42456 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
42466 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
42476 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
42486 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
42496 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
42506 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
42516 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
42528 /*! @name MRC_DOM1_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
42533 /*! MRACSEL - Memory Region Access Control Select
42547 /*! VLD - Valid */
42552 /*! NSE - NonSecure Enable
42562 /*! END_ADDR - End Address */
42567 /*! STRT_ADDR - Start Address */
42580 /*! @name MRC_DOM1_RGD_NSE - MRC Region Descriptor NonSecure Enable */
42585 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
42595 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
42605 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
42615 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
42625 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
42635 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
42645 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
42655 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
42667 /*! @name MRC_DOM2_RGD_W - MRC Region Descriptor Word 0..MRC Region Descriptor Word 1 */
42672 /*! MRACSEL - Memory Region Access Control Select
42686 /*! VLD - Valid */
42691 /*! NSE - NonSecure Enable
42701 /*! END_ADDR - End Address */
42706 /*! STRT_ADDR - Start Address */
42719 /*! @name MRC_DOM2_RGD_NSE - MRC Region Descriptor NonSecure Enable */
42724 /*! BIT0 - Bit n NonSecure Enable [n = 0 - 15]
42734 /*! BIT1 - Bit n NonSecure Enable [n = 0 - 15]
42744 /*! BIT2 - Bit n NonSecure Enable [n = 0 - 15]
42754 /*! BIT3 - Bit n NonSecure Enable [n = 0 - 15]
42764 /*! BIT4 - Bit n NonSecure Enable [n = 0 - 15]
42774 /*! BIT5 - Bit n NonSecure Enable [n = 0 - 15]
42784 /*! BIT6 - Bit n NonSecure Enable [n = 0 - 15]
42794 /*! BIT7 - Bit n NonSecure Enable [n = 0 - 15]
42812 /* TRDC - Peripheral instance base addresses */
42859 /* ----------------------------------------------------------------------------
42860 -- TRGMUX Peripheral Access Layer
42861 ---------------------------------------------------------------------------- */
42868 /** TRGMUX - Register Layout Typedef */
42873 /* ----------------------------------------------------------------------------
42874 -- TRGMUX Register Masks
42875 ---------------------------------------------------------------------------- */
42882 /*! @name TRGCFG - TRGMUX TRGMUX_OUT0 Register..TRGMUX CMP_GP1 Register */
42887 /*! SEL0 - Trigger MUX Source Select 1 */
42892 /*! SEL1 - Trigger MUX Source Select 1 */
42897 /*! SEL2 - Trigger MUX Source Select 2 */
42902 /*! SEL3 - Trigger MUX Source Select 3 */
42907 /*! LK - TRGMUX register lock.
42923 /* TRGMUX - Peripheral instance base addresses */
42957 /* ----------------------------------------------------------------------------
42958 -- TSTMR Peripheral Access Layer
42959 ---------------------------------------------------------------------------- */
42966 /** TSTMR - Register Layout Typedef */
42972 /* ----------------------------------------------------------------------------
42973 -- TSTMR Register Masks
42974 ---------------------------------------------------------------------------- */
42981 /*! @name L - Time Stamp Timer Register Low */
42986 /*! VALUE - Time Stamp Timer Low */
42990 /*! @name H - Time Stamp Timer Register High */
42995 /*! VALUE - Time Stamp Timer High */
43005 /* TSTMR - Peripheral instance base addresses */
43042 /* ----------------------------------------------------------------------------
43043 -- TX_PACKET_RAM Peripheral Access Layer
43044 ---------------------------------------------------------------------------- */
43051 /** TX_PACKET_RAM - Register Layout Typedef */
43056 /* ----------------------------------------------------------------------------
43057 -- TX_PACKET_RAM Register Masks
43058 ---------------------------------------------------------------------------- */
43065 /*! @name PACKET_RAM - Shared Packet RAM for multiple Link Layer usage. */
43070 /*! RAM - One entry in the packet RAM */
43083 /* TX_PACKET_RAM - Peripheral instance base addresses */
43117 /* ----------------------------------------------------------------------------
43118 -- VBAT Peripheral Access Layer
43119 ---------------------------------------------------------------------------- */
43126 /** VBAT - Register Layout Typedef */
43155 /* ----------------------------------------------------------------------------
43156 -- VBAT Register Masks
43157 ---------------------------------------------------------------------------- */
43164 /*! @name VERID - Version ID */
43169 /*! FEATURE - Feature Specification Number */
43174 /*! MINOR - Minor Version Number */
43179 /*! MAJOR - Major Version Number */
43183 /*! @name STATUSA - Status A */
43188 /*! POR_DET - POR Detect
43196 /*! WAKEUP_FLAG - Wakeup Pin Flag
43204 /*! TIMER0_FLAG - Bandgap Timer 0
43212 /*! TIMER1_FLAG - Bandgap Timer 1
43220 /*! LDO_RDY - LDO Ready
43227 /*! @name IRQENA - Interrupt Enable A */
43232 /*! POR_DET - POR Detect
43240 /*! WAKEUP_FLAG - Wakeup Pin Flag
43248 /*! TIMER0_FLAG - Bandgap Timer 0
43256 /*! TIMER1_FLAG - Bandgap Timer 2
43264 /*! LDO_RDY - LDO Ready
43271 /*! @name WAKENA - Wakeup Enable A */
43276 /*! POR_DET - POR Detect
43284 /*! WAKEUP_FLAG - Wakeup Pin Flag
43292 /*! TIMER0_FLAG - Bandgap Timer 0
43300 /*! TIMER1_FLAG - Bandgap Timer 2
43308 /*! LDO_RDY - LDO Ready
43315 /*! @name LOCKA - Lock A */
43320 /*! LOCK - Lock
43327 /*! @name FROCTLA - FRO16K Control A */
43332 /*! FRO_EN - FRO16K enable bit
43339 /*! @name FROLCKA - FRO16K Lock A */
43344 /*! LOCK - Lock
43351 /*! @name FROCLKE - FRO16K Clock Enable */
43356 /*! CLKE - Clock Enable */
43360 /*! @name LDOCTLA - LDO_RAM Control A */
43365 /*! BG_EN - Bandgap Enable
43373 /*! LDO_EN - LDO Enable
43381 /*! REFRESH_EN - Refresh Enable
43388 /*! @name LDOLCKA - LDO_RAM Lock A */
43393 /*! LOCK - Lock
43400 /*! @name LDORAMC - RAM Control */
43405 /*! ISO - Isolate SRAM
43413 /*! SWI - Switch SRAM
43421 /*! RET - Retention
43428 /*! @name LDOTIMER0 - Bandgap Timer 0 */
43433 /*! TIMCFG - Timeout Configuration
43447 /*! TIMEN - Timeout Enable
43454 /*! @name LDOTIMER1 - Bandgap Timer 1 */
43459 /*! TIMCFG - Timeout Configuration */
43464 /*! TIMEN - Timeout Enable
43477 /* VBAT - Peripheral instance base addresses */
43511 /* ----------------------------------------------------------------------------
43512 -- VREF Peripheral Access Layer
43513 ---------------------------------------------------------------------------- */
43520 /** VREF - Register Layout Typedef */
43529 /* ----------------------------------------------------------------------------
43530 -- VREF Register Masks
43531 ---------------------------------------------------------------------------- */
43538 /*! @name VERID - Version ID */
43543 /*! FEATURE - Feature Specification Number */
43548 /*! MINOR - Minor Version Number */
43553 /*! MAJOR - Major Version Number */
43557 /*! @name CSR - Control and Status */
43562 /*! HCBGEN - HC Bandgap Enabled
43570 /*! LPBGEN - Low-Power Bandgap Enable
43578 /*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable
43586 /*! CHOPEN - Chop Oscillator Enable
43594 /*! ICOMPEN - Current Compensation Enable
43602 /*! REGEN - Regulator Enable
43610 /*! REFCHSELN_EN - Reference Channel Select Negative Enable
43618 /*! REFCHSELP_EN - Reference Channel Select Positive Enable
43626 /*! VRSEL - Voltage Reference Selection
43628 * 0b01..Low-power buffered 1v
43635 /*! REFL_GRD_SEL - Ground Select
43643 /*! HI_PWR_LV - High-Power Level
43644 * 0b0..Low-power
43645 * 0b1..High-power
43651 /*! BUF21EN - Internal Buffer21 Enable
43659 /*! VREFST - Internal HC Voltage Reference Stable
43666 /*! @name UTRIM - User Trim */
43671 /*! TRIM2V1 - VREF 2.1V Trim */
43676 /*! VREFTRIM - VREF Trim */
43686 /* VREF - Peripheral instance base addresses */
43720 /* ----------------------------------------------------------------------------
43721 -- WDOG Peripheral Access Layer
43722 ---------------------------------------------------------------------------- */
43729 /** WDOG - Register Layout Typedef */
43737 /* ----------------------------------------------------------------------------
43738 -- WDOG Register Masks
43739 ---------------------------------------------------------------------------- */
43746 /*! @name CS - Control and Status Register */
43751 /*! STOP - Stop Enable
43759 /*! WAIT - Wait Enable
43767 /*! DBG - Debug Enable
43775 /*! TST - Watchdog Test
43786 /*! UPDATE - Allow updates
43794 /*! INT - Watchdog Interrupt
43802 /*! EN - Watchdog Enable
43810 /*! CLK - Watchdog Clock */
43815 /*! RCS - Reconfiguration Success
43823 /*! ULK - Unlock status
43831 /*! PRES - Watchdog prescaler
43839 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unloc…
43840 …* 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is su…
43841 …* 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supp…
43847 /*! FLG - Watchdog Interrupt Flag
43855 /*! WIN - Watchdog Window
43862 /*! @name CNT - Counter Register */
43867 /*! CNTLOW - Low byte of the Watchdog Counter */
43872 /*! CNTHIGH - High byte of the Watchdog Counter */
43876 /*! @name TOVAL - Timeout Value Register */
43881 /*! TOVALLOW - Low byte of the timeout value */
43886 /*! TOVALHIGH - High byte of the timeout value */
43890 /*! @name WIN - Window Register */
43895 /*! WINLOW - Low byte of Watchdog Window */
43900 /*! WINHIGH - High byte of Watchdog Window */
43910 /* WDOG - Peripheral instance base addresses */
43960 /* ----------------------------------------------------------------------------
43961 -- WOR Peripheral Access Layer
43962 ---------------------------------------------------------------------------- */
43969 /** WOR - Register Layout Typedef */
43971 …__IO uint32_t CTRL; /**< WAKE-ON-RADIO CONTROL REGISTER, offset: 0x0 …
43972 …__IO uint32_t TIMEOUT; /**< WAKE-ON-RADIO TIMEOUT REGISTER, offset: 0x4 …
43973 __I uint32_t TIMESTAMP1; /**< WAKE-ON-RADIO TIMESTAMP 1, offset: 0x8 */
43974 __I uint32_t TIMESTAMP2; /**< WAKE-ON-RADIO TIMESTAMP 2, offset: 0xC */
43975 __I uint32_t TIMESTAMP3; /**< WAKE-ON-RADIO TIMESTAMP 3, offset: 0x10 */
43976 …__IO uint32_t STATUS; /**< WAKE-ON-RADIO STATUS REGISTER, offset: 0x14 …
43977 …__IO uint32_t WW_CTRL; /**< WINDOW-WIDENING CONTROL REGISTER, offset: 0x…
43999 /* ----------------------------------------------------------------------------
44000 -- WOR Register Masks
44001 ---------------------------------------------------------------------------- */
44008 /*! @name CTRL - WAKE-ON-RADIO CONTROL REGISTER */
44013 /*! WOR_EN - WAKE-ON-RADIO Enable */
44018 /*! SCHEDULING_MODE - WAKE-ON-RADIO Scheduling Mode */
44023 /*! WOR_PROTOCOL - WAKE-ON-RADIO Protocol Selector */
44028 /*! SLOTS_USED - WAKE-ON-RADIO Number Of Slots Used */
44033 /*! SKIP_FIRST_DSM - WAKE-ON-RADIO Skip DSM On First Slot */
44038 /*! MAN_DSM_SEL - Manual DSM Selector */
44043 /*! RX_SLOT_FAIL_THRESH - RX Slot Fail Thresh */
44048 /*! DSM_GUARDBAND - WAKE-ON-RADIO DSM Guardband */
44053 /*! WOR_RESUME - WAKE-ON-RADIO Resume */
44058 /*! WOR_DEBUG_REG - WAKE-ON-RADIO Debug Register Enable */
44063 /*! AUTO_CAL - Auto calculate and track the drift enable */
44068 /*! SW_CAL - Enable the WOR SW to calculate the drift. Only when AUTO_CAL is set. */
44073 /*! TIME_REC - Enable the WOR HW to record the timing information to the Packet RAM. */
44078 /*! WOR_RX_FAIL_IRQ_EN - WOR_RX_FAIL_IRQ Enable */
44082 /*! @name TIMEOUT - WAKE-ON-RADIO TIMEOUT REGISTER */
44087 /*! RECEIVE_TIMEOUT - WAKE-ON-RADIO Receive Timeout */
44092 /*! WAKE_ON_NTH_SLOT - WAKE-ON-RADIO Force Wake On Nth Slot */
44097 /*! WOR_SLOT_COUNT - WAKE-ON-RADIO Absolute Slot Count */
44101 /*! @name TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP 1 */
44106 /*! TIMESTAMP1 - WAKE-ON-RADIO TIMESTAMP1 */
44110 /*! @name TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP 2 */
44115 /*! TIMESTAMP2 - WAKE-ON-RADIO TIMESTAMP2 */
44119 /*! @name TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP 3 */
44124 /*! TIMESTAMP3 - WAKE-ON-RADIO TIMESTAMP3 */
44128 /*! @name STATUS - WAKE-ON-RADIO STATUS REGISTER */
44133 /*! TIMESTAMP0_STS - WAKE-ON-RADIO Timestamp 0 Status */
44138 /*! TIMESTAMP1_STS - WAKE-ON-RADIO Timestamp 1 Status */
44143 /*! TIMESTAMP2_STS - WAKE-ON-RADIO Timestamp 2 Status */
44148 /*! TIMESTAMP3_STS - WAKE-ON-RADIO Timestamp 3 Status */
44153 /*! SLOT - WAKE-ON-RADIO Current Slot */
44158 /*! WOR_NO_RF_FLAG - WAKE-ON-RADIO NO_RF Slot Flag */
44163 /*! WOR_MAX_SLOT_FLAG - WAKE-ON-RADIO Maximum Slot Count Reached Flag */
44168 /*! WOR_DSM_EXIT_FLAG - WAKE-ON-RADIO Early DSM Exit Flag */
44173 /*! WOR_STATE - WAKE-ON-RADIO Current State */
44178 /*! WOR_RX_FAIL_IRQ - WOR RX Fail Interrupt Flag */
44182 /*! @name WW_CTRL - WINDOW-WIDENING CONTROL REGISTER */
44187 /*! WW_EN - Window-widening Enable */
44192 /*! WW_RESET_ON_RX - Window-widening Reset on Received Good Packet */
44197 /*! WW_NULL - Window-widening Null Command */
44202 /*! WW_ADD - Window-widening Add Command */
44207 /*! WW_DSM_FACTOR - Window-widening DSM Factor */
44212 /*! WW_RUN_FACTOR - Window-widening Runtime Factor */
44217 /*! WW_INCREASE - Window-widening Manual Increase Amount */
44221 /*! @name HOP_CTRL - FREQUENCY HOP CONTROL REGISTER */
44226 /*! HOP_TBL_CFG - Hop Table Configuration */
44231 /*! NEW_HOP_IDX - New Hop Table Index */
44236 /*! UPDATE_HOP_IDX - Update Hop Table Index */
44241 /*! HOP_SEQ_LENGTH - New Hop Table Index */
44245 /*! @name SLOT0_DESC0 - SLOT 0 DESCRIPTOR (LSB) */
44250 /*! SLOT0_DESC0 - Slot 0 Descriptor (LSB's) */
44254 /*! @name SLOT0_DESC1 - SLOT 0 DESCRIPTOR (MSB) */
44259 /*! SLOT0_DESC1 - Slot 0 Descriptor (MSB's) */
44264 /*! WOR_HOP_IDX - Current Hop Table Index */
44269 /*! WOR_HOP_FREQ_WORD - Current Hop Frequency Word */
44273 /*! @name SLOT1_DESC0 - SLOT 1 DESCRIPTOR (LSB) */
44278 /*! SLOT1_DESC0 - Slot 1 Descriptor (LSB's) */
44282 /*! @name SLOT1_DESC1 - SLOT 1 DESCRIPTOR (MSB) */
44287 /*! SLOT1_DESC1 - Slot 1 Descriptor (MSB's) */
44291 /*! @name SLOT2_DESC0 - SLOT 2 DESCRIPTOR (LSB) */
44296 /*! SLOT2_DESC0 - Slot 2 Descriptor (LSB's) */
44300 /*! @name SLOT2_DESC1 - SLOT 2 DESCRIPTOR (MSB) */
44305 /*! SLOT2_DESC1 - Slot 2 Descriptor (MSB's) */
44309 /*! @name SLOT3_DESC0 - SLOT 3 DESCRIPTOR (LSB) */
44314 /*! SLOT3_DESC0 - Slot 3 Descriptor (LSB's) */
44318 /*! @name SLOT3_DESC1 - SLOT 3 DESCRIPTOR (MSB) */
44323 /*! SLOT3_DESC1 - Slot 3 Descriptor (MSB's) */
44327 /*! @name AUTO_DRIFT1 - Auto Drift Calculation Register 1 */
44332 /*! SW_DRIFT_SET - Software calculated drift. */
44337 /*! CAL_DSM_FACTOR - Hardware calculated drift. */
44341 /*! @name AUTO_DRIFT2 - Auto Drift Calculation Register 2 */
44346 /*! AA_SFD_DLY - The time duration of Preamble and Sync Address plus the RX warm up duration. */
44350 /*! @name AUTO_DRIFT3 - Auto Drift Calculation Register 3 */
44355 /*! TIME_MGN - The time margin applied to the start time and timeout. */
44359 /*! @name AUTO_DRIFT4 - Auto Drift Calculation Register 4 */
44367 /*! @name TIME - Timer Count */
44375 /*! @name ENTER_TIME_CAPT - MAN Low Power Entry Time Captured */
44383 /*! @name WKUP_TIME_CAPT - MAN Low Power Wakeup Time Captured */
44391 /*! @name ENTER_TIME - MAN Low Power Entry Time Stamp */
44399 /*! @name WKUP_TIME - MAN Low Power Wakeup Time Stamp */
44413 /* WOR - Peripheral instance base addresses */
44447 /* ----------------------------------------------------------------------------
44448 -- WUU Peripheral Access Layer
44449 ---------------------------------------------------------------------------- */
44456 /** WUU - Register Layout Typedef */
44479 /* ----------------------------------------------------------------------------
44480 -- WUU Register Masks
44481 ---------------------------------------------------------------------------- */
44488 /*! @name VERID - Version ID */
44493 /*! FEATURE - Feature Specification Number
44502 /*! MINOR - Minor Version Number */
44507 /*! MAJOR - Major Version Number */
44511 /*! @name PARAM - Parameter */
44516 /*! FILTERS - Filter Number */
44521 /*! DMAS - DMA Number */
44526 /*! MODULES - Module Number */
44531 /*! PINS - Pin Number */
44535 /*! @name PE1 - Pin Enable 1 */
44540 /*! WUPE0 - Wakeup pin enable for WUU_Pn
44552 /*! WUPE1 - Reserved
44562 /*! WUPE2 - Wakeup pin enable for WUU_Pn
44574 /*! WUPE3 - Wakeup pin enable for WUU_Pn
44586 /*! WUPE4 - Wakeup pin enable for WUU_Pn
44598 /*! WUPE5 - Wakeup pin enable for WUU_Pn
44610 /*! WUPE6 - Reserved
44620 /*! WUPE7 - Wakeup pin enable for WUU_Pn
44632 /*! WUPE8 - Wakeup pin enable for WUU_Pn
44644 /*! WUPE9 - Wakeup pin enable for WUU_Pn
44656 /*! WUPE10 - Wakeup pin enable for WUU_Pn
44668 /*! WUPE11 - Wakeup pin enable for WUU_Pn
44680 /*! WUPE12 - Wakeup pin enable for WUU_Pn
44692 /*! WUPE13 - Wakeup pin enable for WUU_Pn
44704 /*! WUPE14 - Wakeup pin enable for WUU_Pn
44716 /*! WUPE15 - Wakeup pin enable for WUU_Pn
44727 /*! @name PE2 - Pin Enable 2 */
44732 /*! WUPE27 - Wakeup pin enable for WUU_Pn
44744 /*! WUPE28 - Wakeup pin enable for WUU_Pn
44755 /*! @name ME - Module Interrupt Enable */
44760 /*! WUME0 - Module iterrupt wakeup enable for module n
44768 /*! WUME1 - Module iterrupt wakeup enable for module n
44776 /*! WUME2 - Module iterrupt wakeup enable for module n
44784 /*! WUME3 - Module iterrupt wakeup enable for module n
44792 /*! WUME4 - Module iterrupt wakeup enable for module n
44800 /*! WUME5 - Module iterrupt wakeup enable for module n
44808 /*! WUME6 - Module iterrupt wakeup enable for module n
44816 /*! WUME7 - Module iterrupt wakeup enable for module n
44823 /*! @name DE - Module DMA/Trigger Enable */
44828 /*! WUDE0 - DMA/Trigger wakeup enable for module n
44836 /*! WUDE1 - DMA/Trigger wakeup enable for module n
44844 /*! WUDE2 - DMA/Trigger wakeup enable for module n
44852 /*! WUDE4 - DMA/Trigger wakeup enable for module n
44860 /*! WUDE5 - DMA/Trigger wakeup enable for module n
44868 /*! WUDE8 - DMA/Trigger wakeup enable for module n
44876 /*! WUDE9 - DMA/Trigger wakeup enable for module n
44883 /*! @name PF - Pin Flag */
44888 /*! WUF0 - Wakeup flag for WUU_Pn
44896 /*! WUF2 - Wakeup flag for WUU_Pn
44904 /*! WUF3 - Wakeup flag for WUU_Pn
44912 /*! WUF4 - Wakeup flag for WUU_Pn
44920 /*! WUF5 - Wakeup flag for WUU_Pn
44928 /*! WUF7 - Wakeup flag for WUU_Pn
44936 /*! WUF8 - Wakeup flag for WUU_Pn
44944 /*! WUF9 - Wakeup flag for WUU_Pn
44952 /*! WUF10 - Wakeup flag for WUU_Pn
44960 /*! WUF11 - Wakeup flag for WUU_Pn
44968 /*! WUF12 - Wakeup flag for WUU_Pn
44976 /*! WUF13 - Wakeup flag for WUU_Pn
44984 /*! WUF14 - Wakeup flag for WUU_Pn
44992 /*! WUF15 - Wakeup flag for WUU_Pn
45000 /*! WUF27 - Wakeup flag for WUU_Pn
45008 /*! WUF28 - Wakeup flag for WUU_Pn
45015 /*! @name FILT - Pin Filter */
45020 /*! FILTSEL1 - Filter 1 Pin Select */
45025 /*! FILTE1 - Filter 1 Enable
45037 /*! FILTF1 - Filter 1 Flag
45045 /*! FILTSEL2 - Filter 2 Pin Select */
45050 /*! FILTE2 - Filter 2 Enable
45062 /*! FILTF2 - Filter 2 Flag
45069 /*! @name PDC1 - Pin DMA/Trigger Configuration 1 */
45074 /*! WUPDC0 - Wakeup pin configuration for WUU_Pn
45084 /*! WUPDC1 - Reserved
45094 /*! WUPDC2 - Wakeup pin configuration for WUU_Pn
45104 /*! WUPDC3 - Wakeup pin configuration for WUU_Pn
45114 /*! WUPDC4 - Wakeup pin configuration for WUU_Pn
45124 /*! WUPDC5 - Wakeup pin configuration for WUU_Pn
45134 /*! WUPDC6 - Reserved
45144 /*! WUPDC7 - Wakeup pin configuration for WUU_Pn
45154 /*! WUPDC8 - Wakeup pin configuration for WUU_Pn
45164 /*! WUPDC9 - Wakeup pin configuration for WUU_Pn
45174 /*! WUPDC10 - Wakeup pin configuration for WUU_Pn
45184 /*! WUPDC11 - Wakeup pin configuration for WUU_Pn
45194 /*! WUPDC12 - Wakeup pin configuration for WUU_Pn
45204 /*! WUPDC13 - Wakeup pin configuration for WUU_Pn
45214 /*! WUPDC14 - Wakeup pin configuration for WUU_Pn
45224 /*! WUPDC15 - Wakeup pin configuration for WUU_Pn
45233 /*! @name PDC2 - Pin DMA/Trigger Configuration 2 */
45238 /*! WUPDC27 - Wakeup pin configuration for WUU_Pn
45248 /*! WUPDC28 - Wakeup pin configuration for WUU_Pn
45257 /*! @name FDC - Pin Filter DMA/Trigger Configuration */
45262 /*! FILTC1 - Filter configuration for FILTn
45272 /*! FILTC2 - Filter configuration for FILTn
45281 /*! @name PMC - Pin Mode Configuration */
45286 /*! WUPMC0 - Wakeup pin mode configuration for WUU_Pn
45287 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45296 /*! WUPMC2 - Wakeup pin mode configuration for WUU_Pn
45297 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45306 /*! WUPMC3 - Wakeup pin mode configuration for WUU_Pn
45307 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45316 /*! WUPMC4 - Wakeup pin mode configuration for WUU_Pn
45317 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45326 /*! WUPMC5 - Wakeup pin mode configuration for WUU_Pn
45327 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45336 /*! WUPMC7 - Wakeup pin mode configuration for WUU_Pn
45337 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45346 /*! WUPMC8 - Wakeup pin mode configuration for WUU_Pn
45347 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45356 /*! WUPMC9 - Wakeup pin mode configuration for WUU_Pn
45357 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45366 /*! WUPMC10 - Wakeup pin mode configuration for WUU_Pn
45367 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45376 /*! WUPMC11 - Wakeup pin mode configuration for WUU_Pn
45377 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45386 /*! WUPMC12 - Wakeup pin mode configuration for WUU_Pn
45387 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45396 /*! WUPMC13 - Wakeup pin mode configuration for WUU_Pn
45397 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45406 /*! WUPMC14 - Wakeup pin mode configuration for WUU_Pn
45407 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45416 /*! WUPMC15 - Wakeup pin mode configuration for WUU_Pn
45417 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45426 /*! WUPMC27 - Wakeup pin mode configuration for WUU_Pn
45427 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45436 /*! WUPMC28 - Wakeup pin mode configuration for WUU_Pn
45437 …* 0b0..Active only during a low-leakage mode. Software can modify the corresponding fields within…
45445 /*! @name FMC - Pin Filter Mode Configuration */
45450 /*! FILTM1 - Filter Mode for FILTn
45458 /*! FILTM2 - Filter Mode for FILTn
45471 /* WUU - Peripheral instance base addresses */
45507 /* ----------------------------------------------------------------------------
45508 -- XCVR_ANALOG Peripheral Access Layer
45509 ---------------------------------------------------------------------------- */
45516 /** XCVR_ANALOG - Register Layout Typedef */
45529 /* ----------------------------------------------------------------------------
45530 -- XCVR_ANALOG Register Masks
45531 ---------------------------------------------------------------------------- */
45538 /*! @name LDO_0 - RF Analog Baseband LDO Control 1 */
45543 /*! BG_FORCE - reg_bg_force_dig
45551 /*! LDO_LV_TRIM - reg_ldo_lv_trim_dig[1:0]
45561 /*! LDO_LV_BYPASS - reg_ldo_lv_bypass_dig
45569 /*! LDO_RXTXHF_FORCE - reg_ldo_rxtxhf_force_dig
45577 /*! LDO_RXTXHF_PTAT_BUMP - reg_ldo_rxtxhf_ptat_bump_dig
45587 /*! LDO_RXTXHF_BYPASS - reg_ldo_rxtxihf_bypass_dig */
45592 /*! LDO_RXTXLF_FORCE - reg_ldo_rxtxlf_force_dig
45600 /*! LDO_RXTXLF_PTAT_BUMP - reg_ldo_rxtxlf_ptat_bump_dig[1:0]
45610 /*! LDO_RXTXLF_BYPASS - reg_ldo_rxtxlf_bypass_dig
45618 /*! LDO_PLL_FORCE - reg_ldo_pll_force_dig
45626 /*! LDO_PLL_PTAT_BUMP - reg_ldo_pll_ptat_bump_dig[1:0]
45636 /*! LDO_PLL_BYPASS - reg_ldo_pll_bypass_dig
45644 /*! LDO_VCO_FORCE - reg_ldo_vco_force_dig
45652 /*! LDO_VCO_PTAT_BUMP - reg_ldo_vco_ptat_bump_dig[1:0]
45662 /*! LDO_VCO_BYPASS - reg_ldo_vco_bypass_dig
45670 /*! LDO_CAL_FORCE - reg_ldo_cal_force_dig
45678 /*! LDO_CAL_PTAT_BUMP - reg_ldo_vco_ptat_bump_dig[1:0]
45688 /*! LDO_CAL_BYPASS - reg_ldo_cal_bypass_dig
45696 /*! LDOTRIM_TRIM_VREF - reg_ldotrim_trim_vref_dig[1:0]
45705 /*! @name LDO_1 - RF Analog Baseband LDO Control 2 */
45710 /*! LDO_ANT_TRIM - reg_ldo_ant_trim_dig[3:0]
45732 /*! LDO_ANT_HIZ - reg_ldo_ant_hiz_dig
45733 * 0b0..high-impedance disabled.
45734 * 0b1..high-impedance enabled
45740 /*! LDO_ANT_BYPASS - reg_ldo_ant_bypass_dig
45748 /*! LDO_ANT_REF_SEL - reg_ldo_ant_ref_sel_dig
45755 /*! @name XO_DIST - RF Analog XO DIST Control */
45760 /*! XO_DIST_TRIM - reg_xo_dist_trim_dig[1:0]
45770 /*! XO_DIST_FLIP - reg_xo_dist_flip_dig
45778 /*! XO_DIST_BYPASS - reg_xo_dist_bypass
45785 /*! @name PLL - RF Analog PLL Control */
45790 /*! PLL_VCO_TRIM_KVT - reg_vco_trim_kvt_dig[2:0]
45800 /*! PLL_VCO_EN_PKDET - reg_vco_en_pkdet_dig
45808 /*! PLL_PD_EN_VPD_PULLDN - reg_pd_en_vpd_pulldn_dig
45816 /*! PLL_PD_EN_VPD_PULLUP - reg_pd_en_vpd_pullup_dig
45824 /*! PLL_PD_TRIM_FCAL_BIAS - reg_pd_trim_fcal_bias_dig[1:0]
45834 /*! PLL_FCAL_EN_STATIC_RES - reg_fcal_en_static_res_dig
45841 /*! @name RX_0 - RF Analog RX Control0 */
45846 /*! RX_LNA_ITRIM - reg_rx_lna_itrim_dig[1:0]
45847 * 0b00..3.7u -25%
45848 * 0b01..4.4u -15%
45856 /*! RX_LNA_PTAT_FORCE_START - reg_rtfe_ptat_force_dig */
45861 /*! RX_MIX_VBIAS - reg_rx_mix_vbias_dig[1:0]
45871 /*! ADC_TRIM - reg_adc_trim_dig[1:0]
45881 /*! ADC_INVERT_CLK - reg_adc_invert_clk_dig
45888 /*! @name RX_1 - RF Analog RX Control1 */
45893 /*! CBPF_TYPE - reg_cbpf_type_dig
45901 /*! CBPF_TRIM_I - reg_cbpf_trim_i_dig[1:0]
45911 /*! CBPF_TRIM_Q - reg_cbpf_trim_q_dig[1:0]
45921 /*! CBPF_VCM_TRIM - reg_cbpf_vcm_trim_dig[1:0]
45931 /*! CBPF_TRIM_SHORT_DCBIAS - reg_cbpf_trim_short_dcbias_dig[1:0]
45940 /*! @name TX_DAC_PA - RF Analog TX DAC PA Control */
45945 /*! DAC_INVERT_CLK - reg_dac_invert_clk_dig */
45950 /*! DAC_TRIM_RLOAD - reg_dac_trim_rload_dig[1:0]
45960 /*! DAC_TRIM_IBIAS - reg_dac_trim_ibias_dig[1:0]
45970 /*! TX_PA_VBIAS - reg_tx_pa_vbias_dig[1:0]
45980 /*! DAC_TRIM_CFBK - reg_dac_trim_cfbk_dig[1:0]
45990 /*! DAC_TRIM_CFBK_DRS - reg_dac_trim_cfbk_dig[1:0]
45999 /*! @name DIAG - RF Analog DIAG Control 1 */
46004 /*! DIAG_CODE - reg_diag_code_dig[2:0] */
46009 /*! LDO_CAL_DIAG_SEL - reg_ldo_cal_diag_sel_dig */
46014 /*! LDO_VCO_DIAG_SEL - reg_ldo_vco_diag_sel_dig */
46019 /*! LDO_PLL_DIAG_SEL - reg_ldo_pll_diag_sel_dig */
46024 /*! LDO_RXTXLF_DIAG_SEL - reg_ldo_rxtxlf_diag_sel_dig */
46029 /*! LDO_RXTXHF_DIAG_SEL - reg_ldo_rxtxhf_diag_sel_dig */
46034 /*! LDO_LV_DIAG_SEL - reg_ldo_lv_diag_sel_dig */
46039 /*! BG_DIAG_SEL - reg_bg_diag_sel_dig */
46044 /*! LDOTRIM_DIAG_SEL - reg_ldotrim_diag_sel_dig */
46049 /*! PROC_MON_DIAG_SEL - reg_proc_mon_diag_sel_dig */
46054 /*! RTFE_DIAG_SEL - reg_rtfe_diag_sel_dig */
46059 /*! CBPF_I_DIAG_SEL_1 - reg_cbpf_i_diag_sel_1_dig */
46064 /*! CBPF_I_DIAG_SEL_2 - reg_cbpf_i_diag_sel_2_dig */
46069 /*! CBPF_Q_DIAG_SEL_1 - reg_cbpf_q_diag_sel_1_dig */
46074 /*! CBPF_Q_DIAG_SEL_2 - reg_cbpf_q_diag_sel_2_dig */
46079 /*! CBPF_EN_DIAG_MEAS - reg_cbpf_en_diag_meas_dig */
46084 /*! ADC_DIAG_SEL - reg_adc_diag_sel_dig */
46089 /*! PD_DIAG_SEL - reg_pd_diag_sel_dig */
46094 /*! VCO_DIAG_SEL - reg_vco_diag_sel_dig */
46099 /*! DAC_DIAG_SEL - reg_dac_diag_sel_dig */
46104 /*! XO_DIST_DIAG_SEL - reg_xo_dist_diag_sel_dig */
46109 /*! LDO_ANT_DIAG_SEL - reg_ldo_ant_diag_sel_dig */
46114 /*! DAC_AMP_DIAG_SEL - reg_dac_amp_diag_sel_dig */
46119 /*! DIAG_DIS - reg_diag_dis_dig */
46124 /*! ATX_ON_2P4GHZ - reg_2p4ghz_atx_on_dig */
46128 /*! @name SPARE - RF Analog SPARE Control */
46133 /*! SPARELV - reg_sparelv_dig[1:0] */
46138 /*! SPARE_DIAG_SEL - reg_spare_diag_sel_dig[1:0] */
46148 /* XCVR_ANALOG - Peripheral instance base addresses */
46182 /* ----------------------------------------------------------------------------
46183 -- XCVR_MISC Peripheral Access Layer
46184 ---------------------------------------------------------------------------- */
46191 /** XCVR_MISC - Register Layout Typedef */
46234 /* ----------------------------------------------------------------------------
46235 -- XCVR_MISC Register Masks
46236 ---------------------------------------------------------------------------- */
46243 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
46248 /*! XCVR_SOFT_RESET - transciever soft reset control
46256 /*! LPPS_ENABLE - transciever lpps enable control
46264 /*! SDCLK_OUT_EN - sdclk out control
46272 /*! DEMOD_SEL - Demodulator Selector
46274 * 0b01..Use NXP Multi-standard PHY demodulator
46282 /*! DATA_RATE - Radio data rate setting
46293 /*! DATA_RATE_DRS - Radio data rate setting, Data Rate Switch
46304 /*! REF_CLK_FREQ - transciever ref clk freq control
46312 /*! FO_RX_EN - Fast Overwrite RX Enable */
46317 /*! FO_TX_EN - Fast Overwrite TX Enable */
46322 /*! TOF_RX_SEL - Time-of-Flight RX Select
46330 /*! TOF_TX_SEL - Time-of-Flight TX Select
46338 /*! LL_CFG_CAPT_DIS - Link Layer Configuration Capture Disable
46345 /*! @name XCVR_STATUS - TRANSCEIVER STATUS */
46350 /*! TSM_COUNT - TSM_COUNT */
46355 /*! TSM_IRQ0 - TSM Interrupt #0
46363 /*! TSM_IRQ1 - TSM Interrupt #1
46371 /*! TSM_BUSY - tsm busy status */
46376 /*! RX_MODE - Receive Mode */
46381 /*! TX_MODE - Transmit Mode */
46385 /*! @name FAD_CTRL - FAD CONTROL */
46390 /*! FAD_EN - Fast Antenna Diversity Enable
46398 /*! ANTX - Antenna Selection State */
46403 /*! ANTX_OVRD_EN - Antenna State Override Enable */
46408 /*! ANTX_OVRD - Antenna State Override Value */
46413 /*! ANTX_EN - FAD Antenna Controls Enable
46423 /*! ANTX_CTRLMODE - Antenna Diversity Control Mode */
46428 /*! ANTX_POL - FAD Antenna Controls Polarity */
46433 /*! FAD_NOT_GPIO - FAD versus GPIO Mode Selector */
46438 /*! FAD_LANT_SEL - FAD versus LANT_LUT_GPIO Selector
46445 /*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */
46450 /*! DMA_PAGE - Transceiver DMA Page Selector
46452 …* 0b0001..RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan …
46453 …* 0b0010..RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15…
46455 * 0b0011..ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word
46457 …* 0b0101..RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(…
46458 * 0b0110..MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE
46459 * 0b0111..GEN4-PHY
46466 /*! DMA_START_TRG - DMA Start Trigger Selector
46485 /*! DMA_START_EDGE - DMA Start Trigger Edge Selector
46493 /*! DMA_DEC - DMA Decimation Rate
46503 /*! DMA_START_DLY - DMA Start Trigger Delay */
46508 /*! DMA_EN - DMA Enable */
46513 /*! DMA_AA_TRIGGERED - DMA Access Address triggered */
46518 /*! DMA_START_TRIGGERED - DMA Start Trigger Occurred */
46523 /*! DMA_SIGNAL_VALID_MASK_EN - DMA Signal Valid Mask Enable
46530 /*! @name DBG_RAM_CTRL - DBG Ram control register */
46535 /*! DBG_PAGE - Packet RAM Debug Page Selector
46537 …* 0b001..RXDIG-IQ: Select from (mixer, decimator, pd channel filter, src, cfo-mixer, demod chan f…
46538 …* 0b010..RXDIG-IQ-ALT: Same as above + signals on unused LSBs : {antenna switch, GenLL or 802.15.…
46540 * 0b011..ADC-IQ: 11bit samples are MSB aligned in each 16bit half-word
46542 …* 0b101..RSSI-PHASE: select from 8bit Narrowband (rssi, rssi raw, lqi, snr, noise) and Wideband(r…
46543 * 0b110..MAG-PHASE: RSSI magnitude + 8bit high-resolution PHASE
46544 * 0b111..GEN4-PHY
46550 /*! DBG_SIGNAL_VALID_MASK_EN - DBG Signal Valid Mask Enable
46558 /*! DBG_START_TRG - DMA Start Trigger Selector
46577 /*! DBG_START_EDGE - DBG Start Trigger Edge Selector
46585 /*! DBG_STOP_EDGE - DBG Stop Trigger Edge Selector
46593 /*! DBG_DEC - DBG Decimation Rate
46603 /*! DBG_START_DLY - DBG Start Trigger Delay */
46608 /*! DBG_EN - DBG Enable */
46613 /*! DBG_AA_TRIGGERED - DBG Access Address triggered */
46618 /*! DBG_START_TRIGGERED - DBG Start Trigger Occurred */
46623 /*! DBG_STOP_TRIGGERED - DBG Stop Trigger Occurred */
46628 /*! DBG_RAM_FULL - DBG_RAM_FULL
46636 /*! DBG_STOP_TRG - Packet RAM Debug Stop Trigger Selector
46654 /*! @name DBG_RAM_ADDR - DBG RAM ADDRESS */
46659 /*! DBG_RAM_FIRST - DBG RAM First Address */
46664 /*! DBG_RAM_LAST - DBG RAM Last Address */
46668 /*! @name DBG_RAM_STOP_ADDR - DBG RAM STOP ADDRESS */
46673 /*! DBG_RAM_STOP - DBG RAM Stop Address */
46677 /*! @name LDO_TRIM_0 - LDO TRIM Configuration 0 */
46682 /*! LDO_PLL_TRIM_OFFSET - LDO PLL TRIM Offset */
46687 /*! LDO_VCO_TRIM_OFFSET - LDO VCO TRIM Offset */
46692 /*! LDO_RXTXLF_TRIM_OFFSET - LDO RXTXLF TRIM Offset */
46697 /*! LDO_RXTXHF_TRIM_OFFSET - LDO RXTXHF TRIM Offset */
46702 /*! LDO_TRIM_SMPL_DLY - LDO TRIM Sample Delay */
46707 /*! LDO_TRIM_CMPOUT_INV - LDO TRIM CMPOUT Invert */
46712 /*! LDO_CAL_TRIMSEL_OVRD - LDO_CAL_TRIMSEL Override Value */
46717 /*! LDO_PLL_TRIMSEL_OVRD - LDO_PLL_TRIMSEL Override Value */
46722 /*! LDO_VCO_TRIMSEL_OVRD - LDO_VCO_TRIMSEL Override Value */
46727 /*! LDO_RXTXHF_TRIMSEL_OVRD - LDO_RXTXHF_TRIMSEL Override Value */
46732 /*! LDO_TRIM_SAMPLE_OVRD - LDO_TRIM_SAMPLE Override Value */
46737 /*! LDO_SAMPLE_TRIMSEL_OVRD_EN - LDO SAMPLE TRIMSEL Override Enable */
46741 /*! @name LDO_TRIM_1 - LDO TRIM Configuration 1 */
46746 /*! LDO_PLL_TRIM_OVRD - LDO PLL TRIM Override Value */
46751 /*! LDO_PLL_TRIM_OVRD_EN - LDO PLL TRIM Override Enable */
46756 /*! LDO_VCO_TRIM_OVRD - LDO VCO TRIM Override Value */
46761 /*! LDO_VCO_TRIM_OVRD_EN - VCO TRIM Override Enable */
46766 /*! LDO_RXTXLF_TRIM_OVRD - LDO RXTXLF TRIM Override Value */
46771 /*! LDO_RXTXLF_TRIM_OVRD_EN - LDO RXTXLF TRIM Override Enable */
46776 /*! LDO_RXTXHF_TRIM_OVRD - LDO RXTXHF TRIM Override Value */
46781 /*! LDO_RXTXHF_TRIM_OVRD_EN - LDO RXTXHF TRIM Override Enable */
46785 /*! @name LDO_TRIM_RES_0 - RF Analog LDO Trim Res Control 0 */
46790 /*! LDO_PLL_TRIM - LDO_PLL_TRIM Result */
46795 /*! LDO_VCO_TRIM - LDO_VCO_TRIM Result */
46800 /*! LDO_RXTXLF_TRIM - LDO_RXTXLF_TRIM Result */
46805 /*! LDO_RXTXHF_TRIM - LDO_RXTXHF_TRIM Result */
46809 /*! @name LDO_TRIM_RES_1 - RF Analog LDO Trim Res Control 1 */
46814 /*! LDO_CAL_TRIM - LDO_CAL_TRIM Result */
46819 /*! LDO_TRIM_CMPOUT - LDO TRIM CMPOUT */
46823 /*! @name LCL_CFG0 - LCL CTRL CFG 0 */
46828 /*! LCL_EN - Localization Control Module Enable */
46833 /*! TX_LCL_EN - Enable Switching in TX */
46838 /*! RX_LCL_EN - Enable Switching in RX */
46843 /*! LANT_INV - Invert Antenna Switch Output */
46848 /*! COMP_EN - Pattern Matching Enable */
46853 /*! COMP_TX_EN - Pattern Matching Enable in TX */
46858 /*! SW_TRIG - Software Trigger. Can be used with either RX or TX */
46863 /*! LANT_SW_WIGGLE - LANT_SW Wiggle */
46868 /*! PM_NUM_BYTES - Number of Bytes to Match
46878 /*! LANT_BLOCK_TX - Block LANT_SW for TX */
46883 /*! LANT_BLOCK_RX - Block LANT_SW for RX */
46888 /*! CTE_DUR - Total Switching Duration */
46893 /*! LCL_GPIO_SEL - Localization GPIO Select */
46898 /*! LCL_MODE - Localization Mode
46905 /*! @name LCL_CFG1 - LCL CTRL CFG 1 */
46910 /*! M_ON_DELAY - M on Delay */
46915 /*! N_ON_DELAY - N on Delay */
46920 /*! LANT_SW_IE - Localization Antenna Switch Interrupt Enable
46928 /*! LANT_SW_FLAG - Localization Antenna Switch Flag */
46932 /*! @name LCL_TX_CFG0 - LCL CTRL TX CONFIG0 */
46937 /*! TX_DELAY - Interval delay before TX switching begins. */
46942 /*! TX_DELAY_OFF - Fine sample delay after TX_DELAY. */
46946 /*! @name LCL_TX_CFG1 - LCL CTRL TX CONFIG1 */
46951 /*! TX_SPINT - Number of TX Samples that define the length of an Interval, where 0=1sample, 1=2samp…
46956 /*! TX_ANT_TRIG_SEL - Selects Trigger for TX
46969 /*! TX_LO_PER - Primary Number of intervals for antenna LOW */
46974 /*! TX_HI_PER - Primary Number of intervals for antenna HIGH */
46979 /*! TX_LO_PER_1 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
46984 /*! TX_HI_PER_1 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
46988 /*! @name LCL_TX_CFG2 - LCL CTRL TX CONFIG2 */
46993 /*! TX_LO_PER_2 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
46998 /*! TX_HI_PER_2 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
47003 /*! TX_LO_PER_3 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
47008 /*! TX_HI_PER_3 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
47012 /*! @name LCL_RX_CFG0 - LCL CTRL RX CONFIG0 */
47017 /*! RX_DELAY - Interval delay before RX switching begins. */
47022 /*! RX_DELAY_OFF - Fine sample delay after RX_DELAY. */
47026 /*! @name LCL_RX_CFG1 - LCL CTRL RX CONFIG1 */
47031 /*! RX_SPINT - Number of RX Samples that define the length of an Interval, where 0=1sample, 1=2samp…
47036 /*! RX_ANT_TRIG_SEL - Selects Trigger for RX
47049 /*! RX_LO_PER - Primary Number of intervals for antenna LOW */
47054 /*! RX_HI_PER - Primary Number of intervals for antenna HIGH */
47059 /*! RX_LO_PER_1 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
47064 /*! RX_HI_PER_1 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
47068 /*! @name LCL_RX_CFG2 - LCL CTRL RX CONFIG2 */
47073 /*! RX_LO_PER_2 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
47078 /*! RX_HI_PER_2 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
47083 /*! RX_LO_PER_3 - Alternate Number of intervals for antenna LOW. Used only in conjunction with RSM.…
47088 /*! RX_HI_PER_3 - Alternate Number of intervals for antenna HIGH. Used only in conjunction with RSM…
47092 /*! @name LCL_PM_MSB - LCL CTRL PM MSB */
47097 /*! COMP_PATTERN_MSB - Upper bytes of pattern to be matched, bits 63:32 */
47101 /*! @name LCL_PM_LSB - LCL CTRL PM LSB */
47106 /*! COMP_PATTERN_LSB - Lower bytes of pattern to be matched, bits 31:0 */
47110 /*! @name LCL_GPIO_CTRL0 - LCL GPIO CTRL 0 */
47115 /*! LUT_0 - GPIO antenna state LUT entry */
47120 /*! LUT_1 - GPIO antenna state LUT entry */
47125 /*! LUT_2 - GPIO antenna state LUT entry */
47130 /*! LUT_3 - GPIO antenna state LUT entry */
47135 /*! LUT_4 - GPIO antenna state LUT entry */
47140 /*! LUT_5 - GPIO antenna state LUT entry */
47145 /*! LUT_6 - GPIO antenna state LUT entry */
47150 /*! LUT_7 - GPIO antenna state LUT entry */
47154 /*! @name LCL_GPIO_CTRL1 - LCL GPIO CTRL 1 */
47159 /*! LUT_8 - GPIO antenna state LUT entry */
47164 /*! LUT_9 - GPIO antenna state LUT entry */
47169 /*! LUT_10 - GPIO antenna state LUT entry */
47174 /*! LUT_11 - GPIO antenna state LUT entry */
47179 /*! LUT_12 - GPIO antenna state LUT entry */
47184 /*! LUT_13 - GPIO antenna state LUT entry */
47189 /*! LUT_14 - GPIO antenna state LUT entry */
47194 /*! LUT_15 - GPIO antenna state LUT entry */
47198 /*! @name LCL_GPIO_CTRL2 - LCL GPIO CTRL 2 */
47203 /*! LUT_16 - GPIO antenna state LUT entry */
47208 /*! LUT_17 - GPIO antenna state LUT entry */
47213 /*! LUT_18 - GPIO antenna state LUT entry */
47218 /*! LUT_19 - GPIO antenna state LUT entry */
47223 /*! LUT_20 - GPIO antenna state LUT entry */
47228 /*! LUT_21 - GPIO antenna state LUT entry */
47233 /*! LUT_22 - GPIO antenna state LUT entry */
47238 /*! LUT_23 - GPIO antenna state LUT entry */
47242 /*! @name LCL_GPIO_CTRL3 - LCL GPIO CTRL 3 */
47247 /*! LUT_24 - GPIO antenna state LUT entry */
47252 /*! LUT_25 - GPIO antenna state LUT entry */
47257 /*! LUT_26 - GPIO antenna state LUT entry */
47262 /*! LUT_27 - GPIO antenna state LUT entry */
47267 /*! LUT_28 - GPIO antenna state LUT entry */
47272 /*! LUT_29 - GPIO antenna state LUT entry */
47277 /*! LUT_30 - GPIO antenna state LUT entry */
47282 /*! LUT_31 - GPIO antenna state LUT entry */
47286 /*! @name LCL_GPIO_CTRL4 - LCL GPIO CTRL 4 */
47291 /*! LUT_WRAP_PTR - Wrap point for the LUT table in generating the 4 antenna GPIO wire states. */
47295 /*! @name LCL_DMA_MASK_DELAY - LCL_DMA_MASK_DELAY */
47300 /*! DMA_MASK_DELAY_OFF - DMA_MASK_DELAY_OFF */
47305 /*! DMA_MASK_DELAY - DMA_MASK_DELAY */
47309 /*! @name LCL_DMA_MASK_PERIOD - LCL_DMA_MASK_PERIOD */
47314 /*! DMA_MASK_REF_PER - DMA_MASK_REF_PER */
47318 /*! @name RSM_CSR - Ranging Sequence Manager Control and Status */
47323 /*! RSM_IRQ_IP1_EN - RSM_IRQ_IP1_EN */
47328 /*! RSM_IRQ_IP1 - RSM_IRQ_IP1 Flag */
47333 /*! RSM_IRQ_IP2_EN - RSM_IRQ_IP2_EN */
47338 /*! RSM_IRQ_IP2 - RSM_IRQ_IP2 Flag */
47343 /*! RSM_IRQ_FC_EN - RSM_IRQ_FC_EN */
47348 /*! RSM_IRQ_FC - RSM_IRQ_FC Flag */
47353 /*! RSM_IRQ_EOS_EN - RSM_IRQ_EOS_EN */
47358 /*! RSM_IRQ_EOS - RSM_IRQ_EOS Flag */
47363 /*! RSM_IRQ_ABORT_EN - RSM_IRQ_ABORT_EN */
47368 /*! RSM_IRQ_ABORT - RSM_IRQ_ABORT Flag */
47373 /*! RSM_STATE - RSM_STATE
47400 /*! RSM_STEP_FORMAT - RSM_STEP_FORMAT */
47405 /*! RSM_CURRENT_STEPS - RSM_CURRENT_STEPS */
47409 /*! @name RSM_CTRL0 - Ranging Sequence Manager Control */
47414 /*! RSM_MODE - RSM_MODE
47422 /*! RSM_RATE - RSM_RATE
47430 /*! RSM_RX_EN - RSM_RX_EN */
47435 /*! RSM_TX_EN - RSM_TX_EN */
47440 /*! RSM_FAST_IP_RX_WU - RSM_FAST_IP_RX_WU */
47445 /*! RSM_FAST_IP_TX_WU - RSM_FAST_IP_TX_WU */
47450 /*! RSM_FAST_FC_RX_WU - RSM_FAST_FC_RX_WU */
47455 /*! RSM_FAST_FC_TX_WU - RSM_FAST_FC_TX_WU */
47460 /*! RSM_SW_ABORT - RSM_SW_ABORT */
47465 /*! RSM_TRIG_SEL - RSM_TRIG_SEL
47472 * 0b110-0b111..Reserved
47478 /*! RSM_TRIG_DLY - RSM_TRIG_DLY */
47483 /*! RSM_STEPS - RSM_FREQUENCY_STEP */
47487 /*! @name RSM_CTRL1 - Ranging Sequence Manager Control */
47492 /*! RSM_T_FM0 - RSM_T_FM0 */
47497 /*! RSM_T_FM1 - RSM_T_FM1 */
47502 /*! RSM_T_FC - RSM_T_FC */
47507 /*! RSM_T_IP1 - RSM_T_IP1 */
47512 /*! RSM_T_IP2 - RSM_T_IP2 */
47517 /*! RSM_T_S - RSM_T_S */
47521 /*! @name RSM_CTRL2 - Ranging Sequence Manager Control */
47526 /*! RSM_T_PM0 - RSM_T_PM0 */
47531 /*! RSM_T_PM1 - RSM_T_PM1 */
47536 /*! RSM_T_PM2 - RSM_T_PM2 */
47541 /*! RSM_T_PM3 - RSM_T_PM3 */
47546 /*! RSM_ACTIVE_OVRD_LCL - RSM_ACTIVE_OVRD_LCL */
47551 /*! RSM_ACTIVE_OVRD_EN_LCL - RSM_ACTIVE_OVRD_EN_LCL
47559 /*! RSM_ACTIVE_OVRD_TXDIG - RSM_ACTIVE_OVRD_TXDIG */
47564 /*! RSM_ACTIVE_OVRD_EN_TXDIG - RSM_ACTIVE_OVRD_EN_TXDIG
47572 /*! RSM_ACTIVE_OVRD_RXDIG - RSM_ACTIVE_OVRD_RXDIG */
47577 /*! RSM_ACTIVE_OVRD_EN_RXDIG - RSM_ACTIVE_OVRD_EN_RXDIG
47584 /*! @name RSM_CTRL3 - Ranging Sequence Manager Control */
47589 /*! RSM_DT_RX_SYNC_DLY - RSM_DT_RX_SYNC_DLY */
47594 /*! RSM_DT_RX_SYNC_DIS - RSM_DT_RX_SYNC_DIS */
47599 /*! RSM_AA_HAMM - RSM_AA_HAMM */
47604 /*! RSM_HPM_CAL - RSM_HPM_CAL */
47609 /*! RSM_CTUNE - RSM_CTUNE */
47614 /*! RSM_DMA_RX_EN - RSM_DMA_RX_EN */
47619 /*! RSM_RX_PHY_EN_MASK_DIS - RSM_RX_PHY_EN_MASK_DIS */
47624 /*! RSM_RX_SIGNALS_MASK_DIS - RSM_RX_SIGNALS_MASK_DIS */
47629 /*! RSM_SEQ_RCCAL_PUP_MASK_DIS - RSM_SEQ_RCCAL_PUP_MASK_DIS */
47634 /*! RSM_DMA_DUR - DMA Duration */
47638 /*! @name RSM_CTRL4 - Ranging Sequence Manager Control */
47643 /*! RSM_DMA_DLY0 - DMA Delay 0 */
47648 /*! RSM_DMA_DLY - DMA Delay */
47653 /*! RSM_DMA_DUR0 - DMA Duration 0 */
47657 /*! @name RF_DFT_CTRL - RF DFT CTRL */
47662 /*! RADIO_DFT_MODE - Radio DFT mode control
47675 /*! @name IPS_FO_ADDR - IPS FAST OVERWRITE ADDRESS */
47680 /*! ADDR - IPS Address */
47685 /*! ENTRY_RX - Enable Entry for RX */
47690 /*! ENTRY_TX - Enable Entry for TX */
47697 /*! @name IPS_FO_DRS0_DATA - IPS FAST OVERWRITE DRS0 DATA */
47702 /*! DRS0_DATA - Fast Overwrite DRS0 data */
47709 /*! @name IPS_FO_DRS1_DATA - IPS FAST OVERWRITE DRS1 DATA */
47714 /*! DRS1_DATA - Fast Overwrite DRS1 data */
47727 /* XCVR_MISC - Peripheral instance base addresses */
47761 /* ----------------------------------------------------------------------------
47762 -- XCVR_PLL_DIG Peripheral Access Layer
47763 ---------------------------------------------------------------------------- */
47770 /** XCVR_PLL_DIG - Register Layout Typedef */
47806 /* ----------------------------------------------------------------------------
47807 -- XCVR_PLL_DIG Register Masks
47808 ---------------------------------------------------------------------------- */
47815 /*! @name HPM_BUMP - PLL HPM Analog Bump Control */
47820 /*! HPM_VCM_TX - a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Transmission
47834 /*! HPM_VCM_CAL - a_ip_2p4ghz_reg_dac_trim_vcm_dig[2:0] during Calibration
47848 /*! HPM_FDB_RES_TX - a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Transmission
47858 /*! HPM_FDB_RES_CAL - a_ip_2p4ghz_reg_dac_trim_rfbk_dig[1:0] during Calibration
47868 /*! PLL_VCO_TRIM_KVM_TX - reg_vco_trim_kvm_dig[2:0] for transmitt
47878 /*! PLL_VCO_TRIM_KVM_CAL - reg_vco_trim_kvm_dig[2:0] for calibration
47887 /*! @name MOD_CTRL - PLL Modulation Control */
47892 /*! MODULATION_WORD_MANUAL - Manual Modulation Word */
47897 /*! MOD_DISABLE - Disable Modulation Word */
47902 /*! HPM_MOD_MANUAL - Manual HPM Modulation */
47907 /*! HPM_MOD_DISABLE - Disable HPM Modulation */
47912 /*! HPM_SDM_OUT_MANUAL - Manual HPM SDM out */
47917 /*! HPM_SDM_OUT_DISABLE - Disable HPM SDM out */
47921 /*! @name CHAN_MAP - PLL Channel Mapping */
47926 /*! CHANNEL_NUM_OVRD - Channel Selection Override */
47931 /*! BAND_SELECT - Channel Mapping Band Select
47936 * 0b100..IEEE 802.15.4 O-QPSK PHY in ISM band
47937 * 0b101..IEEE 802.15.4 O-QPSK PHY in MBAN band
47938 * 0b110-0b111..Radio Channels 0-127 selectable
47944 /*! BMR - Bluetooth Low Energy MBAN Channel Remap
47952 /*! HOP_TBL_CFG_OVRD - Hop Table Configuration Override
47953 …* 0b000-0b001..CHANNEL_NUM_OVRD[6:0] is used as the mapped channel number. CHANNEL_NUM_OVRD[15:7]…
47961 /*! HOP_TBL_CFG_OVRD_EN - Hop Table Configuration Override Enable */
47965 /*! @name CHAN_MAP_EXT - PLL Channel Mapping Extended */
47970 /*! NUM_OFFSET - Numerator Offset */
47975 /*! CTUNE_TGT_OFFSET - Coarse Tune Target Frequency Offset */
47979 /*! @name LOCK_DETECT - PLL Lock Detect Control */
47984 /*! CT_FAIL - Real time status of Coarse Tune Fail signal */
47989 /*! CTFF - CTUNE Failure Flag, held until cleared */
47994 /*! FT_FAIL - Real time status of Frequency Target Failure */
47999 /*! FTFF - Frequency Target Failure Flag */
48004 /*! CTUNE_LDF_LEV - CTUNE Lock Detect Fail Level */
48009 /*! FTF_RX_THRSH - RX Frequency Target Fail Threshold */
48014 /*! FTF_TX_THRSH - TX Frequency Target Fail Threshold */
48019 /*! FCAL_HOLD_EN - Frequency Counter Hold Enable
48027 /*! FTW_TXRX - TX and RX Frequency Target Window time select
48041 /*! FREQ_COUNT_GO - Start the Frequency Meter */
48046 /*! FREQ_COUNT_FINISHED - Frequency Meter has finished the Count Time */
48051 /*! FREQ_COUNT_TIME - Frequency Meter Count Time
48060 /*! @name HPM_CTRL - PLL High Port Modulator Control */
48065 /*! HPM_SDM_IN_MANUAL - Manual High Port SDM Fractional value */
48070 /*! HPM_CLK_CONFIG - HPM Clock Config */
48075 /*! HPFF - HPM SDM Invalid Flag */
48080 /*! HPM_SDM_OUT_INVERT - Invert HPM SDM Output */
48085 /*! HPM_SDM_IN_DISABLE - Disable HPM SDM Input */
48090 /*! HPM_LFSR_SIZE - HPM LFSR Length
48104 /*! RX_HPM_CAL_EN - Receive HPM Calibration Enable */
48109 /*! HPM_DTH_SCL - HPM Dither Scale */
48114 /*! HPM_DTH_EN - Dither Enable for HPM LFSR */
48119 /*! HPM_SCALE - High Port Modulation Scale
48133 /*! HPM_INTEGER_INVERT - Invert High Port Modulation Integer */
48138 /*! HPM_CAL_INVERT - Invert High Port Modulator Calibration */
48143 /*! HPM_CAL_TIME - High Port Modulation Calibration Time
48153 /*! HPM_MOD_IN_INVERT - Invert High Port Modulation */
48157 /*! @name HPMCAL_CTRL - PLL High Port Calibration Control */
48162 /*! HPM_CAL_FACTOR - High Port Modulation Calibration Factor */
48167 /*! HPM_CAL_ARRAY_SIZE - High Port Modulation Calibration Array Size
48175 /*! HPM_CAL_COUNT_SCALE - HPM_CAL_COUNT_SCALE */
48180 /*! HP_CAL_DISABLE - Disable HPM Manual Calibration */
48185 /*! HPM_CAL_FACTOR_MANUAL - Manual HPM Calibration Factor */
48190 /*! HPM_CAL_SKIP - HPM_CAL_SKIP */
48195 /*! HPM_CAL_BUMPED - HPM_CAL_BUMPED
48204 /*! @name HPM_CAL1 - PLL High Port Calibration Result 1 */
48209 /*! HPM_COUNT_1 - High Port Modulation Counter Value 1 */
48213 /*! @name HPM_CAL2 - PLL High Port Calibration Result 2 */
48218 /*! HPM_COUNT_2 - High Port Modulation Counter Value 2 */
48222 /*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */
48227 /*! HPM_NUM_SELECTED - High Port Modulator SDM Numerator */
48232 /*! HPM_DENOM - High Port Modulator SDM Denominator */
48237 /*! HPM_COUNT_ADJUST - HPM_COUNT_ADJUST */
48241 /*! @name LPM_CTRL - PLL Low Port Modulator Control */
48246 /*! PLL_LD_MANUAL - Manual PLL Loop Divider value */
48251 /*! HPM_CAL_SCALE - High Port Calibration Word Scaling
48252 * 0b0000-0b0010..No Scaling
48262 * 0b1011-0b1111..No Scaling
48268 /*! PLL_LD_DISABLE - Disable PLL Loop Divider */
48273 /*! LPFF - LPM SDM Invalid Flag */
48278 /*! LPM_SDM_INV - Invert LPM SDM */
48283 /*! LPM_DISABLE - Disable LPM SDM */
48288 /*! LPM_DTH_SCL - LPM Dither Scale
48294 * 0b0101..-128 to 96
48295 * 0b0110..-256 to 192
48296 * 0b0111..-512 to 384
48297 * 0b1000..-1024 to 768
48298 * 0b1001..-2048 to 1536
48299 * 0b1010..-4096 to 3072
48300 * 0b1011..-8192 to 6144
48310 /*! LPM_D_CTRL - LPM Dither Control in Override Mode */
48315 /*! LPM_D_OVRD - LPM Dither Override Mode Select */
48320 /*! LPM_SCALE - LPM Scale Factor
48342 /*! LPM_SDM_USE_NEG - Use the Negedge of the Sigma Delta clock */
48346 /*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */
48351 /*! LPM_INTG_SELECTED - Low Port Modulation Integer Value Selected */
48356 /*! HPM_ARRAY_BIAS - Bias value for High Port DAC Array Midpoint */
48361 /*! LPM_INTG - Manual Low Port Modulation Integer Value */
48366 /*! SDM_MAP_DISABLE - Disable SDM Mapping */
48370 /*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */
48375 /*! LPM_NUM - Low Port Modulation Numerator */
48379 /*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */
48384 /*! LPM_DENOM - Low Port Modulation Denominator */
48388 /*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */
48393 /*! LPM_NUM_SELECTED - Low Port Modulation Numerator Applied */
48397 /*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */
48402 /*! LPM_DENOM_SELECTED - Low Port Modulation Denominator Selected */
48406 /*! @name DELAY_MATCH - PLL Delay Matching */
48411 /*! LPM_SDM_DELAY - Low Port SDM Delay Matching */
48416 /*! HPM_SDM_DELAY - High Port SDM Delay Matching */
48421 /*! HPM_INTEGER_DELAY - High Port Integer Delay Matching */
48425 /*! @name TUNING_CAP_TX_CTRL - Tuning Cap Settings in Transmit Mode */
48430 /*! TUNING_RANGE_0 - Tuning Range 0 */
48435 /*! TUNING_RANGE_1 - Tuning Range 1 */
48440 /*! TUNING_RANGE_2 - Tuning Range 2 */
48445 /*! TUNING_RANGE_3 - Tuning Range 3 */
48450 /*! TUNING_RANGE_4 - Tuning Range 4 */
48455 /*! TUNING_RANGE_5 - Tuning Range 5 */
48460 /*! TUNING_RANGE_6 - Tuning Range 6 */
48465 /*! TUNING_RANGE_7 - Tuning Range 7 */
48469 /*! @name TUNING_CAP_RX_CTRL - Tuning Cap Settings in Receive Mode */
48474 /*! TUNING_RANGE_0 - Tuning Range 0 */
48479 /*! TUNING_RANGE_1 - Tuning Range 1 */
48484 /*! TUNING_RANGE_2 - Tuning Range 2 */
48489 /*! TUNING_RANGE_3 - Tuning Range 3 */
48494 /*! TUNING_RANGE_4 - Tuning Range 4 */
48499 /*! TUNING_RANGE_5 - Tuning Range 5 */
48504 /*! TUNING_RANGE_6 - Tuning Range 6 */
48509 /*! TUNING_RANGE_7 - Tuning Range 7 */
48513 /*! @name MAX_TX_CFG1_FREQ - Max Transmit Frequency For TX Configuration 1 */
48518 /*! MAX_TX_CFG1_FREQ - Maximum Transmit Frequency for Standard TX Settings */
48522 /*! @name CTUNE_CTRL - PLL Coarse Tune Control */
48527 /*! CTUNE_TARGET_MANUAL - Manual Coarse Tune Target */
48532 /*! CTUNE_CNTR_RLS_RST - Coarse Tune Counter Release Reset */
48537 /*! CTUNE_TARGET_DISABLE - Disable Coarse Tune Target */
48542 /*! CTUNE_ADJUST - Coarse Tune Count Adjustment */
48547 /*! CTUNE_MANUAL - Manual Coarse Tune Setting */
48552 /*! CTUNE_DISABLE - Coarse Tune Disable */
48556 /*! @name DATA_RATE_OVRD_CTRL1 - PLL Data Rate Override Control */
48561 /*! HPM_CAL_SCALE_CFG1 - HPM Scale Configuration1 */
48566 /*! LPM_SCALE_CFG1 - LPM Scale Configuration1 */
48571 /*! HPM_FDB_RES_CAL_CFG1 - HPM FDB RES Calibration Configuration1 */
48576 /*! HPM_FDB_RES_TX_CFG1 - HPM FDB RES Transmit Configuration1 */
48580 /*! @name DATA_RATE_OVRD_CTRL2 - PLL Data Rate Override Control */
48585 /*! NUM_OFFSET_CFG1 - Numerator Offset Configuration1 */
48589 /*! @name CTUNE_RES - PLL Coarse Tune Results */
48594 /*! CTUNE_SELECTED - Coarse Tune Setting to VCO */
48599 /*! CTUNE_BEST_DIFF - Coarse Tune Absolute Best Difference */
48604 /*! CTUNE_FREQ_SELECTED - Coarse Tune Frequency Selected */
48608 /*! @name HPM_CAL_TIMING - PLL HPM Calibration Timing Attributes */
48613 /*! HPM_CTUNE_SETTLE_TIME - CTUNE Settling Time */
48618 /*! HPM_CAL1_SETTLE_TIME - HPM Calibration1 Settling Time */
48623 /*! HPM_CAL2_SETTLE_TIME - HPM Calibration2 Settling Time */
48628 /*! HPM_VCO_MOD_DELAY - HPM VCO Modification Output Delay */
48632 /*! @name PLL_OFFSET_CTRL - PLL Offset Control */
48637 /*! PLL_NUMERATOR_OFFSET - PLL Numerator Offset */
48641 /*! @name PLL_DATARATE_CTRL - PLL Data Rate Switch Control */
48646 /*! HPM_VCM_TX_DRS - Data Rate Switch for hpm_vcm_tx
48660 /*! HPM_VCM_CAL_DRS - Data Rate Switch for hpm_vcm_cal
48674 /*! PLL_VCO_TRIM_KVM_TX_DRS - Data Rate Switch for pll_vco_trim_kvm_tx.
48684 /*! PLL_VCO_TRIM_KVM_CAL_DRS - Data Rate Switch for pll_vco_trim_kvm_cal
48694 /*! LPM_SDM_DELAY_DRS - DRS LPM_SDM_DELAY */
48699 /*! HPM_SDM_DELAY_DRS - DRS HPM_SDM_DELAY */
48704 /*! HPM_INTEGER_DELAY_DRS - DRS HPM_SDM_DELAY */
48714 /* XCVR_PLL_DIG - Peripheral instance base addresses */
48748 /* ----------------------------------------------------------------------------
48749 -- XCVR_RX_DIG Peripheral Access Layer
48750 ---------------------------------------------------------------------------- */
48757 /** XCVR_RX_DIG - Register Layout Typedef */
48786 __IO uint32_t WB_RSSI_CTRL; /**< Wide-Band RSSI Control, offset: 0x6C */
48787 __IO uint32_t WB_RSSI_RES0; /**< Wide-Band RSSI Result 0, offset: 0x70 */
48788 __I uint32_t WB_RSSI_RES1; /**< Wide-Band RSSI Result 1, offset: 0x74 */
48789 __I uint32_t WB_RSSI_DFT; /**< Wide-Band RSSI DFT Result, offset: 0x78 */
48790 __IO uint32_t NB_RSSI_CTRL0; /**< Narrow-Band RSSI Control 0, offset: 0x7C */
48791 __IO uint32_t NB_RSSI_CTRL1; /**< Narrow-Band RSSI Control 1, offset: 0x80 */
48792 __IO uint32_t NB_RSSI_RES0; /**< Narrow-Band RSSI Result 0, offset: 0x84 */
48793 __I uint32_t NB_RSSI_RES1; /**< Narrow-Band RSSI Result 1, offset: 0x88 */
48794 __I uint32_t NB_RSSI_DFT; /**< Narrow-Band RSSI DFT Result, offset: 0x8C */
48855 /* ----------------------------------------------------------------------------
48856 -- XCVR_RX_DIG Register Masks
48857 ---------------------------------------------------------------------------- */
48864 /*! @name CTRL0 - RXDIG Control 0 */
48869 /*! ADC_CLIP_EN - ADC Output Clip Enable
48877 /*! RX_IQMC_EN - IQ Mismatch Compensation Enable
48885 /*! DIG_MIXER_FREQ - Digital Mixer Frequency */
48890 /*! CIC_ORDER - CIC Order(Stage) Selection
48891 * 0b0..4-stage CIC
48892 * 0b1..3-stage CIC
48898 /*! CIC_RATE - CIC Decimation Rate
48912 /*! RX_DIG_GAIN - RX Digital Gain Value
48926 /*! RX_ACQ_FILT_LEN - Acquisition Filter Length
48934 /*! RX_ACQ_FILT_BYPASS - Acquisition Filter Bypass
48942 /*! RX_SRC_EN - RX Sample Rate Converter Enable
48950 /*! RX_IQ_8B_OUT_MODE - RX 8-bit IQ Output Mode
48951 * 0b000..Disable 8-bit IQ output
48969 /*! CIC_CNTR_FREE_RUN_EN - CIC Dec Counter Free Run Enable */
48974 /*! RX_AGC_EN - AGC Enable
48982 /*! DR_OVRD_IN_CTE - DATARATE_CONFIG_SEL Override In CTE */
48986 /*! @name CTRL0_DRS - RXDIG Control 0 DRS */
48991 /*! DIG_MIXER_FREQ - Digital Mixer Frequency */
48996 /*! CIC_ORDER - CIC Order(Stage) Selection
48997 * 0b0..4-stage CIC
48998 * 0b1..3-stage CIC
49004 /*! CIC_RATE - CIC Decimation Rate
49017 /*! @name CTRL1 - RXDIG Control 1 */
49022 /*! RX_SAMPLE_BUF_BYPASS - Bypass Sample Buffer */
49027 /*! RX_SAMPLE_BUF_BYPASS_IN_CTE - Bypass Sample Buffer During CTE */
49032 /*! RX_SAMPLE_BUF_AUTO_GATE - Sample Buffer Automatically Gate Off */
49037 /*! DC_RESID_EN - DC_RESID Enable */
49042 /*! DIS_WB_NORM_AA_FOUND - Disable WB-NORM when AA found */
49047 /*! RX_NB_NORM_EN - Narrow-Band Normalizer Enable
49048 * 0b0..Narrow-Band normalizer is disabled.
49049 * 0b1..Narrow-Band normalizer is enabled.
49055 /*! RX_HIGH_RES_NORM_SEL - High Resolution Phase Source Select
49063 /*! RX_DEMOD_FILT_BYPASS - Demod Channel Filter Bypass
49071 /*! RX_FRAC_CORR_OVRD - Fractional Correction Coefficient Override Value */
49076 /*! RX_FRAC_CORR_OVRD_EN - Fractional Correction Coefficient Override Enable */
49081 /*! RX_CFO_EST_OVRD - CFO Estimation Override Value */
49086 /*! RX_CFO_EST_OVRD_EN - CFO Estimation Override Enable
49094 /*! RX_MIXER_IDX_OUT_MODE - RX_DIG Mixer Index Output Mode */
49099 /*! RX_IQ_PH_AVG_WIN - RX IQ Phase Output Average Window Config
49113 /*! RX_IQ_PH_OUTPUT_COND - RX IQ or Phase Output Conditioning
49114 * 0b0..Output IQ and/or Phase all-time
49120 /*! @name DFT_CTRL - RXDIG DFT Control */
49125 /*! DFT_RX_PH_OUT_SEL - DFT RXDIG Phase Output Selection
49127 * 0b01..Sel wide-band phase output
49128 * 0b10..Sel narrow-band phase output
49135 /*! DFT_RX_IQ_OUT_SEL - DFT I/Q Output Selection
49149 /*! DFT_RSSI_MAG_OUT_SEL - DFT RSSI Magnitude Output Selection
49151 * 0b001..WB-RSSI fast magnitude
49152 * 0b010..WB-RSSI slow magnitude
49153 * 0b011..NB-RSSI mag IIR
49154 * 0b100..NB-RSSI mag avg
49155 * 0b101..NB-RSSI noise mag IIR
49156 * 0b110..NB-RSSI noise mag avg
49163 /*! DFT_RSSI_OUT_SEL - DFT RSSI Result Output Selection
49165 * 0b001..Wide-band RSSI_RAW output
49166 * 0b010..Wide-band RSSI output
49167 * 0b011..Narrow-band RSSI_RAW output
49168 * 0b100..Narrow-band RSSI output
49169 * 0b101..Narrow-band NOISE_RAW output
49170 * 0b110..Narrow-band SNR output
49171 * 0b111..Narrow-band LQI output
49177 /*! CGM_OVRD - CGM Override
49194 /*! @name RCCAL_CTRL0 - RCCAL Control 0 */
49199 /*! CBPF_BW_CODE - CBPF BW_CODE */
49216 /*! CBPF_CCODE_OFFSET - CBPF_CCODE Offset */
49221 /*! RCCAL_CODE_OFFSET - RCCAL_CODE Offset */
49226 /*! RCCAL_SMPL_DLY - RCCAL Sample Delay
49236 /*! RCCAL_CMPOUT_INV - RCCAL Comparator Output Invert */
49240 /*! @name RCCAL_CTRL1 - RCCAL Control 1 */
49245 /*! CBPF_CCODE_OVRD - CBPF_CCODE Override Value */
49250 /*! CBPF_CCODE_OVRD_EN - CBPF_CCODE Override Enable */
49255 /*! RCCAL_CODE_OVRD - RCCAL_CODE Override Value */
49260 /*! RCCAL_CODE_OVRD_EN - RCCAL_CODE Override Enable */
49265 /*! RCCAL_SAMPLE_OVRD - RCCAL_SAMPLE Override Value */
49270 /*! RCCAL_CHARGE_OVRD - RCCAL_CHARGE Override Value */
49275 /*! RCCAL_DISCHARGE_OVRD - RCCAL_DISCHARGE Override Value */
49280 /*! RCCAL_CTRL_OVRD_EN - RCCAL Control Signals Override Enable */
49284 /*! @name RCCAL_RES - RCCAL Result */
49289 /*! RCCAL_CODE - RCCAL_CODE */
49294 /*! CBPF_CCODE - CBPF_CCODE */
49299 /*! RCCAL_CMPOUT - RCCAL CMPOUT */
49303 /*! @name DCOC_CTRL0 - DCOC Control 0 */
49308 /*! DCOC_SFII - DCOC_SFII */
49313 /*! DCOC_SFQQ - DCOC_SFQQ */
49318 /*! DCOC_SFIIP - DCOC_SFIIP */
49323 /*! DCOC_SFQQP - DCOC_SFQQP */
49328 /*! DCOC_SFIQ - DCOC_SFIQ */
49333 /*! DCOC_SFQI - DCOC_SFQI */
49338 /*! DCOC_I_CAL_POL - DCOC_I_CAL_POL */
49343 /*! DCOC_Q_CAL_POL - DCOC_Q_CAL_POL */
49348 /*! DCOC_DAC_ORDER - DCOC_DAC_ORDER
49360 /*! DCOC_CBPF_STL_TIME - DCOC CBPF Settle Time */
49365 /*! DCOC_SAR_STL_TIME - DCOC CBPF Settle Time */
49378 /*! DCOC_AVG_WIN - DCOC Average Window Select
49379 * 0b0..4-sample
49380 * 0b1..8-sample
49386 /*! DCOC_DIG_CORR_EN - DCOC Digital Correction Enable */
49391 /*! DCOC_DAC_OVRD_EN - DCOC_DAC_OVRD_EN */
49396 /*! DCOC_ADC_OFFSET_OVRD_EN - DCOC_ADC_OFFSET_OVRD_EN */
49401 /*! DCOC_CBPF_SHORT_OVRD - DCOC CBPF_SHORT Override Value */
49406 /*! DCOC_CBPF_HIZ_OVRD - DCOC CBPF_HIZ Override Value */
49411 /*! DCOC_CBPF_HIZ_SHORT_OVRD_EN - DCOC CBPF HIZ SHORT Override Enable */
49415 /*! @name DCOC_CTRL0_DRS - DCOC Control 0 DRS */
49420 /*! DCOC_SFII - DCOC_SFII */
49425 /*! DCOC_SFQQ - DCOC_SFQQ */
49430 /*! DCOC_SFIIP - DCOC_SFIIP */
49435 /*! DCOC_SFQQP - DCOC_SFQQP */
49439 /*! @name DCOC_CTRL1 - DCOC CONTROL 1 */
49444 /*! DCOC_ILNA_OFFSET - DCOC_ILNA_OFFSET */
49449 /*! DCOC_QLNA_OFFSET - DCOC_QLNA_OFFSET */
49454 /*! DCOC_ICBPF_OFFSET - DCOC_ICBPF_OFFSET */
49459 /*! DCOC_QCBPF_OFFSET - DCOC_QCBPF_OFFSET */
49463 /*! @name DCOC_CTRL2 - DCOC CONTROL 2 */
49468 /*! DCOC_DAC_OVRD_I - DCOC_DAC_OVRD_I */
49473 /*! DCOC_DAC_OVRD_Q - DCOC_DAC_OVRD_Q */
49478 /*! DCOC_ADC_OFFSET_OVRD_I - DCOC_ADC_OFFSET_OVRD_I */
49483 /*! DCOC_ADC_OFFSET_OVRD_Q - DCOC_ADC_OFFSET_OVRD_Q */
49487 /*! @name DCOC_STAT - DCOC Status */
49492 /*! CBPF_CODE_DCOC_I - CBPF_CODE_DCOC_I */
49497 /*! CBPF_CODE_DCOC_Q - CBPF_CODE_DCOC_Q */
49502 /*! DCOC_ADC_OFFSET_I - DCOC_ADC_OFFSET_I */
49507 /*! DCOC_ADC_OFFSET_Q - DCOC_ADC_OFFSET_Q */
49511 /*! @name IQMC_CTRL0 - IQ Mismatch Control 0 */
49516 /*! IQMC_CAL_EN - IQ Mismatch Cal Enable */
49521 /*! IQMC_CAL_FREQ_SEL - IQMC_CAL_FREQ_SEL
49529 /*! IQMC_NUM_ITER - IQ Mismatch Cal Num Iter */
49537 /*! @name IQMC_CTRL1 - IQ Mismatch Control 1 */
49542 /*! IQMC_GAIN_ADJ - IQ Mismatch Correction Gain Coeff */
49547 /*! IQMC_PHASE_ADJ - IQ Mismatch Correction Phase Coeff */
49551 /*! @name ACQ_FILT_0_3 - Acquisition Filter Coeffs 0~3 */
49556 /*! H0 - Acquisition Filter Coefficient 0 */
49561 /*! H1 - Acquisition Filter Coefficient 1 */
49566 /*! H2 - Acquisition Filter Coefficient 2 */
49571 /*! H3 - Acquisition Filter Coefficient 3 */
49575 /*! @name ACQ_FILT_4_7 - Acquisition Filter Coeffs 4~7 */
49580 /*! H4 - Acquisition Filter Coefficient 4 */
49585 /*! H5 - Acquisition Filter Coefficient 5 */
49590 /*! H6 - Acquisition Filter Coefficient 6 */
49595 /*! H7 - Acquisition Filter Coefficient 7 */
49599 /*! @name ACQ_FILT_8_9 - Acquisition Filter Coeffs 8~9 */
49604 /*! H8 - Acquisition Filter Coefficient 8 */
49609 /*! H9 - Acquisition Filter Coefficient 9 */
49613 /*! @name ACQ_FILT_10_11 - Acquisition Filter Coeffs 10~11 */
49618 /*! H10 - Acquisition Filter Coefficient 10 */
49623 /*! H11 - Acquisition Filter Coefficient 11 */
49627 /*! @name DEMOD_FILT_0_1 - Demod Filter Coeffs 0~1 */
49632 /*! H0 - Demod Channel Filter Coefficient 0 */
49637 /*! H1 - Demod Channel Filter Coefficient 1 */
49641 /*! @name DEMOD_FILT_2_4 - Demod Filter Coeffs 2~4 */
49646 /*! H2 - Demod Channel Filter Coefficient 2 */
49651 /*! H3 - Demod Channel Filter Coefficient 3 */
49656 /*! H4 - Demod Channel Filter Coefficient 4 */
49660 /*! @name ACQ_FILT_0_3_DRS - Acquisition Filter Coeffs 0~3 DRS */
49665 /*! H0 - Acquisition Filter Coefficient 0 */
49670 /*! H1 - Acquisition Filter Coefficient 1 */
49675 /*! H2 - Acquisition Filter Coefficient 2 */
49680 /*! H3 - Acquisition Filter Coefficient 3 */
49684 /*! @name ACQ_FILT_4_7_DRS - Acquisition Filter Coeffs 4~7 DRS */
49689 /*! H4 - Acquisition Filter Coefficient 4 */
49694 /*! H5 - Acquisition Filter Coefficient 5 */
49699 /*! H6 - Acquisition Filter Coefficient 6 */
49704 /*! H7 - Acquisition Filter Coefficient 7 */
49708 /*! @name ACQ_FILT_8_9_DRS - Acquisition Filter Coeffs 8~9 DRS */
49713 /*! H8 - Acquisition Filter Coefficient 8 */
49718 /*! H9 - Acquisition Filter Coefficient 9 */
49722 /*! @name ACQ_FILT_10_11_DRS - Acquisition Filter Coeffs 10~11 DRS */
49727 /*! H10 - Acquisition Filter Coefficient 10 */
49732 /*! H11 - Acquisition Filter Coefficient 11 */
49736 /*! @name DEMOD_FILT_0_1_DRS - Demod Filter Coeffs 0~1 DRS */
49741 /*! H0 - Demod Channel Filter Coefficient 0 */
49746 /*! H1 - Demod Channel Filter Coefficient 1 */
49750 /*! @name DEMOD_FILT_2_4_DRS - Demod Filter Coeffs 2~4 DRS */
49755 /*! H2 - Demod Channel Filter Coefficient 2 */
49760 /*! H3 - Demod Channel Filter Coefficient 3 */
49765 /*! H4 - Demod Channel Filter Coefficient 4 */
49769 /*! @name RSSI_GLOBAL_CTRL - RSSI Global Control */
49774 /*! NB_RSSI_INPUT_SEL - NB RSSI Input Select
49784 /*! NB_RSSI_AA_MATCH_OVRD - NB RSSI PHY Trigger Override */
49789 /*! NB_RSSI_AA_MATCH_OVRD_EN - NB RSSI PHY Trigger Override Enable */
49794 /*! NB_RSSI_PA_AA_MATCH_SEL - NB RSSI PHY Trigger Select
49795 * 0b0..NB-RSSI starts work when PHY_PD_FOUND asserted
49796 * 0b1..NB-RSSI starts work when PHY_AA_MATCH asserted
49802 /*! NB_CCA1_ED_EN - NB RSSI CCA1 ED Enable
49803 * 0b0..NB-RSSI CCA1/ED is disabled
49804 * 0b1..NB-RSSI CCA1/ED is enabled
49810 /*! NB_CONT_MEAS_OVRD - NB RSSI Onetime Measure Override */
49815 /*! NB_CONT_MEAS_OVRD_EN - NB RSSI One-time Measure Override Enable */
49820 /*! NB_SNR_LQI_ENABLE - NB RSSI SNR LQI Enable
49821 * 0b0..NB-RSSI SNR/LQI calculation is disabled
49822 * 0b1..NB-RSSI SNR/LQI calculation is enabled
49828 /*! CCA1_ED_FROM_NB - CCA1/ED Result Selection
49829 * 0b0..WB-RSSI's CCA1/ED result is selected
49830 * 0b1..NB-RSSI's CCA1/ED result is selected
49836 /*! NB_RSSI_EN - NB RSSI Enable
49837 * 0b0..NB-RSSI is disabled
49838 * 0b1..NB-RSSI is enabled
49844 /*! WB_RSSI_INPUT_SEL - WB RSSI Input Select
49852 /*! WB_CCA1_ED_EN - WB RSSI CCA1 ED Enable
49853 * 0b0..WB-RSSI CCA1/ED disabled
49854 * 0b1..WB-RSSI CCA1/ED enabled
49860 /*! WB_CONT_MEAS_OVRD - WB RSSI Continuous Measurment Override Value */
49865 /*! WB_CONT_MEAS_OVRD_EN - WB RSSI Continuous Measurment Override Enable */
49870 /*! WB_RSSI_EN - WB RSSI Enable
49871 * 0b0..WB-RSSI is disabled
49872 * 0b1..WB-RSSI is enabled
49877 /*! @name WB_RSSI_CTRL - Wide-Band RSSI Control */
49882 /*! RSSI_N_WINDOW_WB - WB RSSI N Window Averager Factor */
49887 /*! RSSI_M_WINDOW_WB - WB RSSI M Window Averager Factor */
49892 /*! RSSI_F_WINDOW_WB - WB RSSI F Window Averager Factor */
49897 /*! RSSI_DB_EN_WB - WB RSSI dB Calculate Enable */
49914 /*! RSSI_ADJ_WB - WB RSSI Adjust Value */
49918 /*! @name WB_RSSI_RES0 - Wide-Band RSSI Result 0 */
49923 /*! RSSI_WB - WB RSSI Result */
49932 /*! RSSI_RAW_WB - WB Raw RSSI Result */
49936 /*! @name WB_RSSI_RES1 - Wide-Band RSSI Result 1 */
49941 /*! ED_WB - WB RSSI ED Result */
49946 /*! CCA1_STATE_WB - WB RSSI CCA1 State */
49951 /*! MEAS_COMPLETE_WB - WB RSSI Measure Complete */
49955 /*! @name WB_RSSI_DFT - Wide-Band RSSI DFT Result */
49960 /*! SLOW_MAG - WB RSSI Slow Magnitude Value */
49965 /*! FAST_MAG - WB RSSI Fast Magnitude Value */
49969 /*! @name NB_RSSI_CTRL0 - Narrow-Band RSSI Control 0 */
49974 /*! RSSI_N_WINDOW_NB - NB RSSI N Window Averager Factor */
49979 /*! RSSI_M_WINDOW_NB - NB RSSI M Window Averager Factor */
49984 /*! RSSI_IIR_WAIT_NB - NB RSSI IIR Filter Initial Wait Time */
49989 /*! RSSI_IIR_WT_NB - NB RSSI IIR Filter Factor */
49994 /*! SNR_ADJ_NB - NB RSSI SNR Adjust Value */
50003 /*! RSSI_ADJ_NB - NB RSSI Adjust Value */
50007 /*! @name NB_RSSI_CTRL1 - Narrow-Band RSSI Control 1 */
50012 /*! LQI_RSSI_WEIGHT - RSSI Weight For LQI Calulation */
50017 /*! LQI_SNR_WEIGHT - SNR Weight For LQI Calulation */
50022 /*! LQI_RSSI_SENS_ADJ - LQI Sensitivity Adjust Value */
50027 /*! LQI_BIAS - LQI Bias Value */
50031 /*! @name NB_RSSI_RES0 - Narrow-Band RSSI Result 0 */
50036 /*! RSSI_NB - NB RSSI Result */
50045 /*! RSSI_RAW_NB - Raw NB RSSI Result */
50050 /*! NOISE_RSSI_RAW_NB - Raw Noise Result */
50054 /*! @name NB_RSSI_RES1 - Narrow-Band RSSI Result 1 */
50059 /*! ED_NB - NB RSSI ED Result */
50064 /*! LQI_NB - NB RSSI LQI Result */
50069 /*! SNR_NB - NB RSSI SNR Result */
50074 /*! CCA1_STATE_NB - NB RSSI CCA1 State */
50079 /*! MEAS_COMPLETE_NB - NB RSSI Measure Complete */
50083 /*! @name NB_RSSI_DFT - Narrow-Band RSSI DFT Result */
50088 /*! AVG_NOISE_MAG_NB - NB RSSI Averaged Noise Magnitude Value */
50093 /*! AVG_MAG_NB - NB RSSI Averaged Magnitude Value */
50097 /*! @name AGC_CTRL - AGC Control */
50102 /*! AGC_UNHOLD_FEAT_EN - AGC Unhold Enalbe */
50107 /*! AGC_HOLD_EN - AGC Hold Mode Enable
50117 /*! AGC_DELTA_SLOW_STEP - AGC Delta Slow Mode Gain Step Up Value */
50122 /*! AGC_DELTA_SLOW_EN - AGC Delta Slow Magitude Mode Enable
50130 /*! AGC_SLOW_EN - AGC Slow Magitude Mode Enable
50138 /*! AGC_FAST_STEP_UP_EN - AGC Fast Magitude Mode Step Up Enable
50146 /*! AGC_FAST_EN - AGC Fast Magitude Mode Enable
50154 /*! AGC_WBD_STEP2_SZ - AGC WBD Step2 Gain Decreas Value */
50159 /*! AGC_WBD_STEP1_SZ - AGC WBD Step1 Gain Decreas Value */
50164 /*! AGC_WBD_THR2 - AGC WBD Step2 threshold */
50169 /*! AGC_WBD_THR1 - AGC WBD Step1 threshold
50191 /*! AGC_WBD_STEP2_DUAL_CLIP_EN - AGC WBD Step2 Dual Clip Enable */
50196 /*! AGC_WBD_STEP1_DUAL_CLIP_EN - AGC WBD Step1 Dual Clip Enable */
50201 /*! AGC_WBD_GAIN_LIMIT_EN - AGC WBD Gain Limit */
50206 /*! AGC_WBD_AUTO_DIS_CFG - AGC WBD Auto Disable */
50211 /*! AGC_WBD_EN - AGC WBD Enable
50220 /*! @name AGC_CTRL_STAT - AGC Control Status */
50225 /*! AGC_MAX_IDX - AGC Max Gain Index */
50230 /*! AGC_INIT_IDX - AGC Initial Gain Index */
50235 /*! AGC_PHY_HOLD_TRIG_SEL - AGC PHY Hold Trigger Select
50243 /*! AGC_PHY_FREEZE_TRIG_SEL - AGC PHY Freeze Trigger Select
50251 /*! AGC_CALC_MAG_IN_FRZ - AGC Calucate Magnitude In Freeze Mode */
50256 /*! AGC_UNFREEZE_FEAT_EN - AGC Unfreeze Feature Enable
50264 /*! AGC_FREEZE_EN - AGC Freeze Mode Enable
50284 /*! AGC_SOFT_RST_GAIN_SEL - PHY AGC Soft Reset Gain Sel
50292 /*! AGC_SOFT_RST_SRC_SEL - PHY AGC Soft Reset Sel
50302 /*! AGC_PREV_GAIN_IDX - AGC Previous Gain Index */
50307 /*! AGC_GAIN_IDX - AGC Gain Index */
50312 /*! AGC_GAIN_CHANGE - AGC Gain Change */
50317 /*! AGC_GAIN_CHANGE_STATUS - AGC Gain Change Status
50331 /*! AGC_STATUS - AGC FSM Status
50344 /*! @name AGC_TIMING0 - AGC Timing Control 0 */
50349 /*! AGC_DELTA_SLOW_WAIT - AGC Delta Slow Mode Timing */
50354 /*! AGC_WBD_STEP2_TIMEOUT - AGC WBD Step2 Timeout */
50359 /*! AGC_WBD_STEP1_TIMEOUT - AGC WBD Timeout */
50364 /*! AGC_GAIN_STEP_WAIT - AGC Gain Change Wait Time */
50369 /*! AGC_MAG_INIT_WAIT - AGC Magnitude Mode Initial Wait Time */
50374 /*! AGC_WBD_INIT_WAIT - AGC WBD Mode Initial Wait Time */
50378 /*! @name AGC_TIMING1 - AGC Timing Control 1 */
50383 /*! AGC_FREEZE_TIMEOUT - AGC FREEZE Mode Wait Time */
50388 /*! AGC_HOLD_TIMEOUT - AGC HOLD Mode Wait Time */
50393 /*! AGC_WBD_STEP2_DUAL_CLIP_WAIT - AGC WBD step2 Debounce Wait Time */
50398 /*! AGC_WBD_STEP1_DUAL_CLIP_WAIT - AGC WBD step1 Debounce Wait Time */
50403 /*! AGC_WBD_STEP2_WAIT - AGC Gain Change Wait For WBD step2 */
50411 /*! @name AGC_TIMING2 - AGC Timing Control 2 */
50416 /*! AGC_UNFREEZE_FEAT_TIMEOUT - AGC Unfreeze Feature Timeout */
50421 /*! AGC_UNHOLD_FEAT_TIMEOUT - AGC Unhold Feature Timeout */
50426 /*! AGC_UNHOLD_GAIN_CHG - AGC Gain Index Change When UNHOLD */
50431 /*! AGC_UNHOLD_MAG_CNT - AGC Unhold Magnitude Count Selection */
50436 /*! AGC_UNHOLD_MAG_SRC - AGC Magnitude Unhold Feature Source Selection
50443 /*! @name AGC_TIMING0_DRS - AGC Timing Control 0 DRS */
50448 /*! AGC_GAIN_STEP_WAIT - AGC Gain Change Wait Time */
50456 /*! @name AGC_TIMING1_DRS - AGC Timing Control 1 DRS */
50461 /*! AGC_FREEZE_TIMEOUT - AGC FREEZE Mode Wait Time */
50466 /*! AGC_HOLD_TIMEOUT - AGC HOLD Mode Wait Time */
50470 /*! @name AGC_TIMING2_DRS - AGC Timing Control 2 DRS */
50475 /*! AGC_UNFREEZE_FEAT_TIMEOUT - AGC Unfreeze Feature Timeout */
50480 /*! AGC_UNHOLD_FEAT_TIMEOUT - AGC Unhold Feature Timeout */
50484 /*! @name AGC_IDX11_GAIN_CFG - AGC IDX11 Gain Config */
50489 /*! CBPF_GAIN_11 - CBPF_GAIN_11
50490 * 0b0..-6 dB
50497 /*! LNA_RTRIM_11 - LNA_RTRIM_11 */
50502 /*! LNA_ATTN_11 - LNA_ATTN_11 */
50507 /*! LNA_HATTN_11 - LNA_HATTN_11 */
50512 /*! LNA_LGAIN_11 - LNA_LGAIN_11 */
50517 /*! LNA_HGAIN_11 - LNA_HGAIN_11 */
50522 /*! ANT_EN_RLOAD_11 - ANT_EN_RLOAD_11 */
50527 /*! MAG_THR_HI_11_DRS_OFS - Mag Thresh High DRS for AGC Gain Index 11 */
50532 /*! MAG_THR_11_DRS_OFS - Mag Thresh High DRS for AGC Gain Index 11 */
50536 /*! @name AGC_IDX10_GAIN_CFG - AGC IDX10 Gain Config */
50541 /*! CBPF_GAIN_10 - CBPF_GAIN_10
50542 * 0b0..-6 dB
50549 /*! LNA_RTRIM_10 - LNA_RTRIM_10 */
50554 /*! LNA_ATTN_10 - LNA_ATTN_10 */
50559 /*! LNA_HATTN_10 - LNA_HATTN_10 */
50564 /*! LNA_LGAIN_10 - LNA_LGAIN_10 */
50569 /*! LNA_HGAIN_10 - LNA_HGAIN_10 */
50574 /*! ANT_EN_RLOAD_10 - ANT_EN_RLOAD_10 */
50586 /*! @name AGC_IDX9_GAIN_CFG - AGC IDX9 Gain Config */
50591 /*! CBPF_GAIN_9 - CBPF_GAIN_9
50592 * 0b0..-6 dB
50599 /*! LNA_RTRIM_9 - LNA_RTRIM_9 */
50604 /*! LNA_ATTN_9 - LNA_ATTN_9 */
50609 /*! LNA_HATTN_9 - LNA_HATTN_9 */
50614 /*! LNA_LGAIN_9 - LNA_LGAIN_9 */
50619 /*! LNA_HGAIN_9 - LNA_HGAIN_9 */
50624 /*! ANT_EN_RLOAD_9 - ANT_EN_RLOAD_9 */
50636 /*! @name AGC_IDX8_GAIN_CFG - AGC IDX8 Gain Config */
50641 /*! CBPF_GAIN_8 - CBPF_GAIN_8
50642 * 0b0..-6 dB
50649 /*! LNA_RTRIM_8 - LNA_RTRIM_8 */
50654 /*! LNA_ATTN_8 - LNA_ATTN_8 */
50659 /*! LNA_HATTN_8 - LNA_HATTN_8 */
50664 /*! LNA_LGAIN_8 - LNA_LGAIN_8 */
50669 /*! LNA_HGAIN_8 - LNA_HGAIN_8 */
50674 /*! ANT_EN_RLOAD_8 - ANT_EN_RLOAD_8 */
50686 /*! @name AGC_IDX7_GAIN_CFG - AGC IDX7 Gain Config */
50691 /*! CBPF_GAIN_7 - CBPF_GAIN_7
50692 * 0b0..-6 dB
50699 /*! LNA_RTRIM_7 - LNA_RTRIM_7 */
50704 /*! LNA_ATTN_7 - LNA_ATTN_7 */
50709 /*! LNA_HATTN_7 - LNA_HATTN_7 */
50714 /*! LNA_LGAIN_7 - LNA_LGAIN_7 */
50719 /*! LNA_HGAIN_7 - LNA_HGAIN_7 */
50724 /*! ANT_EN_RLOAD_7 - ANT_EN_RLOAD_7 */
50736 /*! @name AGC_IDX6_GAIN_CFG - AGC IDX6 Gain Config */
50741 /*! CBPF_GAIN_6 - CBPF_GAIN_6
50742 * 0b0..-6 dB
50749 /*! LNA_RTRIM_6 - LNA_RTRIM_6 */
50754 /*! LNA_ATTN_6 - LNA_ATTN_6 */
50759 /*! LNA_HATTN_6 - LNA_HATTN_6 */
50764 /*! LNA_LGAIN_6 - LNA_LGAIN_6 */
50769 /*! LNA_HGAIN_6 - LNA_HGAIN_6 */
50774 /*! ANT_EN_RLOAD_6 - ANT_EN_RLOAD_6 */
50786 /*! @name AGC_IDX5_GAIN_CFG - AGC IDX5 Gain Config */
50791 /*! CBPF_GAIN_5 - CBPF_GAIN_5
50792 * 0b0..-6 dB
50799 /*! LNA_RTRIM_5 - LNA_RTRIM_5 */
50804 /*! LNA_ATTN_5 - LNA_ATTN_5 */
50809 /*! LNA_HATTN_5 - LNA_HATTN_5 */
50814 /*! LNA_LGAIN_5 - LNA_LGAIN_5 */
50819 /*! LNA_HGAIN_5 - LNA_HGAIN_5 */
50824 /*! ANT_EN_RLOAD_5 - ANT_EN_RLOAD_5 */
50836 /*! @name AGC_IDX4_GAIN_CFG - AGC IDX4 Gain Config */
50841 /*! CBPF_GAIN_4 - CBPF_GAIN_4
50842 * 0b0..-6 dB
50849 /*! LNA_RTRIM_4 - LNA_RTRIM_4 */
50854 /*! LNA_ATTN_4 - LNA_ATTN_4 */
50859 /*! LNA_HATTN_4 - LNA_HATTN_4 */
50864 /*! LNA_LGAIN_4 - LNA_LGAIN_4 */
50869 /*! LNA_HGAIN_4 - LNA_HGAIN_4 */
50874 /*! ANT_EN_RLOAD_4 - ANT_EN_RLOAD_4 */
50886 /*! @name AGC_IDX3_GAIN_CFG - AGC IDX3 Gain Config */
50891 /*! CBPF_GAIN_3 - CBPF_GAIN_3
50892 * 0b0..-6 dB
50899 /*! LNA_RTRIM_3 - LNA_RTRIM_3 */
50904 /*! LNA_ATTN_3 - LNA_ATTN_3 */
50909 /*! LNA_HATTN_3 - LNA_HATTN_3 */
50914 /*! LNA_LGAIN_3 - LNA_LGAIN_3 */
50919 /*! LNA_HGAIN_3 - LNA_HGAIN_3 */
50924 /*! ANT_EN_RLOAD_3 - ANT_EN_RLOAD_3 */
50936 /*! @name AGC_IDX2_GAIN_CFG - AGC IDX2 Gain Config */
50941 /*! CBPF_GAIN_2 - CBPF_GAIN_2
50942 * 0b0..-6 dB
50949 /*! LNA_RTRIM_2 - LNA_RTRIM_2 */
50954 /*! LNA_ATTN_2 - LNA_ATTN_2 */
50959 /*! LNA_HATTN_2 - LNA_HATTN_2 */
50964 /*! LNA_LGAIN_2 - LNA_LGAIN_2 */
50969 /*! LNA_HGAIN_2 - LNA_HGAIN_2 */
50974 /*! ANT_EN_RLOAD_2 - ANT_EN_RLOAD_2 */
50986 /*! @name AGC_IDX1_GAIN_CFG - AGC IDX1 Gain Config */
50991 /*! CBPF_GAIN_1 - CBPF_GAIN_1
50992 * 0b0..-6 dB
50999 /*! LNA_RTRIM_1 - LNA_RTRIM_1 */
51004 /*! LNA_ATTN_1 - LNA_ATTN_1 */
51009 /*! LNA_HATTN_1 - LNA_HATTN_1 */
51014 /*! LNA_LGAIN_1 - LNA_LGAIN_1 */
51019 /*! LNA_HGAIN_1 - LNA_HGAIN_1 */
51024 /*! ANT_EN_RLOAD_1 - ANT_EN_RLOAD_1 */
51036 /*! @name AGC_IDX0_GAIN_CFG - AGC IDX0 Gain Config */
51041 /*! CBPF_GAIN_0 - CBPF_GAIN_0
51042 * 0b0..-6 dB
51049 /*! LNA_RTRIM_0 - LNA_RTRIM_0 */
51054 /*! LNA_ATTN_0 - LNA_ATTN_0 */
51059 /*! LNA_HATTN_0 - LNA_HATTN_0 */
51064 /*! LNA_LGAIN_0 - LNA_LGAIN_0 */
51069 /*! LNA_HGAIN_0 - LNA_HGAIN_0 */
51074 /*! ANT_EN_RLOAD_0 - ANT_EN_RLOAD_0 */
51086 /*! @name AGC_MIS_GAIN_CFG - AGC Miscellaneous Gain Config */
51102 /*! @name AGC_IDX11_GAIN_VAL - AGC IDX11 Gain Value */
51107 /*! LOG_GAIN_11 - LOG_GAIN_11 */
51119 /*! @name AGC_IDX10_GAIN_VAL - AGC_IDX10_GAIN_VAL */
51124 /*! LOG_GAIN_10 - LOG_GAIN_10 */
51136 /*! @name AGC_IDX9_GAIN_VAL - AGC_IDX9_GAIN_VAL */
51141 /*! LOG_GAIN_9 - LOG_GAIN_9 */
51153 /*! @name AGC_IDX8_GAIN_VAL - AGC_IDX8_GAIN_VAL */
51158 /*! LOG_GAIN_8 - LOG_GAIN_8 */
51170 /*! @name AGC_IDX7_GAIN_VAL - AGC_IDX7_GAIN_VAL */
51175 /*! LOG_GAIN_7 - LOG_GAIN_7 */
51187 /*! @name AGC_IDX6_GAIN_VAL - AGC_IDX6_GAIN_VAL */
51192 /*! LOG_GAIN_6 - LOG_GAIN_6 */
51204 /*! @name AGC_IDX5_GAIN_VAL - AGC_IDX5_GAIN_VAL */
51209 /*! LOG_GAIN_5 - LOG_GAIN_5 */
51221 /*! @name AGC_IDX4_GAIN_VAL - AGC_IDX4_GAIN_VAL */
51226 /*! LOG_GAIN_4 - LOG_GAIN_4 */
51238 /*! @name AGC_IDX3_GAIN_VAL - AGC_IDX3_GAIN_VAL */
51243 /*! LOG_GAIN_3 - LOG_GAIN_3 */
51255 /*! @name AGC_IDX2_GAIN_VAL - AGC_IDX2_GAIN_VAL */
51260 /*! LOG_GAIN_2 - LOG_GAIN_2 */
51272 /*! @name AGC_IDX1_GAIN_VAL - AGC_IDX1_GAIN_VAL */
51277 /*! LOG_GAIN_1 - LOG_GAIN_1 */
51289 /*! @name AGC_IDX0_GAIN_VAL - AGC_IDX0_GAIN_VAL */
51294 /*! LOG_GAIN_0 - LOG_GAIN_0 */
51306 /*! @name AGC_THR_FAST - AGC Fast Mode Threshold */
51311 /*! STEP_UP_THR_FAST - STEP_UP_THR_FAST */
51316 /*! STEP_DOWN_THR_FAST - STEP_DOWN_THR_FAST */
51320 /*! @name AGC_THR_FAST_DRS - AGC Fast Mode Threshold DRS */
51325 /*! STEP_UP_THR_FAST - STEP_UP_THR_FAST */
51330 /*! STEP_DOWN_THR_FAST - STEP_DOWN_THR_FAST */
51334 /*! @name AGC_IDX11_THR - AGC IDX11 Slow Mode Threshold */
51339 /*! STEP_DOWN_THR_11 - STEP_DOWN_THR_11 */
51344 /*! STEP_DOWN_THR_11_DRS_OFS - STEP_DOWN_THR_11 DRS Offset */
51348 /*! @name AGC_IDX10_THR - AGC IDX10 Slow Mode Threshold */
51353 /*! STEP_UP_THR_10 - STEP_UP_THR_10 */
51358 /*! STEP_DOWN_THR_10 - STEP_DOWN_THR_10 */
51363 /*! STEP_DOWN_THR_10_DRS_OFS - STEP_DOWN_THR_10 DRS Offset */
51367 /*! @name AGC_IDX9_THR - AGC IDX9 Slow Mode Threshold */
51372 /*! STEP_UP_THR_9 - STEP_UP_THR_9 */
51377 /*! STEP_DOWN_THR_9 - STEP_DOWN_THR_9 */
51382 /*! STEP_DOWN_THR_9_DRS_OFS - STEP_DOWN_THR_9 DRS Offset */
51386 /*! @name AGC_IDX8_THR - AGC IDX8 Slow Mode Threshold */
51391 /*! STEP_UP_THR_8 - STEP_UP_THR_8 */
51396 /*! STEP_DOWN_THR_8 - STEP_DOWN_THR_8 */
51401 /*! STEP_DOWN_THR_8_DRS_OFS - STEP_DOWN_THR_8 DRS Offset */
51405 /*! @name AGC_IDX7_THR - AGC IDX7 Slow Mode Threshold */
51410 /*! STEP_UP_THR_7 - STEP_UP_THR_7 */
51415 /*! STEP_DOWN_THR_7 - STEP_DOWN_THR_7 */
51420 /*! STEP_DOWN_THR_7_DRS_OFS - STEP_DOWN_THR_7 DRS Offset */
51424 /*! @name AGC_IDX6_THR - AGC IDX6 Slow Mode Threshold */
51429 /*! STEP_UP_THR_6 - STEP_UP_THR_6 */
51434 /*! STEP_DOWN_THR_6 - STEP_DOWN_THR_6 */
51439 /*! STEP_DOWN_THR_6_DRS_OFS - STEP_DOWN_THR_6 DRS Offset */
51443 /*! @name AGC_IDX5_THR - AGC IDX5 Slow Mode Threshold */
51448 /*! STEP_UP_THR_5 - STEP_UP_THR_5 */
51453 /*! STEP_DOWN_THR_5 - STEP_DOWN_THR_5 */
51458 /*! STEP_DOWN_THR_5_DRS_OFS - STEP_DOWN_THR_5 DRS Offset */
51462 /*! @name AGC_IDX4_THR - AGC IDX4 Slow Mode Threshold */
51467 /*! STEP_UP_THR_4 - STEP_UP_THR_4 */
51472 /*! STEP_DOWN_THR_4 - STEP_DOWN_THR_4 */
51477 /*! STEP_DOWN_THR_4_DRS_OFS - STEP_DOWN_THR_4 DRS Offset */
51481 /*! @name AGC_IDX3_THR - AGC IDX3 Slow Mode Threshold */
51486 /*! STEP_UP_THR_3 - STEP_UP_THR_3 */
51491 /*! STEP_DOWN_THR_3 - STEP_DOWN_THR_3 */
51496 /*! STEP_DOWN_THR_3_DRS_OFS - STEP_DOWN_THR_3 DRS Offset */
51500 /*! @name AGC_IDX2_THR - AGC IDX2 Slow Mode Threshold */
51505 /*! STEP_UP_THR_2 - STEP_UP_THR_2 */
51510 /*! STEP_DOWN_THR_2 - STEP_DOWN_THR_2 */
51515 /*! STEP_DOWN_THR_2_DRS_OFS - STEP_DOWN_THR_2 DRS Offset */
51519 /*! @name AGC_IDX1_THR - AGC IDX1 Slow Mode Threshold */
51524 /*! STEP_UP_THR_1 - STEP_UP_THR_1 */
51529 /*! STEP_DOWN_THR_1 - STEP_DOWN_THR_1 */
51534 /*! STEP_DOWN_THR_1_DRS_OFS - STEP_DOWN_THR_1 DRS Offset */
51538 /*! @name AGC_IDX0_THR - AGC IDX0 Slow Mode Threshold */
51543 /*! STEP_UP_THR_0 - STEP_UP_THR_0 */
51547 /*! @name AGC_THR_MIS - AGC Miscellaneous Thresholds */
51552 /*! DELTA_SLOW_THR - STEP_UP_THR_VLG2 */
51557 /*! HOLD_MARGIN_THR - STEP_UP_THR_VLG2large */
51561 /*! @name AGC_OVRD - AGC Override Control */
51597 /*! @name DC_RESID_CTRL - DC Residual Control */
51602 /*! DC_RESID_NWIN - DC Residual NWIN */
51607 /*! DC_RESID_ITER_FREEZE - DC Residual Iteration Freeze */
51612 /*! DC_RESID_ALPHA - DC Residual Alpha
51626 /*! DC_RESID_GS_EN - DC Residual Gearshift Enable
51634 /*! DC_RESID_DLY - DC Residual Delay */
51639 /*! DC_RESID_SECOND_RUN_EN - DC Residual Second Run Enable
51647 /*! DC_RESID_EXT_DC_EN - DC Residual External DC Enable
51657 /*! DC_RESID_MIN_AGC_IDX - DC Residual Minimum AGC Table Index */
51662 /*! DC_RESID_GEARSHIFT - DC Residual Gearshift */
51666 /*! @name DC_RESID_CTRL2 - DC Residual Control2 */
51671 /*! DC_RESID_NWIN2 - DC Residual NWIN, for Second Run */
51676 /*! DC_RESID_PHY_STOP_EN - DC Residual PHY Stop Enable */
51681 /*! DC_RESID_CC_EN - DC Residual Continuous Correction Enable */
51686 /*! DC_RESID_SR2_EN - DC Residual Slewrate Enable, for Second Run */
51691 /*! DC_RESID_ALPHA2 - DC Residual Alpha, for Second Run
51705 /*! DC_RESID_GS2_EN - DC Residual Gearshift Enable, for Second Run
51713 /*! DC_RESID_ITER_FREEZE2 - DC Residual Iteration Freeze, for Second Run */
51718 /*! DC_RESID_SLEWRATE2 - DC Residual Slewrate, for Second Run */
51723 /*! DC_RESID_MIN_AGC_IDX2 - DC Residual Minimum AGC Table Index, for Second Run */
51728 /*! DC_RESID_GEARSHIFT2 - DC Residual Gearshift, for Second Run */
51732 /*! @name DC_RESID_CTRL_DRS - DC Residual Control DataRate1 */
51737 /*! DC_RESID_NWIN - DC Residual NWIN */
51742 /*! DC_RESID_DLY - DC Residual Delay */
51747 /*! DC_RESID_NWIN2 - DC Residual NWIN, for Second Run */
51751 /*! @name DC_RESID_EST - DC Residual Estimate */
51756 /*! DC_RESID_OFFSET_I - DC Residual Offset I */
51761 /*! DC_RESID_OFFSET_Q - DC Residual Offset Q */
51765 /*! @name DFT_TONE_ANALYZER0 - DfT tone analyzer */
51770 /*! ipr_dft_ana_start_offset_q - Q Initial Phase */
51775 /*! ipr_dft_ana_start_offset_i - I Initial Phase */
51780 /*! ipr_dft_ana_attenuation_q - Tone Attenuation For Q Path */
51789 /*! ipr_dft_ana_en - Enable for DfT tone analyzer */
51793 /*! @name DFT_TONE_ANALYZER1 - DfT tone analyzer */
51840 /*! @name DFT_TONE_ANALYZER2 - DfT tone analyzer */
51852 /*! @name DFT_TONE_ANALYZER3 - DfT tone analyzer */
51864 /*! @name DCOC_DIG_CORR_RESULT - DCOC Digital Correction Result */
51869 /*! DCOC_DIG_CORR_Q - DCOC I-Channel Residual After Calibration */
51874 /*! DCOC_DIG_CORR_I - DCOC Q-Channel Residual After Calibration */
51884 /* XCVR_RX_DIG - Peripheral instance base addresses */
51918 /* ----------------------------------------------------------------------------
51919 -- XCVR_TSM Peripheral Access Layer
51920 ---------------------------------------------------------------------------- */
51927 /** XCVR_TSM - Register Layout Typedef */
51996 /* ----------------------------------------------------------------------------
51997 -- XCVR_TSM Register Masks
51998 ---------------------------------------------------------------------------- */
52005 /*! @name CTRL - TSM CONTROL */
52010 /*! TSM_SOFT_RESET - TSM Soft Reset
52018 /*! FORCE_TX_EN - Force Transmit Enable
52026 /*! FORCE_RX_EN - Force Receive Enable
52034 /*! TX_ABORT_DIS - Transmit Abort Disable */
52039 /*! RX_ABORT_DIS - Receive Abort Disable */
52044 /*! ABORT_ON_CTUNE - Abort On Coarse Tune Lock Detect Failure
52052 /*! ABORT_ON_FREQ_TARG - Abort On Frequency Target Lock Detect Failure
52060 /*! TSM_IRQ0_EN - TSM_IRQ0 Enable/Disable bit
52068 /*! TSM_IRQ1_EN - TSM_IRQ1 Enable/Disable bit
52076 /*! PLL_UNLOCK_IRQ_EN - PLL Unlock Interrupt Enable
52084 /*! PLL_UNLOCK_IRQ - PLL Unlock IRQ
52092 /*! TSM_LL_INHIBIT - TSM Per-Link-Layer Inhibit */
52097 /*! TSM_SPARE1_EXTEND - TSM RF_ACTIVE Extension Duration */
52102 /*! BKPT - TSM Breakpoint */
52106 /*! @name LPPS_CTRL - TSM CONTROL */
52111 /*! LPPS_LNA_MIX_ALLOW - LPPS_LNA_MIX_ALLOW */
52116 /*! LPPS_CBPF_ALLOW - LPPS_CBPF_ALLOW */
52121 /*! LPPS_ADC_ALLOW - LPPS_ADC_ALLOW */
52126 /*! LPPS_LO_RX_ALLOW - LPPS_LO_RX_ALLOW */
52131 /*! LPPS_LO_RXDRV_ALLOW - LPPS_LO_RXDRV_ALLOW */
52136 /*! LPPS_RX_DIG_ALLOW - LPPS_RX_DIG_ALLOW */
52141 /*! LPPS_RX_PHY_ALLOW - LPPS_RX_PHY_ALLOW */
52146 /*! LPPS_START_RX - LPPS Fast TSM RX Warmup "Jump-from" Point */
52151 /*! LPPS_DEST_RX - LPPS Fast TSM RX Warmup "Jump-to" Point */
52155 /*! @name END_OF_SEQ - TSM END OF SEQUENCE */
52160 /*! END_OF_TX_WU - End of TX Warmup */
52165 /*! END_OF_TX_WD - End of TX Warmdown */
52170 /*! END_OF_RX_WU - End of RX Warmup */
52175 /*! END_OF_RX_WD - End of RX Warmdown */
52179 /*! @name WU_LATENCY - WARMUP LATENCY */
52184 /*! TX_DATAPATH_LATENCY - TX Datapath Latency */
52189 /*! RX_SETTLING_LATENCY - RX Settling Latency */
52193 /*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */
52198 /*! RECYCLE_COUNT0 - TSM RX Recycle Count 0 */
52203 /*! RECYCLE_COUNT1 - TSM RX Recycle Count 1 */
52208 /*! RECYCLE_COUNT2 - TSM RX Recycle Count 2 */
52212 /*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL 1 */
52217 /*! FAST_TX_WU_EN - Fast TSM TX Warmup Enable
52226 /*! FAST_RX_WU_EN - Fast TSM RX Warmup Enable
52235 /*! FAST_RX2TX_EN - Fast TSM RX-to-TX Transition Enable
52236 * 0b0..Disable Fast RX-to-TX transitions
52237 * 0b1..Enable Fast RX-to-TX transitions (if fast_rx2tx_wu is asserted by the Link Layer)
52243 /*! PWRSAVE_TX_WU_EN - Power Save TSM TX Warmup Enable
52251 /*! PWRSAVE_RX_WU_EN - Power Save TSM RX Warmup Enable
52259 /*! PWRSAVE_WU_CLEAR - PowerSave TSM Warmup Clear State */
52264 /*! FAST_RX2TX_START - TSM "Jump-to" point for a Fast TSM RX-to-TX Transition. */
52269 /*! FAST_TX2RX_EN - Fast TSM TX-to-RX Transition Enable
52270 * 0b0..Disable Fast TX-to-RX transitions
52271 * 0b1..Enable Fast TX-to-RX transitions (if fast_tx2rx_wu is asserted by Ranging sequence manager)
52277 /*! FAST_TX2RX_START - TSM "Jump-to" point for a Fast TSM TX-to-RX Transition. */
52281 /*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL 2 */
52286 /*! FAST_START_TX - Fast TSM TX "Jump-from" Point */
52291 /*! FAST_DEST_TX - Fast TSM TX "Jump-to" Point */
52296 /*! FAST_START_RX - Fast TSM RX "Jump-from" Point */
52301 /*! FAST_DEST_RX - Fast TSM RX "Jump-to" Point */
52305 /*! @name FAST_CTRL3 - TSM FAST WARMUP CONTROL 3 */
52310 /*! FAST_RX2TX_START_FC - TSM "Jump-to" point for RSM's FC RX-to-TX Transition */
52315 /*! FAST_TX2RX_START_FC - TSM "Jump-to" point for RSM's FC TX-to-RX Transition */
52319 /*! @name TIMING00 - TSM_TIMING00 */
52324 /*! RF_ACTIVE_TX_HI - Assertion time setting for RF_ACTIVE (TX) */
52329 /*! RF_ACTIVE_TX_LO - De-assertion time setting for RF_ACTIVE (TX) */
52334 /*! RF_ACTIVE_RX_HI - Assertion time setting for RF_ACTIVE_EN (RX) */
52339 /*! RF_ACTIVE_RX_LO - De-assertion time setting for RF_ACTIVE (RX) */
52343 /*! @name TIMING01 - TSM_TIMING01 */
52348 /*! RF_STATUS_TX_HI - Assertion time setting for RF_STATUS (TX) */
52353 /*! RF_STATUS_TX_LO - De-assertion time setting for RF_STATUS (TX) */
52358 /*! RF_STATUS_RX_HI - Assertion time setting for RF_STATUS (RX) */
52363 /*! RF_STATUS_RX_LO - De-assertion time setting for RF_STATUS (RX) */
52367 /*! @name TIMING02 - TSM_TIMING02 */
52372 /*! RF_PRIORITY_TX_HI - Assertion time setting for RF_PRIORITY (TX) */
52377 /*! RF_PRIORITY_TX_LO - De-assertion time setting for RF_PRIORITY (TX) */
52382 /*! RF_PRIORITY_RX_HI - Assertion time setting for RF_PRIORITY (RX) */
52387 /*! RF_PRIORITY_RX_LO - De-assertion time setting for RF_PRIORITY (RX) */
52391 /*! @name TIMING03 - TSM_TIMING03 */
52396 /*! IRQ0_START_TRIG_TX_HI - Assertion time setting for IRQ0_START_TRIG (TX) */
52401 /*! IRQ0_START_TRIG_TX_LO - De-assertion time setting for IRQ0_START_TRIG (TX) */
52406 /*! IRQ0_START_TRIG_RX_HI - Assertion time setting for IRQ0_START_TRIG (RX) */
52411 /*! IRQ0_START_TRIG_RX_LO - De-assertion time setting for IRQ0_START_TRIG (RX) */
52415 /*! @name TIMING04 - TSM_TIMING04 */
52420 /*! IRQ1_STOP_TRIG_TX_HI - Assertion time setting for IRQ1_STOP_TRIG (TX) */
52425 /*! IRQ1_STOP_TRIG_TX_LO - De-assertion time setting for IRQ1_STOP_TRIG (TX) */
52430 /*! IRQ1_STOP_TRIG_RX_HI - Assertion time setting for IRQ1_STOP_TRIG (RX) */
52435 /*! IRQ1_STOP_TRIG_RX_LO - De-assertion time setting for IRQ1_STOP_TRIG (RX) */
52439 /*! @name TIMING05 - TSM_TIMING05 */
52444 /*! GPIO0_TRIG_EN_TX_HI - Assertion time setting for GPIO0_TRIG_EN (TX) */
52449 /*! GPIO0_TRIG_EN_TX_LO - De-assertion time setting for GPIO0_TRIG_EN (TX) */
52454 /*! GPIO0_TRIG_EN_RX_HI - Assertion time setting for GPIO0_TRIG_EN (RX) */
52459 /*! GPIO0_TRIG_EN_RX_LO - De-assertion time setting for GPIO0_TRIG_EN (RX) */
52463 /*! @name TIMING06 - TSM_TIMING06 */
52468 /*! GPIO1_TRIG_EN_TX_HI - Assertion time setting for GPIO1_TRIG_EN (TX) */
52473 /*! GPIO1_TRIG_EN_TX_LO - De-assertion time setting for GPIO1_TRIG_EN (TX) */
52478 /*! GPIO1_TRIG_EN_RX_HI - Assertion time setting for GPIO1_TRIG_EN (RX) */
52483 /*! GPIO1_TRIG_EN_RX_LO - De-assertion time setting for GPIO1_TRIG_EN (RX) */
52487 /*! @name TIMING07 - TSM_TIMING07 */
52492 /*! GPIO2_TRIG_EN_TX_HI - Assertion time setting for GPIO2_TRIG_EN (TX) */
52497 /*! GPIO2_TRIG_EN_TX_LO - De-assertion time setting for GPIO2_TRIG_EN (TX) */
52502 /*! GPIO2_TRIG_EN_RX_HI - Assertion time setting for GPIO2_TRIG_EN (RX) */
52507 /*! GPIO2_TRIG_EN_RX_LO - De-assertion time setting for GPIO2_TRIG_EN (RX) */
52511 /*! @name TIMING08 - TSM_TIMING08 */
52516 /*! GPIO3_TRIG_EN_TX_HI - Assertion time setting for GPIO3_TRIG_EN (TX) */
52521 /*! GPIO3_TRIG_EN_TX_LO - De-assertion time setting for GPIO3_TRIG_EN (TX) */
52526 /*! GPIO3_TRIG_EN_RX_HI - Assertion time setting for GPIO3_TRIG_EN (RX) */
52531 /*! GPIO3_TRIG_EN_RX_LO - De-assertion time setting for GPIO3_TRIG_EN (RX) */
52535 /*! @name TIMING09 - TSM_TIMING09 */
52540 /*! DCOC_GAIN_CFG_EN_TX_HI - Assertion time setting for DCOC_GAIN_CFG_EN (TX) */
52545 /*! DCOC_GAIN_CFG_EN_TX_LO - De-assertion time setting for DCOC_GAIN_CFG_EN (TX) */
52550 /*! DCOC_GAIN_CFG_EN_RX_HI - Assertion time setting for DCOC_GAIN_CFG_EN (RX) */
52555 /*! DCOC_GAIN_CFG_EN_RX_LO - De-assertion time setting for DCOC_GAIN_CFG_EN (RX) */
52559 /*! @name TIMING10 - TSM_TIMING10 */
52564 /*! LDO_CAL_EN_TX_HI - Assertion time setting for LDO_CAL_EN (TX) */
52569 /*! LDO_CAL_EN_TX_LO - De-assertion time setting for LDO_CAL_EN (TX) */
52574 /*! LDO_CAL_EN_RX_HI - Assertion time setting for LDO_CAL_EN (RX) */
52579 /*! LDO_CAL_EN_RX_LO - De-assertion time setting for LDO_CAL_EN (RX) */
52583 /*! @name TIMING11 - TSM_TIMING11 */
52588 /*! PLL_DIG_EN_TX_HI - Assertion time setting for PLL_DIG_EN (TX) */
52593 /*! PLL_DIG_EN_TX_LO - De-assertion time setting for PLL_DIG_EN (TX) */
52598 /*! PLL_DIG_EN_RX_HI - Assertion time setting for PLL_DIG_EN (RX) */
52603 /*! PLL_DIG_EN_RX_LO - De-assertion time setting for PLL_DIG_EN (RX) */
52607 /*! @name TIMING12 - TSM_TIMING12 */
52612 /*! SIGMA_DELTA_EN_TX_HI - Assertion time setting for SIGMA_DELTA_EN (TX) */
52617 /*! SIGMA_DELTA_EN_TX_LO - De-assertion time setting for SIGMA_DELTA_EN (TX) */
52622 /*! SIGMA_DELTA_EN_RX_HI - Assertion time setting for SIGMA_DELTA_EN (RX) */
52627 /*! SIGMA_DELTA_EN_RX_LO - De-assertion time setting for SIGMA_DELTA_EN (RX) */
52631 /*! @name TIMING13 - TSM_TIMING13 */
52636 /*! DCOC_CAL_EN_TX_HI - Assertion time setting for DCOC_CAL_EN (TX) */
52641 /*! DCOC_CAL_EN_TX_LO - De-assertion time setting for DCOC_CAL_EN (TX) */
52646 /*! DCOC_CAL_EN_RX_HI - Assertion time setting for DCOC_CAL_EN (RX) */
52651 /*! DCOC_CAL_EN_RX_LO - De-assertion time setting for DCOC_CAL_EN (RX) */
52655 /*! @name TIMING14 - TSM_TIMING14 */
52660 /*! TX_DIG_EN_TX_HI - Assertion time setting for TX_DIG_EN (TX) */
52665 /*! TX_DIG_EN_TX_LO - De-assertion time setting for TX_DIG_EN (TX) */
52669 /*! @name TIMING15 - TSM_TIMING15 */
52674 /*! FREQ_TARG_LD_EN_TX_HI - Assertion time setting for FREQ_TARG_LD_EN (TX) */
52679 /*! FREQ_TARG_LD_EN_TX_LO - De-assertion time setting for FREQ_TARG_LD_EN (TX) */
52684 /*! FREQ_TARG_LD_EN_RX_HI - Assertion time setting for FREQ_TARG_LD_EN (RX) */
52689 /*! FREQ_TARG_LD_EN_RX_LO - De-assertion time setting for FREQ_TARG_LD_EN (RX) */
52693 /*! @name TIMING16 - TSM_TIMING16 */
52698 /*! RX_INIT_RX_HI - Assertion time setting for RX_INIT (RX) */
52703 /*! RX_INIT_RX_LO - De-assertion time setting for RX_INIT (RX) */
52707 /*! @name TIMING17 - TSM_TIMING17 */
52712 /*! RX_DIG_EN_RX_HI - Assertion time setting for RX_DIG_EN (RX) */
52717 /*! RX_DIG_EN_RX_LO - De-assertion time setting for RX_DIG_EN (RX) */
52721 /*! @name TIMING18 - TSM_TIMING18 */
52726 /*! RX_PHY_EN_RX_HI - Assertion time setting for RX_PHY_EN (RX) */
52731 /*! RX_PHY_EN_RX_LO - De-assertion time setting for RX_PHY_EN (RX) */
52735 /*! @name TIMING19 - TSM_TIMING19 */
52740 /*! SEQ_BG_PUP_IBG_CAL_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_CAL (TX) */
52745 /*! SEQ_BG_PUP_IBG_CAL_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_CAL (TX) */
52750 /*! SEQ_BG_PUP_IBG_CAL_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_CAL (RX) */
52755 /*! SEQ_BG_PUP_IBG_CAL_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_CAL (RX) */
52759 /*! @name TIMING20 - TSM_TIMING20 */
52764 /*! SEQ_LDOTRIM_PUP_TX_HI - Assertion time setting for SEQ_LDOTRIM_PUP (TX) */
52769 /*! SEQ_LDOTRIM_PUP_TX_LO - De-assertion time setting for SEQ_LDOTRIM_PUP (TX) */
52774 /*! SEQ_LDOTRIM_PUP_RX_HI - Assertion time setting for SEQ_LDOTRIM_PUP (RX) */
52779 /*! SEQ_LDOTRIM_PUP_RX_LO - De-assertion time setting for SEQ_LDOTRIM_PUP (RX) */
52783 /*! @name TIMING21 - TSM_TIMING21 */
52788 /*! SEQ_LDO_CAL_PUP_TX_HI - Assertion time setting for SEQ_LDO_CAL_PUP (TX) */
52793 /*! SEQ_LDO_CAL_PUP_TX_LO - De-assertion time setting for SEQ_LDO_CAL_PUP (TX) */
52798 /*! SEQ_LDO_CAL_PUP_RX_HI - Assertion time setting for SEQ_LDO_CAL_PUP (RX) */
52803 /*! SEQ_LDO_CAL_PUP_RX_LO - De-assertion time setting for SEQ_LDO_CAL_PUP (RX) */
52807 /*! @name TIMING22 - TSM_TIMING22 */
52812 /*! SEQ_BG_FC_TX_HI - Assertion time setting for SEQ_BG_FC (TX) */
52817 /*! SEQ_BG_FC_TX_LO - De-assertion time setting for SEQ_BG_FC (TX) */
52822 /*! SEQ_BG_FC_RX_HI - Assertion time setting for SEQ_BG_FC (RX) */
52827 /*! SEQ_BG_FC_RX_LO - De-assertion time setting for SEQ_BG_FC (RX) */
52831 /*! @name TIMING23 - TSM_TIMING23 */
52836 /*! SEQ_LDO_GANG_FC_TX_HI - Assertion time setting for SEQ_LDO_GANG_FC (TX) */
52841 /*! SEQ_LDO_GANG_FC_TX_LO - De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (TX) */
52846 /*! SEQ_LDO_GANG_FC_RX_HI - Assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX) */
52851 /*! SEQ_LDO_GANG_FC_RX_LO - De-assertion time setting for SEQ_LDO_(PLL/RXTXHF/RXTXLF/VCO)_FC (RX) */
52855 /*! @name TIMING24 - TSM_TIMING24 */
52860 /*! SEQ_LDO_GANG_PUP_TX_HI - Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)…
52865 /*! SEQ_LDO_GANG_PUP_TX_LO - De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DI…
52870 /*! SEQ_LDO_GANG_PUP_RX_HI - Assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DIST)…
52875 /*! SEQ_LDO_GANG_PUP_RX_LO - De-assertion time setting for SEQ_LDO_(ANT/PLL/RXTXHF/RXTXLF/VCO/XO_DI…
52879 /*! @name TIMING25 - TSM_TIMING25 */
52884 /*! SEQ_LDO_LV_PUP_TX_HI - Assertion time setting for SEQ_LDO_LV_PUP (TX) */
52889 /*! SEQ_LDO_LV_PUP_TX_LO - De-assertion time setting for SEQ_LDO_LV_PUP (TX) */
52894 /*! SEQ_LDO_LV_PUP_RX_HI - Assertion time setting for SEQ_LDO_LV_PUP (RX) */
52899 /*! SEQ_LDO_LV_PUP_RX_LO - De-assertion time setting for SEQ_LDO_LV_PUP (RX) */
52903 /*! @name TIMING26 - TSM_TIMING26 */
52908 /*! SEQ_BG_PUP_TX_HI - Assertion time setting for SEQ_BG_PUP (TX) */
52913 /*! SEQ_BG_PUP_TX_LO - De-assertion time setting for SEQ_BG_PUP (TX) */
52918 /*! SEQ_BG_PUP_RX_HI - Assertion time setting for SEQ_BG_PUP (RX) */
52923 /*! SEQ_BG_PUP_RX_LO - De-assertion time setting for SEQ_BG_PUP (RX) */
52927 /*! @name TIMING27 - TSM_TIMING27 */
52932 /*! SEQ_BG_PUP_IBG_ANT_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_ANT (TX) */
52937 /*! SEQ_BG_PUP_IBG_ANT_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_ANT (TX) */
52942 /*! SEQ_BG_PUP_IBG_ANT_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_ANT (RX) */
52947 /*! SEQ_BG_PUP_IBG_ANT_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_ANT (RX) */
52951 /*! @name TIMING28 - TSM_TIMING28 */
52956 /*! SEQ_BG_PUP_IBG_XO_DIST_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX) */
52961 /*! SEQ_BG_PUP_IBG_XO_DIST_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (TX) */
52966 /*! SEQ_BG_PUP_IBG_XO_DIST_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX) */
52971 /*! SEQ_BG_PUP_IBG_XO_DIST_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_XO_DIST (RX) */
52975 /*! @name TIMING29 - TSM_TIMING29 */
52980 /*! SEQ_BG_PUP_IBG_TX_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_TX (TX) */
52985 /*! SEQ_BG_PUP_IBG_TX_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_TX (TX) */
52990 /*! SEQ_BG_PUP_IBG_TX_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_TX (RX) */
52995 /*! SEQ_BG_PUP_IBG_TX_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_TX (RX) */
52999 /*! @name TIMING30 - TSM_TIMING30 */
53004 /*! SEQ_BG_PUP_IBG_RX_TX_HI - Assertion time setting for SEQ_BG_PUP_IBG_RX (TX) */
53009 /*! SEQ_BG_PUP_IBG_RX_TX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_RX (TX) */
53014 /*! SEQ_BG_PUP_IBG_RX_RX_HI - Assertion time setting for SEQ_BG_PUP_IBG_RX (RX) */
53019 /*! SEQ_BG_PUP_IBG_RX_RX_LO - De-assertion time setting for SEQ_BG_PUP_IBG_RX (RX) */
53023 /*! @name TIMING31 - TSM_TIMING31 */
53028 /*! SEQ_TSM_ISO_B_2P4GHZ_TX_HI - Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX) */
53033 /*! SEQ_TSM_ISO_B_2P4GHZ_TX_LO - De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (TX) */
53038 /*! SEQ_TSM_ISO_B_2P4GHZ_RX_HI - Assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX) */
53043 /*! SEQ_TSM_ISO_B_2P4GHZ_RX_LO - De-assertion time setting for SEQ_TSM_ISO_B_2P4GHZ (RX) */
53047 /*! @name TIMING32 - TSM_TIMING32 */
53052 /*! SEQ_RCCAL_PUP_TX_HI - Assertion time setting for SEQ_RCCAL_PUP (TX) */
53057 /*! SEQ_RCCAL_PUP_TX_LO - De-assertion time setting for SEQ_RCCAL_PUP (TX) */
53062 /*! SEQ_RCCAL_PUP_RX_HI - Assertion time setting for SEQ_RCCAL_PUP (RX) */
53067 /*! SEQ_RCCAL_PUP_RX_LO - De-assertion time setting for SEQ_RCCAL_PUP (RX) */
53071 /*! @name TIMING33 - TSM_TIMING33 */
53076 /*! SEQ_PD_EN_FCAL_BIAS_TX_HI - Assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX) */
53081 /*! SEQ_PD_EN_FCAL_BIAS_TX_LO - De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (TX) */
53086 /*! SEQ_PD_EN_FCAL_BIAS_RX_HI - Assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX) */
53091 /*! SEQ_PD_EN_FCAL_BIAS_RX_LO - De-assertion time setting for SEQ_PD_EN_FCAL_BIAS (RX) */
53095 /*! @name TIMING34 - TSM_TIMING34 */
53100 /*! SEQ_PD_PUP_TX_HI - Assertion time setting for SEQ_PD_PUP (TX) */
53105 /*! SEQ_PD_PUP_TX_LO - De-assertion time setting for SEQ_PD_PUP (TX) */
53110 /*! SEQ_PD_PUP_RX_HI - Assertion time setting for SEQ_PD_PUP (RX) */
53115 /*! SEQ_PD_PUP_RX_LO - De-assertion time setting for SEQ_PD_PUP (RX) */
53119 /*! @name TIMING35 - TSM_TIMING35 */
53124 /*! SEQ_VCO_PUP_TX_HI - Assertion time setting for SEQ_VCO_PUP (TX) */
53129 /*! SEQ_VCO_PUP_TX_LO - De-assertion time setting for SEQ_VCO_PUP (TX) */
53134 /*! SEQ_VCO_PUP_RX_HI - Assertion time setting for SEQ_VCO_PUP (RX) */
53139 /*! SEQ_VCO_PUP_RX_LO - De-assertion time setting for SEQ_VCO_PUP (RX) */
53143 /*! @name TIMING36 - TSM_TIMING36 */
53148 /*! SEQ_XO_DIST_EN_TX_HI - Assertion time setting for SEQ_XO_DIST_EN (TX) */
53153 /*! SEQ_XO_DIST_EN_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN (TX) */
53158 /*! SEQ_XO_DIST_EN_RX_HI - Assertion time setting for SEQ_XO_DIST_EN (RX) */
53163 /*! SEQ_XO_DIST_EN_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN (RX) */
53167 /*! @name TIMING37 - TSM_TIMING37 */
53172 /*! SEQ_XO_DIST_EN_CLK_REF_TX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX) */
53177 /*! SEQ_XO_DIST_EN_CLK_REF_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (TX) */
53182 /*! SEQ_XO_DIST_EN_CLK_REF_RX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX) */
53187 /*! SEQ_XO_DIST_EN_CLK_REF_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_REF (RX) */
53191 /*! @name TIMING38 - TSM_TIMING38 */
53196 /*! SEQ_XO_EN_CLK_2P4G_TX_HI - Assertion time setting for SEQ_XO_EN_CLK_2P4G (TX) */
53201 /*! SEQ_XO_EN_CLK_2P4G_TX_LO - De-assertion time setting for SEQ_XO_EN_CLK_2P4G (TX) */
53206 /*! SEQ_XO_EN_CLK_2P4G_RX_HI - Assertion time setting for SEQ_XO_EN_CLK_2P4G (RX) */
53211 /*! SEQ_XO_EN_CLK_2P4G_RX_LO - De-assertion time setting for SEQ_XO_EN_CLK_2P4G (RX) */
53215 /*! @name TIMING39 - TSM_TIMING39 */
53220 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_TX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX) */
53225 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_TX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (TX) …
53230 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_RX_HI - Assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX) */
53235 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_RX_LO - De-assertion time setting for SEQ_XO_DIST_EN_CLK_ADCDAC (RX) …
53239 /*! @name TIMING40 - TSM_TIMING40 */
53244 /*! SEQ_DAC_PUP_TX_HI - Assertion time setting for SEQ_DAC_PUP (TX) */
53249 /*! SEQ_DAC_PUP_TX_LO - De-assertion time setting for SEQ_DAC_PUP (TX) */
53254 /*! SEQ_DAC_PUP_RX_HI - Assertion time setting for SEQ_DAC_PUP (RX) */
53259 /*! SEQ_DAC_PUP_RX_LO - De-assertion time setting for SEQ_DAC_PUP (RX) */
53263 /*! @name TIMING41 - TSM_TIMING41 */
53268 /*! SEQ_VCO_EN_HPM_TX_HI - Assertion time setting for SEQ_VCO_EN_HPM (TX) */
53273 /*! SEQ_VCO_EN_HPM_TX_LO - De-assertion time setting for SEQ_VCO_EN_HPM (TX) */
53278 /*! SEQ_VCO_EN_HPM_RX_HI - Assertion time setting for SEQ_VCO_EN_HPM (RX) */
53283 /*! SEQ_VCO_EN_HPM_RX_LO - De-assertion time setting for SEQ_VCO_EN_HPM (RX) */
53287 /*! @name TIMING42 - TSM_TIMING42 */
53292 /*! SEQ_LO_PUP_VLO_FBK_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_FBK (TX) */
53297 /*! SEQ_LO_PUP_VLO_FBK_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_FBK (TX) */
53302 /*! SEQ_LO_PUP_VLO_FBK_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_FBK (RX) */
53307 /*! SEQ_LO_PUP_VLO_FBK_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_FBK (RX) */
53311 /*! @name TIMING43 - TSM_TIMING43 */
53316 /*! SEQ_LO_PUP_VLO_RX_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RX (TX) */
53321 /*! SEQ_LO_PUP_VLO_RX_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RX (TX) */
53326 /*! SEQ_LO_PUP_VLO_RX_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RX (RX) */
53331 /*! SEQ_LO_PUP_VLO_RX_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RX (RX) */
53335 /*! @name TIMING44 - TSM_TIMING44 */
53340 /*! SEQ_LO_PUP_VLO_RXDRV_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX) */
53345 /*! SEQ_LO_PUP_VLO_RXDRV_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (TX) */
53350 /*! SEQ_LO_PUP_VLO_RXDRV_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX) */
53355 /*! SEQ_LO_PUP_VLO_RXDRV_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_RXDRV (RX) */
53359 /*! @name TIMING45 - TSM_TIMING45 */
53364 /*! SEQ_LO_PUP_VLO_TX_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TX (TX) */
53369 /*! SEQ_LO_PUP_VLO_TX_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TX (TX) */
53374 /*! SEQ_LO_PUP_VLO_TX_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TX (RX) */
53379 /*! SEQ_LO_PUP_VLO_TX_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TX (RX) */
53383 /*! @name TIMING46 - TSM_TIMING46 */
53388 /*! SEQ_LO_PUP_VLO_TXDRV_TX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX) */
53393 /*! SEQ_LO_PUP_VLO_TXDRV_TX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (TX) */
53398 /*! SEQ_LO_PUP_VLO_TXDRV_RX_HI - Assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX) */
53403 /*! SEQ_LO_PUP_VLO_TXDRV_RX_LO - De-assertion time setting for SEQ_LO_PUP_VLO_TXDRV (RX) */
53407 /*! @name TIMING47 - TSM_TIMING47 */
53412 /*! SEQ_DIVN_PUP_TX_HI - Assertion time setting for SEQ_DIVN_PUP (TX) */
53417 /*! SEQ_DIVN_PUP_TX_LO - De-assertion time setting for SEQ_DIVN_PUP (TX) */
53422 /*! SEQ_DIVN_PUP_RX_HI - Assertion time setting for SEQ_DIVN_PUP (RX) */
53427 /*! SEQ_DIVN_PUP_RX_LO - De-assertion time setting for SEQ_DIVN_PUP (RX) */
53431 /*! @name TIMING48 - TSM_TIMING48 */
53436 /*! SEQ_DIVN_CLOSEDLOOP_TX_HI - Assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX) */
53441 /*! SEQ_DIVN_CLOSEDLOOP_TX_LO - De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (TX) */
53446 /*! SEQ_DIVN_CLOSEDLOOP_RX_HI - Assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX) */
53451 /*! SEQ_DIVN_CLOSEDLOOP_RX_LO - De-assertion time setting for SEQ_DIVN_CLOSEDLOOP (RX) */
53455 /*! @name TIMING49 - TSM_TIMING49 */
53460 /*! SEQ_PD_EN_PD_DRV_TX_HI - Assertion time setting for SEQ_PD_EN_PD_DRV (TX) */
53465 /*! SEQ_PD_EN_PD_DRV_TX_LO - De-assertion time setting for SEQ_PD_EN_PD_DRV (TX) */
53470 /*! SEQ_PD_EN_PD_DRV_RX_HI - Assertion time setting for SEQ_PD_EN_PD_DRV (RX) */
53475 /*! SEQ_PD_EN_PD_DRV_RX_LO - De-assertion time setting for SEQ_PD_EN_PD_DRV (RX) */
53479 /*! @name TIMING50 - TSM_TIMING50 */
53484 /*! SEQ_CBPF_EN_DCOC_TX_HI - Assertion time setting for SEQ_CBPF_EN_DCOC (TX) */
53489 /*! SEQ_CBPF_EN_DCOC_TX_LO - De-assertion time setting for SEQ_CBPF_EN_DCOC (TX) */
53494 /*! SEQ_CBPF_EN_DCOC_RX_HI - Assertion time setting for SEQ_CBPF_EN_DCOC (RX) */
53499 /*! SEQ_CBPF_EN_DCOC_RX_LO - De-assertion time setting for SEQ_CBPF_EN_DCOC (RX) */
53503 /*! @name TIMING51 - TSM_TIMING51 */
53508 /*! SEQ_RX_GANG_PUP_TX_HI - Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPA…
53513 /*! SEQ_RX_GANG_PUP_TX_LO - De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_…
53518 /*! SEQ_RX_GANG_PUP_RX_HI - Assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_SPA…
53523 /*! SEQ_RX_GANG_PUP_RX_LO - De-assertion time setting for SEQ_(RX_LAN/RX_MIX/CBPF/ADC_PUP) and SEQ_…
53527 /*! @name TIMING52 - TSM_TIMING52 */
53532 /*! SEQ_SPARE3_TX_HI - Assertion time setting for SEQ_SPARE3 (TX) */
53537 /*! SEQ_SPARE3_TX_LO - De-assertion time setting for SEQ_SPARE3 (TX) */
53542 /*! SEQ_SPARE3_RX_HI - Assertion time setting for SEQ_SPARE3 (RX) */
53547 /*! SEQ_SPARE3_RX_LO - De-assertion time setting for SEQ_SPARE3 (RX) */
53551 /*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */
53556 /*! TSM_RF_ACTIVE_OVRD_EN - Override control for TSM_RF_ACTIVE
53564 /*! TSM_RF_ACTIVE_OVRD - Override value for tsm_rf_active */
53569 /*! TSM_RF_STATUS_OVRD_EN - Override control for TSM_RF_STATUS_EN
53577 /*! TSM_RF_STATUS_OVRD - Override value for TSM_RF_STATUS */
53582 /*! TSM_RF_PRIORITY_OVRD_EN - Override control for TSM_RF_PRIORITY_EN
53590 /*! TSM_RF_PRIORITY_OVRD - Override value for tsm_rf_priority */
53595 /*! TSM_IRQ0_START_TRIG_OVRD_EN - Override control for TSM_IRQ0_START_TRIG_EN
53603 /*! TSM_IRQ0_START_TRIG_OVRD - Override value for TSM_IRQ0_START_TRIG */
53608 /*! TSM_IRQ1_STOP_TRIG_OVRD_EN - Override control for TSM_IRQ1_STOP_TRIG
53616 /*! TSM_IRQ1_STOP_TRIG_OVRD - Override value for TSM_IRQ1_STOP_TRIG */
53621 /*! DCOC_GAIN_CFG_EN_OVRD_EN - Override control for DCOC_GAIN_CFG_EN
53629 /*! DCOC_GAIN_CFG_EN_OVRD - Override value for DCOC_GAIN_CFG_EN */
53634 /*! LDO_CAL_EN_OVRD_EN - Override control for LDO_CAL_EN_
53642 /*! LDO_CAL_EN_OVRD - Override value for LDO_CAL_EN */
53647 /*! PLL_DIG_EN_OVRD_EN - Override control for PLL_DIG_EN
53655 /*! PLL_DIG_EN_OVRD - Override value for PLL_DIG_EN */
53660 /*! SIGMA_DELTA_EN_OVRD_EN - Override control for SIGMA_DELTA_EN
53668 /*! SIGMA_DELTA_EN_OVRD - Override value for SIGMA_DELTA_EN */
53673 /*! DCOC_CAL_EN_OVRD_EN - Override control for DCOC_CAL_EN
53681 /*! DCOC_CAL_EN_OVRD - Override value for DCOC_CAL_EN */
53686 /*! TX_DIG_EN_OVRD_EN - Override control for TX_DIG_EN
53694 /*! TX_DIG_EN_OVRD - Override value for TX_DIG_EN */
53699 /*! FREQ_TARG_LD_EN_OVRD_EN - Override control for FREQ_TARG_LD_EN
53707 /*! FREQ_TARG_LD_EN_OVRD - Override value for FREQ_TARG_LD_EN */
53712 /*! RX_INIT_EN_OVRD_EN - Override control for RX_INIT_EN
53720 /*! RX_INIT_EN_OVRD - Override value for RX_INIT_EN */
53725 /*! RX_DIG_EN_OVRD_EN - Override control for RX_DIG_EN
53733 /*! RX_DIG_EN_OVRD - Override value for RX_DIG_EN */
53738 /*! RX_PHY_EN_OVRD_EN - Override control for RX_PHY_EN
53746 /*! RX_PHY_EN_OVRD - Override value for RX_PHY_EN */
53751 /*! SEQ_BG_PUP_IBG_CAL_OVRD_EN - Override control for SEQ_BG_PUP_IBG_CAL
53759 /*! SEQ_BG_PUP_IBG_CAL_OVRD - Override value for SEQ_BG_PUP_IBG_CAL */
53763 /*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */
53768 /*! SEQ_LDOTRIM_PUP_OVRD_EN - Override control for SEQ_LDOTRIM_PUP
53776 /*! SEQ_LDOTRIM_PUP_OVRD - Override value for SEQ_LDOTRIM_PUP */
53781 /*! SEQ_LDO_CAL_PUP_OVRD_EN - Override control for SEQ_LDO_CAL_PUP
53789 /*! SEQ_LDO_CAL_PUP_OVRD - Override value for SEQ_LDO_CAL_PUP */
53794 /*! SEQ_BG_FC_OVRD_EN - Override control for SEQ_BG_FC
53802 /*! SEQ_BG_FC_OVRD - Override value for SEQ_BG_FC */
53807 /*! SEQ_LDO_PLL_FC_OVRD_EN - Override control for SEQ_LDO_PLL_FC
53815 /*! SEQ_LDO_PLL_FC_OVRD - Override value for SEQ_LDO_PLL_FC */
53820 /*! SEQ_LDO_VCO_FC_OVRD_EN - Override control for SEQ_LDO_VCO_FC
53828 /*! SEQ_LDO_VCO_FC_OVRD - Override value for SEQ_LDO_VCO_FC */
53833 /*! SEQ_LDO_RXTXHF_FC_OVRD_EN - Override control for SEQ_LDO_RXTXHF_FC
53841 /*! SEQ_LDO_RXTXHF_FC_OVRD - Override value for SEQ_LDO_RXTXHF_FC */
53846 /*! SEQ_LDO_RXTXLF_FC_OVRD_EN - Override control for SEQ_LDO_RXTXLF_FC
53854 /*! SEQ_LDO_RXTXLF_FC_OVRD - Override value for SEQ_LDO_RXTXLF_FC */
53859 /*! SEQ_LDO_ANT_PUP_OVRD_EN - Override control for SEQ_LDO_ANT_PUP
53867 /*! SEQ_LDO_ANT_PUP_OVRD - Override value for SEQ_LDO_ANT_PUP */
53872 /*! SEQ_LDO_PLL_PUP_OVRD_EN - Override control for SEQ_LDO_PLL_PUP
53880 /*! SEQ_LDO_PLL_PUP_OVRD - Override value for SEQ_LDO_PLL_PUP */
53885 /*! SEQ_LDO_VCO_PUP_OVRD_EN - Override control for SEQ_LDO_VCO_PUP
53893 /*! SEQ_LDO_VCO_PUP_OVRD - Override value for SEQ_LDO_VCO_PUP */
53898 /*! SEQ_LDO_XO_DIST_PUP_OVRD_EN - Override control for SEQ_LDO_XO_DIST_PUP
53906 /*! SEQ_LDO_XO_DIST_PUP_OVRD - Override value for SEQ_LDO_XO_DIST_PUP */
53911 /*! SEQ_LDO_RXTXHF_PUP_OVRD_EN - Override control for SEQ_LDO_RXTXHF_PUP
53919 /*! SEQ_LDO_RXTXHF_PUP_OVRD - Override value for SEQ_LDO_RXTXHF_PUP */
53924 /*! SEQ_LDO_RXTXLF_PUP_OVRD_EN - Override control for SEQ_LDO_RXTXLF_PUP
53932 /*! SEQ_LDO_RXTXLF_PUP_OVRD - Override value for SEQ_LDO_RXTXLF_PUP */
53937 /*! SEQ_LDO_LV_PUP_OVRD_EN - Override control for SEQ_LDO_LV_PUP
53945 /*! SEQ_LDO_LV_PUP_OVRD - Override value for SEQ_LDO_LV_PUP */
53950 /*! SEQ_BG_PUP_OVRD_EN - Override control for SEQ_BG_PUP_OVRD_EN
53958 /*! SEQ_BG_PUP_OVRD - Override value for SEQ_BG_PUP */
53963 /*! SEQ_BG_PUP_IBG_ANT_OVRD_EN - Override control for SEQ_BG_PUP_IBG_ANT
53971 /*! SEQ_BG_PUP_IBG_ANT_OVRD - Override value for SEQ_BG_PUP_IBG_ANT */
53975 /*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */
53980 /*! SEQ_BG_PUP_IBG_XO_DIST_OVRD_EN - Override control for SEQ_BG_PUP_IBG_XO_DIST
53988 /*! SEQ_BG_PUP_IBG_XO_DIST_OVRD - Override value for SEQ_BG_PUP_IBG_XO_DIST */
53993 /*! SEQ_BG_PUP_IBG_TX_OVRD_EN - Override control for SEQ_BG_PUP_IBG_TX
54001 /*! SEQ_BG_PUP_IBG_TX_OVRD - Override value for SEQ_BG_PUP_IBG_TX */
54006 /*! SEQ_BG_PUP_IBG_RX_OVRD_EN - Override control for SEQ_BG_PUP_IBG_RX
54014 /*! SEQ_BG_PUP_IBG_RX_OVRD - Override value for SEQ_BG_PUP_IBG_RX */
54019 /*! SEQ_TSM_ISO_B_2P4GHZ_OVRD_EN - Override control for SEQ_TSM_ISO_B_2P4GHZ
54027 /*! SEQ_TSM_ISO_B_2P4GHZ_OVRD - Override value for SEQ_TSM_ISO_B_2P4GHZ */
54032 /*! SEQ_RCCAL_PUP_OVRD_EN - Override control for SEQ_RCCAL_PUP
54040 /*! SEQ_RCCAL_PUP_OVRD - Override value for SEQ_RCCAL_PUP */
54045 /*! SEQ_PD_EN_FCAL_BIAS_OVRD_EN - Override control for SEQ_PD_EN_FCAL_BIAS
54053 /*! SEQ_PD_EN_FCAL_BIAS_OVRD - Override value for SEQ_PD_EN_FCAL_BIAS */
54058 /*! SEQ_PD_PUP_OVRD_EN - Override control for SEQ_PD_PUP
54066 /*! SEQ_PD_PUP_OVRD - Override value for SEQ_PD_PUP */
54071 /*! SEQ_VCO_PUP_OVRD_EN - Override control for SEQ_VCO_PUP
54079 /*! SEQ_VCO_PUP_OVRD - Override value for SEQ_VCO_PUP */
54084 /*! SEQ_XO_DIST_EN_OVRD_EN - Override control for SEQ_XO_DIST_EN
54092 /*! SEQ_XO_DIST_EN_OVRD - Override value for SEQ_XO_DIST_EN */
54097 /*! SEQ_XO_DIST_EN_CLK_REF_OVRD_EN - Override control for SEQ_XO_DIST_EN_CLK_REF
54105 /*! SEQ_XO_DIST_EN_CLK_REF_OVRD - Override value for SEQ_XO_DIST_EN_CLK_REF */
54110 /*! SEQ_XO_EN_CLK_2P4G_OVRD_EN - Override control for SEQ_XO_EN_CLK_2P4G
54118 /*! SEQ_XO_EN_CLK_2P4G_OVRD - Override value for SEQ_XO_EN_CLK_2P4G_OVRD_EN */
54123 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD_EN - Override control for SEQ_XO_DIST_EN_CLK_ADCDAC
54131 /*! SEQ_XO_DIST_EN_CLK_ADCDAC_OVRD - Override value for SEQ_XO_DIST_EN_CLK_ADCDAC */
54136 /*! SEQ_DAC_PUP_OVRD_EN - Override control for SEQ_DAC_PUP
54144 /*! SEQ_DAC_PUP_OVRD - Override value for SEQ_DAC_PUP */
54149 /*! SEQ_VCO_EN_HPM_OVRD_EN - Override control for SEQ_VCO_EN_HPM
54157 /*! SEQ_VCO_EN_HPM_OVRD - Override value for SEQ_VCO_EN_HPM */
54162 /*! SEQ_LO_PUP_VLO_FBK_OVRD_EN - Override control for SEQ_LO_PUP_VLO_FBK
54170 /*! SEQ_LO_PUP_VLO_FBK_OVRD - Override value for SEQ_LO_PUP_VLO_FBK */
54175 /*! SEQ_LO_PUP_VLO_RXDRV_OVRD_EN - Override control for SEQ_LO_PUP_VLO_RXDRV
54183 /*! SEQ_LO_PUP_VLO_RXDRV_OVRD - Override value for SEQ_LO_PUP_VLO_RXDRV */
54187 /*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */
54192 /*! SEQ_LO_PUP_VLO_RX_OVRD_EN - Override control for SEQ_LO_PUP_VLO_RX
54200 /*! SEQ_LO_PUP_VLO_RX_OVRD - Override value for SEQ_LO_PUP_VLO_RX */
54205 /*! SEQ_LO_PUP_VLO_TX_OVRD_EN - Override control for SEQ_LO_PUP_VLO_TX
54213 /*! SEQ_LO_PUP_VLO_TX_OVRD - Override value for SEQ_LO_PUP_VLO_TX */
54218 /*! SEQ_LO_PUP_VLO_TXDRV_OVRD_EN - Override control for SEQ_LO_PUP_VLO_TXDRV
54226 /*! SEQ_LO_PUP_VLO_TXDRV_OVRD - Override value for SEQ_LO_PUP_VLO_TXDRV */
54231 /*! SEQ_DIVN_PUP_OVRD_EN - Override control for SEQ_DIVN_PUP
54239 /*! SEQ_DIVN_PUP_OVRD - Override value for SEQ_DIVN_PUP */
54244 /*! SEQ_DIVN_OPENLOOP_OVRD_EN - Override control for SEQ_DIVN_OPENLOOP
54252 /*! SEQ_DIVN_OPENLOOP_OVRD - Override value for SEQ_DIVN_OPENLOOP */
54257 /*! SEQ_PD_EN_PD_DRV_OVRD_EN - Override control for SEQ_PD_EN_PD_DRV
54265 /*! SEQ_PD_EN_PD_DRV_OVRD - Override value for SEQ_PD_EN_PD_DRV */
54270 /*! SEQ_CBPF_EN_DCOC_OVRD_EN - Override control for SEQ_CBPF_EN_DCOC
54278 /*! SEQ_CBPF_EN_DCOC_OVRD - Override value for SEQ_CBPF_EN_DCOC */
54283 /*! SEQ_RX_LNA_PUP_OVRD_EN - Override control for SEQ_RX_LNA_PUP
54291 /*! SEQ_RX_LNA_PUP_OVRD - Override value for SEQ_RX_LNA_PUP */
54296 /*! SEQ_ADC_PUP_OVRD_EN - Override control for SEQ_ADC_PUP
54304 /*! SEQ_ADC_PUP_OVRD - Override value for RX_DIG_EN */
54309 /*! SEQ_CBPF_PUP_OVRD_EN - Override control for SEQ_CBPF_PUP
54317 /*! SEQ_CBPF_PUP_OVRD - Override value for SEQ_CBPF_PUP */
54322 /*! SEQ_RX_MIX_PUP_OVRD_EN - Override control for SEQ_RX_MIX_PUP
54330 /*! SEQ_RX_MIX_PUP_OVRD - Override control for SEQ_RX_MIX_PUP
54338 /*! SEQ_SPARE1_OVRD_EN - Override control for SEQ_SPARE1
54346 /*! SEQ_SPARE1_OVRD - Override value for SEQ_SPARE1 */
54351 /*! SEQ_SPARE3_OVRD_EN - Override control for SEQ_SPARE3
54359 /*! SEQ_SPARE3_OVRD - Override value for SEQ_SPARE3 */
54364 /*! TX_MODE_OVRD_EN - Override control for TX_MODE_OVRD
54372 /*! TX_MODE_OVRD - Override value for TX_MODE */
54377 /*! RX_MODE_OVRD_EN - Override control for RX_MODE
54385 /*! RX_MODE_OVRD - Override value for RX_MODE */
54395 /* XCVR_TSM - Peripheral instance base addresses */
54429 /* ----------------------------------------------------------------------------
54430 -- XCVR_TX_DIG Peripheral Access Layer
54431 ---------------------------------------------------------------------------- */
54438 /** XCVR_TX_DIG - Register Layout Typedef */
54466 /* ----------------------------------------------------------------------------
54467 -- XCVR_TX_DIG Register Masks
54468 ---------------------------------------------------------------------------- */
54475 /*! @name TXDIG_CTRL - TXDIG_CTRL */
54480 /*! MODULATOR_SEL - MODULATOR_SEL */
54485 /*! PFC_EN - PFC_EN */
54490 /*! DATA_STREAM_SEL - DATA_STREAM_SEL */
54495 /*! INV_DATA_OUT - INV_DATA_OUT */
54499 /*! @name DATA_PADDING_CTRL - DATA_PADDING_CTRL */
54504 /*! DATA_PADDING_SEL - DATA_PADDING_SEL */
54509 /*! TX_CAPTURE_POL - TX_CAPTURE_POL */
54514 /*! CTE_DATA - CTE_DATA */
54519 /*! PAD_DLY - PAD_DLY */
54524 /*! PAD_DLY_EN - PAD_DLY_EN */
54529 /*! RAMP_DN_PAD_EN - RAMP_DN_PAD_EN */
54533 /*! @name DATA_PADDING_CTRL_1 - DATA_PADDING_CTRL_1 */
54538 /*! RAMP_UP_DLY - RAMP_UP_DLY */
54543 /*! TX_DATA_FLUSH_DLY - TX_DATA_FLUSH_DLY */
54548 /*! PA_PUP_ADJ - PA_PUP_ADJ */
54552 /*! @name DATA_PADDING_CTRL_2 - DATA_PADDING_CTRL_2 */
54557 /*! DATA_PAD_MFDEV - DATA_PAD_MFDEV */
54562 /*! DATA_PAD_PFDEV - DATA_PAD_PFDEV */
54566 /*! @name FSK_CTRL - FSK_CTRL */
54571 /*! FSK_FDEV_0 - FSK_FDEV_0 */
54576 /*! FSK_FDEV_1 - FSK_FDEV_1 */
54580 /*! @name GFSK_CTRL - GFSK_CTRL */
54585 /*! GFSK_FDEV - GFSK_FDEV */
54590 /*! GFSK_COEFF_MAN - GFSK_COEFF_MAN */
54595 /*! BT_EQ_OR_GTR_ONE - BT_EQ_OR_GTR_ONE */
54599 /*! @name GFSK_COEFF_0_1 - GFSK_COEFF_0_1 */
54604 /*! GFSK_COEFF_0 - GFSK_COEFF_0 */
54609 /*! GFSK_COEFF_1 - GFSK_COEFF_1 */
54613 /*! @name GFSK_COEFF_2_3 - GFSK_COEFF_2_3 */
54618 /*! GFSK_COEFF_2 - GFSK_COEFF_2 */
54623 /*! GFSK_COEFF_3 - GFSK_COEFF_3 */
54627 /*! @name GFSK_COEFF_4_5 - GFSK_COEFF_4_5 */
54632 /*! GFSK_COEFF_4 - GFSK_COEFF_4 */
54637 /*! GFSK_COEFF_5 - GFSK_COEFF_5 */
54641 /*! @name GFSK_COEFF_6_7 - GFSK_COEFF_6_7 */
54646 /*! GFSK_COEFF_6 - GFSK_COEFF_6 */
54651 /*! GFSK_COEFF_7 - GFSK_COEFF_7 */
54655 /*! @name IMAGE_FILTER_CTRL - IMAGE_FILTER_CTRL */
54660 /*! IMAGE_FIR_FILTER_SEL - IMAGE_FIR_FILTER_SEL */
54665 /*! IMAGE_FILTER_OVRD_EN - IMAGE_FILTER_OVRD_EN */
54670 /*! IMAGE_FIR_FILTER_OVRD - IMAGE_FIR_FILTER_OVRD */
54675 /*! IMAGE_SYNC1_FILTER_OVRD - IMAGE_SYNC1_FILTER_OVRD */
54680 /*! IMAGE_SYNC0_FILTER_OVRD - IMAGE_SYNC0_FILTER_OVRD */
54685 /*! FREQ_WORD_ADJ - FREQ_WORD_ADJ */
54689 /*! @name PA_CTRL - PA_CTRL */
54694 /*! PA_TGT_POWER - PA_TGT_POWER */
54699 /*! TGT_PWR_SRC - TGT_PWR_SRC */
54704 /*! EARLY_WU_COMPLETE - EARLY_WU_COMPLETE */
54709 /*! RAMP_CS - RAMP_CS */
54714 /*! PA_RAMP_SEL - PA_RAMP_SEL */
54719 /*! TX_PA_PUP_OVRD - TX_PA_PUP_OVRD */
54724 /*! TX_PA_PUP_OVRD_EN - TX_PA_PUP_OVRD_EN */
54728 /*! @name PA_RAMP_TBL0 - PA_RAMP_TBL0 */
54733 /*! PA_RAMP0 - PA_RAMP0 */
54738 /*! PA_RAMP1 - PA_RAMP1 */
54743 /*! PA_RAMP2 - PA_RAMP2 */
54748 /*! PA_RAMP3 - PA_RAMP3 */
54752 /*! @name PA_RAMP_TBL1 - PA_RAMP_TBL1 */
54757 /*! PA_RAMP4 - PA_RAMP4 */
54762 /*! PA_RAMP5 - PA_RAMP5 */
54767 /*! PA_RAMP6 - PA_RAMP6 */
54772 /*! PA_RAMP7 - PA_RAMP7 */
54776 /*! @name PA_RAMP_TBL2 - PA_RAMP_TBL2 */
54781 /*! PA_RAMP8 - PA_RAMP8 */
54786 /*! PA_RAMP9 - PA_RAMP9 */
54791 /*! PA_RAMP10 - PA_RAMP10 */
54796 /*! PA_RAMP11 - PA_RAMP11 */
54800 /*! @name PA_RAMP_TBL3 - PA_RAMP_TBL3 */
54805 /*! PA_RAMP12 - PA_RAMP12 */
54810 /*! PA_RAMP13 - PA_RAMP13 */
54815 /*! PA_RAMP14 - PA_RAMP14 */
54820 /*! PA_RAMP15 - PA_RAMP15 */
54824 /*! @name SWITCH_TX_CTRL - SWITCH_TX_CTRL */
54829 /*! SWITCH_MOD - SWITCH_MOD */
54834 /*! SWITCH_FIR_SEL - SWITCH_FIR_SEL */
54839 /*! SWITCH_GFSK_COEFF - SWITCH_GFSK_COEFF */
54844 /*! SWITCH_TGT_PWR - SWITCH_TGT_PWR */
54848 /*! @name RF_DFT_TX_CTRL0 - RF_DFT_TX_CTRL0 */
54853 /*! DFT_MAX_RAM_SIZE - DFT_MAX_RAM_SIZE */
54858 /*! DFT_RAM_BASE_ADDR - DFT_RAM_BASE_ADDR */
54863 /*! DFT_RAM_EN - DFT_RAM_EN */
54867 /*! @name RF_DFT_TX_CTRL1 - RF_DFT_TX_CTRL1 */
54872 /*! LFSR_OUT - LFSR_OUT */
54877 /*! LFSR_CLK_SEL - LFSR_CLK_SEL */
54882 /*! LFSR_LENGTH - LFSR_LENGTH */
54887 /*! LRM - LRM */
54892 /*! LFSR_EN - LFSR_EN */
54896 /*! @name RF_DFT_TX_CTRL2 - RF_DFT_TX_CTRL2 */
54901 /*! DFT_PA_AM_MOD_FREQ - DFT_PA_AM_MOD_FREQ */
54906 /*! DFT_PA_AM_MOD_ENTRIES - DFT_PA_AM_MOD_ENTRIES */
54911 /*! DFT_PA_AM_MOD_EN - DFT_PA_AM_MOD_EN */
54916 /*! DFT_PATTERN_EN - DFT_PATTERN_EN */
54920 /*! @name RF_DFT_PATTERN - RF_DFT_PATTERN */
54925 /*! DFT_MOD_PATTERN - DFT_MOD_PATTERN */
54929 /*! @name DATARATE_CONFIG_FSK_CTRL - DATARATE_CONFIG_FSK_CTRL */
54934 /*! DATARATE_CONFIG_FSK_FDEV0 - DATARATE_CONFIG_DATA_PAD_MFDEV */
54939 /*! DATARATE_CONFIG_FSK_FDEV1 - DATARATE_CONFIG_DATA_PAD_PFDEV */
54943 /*! @name DATARATE_CONFIG_GFSK_CTRL - DATARATE_CONFIG_GFSK_CTRL */
54948 /*! DATARATE_CONFIG_GFSK_FDEV - DATARATE_CONFIG_GFSK_FDEV */
54952 /*! @name DATARATE_CONFIG_FILTER_CTRL - DATARATE_CONFIG_FILTER_CTRL */
54957 /*! DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN - DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN */
54962 /*! DATARATE_CONFIG_FIR_FILTER_OVRD - DATARATE_CONFIG_FIR_FILTER_OVRD */
54967 /*! DATARATE_CONFIG_SYNC0_FILTER_OVRD - DATARATE_CONFIG_SYNC0_FILTER_OVRD */
54972 /*! DATARATE_CONFIG_SYNC1_FILTER_OVRD - DATARATE_CONFIG_SYNC1_FILTER_OVRD */
54977 /*! DATARATE_CONFIG_GFSK_FILT_CLK_SEL - DATARATE_CONFIG_GFSK_FILT_CLK_SEL */
54982 /*! DATARATE_CONFIG_SYNC0_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC0_CLK_SEL */
54987 /*! DATARATE_CONFIG_SYNC1_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC1_CLK_SEL */
54992 /*! DATARATE_CONFIG_IMAGE_FIR_CLK_SEL - DATARATE_CONFIG_IMAGE_FIR_CLK_SEL */
55002 /* XCVR_TX_DIG - Peripheral instance base addresses */
55036 /* ----------------------------------------------------------------------------
55037 -- XCVR_ZBDEMOD Peripheral Access Layer
55038 ---------------------------------------------------------------------------- */
55045 /** XCVR_ZBDEMOD - Register Layout Typedef */
55060 /* ----------------------------------------------------------------------------
55061 -- XCVR_ZBDEMOD Register Masks
55062 ---------------------------------------------------------------------------- */
55069 /*! @name CORR_CTRL - 802.15.4 DEMOD CORRELATOR CONTROL */
55074 /*! CORR_VT - CORR_VT */
55079 /*! CORR_NVAL - CORR_NVAL */
55084 /*! MAX_CORR_EN - MAX_CORR_EN */
55089 /*! ZBDEM_CLK_ON - Force 802.15.4 Demodulator Clock On
55097 /*! RX_MAX_CORR - RX_MAX_CORR */
55102 /*! RX_MAX_PREAMBLE - RX_MAX_PREAMBLE */
55106 /*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */
55111 /*! PN_TYPE - PN_TYPE */
55116 /*! TX_INV - TX_INV */
55120 /*! @name PN_CODE - 802.15.4 DEMOD PN CODE */
55125 /*! PN_LSB - PN_LSB */
55130 /*! PN_MSB - PN_MSB */
55134 /*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */
55139 /*! SYNC_PER - Symbol Sync Tracking Period */
55144 /*! TRACK_ENABLE - TRACK_ENABLE
55151 /*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */
55156 /*! CCA1_FROM_RX_DIG - Selects the Source of CCA1 (Clear Channel Assessment Mode 1) Information Pro…
55164 /*! LQI_FROM_RX_DIG - Selects the Source of LQI (Link Quality Indicator) Information Provided to th…
55172 /*! LQI_START_AT_SFD - Select Start Point for LQI Computation
55180 /*! ZBDEM_CCA_CLK_ON - 802.15.4 Demodulator CCA Clock Enable */
55184 /*! @name FAD_LPPS_THR - FAD CORRELATOR THRESHOLD */
55189 /*! FAD_THR - FAD_THR */
55194 /*! FAD_FILL1 - Pre-detection buffer filling duration */
55199 /*! LPPS_FILL_COUNT - Wait duration after lpps_lp_enable is de-asserted */
55204 /*! LPPS_LP_EN_COUNT - LPPS_LP_EN high time */
55208 /*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */
55213 /*! AFC_EN - AFC_EN
55221 /*! DCD_EN - DCD_EN
55229 /*! AFC_OUT - AFC_OUT */
55233 /*! @name CCA2_CTRL - CCA MODE 2 CONTROL REGISTER */
55238 /*! CCA2_INTERVAL - CCA Mode 2 Measurement Window Duration
55248 /*! USE_DEMOD_CCA2 - Selects CCA Mode 2 Computation Engine
55250 * 0b1..Use 802.15.4 demodulator-based (legacy) CCA Mode 2 Engine (default)
55256 /*! CCA2_REF_SEQ - CCA Mode 2 Sequence Address */
55260 /*! @name CCA2_THRESH - CCA MODE 2 CONTROL REGISTER */
55265 /*! CCA2_CNT_THRESH - CCA Mode 2 Count Threshold */
55270 /*! CCA2_SYM_THRESH - CCA Mode 2 Symbol Threshold */
55274 /*! @name CCA2_STATUS - CCA MODE 2 STATUS REGISTER */
55279 /*! CCA2_CNT_MAX - CCA Mode 2 Maximum Count */
55284 /*! CCA2_COMPLETE - CCA Mode 2 Measurement Complete */
55289 /*! CCA2_CHANNEL_STATE - CCA Mode 2 Channel State */
55294 /*! CCA2_CNT_SYM - CCA Mode 2 Repetition Sequence Addresses Count */
55298 /*! @name CORR_CTRL2 - 802.15.4 DEMOD CORRELATOR CONTROL2 */
55303 /*! EARLY_PD_THRESH - EARLY_PD_THRESH */
55313 /* XCVR_ZBDEMOD - Peripheral instance base addresses */
55347 /* ----------------------------------------------------------------------------
55348 -- ZLL Peripheral Access Layer
55349 ---------------------------------------------------------------------------- */
55356 /** ZLL - Register Layout Typedef */
55404 /* ----------------------------------------------------------------------------
55405 -- ZLL Register Masks
55406 ---------------------------------------------------------------------------- */
55413 /*! @name IRQSTS - INTERRUPT REQUEST STATUS */
55418 /*! SEQIRQ - Sequencer IRQ
55426 /*! TXIRQ - TX IRQ
55434 /*! RXIRQ - RX IRQ
55442 /*! CCAIRQ - CCA IRQ
55450 /*! RXWTRMRKIRQ - Receive Watermark IRQ
55458 /*! FILTERFAIL_IRQ - Filter Fail IRQ
55466 /*! PLL_UNLOCK_IRQ - PLL Unlock IRQ
55474 /*! RX_FRM_PEND - RX Frame Pending */
55479 /*! WAKE_IRQ - WAKE Interrupt Request
55487 /*! ARB_GRANT_DEASSERTION_IRQ - arb_grant Deassertion IRQ
55495 /*! TSM_IRQ - TSM IRQ
55503 /*! ENH_PKT_STATUS - Enhanced Packet Status
55504 * 0b0..The last packet received was neither 4e- nor 2015-compliant
55505 …* 0b1..The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be que…
55511 /*! PI - Poll Indication
55520 /*! SRCADDR - Source Address Match Status */
55525 /*! CCA - CCA Status
55533 /*! CRCVALID - CRC Valid Status
55541 /*! TMR1IRQ - Timer 1 IRQ */
55546 /*! TMR2IRQ - Timer 2 IRQ */
55551 /*! TMR3IRQ - Timer 3 IRQ */
55556 /*! TMR4IRQ - Timer 4 IRQ */
55561 /*! TMR1MSK - Timer Comparator 1 Interrupt Mask bit
55569 /*! TMR2MSK - Timer Comparator 2 Interrupt Mask bit
55577 /*! TMR3MSK - Timer Comparator 3 Interrupt Mask bit
55585 /*! TMR4MSK - Timer Comparator 4 Interrupt Mask bit
55593 /*! RX_FRAME_LENGTH - Receive Frame Length */
55597 /*! @name PHY_CTRL - PHY CONTROL */
55602 /*! XCVSEQ - 802.15.4 Transceiver Sequence Selector
55616 /*! AUTOACK - Auto Acknowledge Enable
55619 …* 0b1..sequence manager will follow a receive frame with an automatic hardware-generated Tx Ack f…
55625 /*! RXACKRQD - Receive Acknowledge Frame required
55627 * 0b1..A receive Ack frame is expected to follow the transmit frame (non-Ack frames are rejected).
55633 /*! CCABFRTX - CCA Before TX
55641 /*! SLOTTED - Slotted Mode */
55646 /*! TMRTRIGEN - Timer2 Trigger Enable
55654 /*! SEQMSK - Sequencer Interrupt Mask
55662 /*! TXMSK - TX Interrupt Mask
55670 /*! RXMSK - RX Interrupt Mask
55678 /*! CCAMSK - CCA Interrupt Mask
55686 /*! RX_WMRK_MSK - RX Watermark Interrupt Mask
55695 /*! FILTERFAIL_MSK - FilterFail Interrupt Mask
55703 /*! PLL_UNLOCK_MSK - PLL Unlock Interrupt Mask
55711 /*! CRC_MSK - CRC Mask
55714 …* to complete successfully; if CRCVALID=0, sequence manager will return to preamble-detect m…
55721 /*! WAKE_MSK - Mask wakeup from DSM
55729 /*! ARB_GRANT_DEASSERTION_MSK - arb_grant Deassertion Interrupt Mask
55737 /*! TSM_MSK - Mask generating interrupt from TSM
55745 /*! TMR1CMP_EN - Timer 1 Compare Enable
55753 /*! TMR2CMP_EN - Timer 2 Compare Enable
55761 /*! TMR3CMP_EN - Timer 3 Compare Enable
55769 /*! TMR4CMP_EN - Timer 4 Compare Enable
55777 /*! TC2PRIME_EN - Timer 2 Prime Compare Enable
55785 /*! PROMISCUOUS - Promiscuous Mode Enable
55793 /*! TC3_POSTPONE_ON_SFD - Postpone TC3 Timeout On SFD Enable
55801 /*! CCATYPE - Clear Channel Assessment Type
55811 /*! PANCORDNTR0 - Device is a PAN Coordinator on PAN0 */
55816 /*! TC3TMOUT - TMR3 Timeout Enable
55824 /*! TRCV_MSK - Transceiver Global Interrupt Mask
55831 /*! @name EVENT_TMR - EVENT TIMER */
55836 /*! EVENT_TMR_LD - Event Timer Load Enable */
55841 /*! EVENT_TMR_ADD - Event Timer Add Enable */
55846 /*! EVENT_TMR_FRAC - Event Timer Fractional Component */
55851 /*! EVENT_TMR - Event Timer Integer Component */
55855 /*! @name TIMESTAMP - TIMESTAMP */
55860 /*! TIMESTAMP_FRAC - Timestamp Fractional */
55865 /*! TIMESTAMP - Timestamp */
55869 /*! @name T1CMP - T1 COMPARE */
55874 /*! T1CMP - TMR1 Compare Value */
55878 /*! @name T2CMP - T2 COMPARE */
55883 /*! T2CMP - TMR2 Compare Value */
55887 /*! @name T2PRIMECMP - T2 PRIME COMPARE */
55892 /*! T2PRIMECMP - TMR2 Prime Compare Value */
55896 /*! @name T3CMP - T3 COMPARE */
55901 /*! T3CMP - TMR3 Compare Value */
55905 /*! @name T4CMP - T4 COMPARE */
55910 /*! T4CMP - TMR4 Compare Value */
55914 /*! @name PA_PWR - PA POWER */
55919 /*! PA_PWR - PA Power */
55924 /*! EXT_PA_PWR - External PA Power */
55929 /*! EXT_PA_PWR_CHG - External PA Power Change Flag */
55933 /*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
55938 /*! CHANNEL_NUM0 - Channel Number for PAN0 */
55942 /*! @name LQI_AND_RSSI - LQI AND RSSI */
55947 /*! LQI_VALUE - LQI Value */
55952 /*! RSSI - RSSI Value */
55957 /*! CCA1_ED_FNL - Final Result for CCA Mode 1 and Energy Detect */
55961 /*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
55966 /*! MACPANID0 - MAC PAN ID for PAN0 */
55971 /*! MACSHORTADDRS0 - MAC SHORT ADDRESS FOR PAN0 */
55975 /*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
55980 /*! MACLONGADDRS0_LSB - MAC LONG ADDRESS for PAN0 LSB */
55984 /*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
55989 /*! MACLONGADDRS0_MSB - MAC LONG ADDRESS for PAN0 MSB */
55993 /*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
55998 /*! BEACON_FT - Beacon Frame Type Enable
56006 /*! DATA_FT - Data Frame Type Enable
56014 /*! ACK_FT - Ack Frame Type Enable
56022 /*! CMD_FT - MAC Command Frame Type Enable
56030 /*! LLDN_FT - LLDN Frame Type Enable
56038 /*! MULTIPURPOSE_FT - Multipurpose Frame Type Enable
56046 /*! NS_FT - "Not Specified" Frame Type Enable
56048 …* 0b1..Not-specified (reserved) frame type enabled. Applies to Frame Type 6. No packet filtering …
56056 /*! EXTENDED_FT - Extended Frame Type Enable
56064 /*! FRM_VER_FILTER - Frame Version selector. */
56069 /*! ACTIVE_PROMISCUOUS - Active Promiscuous
56072 * however acknowledge those packets under rules which apply in non-PROMISCUOUS mode
56078 /*! EXTENDED_FCS_CHK - Verify FCS on Frame Type Extended
56080 …* 0b1..Packet Processor will check FCS at end-of-packet based on packet length derived from PHR, …
56086 /*! FV2_BEACON_RECD - Frame Version 2 Beacon Packet Received
56094 /*! FV2_DATA_RECD - Frame Version 2 Data Packet Received
56102 /*! FV2_ACK_RECD - Frame Version 2 Acknowledge Packet Received
56110 /*! FV2_CMD_RECD - Frame Version 2 MAC Command Packet Received
56118 /*! LLDN_RECD - LLDN Packet Received
56126 /*! MULTIPURPOSE_RECD - Multipurpose Packet Received
56134 /*! EXTENDED_RECD - Extended Packet Received
56141 /*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
56146 /*! CCA1_THRESH - CCA Mode 1 Threshold */
56151 /*! LQI_OFFSET_COMP - LQI Offset Compensation */
56156 /*! SIMUL_CCA_RX - Simultaneous CCA and Receive Enable
56164 /*! CCA3_AND_NOT_OR - CCA Mode 3 AND not OR
56171 /*! @name CCA2_CTRL - CCA2 CONTROL */
56176 /*! CCA2_NUM_CORR_PEAKS - CCA Mode 2 Number of Correlation Peaks Detected */
56181 /*! CCA2_MIN_NUM_CORR_TH - CCA Mode 2 Threshold Number of Correlation Peaks */
56186 /*! CCA2_CORR_THRESH - CCA Mode 2 Correlation Threshold */
56190 /*! @name DSM_CTRL - DSM CONTROL */
56195 /*! ZIGBEE_SLEEP_REQUEST - 802.15.4 Deep Sleep Mode Request for Manual DSM */
56199 /*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
56204 /*! MACPANID1 - MAC PAN ID for PAN1 */
56209 /*! MACSHORTADDRS1 - MAC SHORT ADDRESS for PAN1 */
56213 /*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
56218 /*! MACLONGADDRS1_LSB - MAC LONG ADDRESS for PAN1 LSB */
56222 /*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
56227 /*! MACLONGADDRS1_MSB - MAC LONG ADDRESS for PAN1 MSB */
56231 /*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
56236 /*! ACTIVE_NETWORK - Active Network Selector
56244 /*! DUAL_PAN_AUTO - Activates automatic Dual PAN operating mode */
56249 /*! PANCORDNTR1 - Device is a PAN Coordinator on PAN1 */
56254 /*! CURRENT_NETWORK - Indicates which PAN is currently selected by hardware
56262 /*! ZB_DP_CHAN_OVRD_EN - Dual PAN Channel Override Enable */
56267 /*! ZB_DP_CHAN_OVRD_SEL - Dual PAN Channel Override Selector */
56272 /*! DUAL_PAN_DWELL - Dual PAN Channel Frequency Dwell Time */
56277 /*! DUAL_PAN_REMAIN - Time Remaining before next PAN switch in auto Dual PAN mode */
56282 /*! RECD_ON_PAN0 - Last Packet was Received on PAN0 */
56287 /*! RECD_ON_PAN1 - Last Packet was Received on PAN1 */
56291 /*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
56296 /*! CHANNEL_NUM1 - Channel Number for PAN1 */
56300 /*! @name SAM_CTRL - SAM CONTROL */
56305 /*! SAP0_EN - Enables SAP0 Partition of the SAM Table
56313 /*! SAA0_EN - Enables SAA0 Partition of the SAM Table
56321 /*! SAP1_EN - Enables SAP1 Partition of the SAM Table
56329 /*! SAA1_EN - Enables SAA1 Partition of the SAM Table
56337 /*! SAA0_START - First Index of SAA0 partition */
56342 /*! SAP1_START - First Index of SAP1 partition */
56347 /*! SAA1_START - First Index of SAA1 partition */
56351 /*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
56356 /*! SAM_INDEX - Contains the SAM table index to be enabled or invalidated */
56361 /*! SAM_INDEX_WR - Enables SAM Table Contents to be updated */
56366 /*! SAM_CHECKSUM - Software-computed source address checksum, to be installed into a table index */
56371 /*! SAM_INDEX_INV - Invalidate the SAM table index selected by SAM_INDEX */
56376 /*! SAM_INDEX_EN - Enable the SAM table index selected by SAM_INDEX */
56381 /*! ACK_FRM_PND - State of AutoTxAck FramePending field when SAM Accelleration is Disabled */
56386 /*! ACK_FRM_PND_CTRL - Manual Control for AutoTxAck FramePending field
56394 /*! FIND_FREE_IDX - Find First Free Index */
56399 /*! INVALIDATE_ALL - Invalidate Entire SAM Table */
56404 /*! SAM_BUSY - SAM Table Update Status Bit */
56408 /*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
56413 /*! SAP0_MATCH - Index in the SAP0 Partition of the SAM Table corresponding to the first checksum m…
56418 /*! SAP0_ADDR_PRESENT - A Checksum Match is Present in the SAP0 Partition of the SAM Table */
56423 /*! SAA0_MATCH - Index in the SAA0 Partition of the SAM Table corresponding to the first checksum m…
56428 /*! SAA0_ADDR_ABSENT - A Checksum Match is Absent in the SAA0 Partition of the SAM Table */
56433 /*! SAP1_MATCH - Index in the SAP1 Partition of the SAM Table corresponding to the first checksum m…
56438 /*! SAP1_ADDR_PRESENT - A Checksum Match is Present in the SAP1 Partition of the SAM Table */
56443 /*! SAA1_MATCH - Index in the SAA1 Partition of the SAM Table corresponding to the first checksum m…
56448 /*! SAA1_ADDR_ABSENT - A Checksum Match is Absent in the SAP1 Partition of the SAM Table */
56452 /*! @name SAM_FREE_IDX - SAM FREE INDEX */
56457 /*! SAP0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP0 partition */
56462 /*! SAA0_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA0 partition */
56467 /*! SAP1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAP1 partition */
56472 /*! SAA1_1ST_FREE_IDX - First non-enabled (invalid) index in the SAA1 partition */
56476 /*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */
56481 /*! FORCE_CLK_ON - Force On 802.15.4 phy_gck
56489 /*! CLR_NEW_SEQ_INHIBIT - Overrides the automatic hardware locking of the programmed XCVSEQ while a…
56494 /*! EVENT_TMR_DO_NOT_LATCH - Overrides the automatic hardware latching of the Event Timer */
56499 /*! LATCH_PREAMBLE - Stickiness Control for Preamble Detection
56509 /*! NO_RX_RECYCLE - Disable Automatic RX Sequence Recycling */
56514 /*! FORCE_CRC_ERROR - Induce a CRC Error in Transmitted Packets
56522 /*! CONTINUOUS_EN - Enable Continuous TX or RX Mode
56530 /*! XCVSEQ_ACTUAL - Indicates the programmed sequence that has been recognized by the ZSM Sequence …
56535 /*! SEQ_IDLE - ZSM Sequence Idle Indicator */
56540 /*! NEW_SEQ_INHIBIT - New Sequence Inhibit */
56545 /*! RX_TIMEOUT_PENDING - Indicates a TMR3 RX Timeout is Pending */
56550 /*! RX_MODE - RX Operation in Progress */
56555 /*! TMR2_SEQ_TRIG_ARMED - indicates that TMR2 has been programmed and is armed to trigger a new aut…
56560 /*! SEQ_T_STATUS - Status of the just-completed or ongoing Sequence T or Sequence TR */
56565 /*! SW_ABORTED - Autosequence has terminated due to a Software abort. */
56570 /*! TC3_ABORTED - autosequence has terminated due to an TMR3 timeout */
56575 /*! PLL_ABORTED - Autosequence has terminated due to an PLL unlock event */
56580 /*! EXT_ABORTED - Autosequence has terminated due to a Wake-On-Radio command */
56585 /*! ARB_GRANT_DEASSERTION_ABORTED - Autosequence has terminated due to an arb_grant deassertion eve…
56589 /*! @name ACKDELAY - ACK DELAY */
56594 /*! ACKDELAY - ACK Delay */
56599 /*! TXDELAY - TX Delay */
56604 /*! RXDELAY - RX Delay */
56609 /*! FAST_TX_WD_EN - Fast TX_WD enable/disable
56617 /*! FAST_TX_WD_DELAY - FAST_TX_WD_DELAY */
56621 /*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
56626 /*! FILTERFAIL_CODE - Filter Fail Code */
56631 /*! FILTERFAIL_PAN_SEL - PAN Selector for Filter Fail Code
56638 /*! @name RX_WTR_MARK - RECEIVE WATER MARK */
56643 /*! RX_WTR_MARK - RECEIVE WATER MARK */
56647 /*! @name SLOT_PRELOAD - SLOT PRELOAD */
56652 /*! SLOT_PRELOAD - Slotted Mode Preload */
56656 /*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */
56661 /*! SEQ_STATE - ZSM Sequence State */
56666 /*! PREAMBLE_DET - Preamble Detected */
56671 /*! SFD_DET - SFD Detected */
56676 /*! FILTERFAIL_FLAG_SEL - Consolidated Filter Fail Flag */
56681 /*! CRCVALID - CRC Valid Indicator
56689 /*! PLL_ABORT - Raw PLL Abort Signal */
56694 /*! PLL_ABORTED - Autosequence has terminated due to an PLL unlock event */
56699 /*! RX_BYTE_COUNT - Realtime Received Byte Count */
56704 /*! CCCA_BUSY_CNT - Number of CCA Measurements resulting in Busy Channel */
56708 /*! @name TMR_PRESCALE - TIMER PRESCALER */
56713 /*! TMR_PRESCALE - Timer Prescaler
56719 * 0b101..62.5kHz (268.44 S) -- default
56726 /*! @name LENIENCY_LSB - LENIENCY LSB */
56731 /*! LENIENCY_LSB - Leniency LSB Register */
56735 /*! @name LENIENCY_MSB - LENIENCY MSB */
56740 /*! LENIENCY_MSB - Leniency MSB Register */
56744 /*! @name PART_ID - PART ID */
56749 /*! PART_ID - 802.15.4 Part ID */
56753 /*! @name COEX_CTRL - COEXISTENCE CONTROL */
56758 /*! COEX_EN - Coexistence Enable
56766 /*! COEX_REQ_DELAY_EN - Coexistence Request Delay Enable
56774 /*! COEX_REQ_ON_PD - Coexistence Request on Preamble detected
56782 /*! COEX_TIMEOUT_MSK - Coexistence Timeout Interrupt Mask bit
56790 /*! COEX_TIMEOUT_IRQ - Coexistence Timeout Interrupt */
56795 /*! COEX_TIMEOUT - Coexistence timeout value */
56799 /*! @name COEX_PRIORITY - COEXISTENCE PRIORITY */
56804 /*! PRIORITY_T - PRIORITY_T */
56809 /*! PRIORITY_R_PRE - PRIORITY_R_PRE */
56814 /*! PRIORITY_R_PKT - PRIORITY_R_PKT */
56819 /*! PRIORITY_TACK - PRIORITY_TACK */
56824 /*! PRIORITY_CCA - PRIORITY_CCA */
56829 /*! PRIORITY_CCCA - PRIORITY_CCCA */
56834 /*! PRIORITY_CTX - PRIORITY_CT */
56839 /*! PRIORITY_RACK_PRE - PRIORITY_RACK_PRE */
56844 /*! PRIORITY_RACK_PKT - PRIORITY_RACK_PKT */
56849 /*! PRIORITY_OVRD - PRIORITY_OVRD */
56854 /*! PRIORITY_OVRD_EN - PRIORITY_OVRD_EN
56861 /*! @name ENHACK_CTRL0 - ENHACK_CTRL 0 */
56866 /*! ENHACK_EN - Enhanced Acknowledgment Enable
56874 /*! SW_LEN_RDY - Software enhanced acknowledgment frame Length field ready
56882 /*! SW_HIE_RDY - Software enhanced acknowledgment frame HIE field ready
56890 /*! EMPTY_SECURITY_ENABLED_OVRD - Override value of Security Enabled field in Empty Enhanced Acknow…
56895 /*! EMPTY_SRC_ADDR_MODE - Source Address Mode field in Empty Enhanced Acknowledgment */
56900 /*! SW_MHR_LENGTH - Software calculated MHR(excludes the HIE field) Length in bytes. */
56905 /*! HW_FRAME_PENDING - Hardware calculated Frame Pending field */
56910 /*! EMPTY_SECURITY_ENABLED_OVRD_EN - Override enable of Security Enabled field in Empty Enhanced Ac…
56918 /*! ACK_ABORT_MSK - Enhanced Acknowledgment Abort IRQ Mask bit
56926 /*! ACK_ABORT_IRQ - Enhanced Acknowledgment Abort IRQ */
56931 /*! EMPTY_ACK_MSK - Empty Enhanced Acknowledgment IRQ Mask bit
56939 /*! EMPTY_ACK_IRQ - Empty Enhanced Acknowledgment IRQ */
56944 /*! RECYC_MSK - Recycle IRQ Mask bit
56952 /*! RECYC_IRQ - Recycle IRQ */
56962 /* ZLL - Peripheral instance base addresses */
57019 /* ----------------------------------------------------------------------------
57020 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
57021 ---------------------------------------------------------------------------- */
57037 * @brief Mask and left-shift a bit field value for use in a register bit range.
57044 * @brief Mask and right-shift a register value to extract a bit field value.
57056 /* ----------------------------------------------------------------------------
57057 -- SDK Compatibility
57058 ---------------------------------------------------------------------------- */
57079 #define IMU_CUR_CPU_BASE(link) (&(CIU2->CIU2_IMU_CPU1_WR_MSG_TO_CPU2))
57081 #define IMU_PEER_CPU_BASE(link) (&(CIU2->CIU2_IMU_CPU2_WR_MSG_TO_CPU1))
57115 … if ((MSCM->SID & MSCM_SID_SIREV_MASK) == MSCM_SID_SIREV(0x2u)) /* A1 silicon revision is 0x2 */ in Chip_GetVersion()
57119 …else if ((MSCM->SID & MSCM_SID_SIREV_MASK) == MSCM_SID_SIREV(0x1u)) /* A2 silicon revision is 0x1 … in Chip_GetVersion()
57123 …else if ((MSCM->SID & MSCM_SID_SIREV_MASK) == MSCM_SID_SIREV(0x3u)) /* Previous A1 silicon revisio… in Chip_GetVersion()