Lines Matching refs:SCG0
153 SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); in CLOCK_SetupFROHFClocking()
156 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; in CLOCK_SetupFROHFClocking()
159 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
161 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; in CLOCK_SetupFROHFClocking()
164 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; in CLOCK_SetupFROHFClocking()
167 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) in CLOCK_SetupFROHFClocking()
205 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtClocking()
211 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtClocking()
212 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtClocking()
218 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtClocking()
224 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_SetupExtClocking()
227 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetupExtClocking()
230 SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); in CLOCK_SetupExtClocking()
233 SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; in CLOCK_SetupExtClocking()
236 SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); in CLOCK_SetupExtClocking()
239 while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) in CLOCK_SetupExtClocking()
279 if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) in CLOCK_SetupExtRefClocking()
285 …if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_… in CLOCK_SetupExtRefClocking()
286 …(((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK… in CLOCK_SetupExtRefClocking()
292 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) in CLOCK_SetupExtRefClocking()
298 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; in CLOCK_SetupExtRefClocking()
301 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetupExtRefClocking()
304 SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; in CLOCK_SetupExtRefClocking()
307 SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range); in CLOCK_SetupExtRefClocking()
310 SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; in CLOCK_SetupExtRefClocking()
313 SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); in CLOCK_SetupExtRefClocking()
316 while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) in CLOCK_SetupExtRefClocking()
333 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK | SCG_LDOCSR_VOUT_OK_MASK; in CLOCK_SetupOsc32KClocking()
349 SCG0->ROSCCSR = SCG_ROSCCSR_ROSCERR_MASK; in CLOCK_SetupOsc32KClocking()
352 SCG0->ROSCCSR &= ~SCG_ROSCCSR_LK_MASK; in CLOCK_SetupOsc32KClocking()
355 SCG0->ROSCCSR |= SCG_ROSCCSR_ROSCCM_MASK; in CLOCK_SetupOsc32KClocking()
358 while ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) == 0U) in CLOCK_SetupOsc32KClocking()
392 SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc); in CLOCK_FROHFTrimConfig()
396 SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); in CLOCK_FROHFTrimConfig()
400 SCG0->FIRCCSR = (uint32_t)config.trimMode; in CLOCK_FROHFTrimConfig()
402 if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) in CLOCK_FROHFTrimConfig()
417 SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); in CLOCK_FRO12MTrimConfig()
421 SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); in CLOCK_FRO12MTrimConfig()
422 SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); in CLOCK_FRO12MTrimConfig()
426 SCG0->SIRCCSR = (uint32_t)config.trimMode; in CLOCK_FRO12MTrimConfig()
428 if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) in CLOCK_FRO12MTrimConfig()
446 uint32_t reg = SCG0->SOSCCSR; in CLOCK_SetSysOscMonitorMode()
452 SCG0->SOSCCSR = reg; in CLOCK_SetSysOscMonitorMode()
465 uint32_t reg = SCG0->ROSCCSR; in CLOCK_SetRoscMonitorMode()
471 SCG0->ROSCCSR = reg; in CLOCK_SetRoscMonitorMode()
484 uint32_t reg = SCG0->UPLLCSR; in CLOCK_SetUpllMonitorMode()
490 SCG0->UPLLCSR = reg; in CLOCK_SetUpllMonitorMode()
503 uint32_t reg = SCG0->APLLCSR; in CLOCK_SetPll0MonitorMode()
509 SCG0->APLLCSR = reg; in CLOCK_SetPll0MonitorMode()
522 uint32_t reg = SCG0->SPLLCSR; in CLOCK_SetPll1MonitorMode()
528 SCG0->SPLLCSR = reg; in CLOCK_SetPll1MonitorMode()
691 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); in CLOCK_AttachClk()
692 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(sel)) in CLOCK_AttachClk()
738 actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); in CLOCK_GetClockAttachId()
2004 switch ((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) in CLOCK_GetPLL0InClockRate()
2028 switch ((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) in CLOCK_GetPLL1InClockRate()
2136 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetPLL0Freq()
2139 SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2142 SCG0->APLLCTRL = pSetup->pllctrl; in CLOCK_SetPLL0Freq()
2143 SCG0->APLLNDIV = pSetup->pllndiv; in CLOCK_SetPLL0Freq()
2144 SCG0->APLLNDIV = pSetup->pllndiv | (1UL << SCG_APLLNDIV_NREQ_SHIFT); /* latch */ in CLOCK_SetPLL0Freq()
2145 SCG0->APLLPDIV = pSetup->pllpdiv; in CLOCK_SetPLL0Freq()
2146 SCG0->APLLPDIV = pSetup->pllpdiv | (1UL << SCG_APLLPDIV_PREQ_SHIFT); /* latch */ in CLOCK_SetPLL0Freq()
2147 SCG0->APLLMDIV = pSetup->pllmdiv; in CLOCK_SetPLL0Freq()
2148 SCG0->APLLMDIV = pSetup->pllmdiv | (1UL << SCG_APLLMDIV_MREQ_SHIFT); /* latch */ in CLOCK_SetPLL0Freq()
2149 SCG0->APLLSSCG0 = pSetup->pllsscg[0]; in CLOCK_SetPLL0Freq()
2150 SCG0->APLLSSCG1 = pSetup->pllsscg[1]; in CLOCK_SetPLL0Freq()
2153 SCG0->TRIM_LOCK = 0x5a5a0001; in CLOCK_SetPLL0Freq()
2160 SCG0->APLLLOCK_CNFG = SCG_APLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); in CLOCK_SetPLL0Freq()
2163 SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); in CLOCK_SetPLL0Freq()
2194 SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; in CLOCK_SetPLL1Freq()
2197 SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2200 SCG0->SPLLCTRL = pSetup->pllctrl; in CLOCK_SetPLL1Freq()
2201 SCG0->SPLLNDIV = pSetup->pllndiv; in CLOCK_SetPLL1Freq()
2202 SCG0->SPLLNDIV = pSetup->pllndiv | (1UL << SCG_SPLLNDIV_NREQ_SHIFT); /* latch */ in CLOCK_SetPLL1Freq()
2203 SCG0->SPLLPDIV = pSetup->pllpdiv; in CLOCK_SetPLL1Freq()
2204 SCG0->SPLLPDIV = pSetup->pllpdiv | (1UL << SCG_SPLLPDIV_PREQ_SHIFT); /* latch */ in CLOCK_SetPLL1Freq()
2205 SCG0->SPLLMDIV = pSetup->pllmdiv; in CLOCK_SetPLL1Freq()
2206 SCG0->SPLLMDIV = pSetup->pllmdiv | (1UL << SCG_SPLLMDIV_MREQ_SHIFT); /* latch */ in CLOCK_SetPLL1Freq()
2207 SCG0->SPLLSSCG0 = pSetup->pllsscg[0]; in CLOCK_SetPLL1Freq()
2208 SCG0->SPLLSSCG1 = pSetup->pllsscg[1]; in CLOCK_SetPLL1Freq()
2211 SCG0->TRIM_LOCK = 0x5a5a0001; in CLOCK_SetPLL1Freq()
2218 SCG0->SPLLLOCK_CNFG = SCG_SPLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); in CLOCK_SetPLL1Freq()
2221 SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); in CLOCK_SetPLL1Freq()
2250 return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0UL) ? 12000000U : 0U; in CLOCK_GetFro12MFreq()
2270 if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0UL) in CLOCK_GetFroHfFreq()
2274 else if ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) != 0UL) in CLOCK_GetFroHfFreq()
2292 return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) ? 48000000U : 0U; in CLOCK_GetClk48MFreq()
2301 return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) != 0U) ? 144000000U : 0U; in CLOCK_GetClk144MFreq()
2321 return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; in CLOCK_GetExtClkFreq()
2330 return ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) != 0UL) ? in CLOCK_GetOsc32KFreq()
2343 switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) in CLOCK_GetMainClkFreq()
2484 if ((SCG0->APLLCTRL & SCG_APLLCTRL_LIMUPOFF_MASK) == 0UL) /* normal mode */ in pllFindSel()
2529 if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) in findPll0PreDiv()
2531 preDiv = SCG0->APLLNDIV & SCG_APLLNDIV_NDIV_MASK; in findPll0PreDiv()
2546 if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) in findPll1PreDiv()
2548 preDiv = SCG0->SPLLNDIV & SCG_SPLLNDIV_NDIV_MASK; in findPll1PreDiv()
2562 if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) in findPll0PostDiv()
2564 if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) in findPll0PostDiv()
2566 postDiv = SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK; in findPll0PostDiv()
2570 postDiv = 2UL * (SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK); in findPll0PostDiv()
2586 if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) in findPll1PostDiv()
2588 if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) in findPll1PostDiv()
2590 postDiv = SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK; in findPll1PostDiv()
2594 postDiv = 2UL * (SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK); in findPll1PostDiv()
2612 if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPll0MMult()
2614 mMult = (float)(uint32_t)(SCG0->APLLMDIV & SCG_APLLMDIV_MDIV_MASK); in findPll0MMult()
2618 mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll0MMult()
2619 mMult_int = mMult_int | ((SCG0->APLLSSCG0) >> PLL_SSCG_MD_INT_P); in findPll0MMult()
2621 …((float)(uint32_t)((SCG0->APLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD… in findPll0MMult()
2638 if ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) in findPll1MMult()
2640 mMult = (float)(uint32_t)(SCG0->SPLLMDIV & SCG_SPLLMDIV_MDIV_MASK); in findPll1MMult()
2644 mMult_int = ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); in findPll1MMult()
2645 mMult_int = mMult_int | ((SCG0->SPLLSSCG0) >> PLL_SSCG_MD_INT_P); in findPll1MMult()
2647 …((float)(uint32_t)((SCG0->SPLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD… in findPll1MMult()