169   switch (SCG0->CSR & SCG_CSR_SCS_MASK)  in SystemCoreClockUpdate()
177       SCGOUTClock = ((0u == (SCG0->SIRCCFG & SCG_SIRCCFG_RANGE_MASK)) ? 4000000u : 16000000u);  in SystemCoreClockUpdate()
181 …SCGOUTClock = 48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * …  in SystemCoreClockUpdate()
190       SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ :  in SystemCoreClockUpdate()
191 …    (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u);  in SystemCoreClockUpdate()
192       SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u;  in SystemCoreClockUpdate()
193       SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)];  in SystemCoreClockUpdate()
195       if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK))  in SystemCoreClockUpdate()
198         switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK)  in SystemCoreClockUpdate()
202 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD0_MASK) >> SCG_SPLLPFD_PFD0_SHIFT));  in SystemCoreClockUpdate()
206 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD1_MASK) >> SCG_SPLLPFD_PFD1_SHIFT));  in SystemCoreClockUpdate()
210 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD2_MASK) >> SCG_SPLLPFD_PFD2_SHIFT));  in SystemCoreClockUpdate()
214 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD3_MASK) >> SCG_SPLLPFD_PFD3_SHIFT));  in SystemCoreClockUpdate()
225       SCGOUTClock = (0u == (SCG0->APLLCFG & SCG_APLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ :  in SystemCoreClockUpdate()
226 …    (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u);  in SystemCoreClockUpdate()
227       SCGOUTClock /= ((SCG0->APLLCFG & SCG_APLLCFG_PREDIV_MASK) >> SCG_APLLCFG_PREDIV_SHIFT) + 1u;  in SystemCoreClockUpdate()
228       apllNum = SCG0->APLLNUM;  in SystemCoreClockUpdate()
229       apllDenom = SCG0->APLLDENOM;  in SystemCoreClockUpdate()
231 …SCGOUTClock = SCGOUTClock * ((SCG0->APLLCFG & SCG_APLLCFG_MULT_MASK) >> SCG_APLLCFG_MULT_SHIFT) + …  in SystemCoreClockUpdate()
233       if (0u == (SCG0->APLLCFG & SCG_APLLCFG_PLLS_MASK))  in SystemCoreClockUpdate()
236 …SCGOUTClock /= (((SCG0->APLLCFG & SCG_APLLCFG_PLLPOSTDIV1_MASK) >> SCG_APLLCFG_PLLPOSTDIV1_SHIFT) …  in SystemCoreClockUpdate()
237 …SCGOUTClock /= (((SCG0->APLLCFG & SCG_APLLCFG_PLLPOSTDIV2_MASK) >> SCG_APLLCFG_PLLPOSTDIV2_SHIFT) …  in SystemCoreClockUpdate()
242         switch (SCG0->APLLCFG & SCG_APLLCFG_PFDSEL_MASK)  in SystemCoreClockUpdate()
246 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD0_MASK) >> SCG_APLLPFD_PFD0_SHIFT));  in SystemCoreClockUpdate()
250 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD1_MASK) >> SCG_APLLPFD_PFD1_SHIFT));  in SystemCoreClockUpdate()
254 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD2_MASK) >> SCG_APLLPFD_PFD2_SHIFT));  in SystemCoreClockUpdate()
258 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD3_MASK) >> SCG_APLLPFD_PFD3_SHIFT));  in SystemCoreClockUpdate()
272   SCGOUTClock /= ((SCG0->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1u;  in SystemCoreClockUpdate()