168   switch (SCG0->CSR & SCG_CSR_SCS_MASK)  in SystemCoreClockUpdate()
176       SCGOUTClock = ((0u == (SCG0->SIRCCFG & SCG_SIRCCFG_RANGE_MASK)) ? 4000000u : 16000000u);  in SystemCoreClockUpdate()
180 …SCGOUTClock = 48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * …  in SystemCoreClockUpdate()
189       SCGOUTClock = (0u == (SCG0->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ :  in SystemCoreClockUpdate()
190 …    (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u);  in SystemCoreClockUpdate()
191       SCGOUTClock /= ((SCG0->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1u;  in SystemCoreClockUpdate()
192       SCGOUTClock *= spllMulti[((SCG0->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT)];  in SystemCoreClockUpdate()
194       if (0u != (SCG0->SPLLCFG & SCG_SPLLCFG_PLLS_MASK))  in SystemCoreClockUpdate()
197         switch (SCG0->SPLLCFG & SCG_SPLLCFG_PFDSEL_MASK)  in SystemCoreClockUpdate()
201 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD0_MASK) >> SCG_SPLLPFD_PFD0_SHIFT));  in SystemCoreClockUpdate()
205 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD1_MASK) >> SCG_SPLLPFD_PFD1_SHIFT));  in SystemCoreClockUpdate()
209 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD2_MASK) >> SCG_SPLLPFD_PFD2_SHIFT));  in SystemCoreClockUpdate()
213 …                              ((SCG0->SPLLPFD & SCG_SPLLPFD_PFD3_MASK) >> SCG_SPLLPFD_PFD3_SHIFT));  in SystemCoreClockUpdate()
224       SCGOUTClock = (0u == (SCG0->APLLCFG & SCG_APLLCFG_SOURCE_MASK)) ? CPU_XTAL_SOSC_CLK_HZ :  in SystemCoreClockUpdate()
225 …    (48000000u + ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000u);  in SystemCoreClockUpdate()
226       SCGOUTClock /= ((SCG0->APLLCFG & SCG_APLLCFG_PREDIV_MASK) >> SCG_APLLCFG_PREDIV_SHIFT) + 1u;  in SystemCoreClockUpdate()
227       apllNum = SCG0->APLLNUM;  in SystemCoreClockUpdate()
228       apllDenom = SCG0->APLLDENOM;  in SystemCoreClockUpdate()
230 …SCGOUTClock = SCGOUTClock * ((SCG0->APLLCFG & SCG_APLLCFG_MULT_MASK) >> SCG_APLLCFG_MULT_SHIFT) + …  in SystemCoreClockUpdate()
232       if (0u == (SCG0->APLLCFG & SCG_APLLCFG_PLLS_MASK))  in SystemCoreClockUpdate()
235 …SCGOUTClock /= (((SCG0->APLLCFG & SCG_APLLCFG_PLLPOSTDIV1_MASK) >> SCG_APLLCFG_PLLPOSTDIV1_SHIFT) …  in SystemCoreClockUpdate()
236 …SCGOUTClock /= (((SCG0->APLLCFG & SCG_APLLCFG_PLLPOSTDIV2_MASK) >> SCG_APLLCFG_PLLPOSTDIV2_SHIFT) …  in SystemCoreClockUpdate()
241         switch (SCG0->APLLCFG & SCG_APLLCFG_PFDSEL_MASK)  in SystemCoreClockUpdate()
245 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD0_MASK) >> SCG_APLLPFD_PFD0_SHIFT));  in SystemCoreClockUpdate()
249 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD1_MASK) >> SCG_APLLPFD_PFD1_SHIFT));  in SystemCoreClockUpdate()
253 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD2_MASK) >> SCG_APLLPFD_PFD2_SHIFT));  in SystemCoreClockUpdate()
257 …                              ((SCG0->APLLPFD & SCG_APLLPFD_PFD3_MASK) >> SCG_APLLPFD_PFD3_SHIFT));  in SystemCoreClockUpdate()
271   SCGOUTClock /= ((SCG0->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1u;  in SystemCoreClockUpdate()