Lines Matching refs:divider

1187 static inline void CLOCK_SetSysOscAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider)  in CLOCK_SetSysOscAsyncClkDiv()  argument
1194 reg = (reg & ~SCG_SOSCDIV_SOSCDIV3_MASK) | SCG_SOSCDIV_SOSCDIV3(divider); in CLOCK_SetSysOscAsyncClkDiv()
1197 reg = (reg & ~SCG_SOSCDIV_SOSCDIV2_MASK) | SCG_SOSCDIV_SOSCDIV2(divider); in CLOCK_SetSysOscAsyncClkDiv()
1200 reg = (reg & ~SCG_SOSCDIV_SOSCDIV1_MASK) | SCG_SOSCDIV_SOSCDIV1(divider); in CLOCK_SetSysOscAsyncClkDiv()
1313 static inline void CLOCK_SetSircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) in CLOCK_SetSircAsyncClkDiv() argument
1320 reg = (reg & ~SCG_SIRCDIV_SIRCDIV3_MASK) | SCG_SIRCDIV_SIRCDIV3(divider); in CLOCK_SetSircAsyncClkDiv()
1323 reg = (reg & ~SCG_SIRCDIV_SIRCDIV2_MASK) | SCG_SIRCDIV_SIRCDIV2(divider); in CLOCK_SetSircAsyncClkDiv()
1326 reg = (reg & ~SCG_SIRCDIV_SIRCDIV1_MASK) | SCG_SIRCDIV_SIRCDIV1(divider); in CLOCK_SetSircAsyncClkDiv()
1422 static inline void CLOCK_SetFircAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) in CLOCK_SetFircAsyncClkDiv() argument
1429 reg = (reg & ~SCG_FIRCDIV_FIRCDIV3_MASK) | SCG_FIRCDIV_FIRCDIV3(divider); in CLOCK_SetFircAsyncClkDiv()
1432 reg = (reg & ~SCG_FIRCDIV_FIRCDIV2_MASK) | SCG_FIRCDIV_FIRCDIV2(divider); in CLOCK_SetFircAsyncClkDiv()
1435 reg = (reg & ~SCG_FIRCDIV_FIRCDIV1_MASK) | SCG_FIRCDIV_FIRCDIV1(divider); in CLOCK_SetFircAsyncClkDiv()
1600 static inline void CLOCK_SetAuxPllAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) in CLOCK_SetAuxPllAsyncClkDiv() argument
1607 reg = (reg & ~SCG_APLLDIV_APLLDIV1_MASK) | SCG_APLLDIV_APLLDIV1(divider); in CLOCK_SetAuxPllAsyncClkDiv()
1610 reg = (reg & ~SCG_APLLDIV_APLLDIV2_MASK) | SCG_APLLDIV_APLLDIV2(divider); in CLOCK_SetAuxPllAsyncClkDiv()
1613 reg = (reg & ~SCG_APLLDIV_APLLDIV1_MASK) | SCG_APLLDIV_APLLDIV1(divider); in CLOCK_SetAuxPllAsyncClkDiv()
1785 static inline void CLOCK_SetSysPllAsyncClkDiv(scg_async_clk_t asyncClk, scg_async_clk_div_t divider) in CLOCK_SetSysPllAsyncClkDiv() argument
1792 reg = (reg & ~SCG_SPLLDIV_SPLLDIV3_MASK) | SCG_SPLLDIV_SPLLDIV3(divider); in CLOCK_SetSysPllAsyncClkDiv()
1795 reg = (reg & ~SCG_SPLLDIV_SPLLDIV2_MASK) | SCG_SPLLDIV_SPLLDIV2(divider); in CLOCK_SetSysPllAsyncClkDiv()
1798 reg = (reg & ~SCG_SPLLDIV_SPLLDIV1_MASK) | SCG_SPLLDIV_SPLLDIV1(divider); in CLOCK_SetSysPllAsyncClkDiv()