Lines Matching refs:FCLKSEL

302     kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U),          /*!< Mux UART0_Clk from Fro. */
304 …kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U),      /*!< Mux UART0_Clk from MainClk. */
306 …kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U),      /*!< Mux UART0_Clk from Frg0Clk. */
308 …kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U),      /*!< Mux UART0_Clk from Frg1Clk. */
310 …kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U),      /*!< Mux UART0_Clk from Fro_Div. */
312     kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U),          /*!< Mux UART1_Clk from Fro. */
314 …kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U),      /*!< Mux UART1_Clk from MainClk. */
316 …kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U),      /*!< Mux UART1_Clk from Frg0Clk. */
318 …kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U),      /*!< Mux UART1_Clk from Frg1Clk. */
320 …kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U),      /*!< Mux UART1_Clk from Fro_Div. */
322     kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U),          /*!< Mux UART2_Clk from Fro. */
324 …kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U),      /*!< Mux UART2_Clk from MainClk. */
326 …kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U),      /*!< Mux UART2_Clk from Frg0Clk. */
328 …kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U),      /*!< Mux UART2_Clk from Frg1Clk. */
330 …kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U),      /*!< Mux UART2_Clk from Fro_Div. */
332     kUART3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[3U], 0U),          /*!< Mux UART3_Clk from Fro. */
334 …kUART3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[3U], 1U),      /*!< Mux UART3_Clk from MainClk. */
336 …kUART3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 2U),      /*!< Mux UART3_Clk from Frg0Clk. */
338 …kUART3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 3U),      /*!< Mux UART3_Clk from Frg1Clk. */
340 …kUART3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[3U], 4U),      /*!< Mux UART3_Clk from Fro_Div. */
342     kUART4_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[4U], 0U),          /*!< Mux UART4_Clk from Fro. */
344 …kUART4_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[4U], 1U),      /*!< Mux UART4_Clk from MainClk. */
346 …kUART4_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 2U),      /*!< Mux UART4_Clk from Frg0Clk. */
348 …kUART4_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 3U),      /*!< Mux UART4_Clk from Frg1Clk. */
350 …kUART4_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[4U], 4U),      /*!< Mux UART4_Clk from Fro_Div. */
352     kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U),           /*!< Mux I2C0_Clk from Fro. */
354 … kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U),       /*!< Mux I2C0_Clk from MainClk. */
356 … kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U),       /*!< Mux I2C0_Clk from Frg0Clk. */
358 … kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U),       /*!< Mux I2C0_Clk from Frg1Clk. */
360 … kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U),       /*!< Mux I2C0_Clk from Fro_Div. */
362     kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[6U], 0U),           /*!< Mux I2C1_Clk from Fro. */
364 … kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[6U], 1U),       /*!< Mux I2C1_Clk from MainClk. */
366 … kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 2U),       /*!< Mux I2C1_Clk from Frg0Clk. */
368 … kI2C1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 3U),       /*!< Mux I2C1_Clk from Frg1Clk. */
370 … kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[6U], 4U),       /*!< Mux I2C1_Clk from Fro_Div. */
372     kI2C2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[7U], 0U),           /*!< Mux I2C2_Clk from Fro. */
374 … kI2C2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[7U], 1U),       /*!< Mux I2C2_Clk from MainClk. */
376 … kI2C2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 2U),       /*!< Mux I2C2_Clk from Frg0Clk. */
378 … kI2C2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[7U], 3U),       /*!< Mux I2C2_Clk from Frg1Clk. */
380 … kI2C2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[7U], 4U),       /*!< Mux I2C2_Clk from Fro_Div. */
382     kI2C3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[8U], 0U),           /*!< Mux I2C3_Clk from Fro. */
384 … kI2C3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[8U], 1U),       /*!< Mux I2C3_Clk from MainClk. */
386 … kI2C3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 2U),       /*!< Mux I2C3_Clk from Frg0Clk. */
388 … kI2C3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[8U], 3U),       /*!< Mux I2C3_Clk from Frg1Clk. */
390 … kI2C3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[8U], 4U),       /*!< Mux I2C3_Clk from Fro_Div. */
392     kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[9U], 0U),           /*!< Mux SPI0_Clk from Fro. */
394 … kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[9U], 1U),       /*!< Mux SPI0_Clk from MainClk. */
396 … kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 2U),       /*!< Mux SPI0_Clk from Frg0Clk. */
398 … kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 3U),       /*!< Mux SPI0_Clk from Frg1Clk. */
400 … kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[9U], 4U),       /*!< Mux SPI0_Clk from Fro_Div. */
402     kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[10U], 0U),          /*!< Mux SPI1_Clk from Fro. */
404 … kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[10U], 1U),      /*!< Mux SPI1_Clk from MainClk. */
406 … kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 2U),      /*!< Mux SPI1_Clk from Frg0Clk. */
408 … kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 3U),      /*!< Mux SPI1_Clk from Frg1Clk. */
410 … kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[10U], 4U),      /*!< Mux SPI1_Clk from Fro_Div. */