Lines Matching refs:FCLKSEL

272     kUART0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[0U], 0U),          /*!< Mux UART0_Clk from Fro. */
274 …kUART0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[0U], 1U),      /*!< Mux UART0_Clk from MainClk. */
276 …kUART0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 2U),      /*!< Mux UART0_Clk from Frg0Clk. */
278 …kUART0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[0U], 3U),      /*!< Mux UART0_Clk from Frg1Clk. */
280 …kUART0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[0U], 4U),      /*!< Mux UART0_Clk from Fro_Div. */
282     kUART1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[1U], 0U),          /*!< Mux UART1_Clk from Fro. */
284 …kUART1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[1U], 1U),      /*!< Mux UART1_Clk from MainClk. */
286 …kUART1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 2U),      /*!< Mux UART1_Clk from Frg0Clk. */
288 …kUART1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[1U], 3U),      /*!< Mux UART1_Clk from Frg1Clk. */
290 …kUART1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[1U], 4U),      /*!< Mux UART1_Clk from Fro_Div. */
292     kUART2_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[2U], 0U),          /*!< Mux UART2_Clk from Fro. */
294 …kUART2_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[2U], 1U),      /*!< Mux UART2_Clk from MainClk. */
296 …kUART2_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 2U),      /*!< Mux UART2_Clk from Frg0Clk. */
298 …kUART2_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[2U], 3U),      /*!< Mux UART2_Clk from Frg1Clk. */
300 …kUART2_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[2U], 4U),      /*!< Mux UART2_Clk from Fro_Div. */
302     kUART3_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[3U], 0U),          /*!< Mux UART3_Clk from Fro. */
304 …kUART3_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[3U], 1U),      /*!< Mux UART3_Clk from MainClk. */
306 …kUART3_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 2U),      /*!< Mux UART3_Clk from Frg0Clk. */
308 …kUART3_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[3U], 3U),      /*!< Mux UART3_Clk from Frg1Clk. */
310 …kUART3_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[3U], 4U),      /*!< Mux UART3_Clk from Fro_Div. */
312     kUART4_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[4U], 0U),          /*!< Mux UART4_Clk from Fro. */
314 …kUART4_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[4U], 1U),      /*!< Mux UART4_Clk from MainClk. */
316 …kUART4_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 2U),      /*!< Mux UART4_Clk from Frg0Clk. */
318 …kUART4_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[4U], 3U),      /*!< Mux UART4_Clk from Frg1Clk. */
320 …kUART4_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[4U], 4U),      /*!< Mux UART4_Clk from Fro_Div. */
322     kI2C0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[5U], 0U),           /*!< Mux I2C0_Clk from Fro. */
324 … kI2C0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[5U], 1U),       /*!< Mux I2C0_Clk from MainClk. */
326 … kI2C0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 2U),       /*!< Mux I2C0_Clk from Frg0Clk. */
328 … kI2C0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[5U], 3U),       /*!< Mux I2C0_Clk from Frg1Clk. */
330 … kI2C0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[5U], 4U),       /*!< Mux I2C0_Clk from Fro_Div. */
332     kI2C1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[6U], 0U),           /*!< Mux I2C1_Clk from Fro. */
334 … kI2C1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[6U], 1U),       /*!< Mux I2C1_Clk from MainClk. */
336 … kI2C1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 2U),       /*!< Mux I2C1_Clk from Frg0Clk. */
338 … kI2C1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[6U], 3U),       /*!< Mux I2C1_Clk from Frg1Clk. */
340 … kI2C1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[6U], 4U),       /*!< Mux I2C1_Clk from Fro_Div. */
342     kSPI0_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[9U], 0U),           /*!< Mux SPI0_Clk from Fro. */
344 … kSPI0_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[9U], 1U),       /*!< Mux SPI0_Clk from MainClk. */
346 … kSPI0_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 2U),       /*!< Mux SPI0_Clk from Frg0Clk. */
348 … kSPI0_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[9U], 3U),       /*!< Mux SPI0_Clk from Frg1Clk. */
350 … kSPI0_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[9U], 4U),       /*!< Mux SPI0_Clk from Fro_Div. */
352     kSPI1_Clk_From_Fro = CLK_MUX_DEFINE(FCLKSEL[10U], 0U),          /*!< Mux SPI1_Clk from Fro. */
354 … kSPI1_Clk_From_MainClk = CLK_MUX_DEFINE(FCLKSEL[10U], 1U),      /*!< Mux SPI1_Clk from MainClk. */
356 … kSPI1_Clk_From_Frg0Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 2U),      /*!< Mux SPI1_Clk from Frg0Clk. */
358 … kSPI1_Clk_From_Frg1Clk = CLK_MUX_DEFINE(FCLKSEL[10U], 3U),      /*!< Mux SPI1_Clk from Frg1Clk. */
360 … kSPI1_Clk_From_Fro_Div = CLK_MUX_DEFINE(FCLKSEL[10U], 4U),      /*!< Mux SPI1_Clk from Fro_Div. */