Lines Matching full:description
6 <description>LPC55S36JBD100,LPC55S36JHI48</description>
28 <description>no description available</description>
43 <description>Status register</description>
52 …<description>PKC active: ACTIV=1 signals that a calculation is in progress or about to start</desc…
59 …description>Carry overflow flag: CARRY is set by the PKC at the end of a calculation in case; - an…
66 …<description>Zero result flag: ZERO is set by the PKC at the end of a calculation in case the resu…
73 … <description>Combined GO status flag: GOANY is set in case either PKC_CTRL</description>
80 <description>Asserted high by HW when the PKC_PROT_WORD is ready</description>
87 …<description>Parameter set locked: Indicates if parameter set is locked due to a pending calculati…
96 <description>Control register</description>
105 …description>PKC reset control bit: RESET=1 enforces the PKC's reset state during which a calculati…
112 … <description>Freeze PKC calculation: STOP=1 freezes all PKC activity incl</description>
119 …description>Control bit to start direct operation using parameter set 1: If GOD1 is set PKC will s…
126 …description>Control bit to start direct operation using parameter set 2: If GOD2 is set PKC will s…
133 …description>Control bit to start MC pattern using parameter set 1: If GOM1 is set PKC will start a…
140 …description>Control bit to start MC pattern using parameter set 2: If GOM2 is set PKC will start a…
147 …description>Control bit to start pipe operation: If GOU is set PKC will start the pipe / layer2 op…
154 …<description>Convert to GF2 calculation modes: If GF2CONV is set operations are mapped to their GF…
161 …description>Clear universal pointer cache: Invalidates the cache such that all previously fetched …
168 …<description>Enable universal pointer cache: If CACHE_EN=1 the cache for the universal pointer par…
175 …<description>Reduced multiplier mode: REDMUL defines the operand width processed by the PKC coproc…
182 …<description>Asserted by SW to initiate a reload of the PKC_PROT_WORD, causes PW_READY to be clear…
191 <description>Configuration register</description>
200 …<description>Idle operation configuration: If IDLEOP is set idle / dummy operations are executed a…
207 <description>RFU</description>
214 <description>RFU</description>
221 …<description>Clock randomization configuration: CLKRND=1 activates the PKC clock randomization</de…
228 …<description>Noise in reduced multiplier mode feature not available in this version (flag is don't…
235 …<description>Random delay configuration: Define random delay cycles introduced randomly before and…
242 …<description>Noise in the SBOXES: When the SBOXES are not used circuitry is loaded with random dat…
249 …<description>Noise in Arith & Logic Path: When not used circuitry is loaded with random data t…
256 …<description>Noise in Full Multiplier Path: When not used circuitry is loaded with random data to …
265 <description>Mode register, parameter set 1</description>
274 …description>Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) …
283 <description>X+Y pointer register, parameter set 1</description>
292 …<description>Start address of X operand in PKCRAM with byte granularity: Least significant bits ar…
299 …<description>Start address of Y operand in PKCRAM with byte granularity: Least significant bits ar…
308 <description>Z+R pointer register, parameter set 1</description>
317 …description>Start address of Z operand in PKCRAM with byte granularity or constant for calculation…
324 …<description>Start address of R result in PKCRAM with byte granularity: Least significant bits are…
333 <description>Length register, parameter set 1</description>
342 …<description>Operand length: LEN defines the length of the operands and the result in bytes</descr…
349 …description>Loop counter for microcode pattern: MCLEN defines the length of the loop counter that …
358 <description>Mode register, parameter set 2</description>
367 …description>Calculation Mode / MC Start address:; Calculation mode of direct calculation (layer0) …
376 <description>X+Y pointer register, parameter set 2</description>
385 …<description>Start address of X operand in PKCRAM with byte granularity: Least significant bits ar…
392 …<description>Start address of Y operand in PKCRAM with byte granularity: Least significant bits ar…
401 <description>Z+R pointer register, parameter set 2</description>
410 …description>Start address of Z operand in PKCRAM with byte granularity or constant for calculation…
417 …<description>Start address of R result in PKCRAM with byte granularity: Least significant bits are…
426 <description>Length register, parameter set 2</description>
435 …<description>Operand length: LEN defines the length of the operands and the result in bytes</descr…
442 …description>Loop counter for microcode pattern: MCLEN defines the length of the loop counter that …
451 <description>Universal pointer FUP program</description>
460 …description>Pointer to start address of PKC FUP program: PKC_UPTR needs to be defined before start…
469 <description>Universal pointer FUP table</description>
478 …description>Pointer to start address of PKC FUP table: PKC_UPTRT needs to be defined before starti…
487 <description>Universal pointer length</description>
496 …description>Length of universal pointer calculation: PKC_ULEN defines how many FUP program entries…
505 <description>MC pattern data interface</description>
514 …<description>Microcode read/write data: Read access to PKC_MCDATA returns the 32-bit MC pattern ad…
523 <description>PKC version register</description>
532 <description>native multiplier size and operand granularity</description>
539 <description>MC feature (layer1 calculation) is available</description>
546 <description>UP feature (layer2 calculation) is available</description>
553 <description>UP cache is available</description>
560 <description>GF2 calculation modes are available</description>
567 <description>Number of parameter sets for real calculation</description>
574 <description>SBX0 operation is available</description>
581 <description>SBX1 operation is available</description>
588 <description>SBX2 operation is available</description>
595 <description>SBX3 operation is available</description>
602 <description>Size of reconfigurable MC table in bytes</description>
611 <description>Software reset</description>
620 <description>Write 1 to reset module (0 has no effect)</description>
629 <description>Access Error</description>
638 <description>APB Error: address not available</description>
645 <description>APB Error: Wrong access mode</description>
652 … <description>APB Master that triggered first APB error (APB_WRGMD or APB_NOTAV)</description>
659 <description>AHB Error: invalid AHB access Layer2 Only</description>
666 <description>Error in PKC coprocessor kernel</description>
673 <description>Error due to error detection circuitry</description>
680 <description>Error in PKC software control</description>
687 <description>Error in layer2 CRC check</description>
696 <description>Clear Access Error</description>
705 <description>Write 1 to reset PKC_ACCESS_ERR SFR.</description>
714 <description>Interrupt enable clear</description>
723 … <description>Write to clear PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=0).</description>
732 <description>Interrupt enable set</description>
741 … <description>Write to set PDONE interrupt enable flag (PKC_INT_ENABLE.EN_PDONE=1).</description>
750 <description>Interrupt status</description>
759 …<description>End-of-computation status flag: INT_PDONE is set after EACH single PKC layer0 or laye…
768 <description>Interrupt enable</description>
777 …<description>PDONE interrupt enable flag: If EN_PDONE=1 an interrupt is triggered every time PKC_I…
786 <description>Interrupt status clear</description>
795 …<description>Write to clear End-of-computation status flag (PKC_INT_STATUS.INT_PDONE=0).</descript…
804 <description>Interrupt status set</description>
813 <description>Write to set End-of-computation status flag (PKC_INT_STATUS</description>
822 <description>SFR Data Mask</description>
831 …description>32-bit mask used for SW assisted SFR-IF masking; The PKC applies the mask on all APB r…
840 <description>Module ID</description>
849 <description>Address space of the IP</description>
856 <description>Minor revision</description>
863 <description>Major revision</description>
870 <description>Module ID</description>
881 <description>SYSCON</description>
892 <description>Memory Remap Control</description>
901 <description>Select the location of the vector table:</description>
908 <description>Vector Table in ROM.</description>
913 <description>Vector Table in RAM.</description>
918 <description>Vector Table in Flash.</description>
927 <description>AHB Matrix priority control</description>
936 <description>CPU0 C-AHB bus.</description>
943 <description>CPU0 S-AHB bus.</description>
950 <description>USB0-FS Device.(USB0)</description>
957 <description>DMA0 controller priority.</description>
964 <description>EZH B data bus.</description>
971 <description>EZH B instruction bus.</description>
978 <description>PQ (HW Accelerator).</description>
985 <description>CSSV2</description>
992 <description>USB-FS host</description>
999 <description>DMA1 controller priority.</description>
1006 <description>MCAN</description>
1013 <description>PKC</description>
1022 <description>AHB Matrix priority control</description>
1031 <description>DSP D bus</description>
1038 <description>DSP I bus</description>
1047 …<description>Buffering of write accesses on Synchronous System configuration APB interface</descri…
1056 …<description>Enable buffering of write accesses on Synchronous System configuration APB interface:…
1063 <description>Disable buffering.</description>
1068 <description>Enable buffering.</description>
1075 … <description>Enable buffering of write accesses on IO Configuration APB interface:</description>
1082 <description>Disable buffering.</description>
1087 <description>Enable buffering.</description>
1094 …<description>Enable buffering of write accesses on GPIO Global Interrupt APB interface:</descripti…
1101 <description>Disable buffering.</description>
1106 <description>Enable buffering.</description>
1113 …<description>Enable buffering of write accesses on GPIO Global Interrupt APB interface:</descripti…
1120 <description>Disable buffering.</description>
1125 <description>Enable buffering.</description>
1132 … <description>Enable buffering of write accesses on GPIO Int APB interface:</description>
1139 <description>Disable buffering.</description>
1144 <description>Enable buffering.</description>
1151 … <description>Enable buffering of write accesses on secure GPIO Int APB interface:</description>
1158 <description>Disable buffering.</description>
1163 <description>Enable buffering.</description>
1170 …<description>Enable buffering of write accesses on Peripheral Input Mux APB interface:</descriptio…
1177 <description>Disable buffering.</description>
1182 <description>Enable buffering.</description>
1189 … <description>Enable buffering of write accesses on Counter/Timer0 APB interface:</description>
1196 <description>Disable buffering.</description>
1201 <description>Enable buffering.</description>
1208 … <description>Enable buffering of write accesses on Counter/Timer1 APB interface:</description>
1215 <description>Disable buffering.</description>
1220 <description>Enable buffering.</description>
1227 … <description>Enable buffering of write accesses on Watchdog Timer APB interface:</description>
1234 <description>Disable buffering.</description>
1239 <description>Enable buffering.</description>
1246 <description>Enable buffering of write ac.</description>
1253 <description>Disable buffering.</description>
1258 <description>Enable buffering.</description>
1265 … <description>Enable buffering of write accesses on micro Tick APB interface:</description>
1272 <description>Disable buffering.</description>
1277 <description>Enable buffering.</description>
1284 <description>ITRC</description>
1291 <description>Disable buffering.</description>
1296 <description>Enable buffering.</description>
1303 … <description>Enable buffering of write accesses on analog control APB interface:</description>
1310 <description>Disable buffering.</description>
1315 <description>Enable buffering.</description>
1322 … <description>Enable buffering of write accesses on eFUSE controller APB interface:</description>
1329 <description>Disable buffering.</description>
1334 <description>Enable buffering.</description>
1341 <description>Enable buffering of write accesses on I3C APB interface:</description>
1348 <description>Disable buffering.</description>
1353 <description>Enable buffering.</description>
1360 …<description>Enable buffering of write accesses on capacitive touch control APB interface:</descri…
1367 <description>Disable buffering.</description>
1372 <description>Enable buffering.</description>
1379 <description>Enable buffering of write accesses on SCTIUP APB interface:</description>
1386 <description>Disable buffering.</description>
1391 <description>Enable buffering.</description>
1398 <description>Enable buffering of write accesses on EZH APB interface:</description>
1405 <description>Disable buffering.</description>
1410 <description>Enable buffering.</description>
1417 … <description>Enable buffering of write accesses on prob IS (sync) APB interface:</description>
1424 <description>Disable buffering.</description>
1429 <description>Enable buffering.</description>
1436 … <description>Enable buffering of write accesses on prob IS (XVC) APB interface:</description>
1443 <description>Disable buffering.</description>
1448 <description>Enable buffering.</description>
1457 …<description>Buffering of write accesses on Synchronous System configuration APB interface</descri…
1466 …<description>Enable buffering of write accesses on Power Management Controller APB interface:</des…
1473 <description>Disable buffering.</description>
1478 <description>Enable buffering.</description>
1485 … <description>Enable buffering of write accesses on PVT monitor APB interface:</description>
1492 <description>Disable buffering.</description>
1497 <description>Enable buffering.</description>
1504 … <description>Enable buffering of write accesses on system control APB interface:</description>
1511 <description>Disable buffering.</description>
1516 <description>Enable buffering.</description>
1523 <description>Enable buffering of write accesses on SPIF APB interface:</description>
1530 <description>Disable buffering.</description>
1535 <description>Enable buffering.</description>
1542 … <description>Enable buffering of write accesses on Counter/Timer2 APB interface:</description>
1549 <description>Disable buffering.</description>
1554 <description>Enable buffering.</description>
1561 … <description>Enable buffering of write accesses on Counter/Timer3 APB interface:</description>
1568 <description>Disable buffering.</description>
1573 <description>Enable buffering.</description>
1580 … <description>Enable buffering of write accesses on Counter/Timer4 APB interface:</description>
1587 <description>Disable buffering.</description>
1592 <description>Enable buffering.</description>
1599 <description>Enable buffering of write accesses on RTC APB interface:</description>
1606 <description>Disable buffering.</description>
1611 <description>Enable buffering.</description>
1618 … <description>Enable buffering of write accesses on OS event timer APB interface:</description>
1625 <description>Disable buffering.</description>
1630 <description>Enable buffering.</description>
1637 <description>Enable buffering of write accesses on CSS APB interface:</description>
1644 <description>Disable buffering.</description>
1649 <description>Enable buffering.</description>
1656 <description>Enable buffering of write accesses on PKC APB interface:</description>
1663 <description>Disable buffering.</description>
1668 <description>Enable buffering.</description>
1675 … <description>Enable buffering of write accesses on Flash Controller APB interface:</description>
1682 <description>Disable buffering.</description>
1687 <description>Enable buffering.</description>
1694 <description>Enable buffering of write accesses on Prince APB interface:</description>
1701 <description>Disable buffering.</description>
1706 <description>Enable buffering.</description>
1713 …<description>Enable buffering of write accesses on Random Number Generator APB interface:</descrip…
1720 <description>Disable buffering.</description>
1725 <description>Enable buffering.</description>
1732 <description>Enable buffering of write accesses on PUFF interface:</description>
1739 <description>Disable buffering.</description>
1744 <description>Enable buffering.</description>
1751 … <description>Enable buffering of write accesses on Code Patch Unit APB interface:</description>
1758 <description>Disable buffering.</description>
1763 <description>Enable buffering.</description>
1772 <description>System tick calibration for secure part of CPU0</description>
1781 …description>Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the valu…
1788 <description>Indicates whether the TENMS value is exact:</description>
1795 <description>TENMS value is exact</description>
1800 <description>TENMS value is inexact, or not given</description>
1807 …<description>Indicates whether the device provides a reference clock to the processor</description>
1814 <description>Reference clock provided</description>
1819 <description>No reference clock provided</description>
1828 <description>System tick calibration for non-secure part of CPU0</description>
1837 …description>Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the va…
1844 <description>Indicates whether the TENMS value is exact:</description>
1851 <description>TENMS value is exact</description>
1856 <description>TENMS value is inexact, or not given</description>
1863 …<description>Indicates whether the device provides a reference clock to the processor:</descriptio…
1870 <description>Reference clock provided</description>
1875 <description>No reference clock provided</description>
1884 <description>CPU IRQ latency control - SPARE REGISTER - NOT USED</description>
1893 <description>CPU0 interrupt latency control.</description>
1902 <description>NMI Source Select</description>
1911 …<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the…
1918 …<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by I…
1927 <description>Peripheral reset control 0</description>
1936 <description>ROM reset control.</description>
1943 <description>Block is not reset.</description>
1948 <description>Block is reset.</description>
1955 <description>SRAM Controller 1 reset control.</description>
1962 <description>Block is not reset.</description>
1967 <description>Block is reset.</description>
1974 <description>SRAM Controller 2 reset control.</description>
1981 <description>Block is not reset.</description>
1986 <description>Block is reset.</description>
1993 <description>SRAM Controller 3 reset control.</description>
2000 <description>Block is not reset.</description>
2005 <description>Block is reset.</description>
2012 <description>SRAM Controller 4 reset control.</description>
2019 <description>Block is not reset.</description>
2024 <description>Block is reset.</description>
2031 <description>Flash controller reset control.</description>
2038 <description>Block is not reset.</description>
2043 <description>Block is reset.</description>
2050 <description>FMC controller reset control.</description>
2057 <description>Block is not reset.</description>
2062 <description>Block is reset.</description>
2069 <description>FLEXSPI reset control</description>
2076 <description>Block is not reset.</description>
2081 <description>Block is reset.</description>
2088 <description>Input Mux reset control.</description>
2095 <description>Block is not reset.</description>
2100 <description>Block is reset.</description>
2107 <description>I/O controller reset control.</description>
2114 <description>Block is not reset.</description>
2119 <description>Block is reset.</description>
2126 <description>GPIO0 reset control.</description>
2133 <description>Block is not reset.</description>
2138 <description>Block is reset.</description>
2145 <description>GPIO1 reset control.</description>
2152 <description>Block is not reset.</description>
2157 <description>Block is reset.</description>
2164 <description>GPIO2 reset control.</description>
2171 <description>Block is not reset.</description>
2176 <description>Block is reset.</description>
2183 <description>GPIO3 reset control.</description>
2190 <description>Block is not reset.</description>
2195 <description>Block is reset.</description>
2202 <description>Pin interrupt (PINT) reset control.</description>
2209 <description>Block is not reset.</description>
2214 <description>Block is reset.</description>
2221 <description>Group interrupt (GINT) reset control.</description>
2228 <description>Block is not reset.</description>
2233 <description>Block is reset.</description>
2240 <description>DMA0 reset control.</description>
2247 <description>Block is not reset.</description>
2252 <description>Block is reset.</description>
2259 <description>CRCGEN reset control.</description>
2266 <description>Block is not reset.</description>
2271 <description>Block is reset.</description>
2278 <description>Watchdog Timer reset control.</description>
2285 <description>Block is not reset.</description>
2290 <description>Block is reset.</description>
2297 <description>Real Time Clock (RTC) reset control.</description>
2304 <description>Block is not reset.</description>
2309 <description>Block is reset.</description>
2316 <description>Inter CPU communication Mailbox reset control.</description>
2323 <description>Block is not reset.</description>
2328 <description>Block is reset.</description>
2335 <description>ADC0 reset control.</description>
2342 <description>Block is not reset.</description>
2347 <description>Block is reset.</description>
2354 <description>ADC1 reset control.</description>
2361 <description>Block is not reset.</description>
2366 <description>Block is reset.</description>
2373 <description>DAC0 reset control.</description>
2380 <description>Block is not reset.</description>
2385 <description>Block is reset.</description>
2394 <description>Peripheral reset control 1</description>
2403 <description>MRT reset control.</description>
2410 <description>Block is not reset.</description>
2415 <description>Block is reset.</description>
2422 <description>OS Event Timer reset control.</description>
2429 <description>Block is not reset.</description>
2434 <description>Block is reset.</description>
2441 <description>SCT reset control.</description>
2448 <description>Block is not reset.</description>
2453 <description>Block is reset.</description>
2460 <description>UTICK reset control.</description>
2467 <description>Block is not reset.</description>
2472 <description>Block is reset.</description>
2479 <description>FC0 reset control.</description>
2486 <description>Block is not reset.</description>
2491 <description>Block is reset.</description>
2498 <description>FC1 reset control.</description>
2505 <description>Block is not reset.</description>
2510 <description>Block is reset.</description>
2517 <description>FC2 reset control.</description>
2524 <description>Block is not reset.</description>
2529 <description>Block is reset.</description>
2536 <description>FC3 reset control.</description>
2543 <description>Block is not reset.</description>
2548 <description>Block is reset.</description>
2555 <description>FC4 reset control.</description>
2562 <description>Block is not reset.</description>
2567 <description>Block is reset.</description>
2574 <description>FC5 reset control.</description>
2581 <description>Block is not reset.</description>
2586 <description>Block is reset.</description>
2593 <description>FC6 reset control.</description>
2600 <description>Block is not reset.</description>
2605 <description>Block is reset.</description>
2612 <description>FC7 reset control.</description>
2619 <description>Block is not reset.</description>
2624 <description>Block is reset.</description>
2631 <description>DMIC reset control.</description>
2638 <description>Block is not reset.</description>
2643 <description>Block is reset.</description>
2650 <description>Timer 2 reset control.</description>
2657 <description>Block is not reset.</description>
2662 <description>Block is reset.</description>
2669 <description>USB0-FS DEV reset control.</description>
2676 <description>Block is not reset.</description>
2681 <description>Block is reset.</description>
2688 <description>Timer 0 reset control.</description>
2695 <description>Block is not reset.</description>
2700 <description>Block is reset.</description>
2707 <description>Timer 1 reset control.</description>
2714 <description>Block is not reset.</description>
2719 <description>Block is reset.</description>
2726 <description>PVT reset control.</description>
2733 <description>Block is not reset.</description>
2738 <description>Block is reset.</description>
2745 <description>EZH a reset control.</description>
2752 <description>Block is not reset.</description>
2757 <description>Block is reset.</description>
2764 <description>EZH b reset control.</description>
2771 <description>Block is not reset.</description>
2776 <description>Block is reset.</description>
2785 <description>Peripheral reset control 2</description>
2794 <description>DMA1 reset control.</description>
2801 <description>Block is not reset.</description>
2806 <description>Block is reset.</description>
2813 <description>Comparator reset control.</description>
2820 <description>Block is not reset.</description>
2825 <description>Block is reset.</description>
2832 <description>Frequency meter reset control.</description>
2839 <description>Block is not reset.</description>
2844 <description>Block is reset.</description>
2851 <description>GPIO4 reset control.</description>
2858 <description>Block is not reset.</description>
2863 <description>Block is reset.</description>
2870 <description>GPIO5 reset control.</description>
2877 <description>Block is not reset.</description>
2882 <description>Block is reset.</description>
2889 <description>OTP reset control.</description>
2896 <description>Block is not reset.</description>
2901 <description>Block is reset.</description>
2908 <description>RNG reset control.</description>
2915 <description>Block is not reset.</description>
2920 <description>Block is reset.</description>
2927 <description>Peripheral Input Mux 1 reset control.</description>
2934 <description>Block is not reset.</description>
2939 <description>Block is reset.</description>
2946 <description>SYSCTL Block reset.</description>
2953 <description>Block is not reset.</description>
2958 <description>Block is reset.</description>
2965 <description>USB0-FS Host Master reset control.</description>
2972 <description>Block is not reset.</description>
2977 <description>Block is reset.</description>
2984 <description>USB0-FS Host Slave reset control.</description>
2991 <description>Block is not reset.</description>
2996 <description>Block is reset.</description>
3003 <description>CSS reset control.</description>
3010 <description>Block is not reset.</description>
3015 <description>Block is reset.</description>
3022 <description>Power Quad reset control.</description>
3029 <description>Block is not reset.</description>
3034 <description>Block is reset.</description>
3041 <description>Timer 3 reset control.</description>
3048 <description>Block is not reset.</description>
3053 <description>Block is reset.</description>
3060 <description>Timer 4 reset control.</description>
3067 <description>Block is not reset.</description>
3072 <description>Block is reset.</description>
3079 <description>PKC reset control.</description>
3086 <description>Block is not reset.g</description>
3091 <description>Block is reset.</description>
3098 <description>CAPT0 reset control.</description>
3105 <description>Block is not reset.</description>
3110 <description>Block is reset.</description>
3117 <description>Analog control reset control.</description>
3124 <description>Block is not reset.</description>
3129 <description>Block is reset.</description>
3136 <description>PMUX1 reset control.</description>
3143 <description>Block is not reset.</description>
3148 <description>Block is reset.</description>
3155 <description>GPIO secure reset control.</description>
3162 <description>Block is not reset.</description>
3167 <description>Block is reset.</description>
3174 <description>GPIO secure int reset control.</description>
3181 <description>Block is not reset.</description>
3186 <description>Block is reset.</description>
3193 <description>SPI Filter reset control.</description>
3200 <description>Block is not reset.</description>
3205 <description>Block is reset.</description>
3214 <description>Peripheral reset control 3</description>
3223 <description>I3C reset control</description>
3230 <description>Block is not reset.</description>
3235 <description>Block is reset.</description>
3242 <description>ENC0 reset control</description>
3249 <description>Block is not reset.</description>
3254 <description>Block is reset.</description>
3261 <description>ENC1 reset control</description>
3268 <description>Block is not reset.</description>
3273 <description>Block is reset.</description>
3280 <description>PWM0 reset control</description>
3287 <description>Block is not reset.</description>
3292 <description>Block is reset.</description>
3299 <description>PWM1 reset control</description>
3306 <description>Block is not reset.</description>
3311 <description>Block is reset.</description>
3318 <description>AOI0 reset control</description>
3325 <description>Block is not reset.</description>
3330 <description>Block is reset.</description>
3337 <description>AOI1 reset control</description>
3344 <description>Block is not reset.</description>
3349 <description>Block is reset.</description>
3356 <description>FTM0 reset control</description>
3363 <description>Block is not reset.</description>
3368 <description>Block is reset.</description>
3375 <description>DAC1 reset control</description>
3382 <description>Block is not reset.</description>
3387 <description>Block is reset.</description>
3394 <description>DAC2 reset control</description>
3401 <description>Block is not reset.</description>
3406 <description>Block is reset.</description>
3413 <description>OPAMP0 reset control</description>
3420 <description>Block is not reset.</description>
3425 <description>Block is reset.</description>
3432 <description>OPAMP1 reset control</description>
3439 <description>Block is not reset.</description>
3444 <description>Block is reset.</description>
3451 <description>OPAMP2 reset control</description>
3458 <description>Block is not reset.</description>
3463 <description>Block is reset.</description>
3470 <description>HSCMP0 reset control</description>
3477 <description>Block is not reset.</description>
3482 <description>Block is reset.</description>
3489 <description>HSCMP1 reset control</description>
3496 <description>Block is not reset.</description>
3501 <description>Block is reset.</description>
3508 <description>HSCMP2 reset control</description>
3515 <description>Block is not reset.</description>
3520 <description>Block is reset.</description>
3527 <description>VREF reset control</description>
3534 <description>Block is not reset.</description>
3539 <description>Block is reset.</description>
3548 <description>Peripheral reset control set n</description>
3557 <description>Data array value</description>
3566 <description>Peripheral reset control set n</description>
3575 <description>Data array value</description>
3584 <description>Peripheral reset control set n</description>
3593 <description>Data array value</description>
3600 <description>Data array value</description>
3609 <description>Peripheral reset control set n</description>
3618 <description>Data array value</description>
3627 <description>Peripheral reset control clear n</description>
3636 <description>Data array value</description>
3645 <description>Peripheral reset control clear n</description>
3654 <description>Data array value</description>
3663 <description>Peripheral reset control clear n</description>
3672 <description>Data array value</description>
3679 <description>Data array value</description>
3688 <description>Peripheral reset control clear n</description>
3697 <description>Data array value</description>
3706 <description>Software Reset</description>
3715 <description>Write 0x5A00_0001 to generate a software_reset.</description>
3724 <description>AHB Clock control 0</description>
3733 <description>Enables the clock for the ROM.</description>
3740 <description>Disable Clock.</description>
3745 <description>Enable Clock.</description>
3752 <description>Enables the clock for the SRAM Controller 1.</description>
3759 <description>Disable Clock.</description>
3764 <description>Enable Clock.</description>
3771 <description>Enables the clock for the SRAM Controller 2.</description>
3778 <description>Disable Clock.</description>
3783 <description>Enable Clock.</description>
3790 <description>Enables the clock for the SRAM Controller 3.</description>
3797 <description>Disable Clock.</description>
3802 <description>Enable Clock.</description>
3809 <description>Enables the clock for the SRAM Controller 4.</description>
3816 <description>Disable Clock.</description>
3821 <description>Enable Clock.</description>
3828 <description>Enables the clock for the Flash controller.</description>
3835 <description>Disable Clock.</description>
3840 <description>Enable Clock.</description>
3847 <description>Enables the clock for the FMC controller.</description>
3854 <description>Disable Clock.</description>
3859 <description>Enable Clock.</description>
3866 <description>Enables the clock for the Flexspi.</description>
3873 <description>Disable Clock.</description>
3878 <description>Enable Clock.</description>
3885 <description>Enables the clock for the Input Mux.</description>
3892 <description>Disable Clock.</description>
3897 <description>Enable Clock.</description>
3904 <description>Enables the clock for the I/O controller.</description>
3911 <description>Disable Clock.</description>
3916 <description>Enable Clock.</description>
3923 <description>Enables the clock for the GPIO0.</description>
3930 <description>Disable Clock.</description>
3935 <description>Enable Clock.</description>
3942 <description>Enables the clock for the GPIO1.</description>
3949 <description>Disable Clock.</description>
3954 <description>Enable Clock.</description>
3961 <description>Enables the clock for the GPIO2.</description>
3968 <description>Disable Clock.</description>
3973 <description>Enable Clock.</description>
3980 <description>Enables the clock for the GPIO3.</description>
3987 <description>Disable Clock.</description>
3992 <description>Enable Clock.</description>
3999 <description>Enables the clock for the Pin interrupt (PINT).</description>
4006 <description>Disable Clock.</description>
4011 <description>Enable Clock.</description>
4018 <description>Enables the clock for the Group interrupt (GINT).</description>
4025 <description>Disable Clock.</description>
4030 <description>Enable Clock.</description>
4037 <description>Enables the clock for the DMA0.</description>
4044 <description>Disable Clock.</description>
4049 <description>Enable Clock.</description>
4056 <description>Enables the clock for the CRCGEN.</description>
4063 <description>Disable Clock.</description>
4068 <description>Enable Clock.</description>
4075 <description>Enables the clock for the Watchdog Timer.</description>
4082 <description>Disable Clock.</description>
4087 <description>Enable Clock.</description>
4094 <description>Enables the clock for the Real Time Clock (RTC).</description>
4101 <description>Disable Clock.</description>
4106 <description>Enable Clock.</description>
4113 <description>Enables the clock for the Inter CPU communication Mailbox.</description>
4120 <description>Disable Clock.</description>
4125 <description>Enable Clock.</description>
4132 <description>Enables the clock for ADC0.</description>
4139 <description>Disable Clock.</description>
4144 <description>Enable Clock.</description>
4151 <description>Enables the clock for ADC1.</description>
4158 <description>Disable Clock.</description>
4163 <description>Enable Clock.</description>
4170 <description>Enables the clock for DAC0.</description>
4177 <description>Disable Clock.</description>
4182 <description>Enable Clock.</description>
4191 <description>AHB Clock control 1</description>
4200 <description>Enables the clock for the MRT.</description>
4207 <description>Disable Clock.</description>
4212 <description>Enable Clock.</description>
4219 <description>Enables the clock for the OS Event Timer.</description>
4226 <description>Disable Clock.</description>
4231 <description>Enable Clock.</description>
4238 <description>Enables the clock for the SCT.</description>
4245 <description>Disable Clock.</description>
4250 <description>Enable Clock.</description>
4257 <description>Enables the clock for the SCTIPU.</description>
4264 <description>Disable Clock.</description>
4269 <description>Enable Clock.</description>
4276 <description>Enables the clock for the CAN.</description>
4283 <description>Disable Clock.</description>
4288 <description>Enable Clock.</description>
4295 <description>Enables the clock for the UTICK.</description>
4302 <description>Disable Clock.</description>
4307 <description>Enable Clock.</description>
4314 <description>Enables the clock for the FC0.</description>
4321 <description>Disable Clock.</description>
4326 <description>Enable Clock.</description>
4333 <description>Enables the clock for the FC1.</description>
4340 <description>Disable Clock.</description>
4345 <description>Enable Clock.</description>
4352 <description>Enables the clock for the FC2.</description>
4359 <description>Disable Clock.</description>
4364 <description>Enable Clock.</description>
4371 <description>Enables the clock for the FC3.</description>
4378 <description>Disable Clock.</description>
4383 <description>Enable Clock.</description>
4390 <description>Enables the clock for the FC4.</description>
4397 <description>Disable Clock.</description>
4402 <description>Enable Clock.</description>
4409 <description>Enables the clock for the FC5.</description>
4416 <description>Disable Clock.</description>
4421 <description>Enable Clock.</description>
4428 <description>Enables the clock for the FC6.</description>
4435 <description>Disable Clock.</description>
4440 <description>Enable Clock.</description>
4447 <description>Enables the clock for the FC7.</description>
4454 <description>Disable Clock.</description>
4459 <description>Enable Clock.</description>
4466 <description>Enables the clock for DMIC.</description>
4473 <description>Disable Clock.</description>
4478 <description>Enable Clock.</description>
4485 <description>Enables the clock for the Timer 2.</description>
4492 <description>Disable Clock.</description>
4497 <description>Enable Clock.</description>
4504 <description>Enables the clock for the USB0-FS device.</description>
4511 <description>Disable Clock.</description>
4516 <description>Enable Clock.</description>
4523 <description>Enables the clock for the Timer 0.</description>
4530 <description>Disable Clock.</description>
4535 <description>Enable Clock.</description>
4542 <description>Enables the clock for the Timer 1.</description>
4549 <description>Disable Clock.</description>
4554 <description>Enable Clock.</description>
4561 <description>Enables the clock for the PVT.</description>
4568 <description>Disable Clock.</description>
4573 <description>Enable Clock.</description>
4580 <description>Enables the clock for the EZH a.</description>
4587 <description>Disable Clock.</description>
4592 <description>Enable Clock.</description>
4599 <description>Enables the clock for the EZH b.</description>
4606 <description>Disable Clock.</description>
4611 <description>Enable Clock.</description>
4620 <description>AHB Clock control 2</description>
4629 <description>Enables the clock for the DMA1.</description>
4636 <description>Disable Clock.</description>
4641 <description>Enable Clock.</description>
4648 <description>Enables the clock for the Comparator.</description>
4655 <description>Disable Clock.</description>
4660 <description>Enable Clock.</description>
4667 <description>Enables the clock for the Frequency meter.</description>
4674 <description>Disable Clock.</description>
4679 <description>Enable Clock.</description>
4686 <description>Enables the clock for the GPIO4.</description>
4693 <description>Disable Clock.</description>
4698 <description>Enable Clock.</description>
4705 <description>Enables the clock for the GPIO5.</description>
4712 <description>Disable Clock.</description>
4717 <description>Enable Clock.</description>
4724 <description>Enables the clock for the code watchdog.</description>
4731 <description>Disable Clock.</description>
4736 <description>Enable Clock.</description>
4743 <description>Enables the clock for the OTP.</description>
4750 <description>Disable Clock.</description>
4755 <description>Enable Clock.</description>
4762 <description>Enables the clock for the RNG.</description>
4769 <description>Disable Clock.</description>
4774 <description>Enable Clock.</description>
4781 <description>Enables the clock for Peripheral Input Mux 1.</description>
4788 <description>Disable Clock.</description>
4793 <description>Enable Clock.</description>
4800 <description>SYSCTL block clock.</description>
4807 <description>Disable Clock.</description>
4812 <description>Enable Clock.</description>
4819 <description>Enables the clock for the USB0-FS Host Master.</description>
4826 <description>Disable Clock.</description>
4831 <description>Enable Clock.</description>
4838 <description>Enables the clock for the USB0-FS Host Slave.</description>
4845 <description>Disable Clock.</description>
4850 <description>Enable Clock.</description>
4857 <description>Enables the clock for CSS.</description>
4864 <description>Disable Clock.</description>
4869 <description>Enable Clock.</description>
4876 <description>Enables the clock for the Power Quad.</description>
4883 <description>Disable Clock.</description>
4888 <description>Enable Clock.</description>
4895 <description>Enables the clock for the Timer 3.</description>
4902 <description>Disable Clock.</description>
4907 <description>Enable Clock.</description>
4914 <description>Enables the clock for the Timer 4.</description>
4921 <description>Disable Clock.</description>
4926 <description>Enable Clock.</description>
4933 <description>Enables the clock for the PKC.</description>
4940 <description>Disable Clock.</description>
4945 <description>Enable Clock.</description>
4952 <description>Enables the clock for the CAPT0.</description>
4959 <description>Disable Clock.</description>
4964 <description>Enable Clock.</description>
4971 <description>Enables the clock for the analog control.</description>
4978 <description>Disable Clock.</description>
4983 <description>Enable Clock.</description>
4990 <description>Enables the clock for the HS LSPI.</description>
4997 <description>Disable Clock.</description>
5002 <description>Enable Clock.</description>
5009 <description>Enables the clock for the GPIO secure.</description>
5016 <description>Disable Clock.</description>
5021 <description>Enable Clock.</description>
5028 <description>Enables the clock for the GPIO secure int.</description>
5035 <description>Disable Clock.</description>
5040 <description>Enable Clock.</description>
5047 <description>Enables the clock for the SPI Filter.</description>
5054 <description>Disable Clock.</description>
5059 <description>Enable Clock.</description>
5068 <description>AHB Clock Control 3</description>
5077 <description>Enables the clock for I3C0.</description>
5084 <description>Disable Clock.</description>
5089 <description>Enable Clock.</description>
5096 <description>Enables the clock for ENC0.</description>
5103 <description>Disable Clock.</description>
5108 <description>Enable Clock.</description>
5115 <description>Enables the clock for ENC1.</description>
5122 <description>Disable Clock.</description>
5127 <description>Enable Clock.</description>
5134 <description>Enables the clock for PWM0.</description>
5141 <description>Disable Clock.</description>
5146 <description>Enable Clock.</description>
5153 <description>Enables the clock for PWM1.</description>
5160 <description>Disable Clock.</description>
5165 <description>Enable Clock.</description>
5172 <description>Enables the clock for AOI0.</description>
5179 <description>Disable Clock.</description>
5184 <description>Enable Clock.</description>
5191 <description>Enables the clock for AOI1.</description>
5198 <description>Disable Clock.</description>
5203 <description>Enable Clock.</description>
5210 <description>Enables the clock for FTM0.</description>
5217 <description>Disable Clock.</description>
5222 <description>Enable Clock.</description>
5229 <description>Enables the clock for DAC1.</description>
5236 <description>Disable Clock.</description>
5241 <description>Enable Clock.</description>
5248 <description>Enables the clock for DAC2.</description>
5255 <description>Disable Clock.</description>
5260 <description>Enable Clock.</description>
5267 <description>Enables the clock for OPAMP0.</description>
5274 <description>Disable Clock.</description>
5279 <description>Enable Clock.</description>
5286 <description>Enables the clock for OPAMP1.</description>
5293 <description>Disable Clock.</description>
5298 <description>Enable Clock.</description>
5305 <description>Enables the clock for OPAMP2.</description>
5312 <description>Disable Clock.</description>
5317 <description>Enable Clock.</description>
5324 <description>Enables the clock for HSCMP0.</description>
5331 <description>Disable Clock.</description>
5336 <description>Enable Clock.</description>
5343 <description>Enables the clock for HSCMP1.</description>
5350 <description>Disable Clock.</description>
5355 <description>Enable Clock.</description>
5362 <description>Enables the clock for HSCMP2.</description>
5369 <description>Disable Clock.</description>
5374 <description>Enable Clock.</description>
5381 <description>Enables the clock for VREF.</description>
5388 <description>Disable Clock.</description>
5393 <description>Enable Clock.</description>
5404 <description>AHB Clock Control Set</description>
5413 <description>Data array value</description>
5424 <description>AHB Clock Control Clear</description>
5433 <description>Data array value</description>
5442 <description>System Tick Timer for CPU0 source select</description>
5451 <description>System Tick Timer for CPU0 source select.</description>
5458 <description>System Tick 0 divided clock.</description>
5463 <description>FRO 1MHz clock.</description>
5468 <description>Oscillator 32 kHz clock.</description>
5473 <description>No clock.</description>
5478 <description>No clock.</description>
5483 <description>No clock.</description>
5488 <description>No clock.</description>
5493 <description>No clock.</description>
5502 <description>Trace clock source select</description>
5511 <description>Trace clock source select.</description>
5518 <description>Trace divided clock.</description>
5523 <description>FRO 1MHz clock.</description>
5528 <description>Oscillator 32 kHz clock.</description>
5533 <description>No clock.</description>
5538 <description>No clock.</description>
5543 <description>No clock.</description>
5548 <description>No clock.</description>
5553 <description>No clock.</description>
5562 <description>CTimer 0 clock source select</description>
5571 <description>CTimer 0 clock source select.</description>
5578 <description>Main clock.</description>
5583 <description>PLL0 clock.</description>
5588 <description>PLL1 clock.</description>
5593 <description>FRO 96 MHz clock.</description>
5598 <description>FRO 1MHz clock.</description>
5603 <description>MCLK clock.</description>
5608 <description>Oscillator 32kHz clock.</description>
5613 <description>No clock.</description>
5622 <description>CTimer 1 clock source select</description>
5631 <description>CTimer 1 clock source select.</description>
5638 <description>Main clock.</description>
5643 <description>PLL0 clock.</description>
5648 <description>PLL1 clock.</description>
5653 <description>FRO 96 MHz clock.</description>
5658 <description>FRO 1MHz clock.</description>
5663 <description>MCLK clock.</description>
5668 <description>Oscillator 32kHz clock.</description>
5673 <description>No clock.</description>
5682 <description>CTimer 2 clock source select</description>
5691 <description>CTimer 2 clock source select.</description>
5698 <description>Main clock.</description>
5703 <description>PLL0 clock.</description>
5708 <description>PLL1 clock.</description>
5713 <description>FRO 96 MHz clock.</description>
5718 <description>FRO 1MHz clock.</description>
5723 <description>MCLK clock.</description>
5728 <description>Oscillator 32kHz clock.</description>
5733 <description>No clock.</description>
5742 <description>CTimer 3 clock source select</description>
5751 <description>CTimer 3 clock source select.</description>
5758 <description>Main clock.</description>
5763 <description>PLL0 clock.</description>
5768 <description>PLL1 clock.</description>
5773 <description>FRO 96 MHz clock.</description>
5778 <description>FRO 1MHz clock.</description>
5783 <description>MCLK clock.</description>
5788 <description>Oscillator 32kHz clock.</description>
5793 <description>No clock.</description>
5802 <description>CTimer 4 clock source select</description>
5811 <description>CTimer 4 clock source select.</description>
5818 <description>Main clock.</description>
5823 <description>PLL0 clock.</description>
5828 <description>PLL1 clock.</description>
5833 <description>FRO 96 MHz clock.</description>
5838 <description>FRO 1MHz clock.</description>
5843 <description>MCLK clock.</description>
5848 <description>Oscillator 32kHz clock.</description>
5853 <description>No clock.</description>
5862 <description>Main clock source select A</description>
5871 <description>Main clock source select A</description>
5878 <description>FRO 12 MHz clock.</description>
5883 <description>CLKIN clock.</description>
5888 <description>FRO 1MHz clock.</description>
5893 <description>FRO 96 MHz clock.</description>
5898 <description>FRO 12 MHz clock.</description>
5903 <description>CLKIN clock.</description>
5908 <description>FRO 1MHz clock.</description>
5913 <description>FRO 96 MHz clock.</description>
5922 <description>Main clock source select B</description>
5931 <description>Main clock source select B</description>
5938 <description>Use the source selected in MAINCLKSELA.</description>
5943 <description>PLL0 clock.</description>
5948 <description>PLL1 clock.</description>
5953 <description>Oscillator 32 kHz clock.</description>
5962 <description>CLKOUT clock source select</description>
5971 <description>CLKOUT clock source select.</description>
5978 <description>Main clock.</description>
5983 <description>PLL0 clock.</description>
5988 <description>CLKIN clock.</description>
5993 <description>FRO 96 MHz clock.</description>
5998 <description>FRO 1MHz clock.</description>
6003 <description>PLL1 clock.</description>
6008 <description>Oscillator 32kHz clock.</description>
6013 <description>No clock.</description>
6018 <description>ipg_clk_usbpll_postdiv_out0</description>
6023 <description>ipg_clk_usbpll_postdiv_out0</description>
6028 <description>ipg_clk_usbpll_postdiv_out0</description>
6033 <description>ipg_clk_usbpll_postdiv_out0</description>
6038 <description>No clock.</description>
6043 <description>No clock.</description>
6048 <description>No clock.</description>
6053 <description>No clock.</description>
6062 <description>PLL0 clock source select</description>
6071 <description>PLL0 clock source select.</description>
6078 <description>FRO 12 MHz clock.</description>
6083 <description>CLKIN clock.</description>
6088 <description>FRO 1MHz clock.</description>
6093 <description>Oscillator 32kHz clock.</description>
6098 <description>No clock.</description>
6103 <description>No clock.</description>
6108 <description>No clock.</description>
6113 <description>No clock.</description>
6122 <description>PLL1 clock source select</description>
6131 <description>PLL1 clock source select.</description>
6138 <description>FRO 12 MHz clock.</description>
6143 <description>CLKIN clock.</description>
6148 <description>FRO 1MHz clock.</description>
6153 <description>Oscillator 32kHz clock.</description>
6158 <description>No clock.</description>
6163 <description>No clock.</description>
6168 <description>No clock.</description>
6173 <description>No clock.</description>
6182 <description>ADC0 clock source select</description>
6191 <description>ADC clock source select.</description>
6198 <description>Main clock.</description>
6203 <description>PLL0 clock.</description>
6208 <description>FRO 96 MHz clock.</description>
6213 <description>FRO 1 MHz clock.</description>
6218 <description>No clock.</description>
6223 <description>No clock.</description>
6228 <description>No clock.</description>
6233 <description>No clock.</description>
6242 <description>FS USB clock source select</description>
6251 <description>FS USB clock source select.</description>
6258 <description>Main clock.</description>
6263 <description>PLL0 clock.</description>
6268 <description>No clock.</description>
6273 <description>FRO 96 MHz clock.</description>
6278 <description>No clock.</description>
6283 <description>PLL1 clock.</description>
6288 <description>No clock.</description>
6293 <description>No clock.</description>
6302 <description>Flexcomm 0 clock source select for Fractional Rate Divider</description>
6311 <description>Flexcomm 0 clock source select for Fractional Rate Divider.</description>
6318 <description>Main clock.</description>
6323 <description>system PLL divided clock.</description>
6328 <description>FRO 12 MHz clock.</description>
6333 <description>FRO 96 MHz clock.</description>
6338 <description>FRO 1MHz clock.</description>
6343 <description>MCLK clock.</description>
6348 <description>Oscillator 32 kHz clock.</description>
6353 <description>No clock.</description>
6362 <description>Flexcomm 1 clock source select for Fractional Rate Divider</description>
6371 <description>Flexcomm 1 clock source select for Fractional Rate Divider.</description>
6378 <description>Main clock.</description>
6383 <description>system PLL divided clock.</description>
6388 <description>FRO 12 MHz clock.</description>
6393 <description>FRO 96 MHz clock.</description>
6398 <description>FRO 1MHz clock.</description>
6403 <description>MCLK clock.</description>
6408 <description>Oscillator 32 kHz clock.</description>
6413 <description>No clock.</description>
6422 <description>Flexcomm 2 clock source select for Fractional Rate Divider</description>
6431 <description>Flexcomm 2 clock source select for Fractional Rate Divider.</description>
6438 <description>Main clock.</description>
6443 <description>system PLL divided clock.</description>
6448 <description>FRO 12 MHz clock.</description>
6453 <description>FRO 96 MHz clock.</description>
6458 <description>FRO 1MHz clock.</description>
6463 <description>MCLK clock.</description>
6468 <description>Oscillator 32 kHz clock.</description>
6473 <description>No clock.</description>
6482 <description>Flexcomm 3 clock source select for Fractional Rate Divider</description>
6491 <description>Flexcomm 3 clock source select for Fractional Rate Divider.</description>
6498 <description>Main clock.</description>
6503 <description>system PLL divided clock.</description>
6508 <description>FRO 12 MHz clock.</description>
6513 <description>FRO 96 MHz clock.</description>
6518 <description>FRO 1MHz clock.</description>
6523 <description>MCLK clock.</description>
6528 <description>Oscillator 32 kHz clock.</description>
6533 <description>No clock.</description>
6542 <description>Flexcomm 4 clock source select for Fractional Rate Divider</description>
6551 <description>Flexcomm 4 clock source select for Fractional Rate Divider.</description>
6558 <description>Main clock.</description>
6563 <description>system PLL divided clock.</description>
6568 <description>FRO 12 MHz clock.</description>
6573 <description>FRO 96 MHz clock.</description>
6578 <description>FRO 1MHz clock.</description>
6583 <description>MCLK clock.</description>
6588 <description>Oscillator 32 kHz clock.</description>
6593 <description>No clock.</description>
6602 <description>Flexcomm 5 clock source select for Fractional Rate Divider</description>
6611 <description>Flexcomm 5 clock source select for Fractional Rate Divider.</description>
6618 <description>Main clock.</description>
6623 <description>system PLL divided clock.</description>
6628 <description>FRO 12 MHz clock.</description>
6633 <description>FRO 96 MHz clock.</description>
6638 <description>FRO 1MHz clock.</description>
6643 <description>MCLK clock.</description>
6648 <description>Oscillator 32 kHz clock.</description>
6653 <description>No clock.</description>
6662 <description>Flexcomm 6 clock source select for Fractional Rate Divider</description>
6671 <description>Flexcomm 6 clock source select for Fractional Rate Divider.</description>
6678 <description>Main clock.</description>
6683 <description>system PLL divided clock.</description>
6688 <description>FRO 12 MHz clock.</description>
6693 <description>FRO 96 MHz clock.</description>
6698 <description>FRO 1MHz clock.</description>
6703 <description>MCLK clock.</description>
6708 <description>Oscillator 32 kHz clock.</description>
6713 <description>No clock.</description>
6722 <description>Flexcomm 7 clock source select for Fractional Rate Divider</description>
6731 <description>Flexcomm 7 clock source select for Fractional Rate Divider.</description>
6738 <description>Main clock.</description>
6743 <description>system PLL divided clock.</description>
6748 <description>FRO 12 MHz clock.</description>
6753 <description>FRO 96 MHz clock.</description>
6758 <description>FRO 1MHz clock.</description>
6763 <description>MCLK clock.</description>
6768 <description>Oscillator 32 kHz clock.</description>
6773 <description>No clock.</description>
6782 <description>HS LSPI clock source select</description>
6791 <description>HS LSPI clock source select.</description>
6798 <description>Main clock.</description>
6803 <description>system PLL divided clock.</description>
6808 <description>FRO 12 MHz clock.</description>
6813 <description>FRO 96 MHz clock.</description>
6818 <description>FRO 1MHz clock.</description>
6823 <description>No clock.</description>
6828 <description>Oscillator 32 kHz clock.</description>
6833 <description>No clock.</description>
6842 <description>MCLK clock source select</description>
6851 <description>MCLK clock source select.</description>
6858 <description>FRO 96 MHz clock.</description>
6863 <description>PLL0 clock.</description>
6868 <description>FRO 1 MHz clock.</description>
6873 <description>Main clock.</description>
6878 <description>No clock.</description>
6883 <description>No clock.</description>
6888 <description>No clock.</description>
6893 <description>No clock.</description>
6902 <description>Flash rclk clock source select</description>
6911 <description>MCLK clock source select.</description>
6918 <description>FRO 48 MHz clock.</description>
6923 <description>FRO 96 MHz clock.</description>
6932 <description>SCTimer/PWM clock source select</description>
6941 <description>SCTimer/PWM clock source select.</description>
6948 <description>Main clock.</description>
6953 <description>PLL0 clock.</description>
6958 <description>CLKIN clock.</description>
6963 <description>FRO 96 MHz clock.</description>
6968 <description>No clock.</description>
6973 <description>MCLK clock.</description>
6978 <description>No clock.</description>
6983 <description>No clock.</description>
6992 <description>Capacitive Touch clock source select</description>
7001 <description>Capacitive Touch clock source select.</description>
7008 <description>FRO 12 MHz clock.</description>
7013 <description>FRO 1 MHz clock.</description>
7018 <description>No clock.</description>
7023 <description>No clock.</description>
7028 <description>No clock.</description>
7033 <description>No clock.</description>
7038 <description>No clock.</description>
7043 <description>No clock.</description>
7052 <description>System Tick Timer divider for CPU0</description>
7061 <description>Clock divider value.</description>
7068 <description>Resets the divider counter.</description>
7075 <description>Divider is not reset.</description>
7080 <description>Divider is reset.</description>
7087 <description>Halts the divider counter.</description>
7094 <description>Divider clock is running.</description>
7099 <description>Divider clock is stopped.</description>
7106 <description>Divider status flag.</description>
7113 <description>Divider clock is stable.</description>
7118 <description>Clock frequency is not stable.</description>
7127 <description>TRACE clock divider</description>
7136 <description>Clock divider value.</description>
7143 <description>Resets the divider counter.</description>
7150 <description>Divider is not reset.</description>
7155 <description>Divider is reset.</description>
7162 <description>Halts the divider counter.</description>
7169 <description>Divider clock is running.</description>
7174 <description>Divider clock is stopped.</description>
7181 <description>Divider status flag.</description>
7188 <description>Divider clock is stable.</description>
7193 <description>Clock frequency is not stable.</description>
7202 <description>System clock divider</description>
7211 <description>Clock divider value.</description>
7218 <description>Resets the divider counter.</description>
7225 <description>Divider is not reset.</description>
7230 <description>Divider is reset.</description>
7237 <description>Halts the divider counter.</description>
7244 <description>Divider clock is running.</description>
7249 <description>Divider clock is stopped.</description>
7256 <description>Divider status flag.</description>
7263 <description>Divider clock is stable.</description>
7268 <description>Clock frequency is not stable.</description>
7277 <description>CLKOUT clock divider</description>
7286 <description>Clock divider value.</description>
7293 <description>Resets the divider counter.</description>
7300 <description>Divider is not reset.</description>
7305 <description>Divider is reset.</description>
7312 <description>Halts the divider counter.</description>
7319 <description>Divider clock is running.</description>
7324 <description>Divider clock is stopped.</description>
7331 <description>Divider status flag.</description>
7338 <description>Divider clock is stable.</description>
7343 <description>Clock frequency is not stable.</description>
7352 <description>FRO_HF (96MHz) clock divider</description>
7361 <description>Clock divider value.</description>
7368 <description>Resets the divider counter.</description>
7375 <description>Divider is not reset.</description>
7380 <description>Divider is reset.</description>
7387 <description>Halts the divider counter.</description>
7394 <description>Divider clock is running.</description>
7399 <description>Divider clock is stopped.</description>
7406 <description>Divider status flag.</description>
7413 <description>Divider clock is stable.</description>
7418 <description>Clock frequency is not stable.</description>
7427 <description>WDT clock divider</description>
7436 <description>Clock divider value.</description>
7443 <description>Resets the divider counter.</description>
7450 <description>Divider is not reset.</description>
7455 <description>Divider is reset.</description>
7462 <description>Halts the divider counter.</description>
7469 <description>Divider clock is running.</description>
7474 <description>Divider clock is stopped.</description>
7481 <description>Divider status flag.</description>
7488 <description>Divider clock is stable.</description>
7493 <description>Clock frequency is not stable.</description>
7502 <description>ADC0 clock divider</description>
7511 <description>Clock divider value.</description>
7518 <description>Resets the divider counter.</description>
7525 <description>Divider is not reset.</description>
7530 <description>Divider is reset.</description>
7537 <description>Halts the divider counter.</description>
7544 <description>Divider clock is running.</description>
7549 <description>Divider clock is stopped.</description>
7556 <description>Divider status flag.</description>
7563 <description>Divider clock is stable.</description>
7568 <description>Clock frequency is not stable.</description>
7577 <description>USB0-FS Clock divider</description>
7586 <description>Clock divider value.</description>
7593 <description>Resets the divider counter.</description>
7600 <description>Divider is not reset.</description>
7605 <description>Divider is reset.</description>
7612 <description>Halts the divider counter.</description>
7619 <description>Divider clock is running.</description>
7624 <description>Divider clock is stopped.</description>
7631 <description>Divider status flag.</description>
7638 <description>Divider clock is stable.</description>
7643 <description>Clock frequency is not stable.</description>
7652 <description>I2S MCLK clock divider</description>
7661 <description>Clock divider value.</description>
7668 <description>Resets the divider counter.</description>
7675 <description>Divider is not reset.</description>
7680 <description>Divider is reset.</description>
7687 <description>Halts the divider counter.</description>
7694 <description>Divider clock is running.</description>
7699 <description>Divider clock is stopped.</description>
7706 <description>Divider status flag.</description>
7713 <description>Divider clock is stable.</description>
7718 <description>Clock frequency is not stable.</description>
7727 <description>SCT/PWM clock divider</description>
7736 <description>Clock divider value.</description>
7743 <description>Resets the divider counter.</description>
7750 <description>Divider is not reset.</description>
7755 <description>Divider is reset.</description>
7762 <description>Halts the divider counter.</description>
7769 <description>Divider clock is running.</description>
7774 <description>Divider clock is stopped.</description>
7781 <description>Divider status flag.</description>
7788 <description>Divider clock is stable.</description>
7793 <description>Clock frequency is not stable.</description>
7802 <description>Capacitive Touch clock divider</description>
7811 <description>Clock divider value.</description>
7818 <description>Resets the divider counter.</description>
7825 <description>Divider is not reset.</description>
7830 <description>Divider is reset.</description>
7837 <description>Halts the divider counter.</description>
7844 <description>Divider clock is running.</description>
7849 <description>Divider clock is stopped.</description>
7856 <description>Divider status flag.</description>
7863 <description>Divider clock is stable.</description>
7868 <description>Clock frequency is not stable.</description>
7877 <description>PLL0 clock divider</description>
7886 <description>Clock divider value.</description>
7893 <description>Resets the divider counter.</description>
7900 <description>Divider is not reset.</description>
7905 <description>Divider is reset.</description>
7912 <description>Halts the divider counter.</description>
7919 <description>Divider clock is running.</description>
7924 <description>Divider clock is stopped.</description>
7931 <description>Divider status flag.</description>
7938 <description>Divider clock is stable.</description>
7943 <description>Clock frequency is not stable.</description>
7954 <description>CTimer i clock divider</description>
7963 <description>Clock divider value</description>
7970 <description>Resets the divider counter</description>
7977 <description>Divider is not reset</description>
7982 <description>Divider is reset</description>
7989 <description>Halts the divider counter</description>
7996 <description>Divider clock is running.</description>
8001 <description>Divider clock has stopped.</description>
8008 <description>Divider status flag</description>
8015 <description>Stable divider clock.</description>
8020 <description>Unstable clock frequency.</description>
8029 <description>Clock configuration unlock</description>
8038 …<description>Control clock configuration registers access (for example, xxxDIV, xxxSEL).</descript…
8045 <description>All hardware clock configruration are freeze.</description>
8050 <description>Update all clock configuration.</description>
8059 <description>FMC configuration</description>
8068 <description>Instruction fetch configuration.</description>
8075 <description>Instruction fetches from flash are not buffered.</description>
8080 <description>One buffer is used for all instruction fetches.</description>
8085 <description>All buffers may be used for instruction fetches.</description>
8092 <description>Data read configuration.</description>
8099 <description>Data accesses from flash are not buffered.</description>
8104 <description>One buffer is used for all data accesses.</description>
8109 <description>All buffers can be used for data accesses.</description>
8116 <description>Acceleration enable.</description>
8123 <description>Flash acceleration is disabled.</description>
8128 <description>Flash acceleration is enabled.</description>
8135 <description>Prefetch enable.</description>
8142 <description>No instruction prefetch is performed.</description>
8147 <description>Instruction prefetch is enabled.</description>
8154 <description>Prefetch override.</description>
8161 <description>Any previously initiated prefetch will be completed.</description>
8166 …description>Any previously initiated prefetch will be aborted, and the next flash line following t…
8173 <description>Flash memory access time.</description>
8180 … <description>1 system clock flash access time (for system clock rates up to 11 MHz).</description>
8185 …<description>2 system clocks flash access time (for system clock rates up to 22 MHz).</description>
8190 …<description>3 system clocks flash access time (for system clock rates up to 33 MHz).</description>
8195 …<description>4 system clocks flash access time (for system clock rates up to 44 MHz).</description>
8200 …<description>5 system clocks flash access time (for system clock rates up to 55 MHz).</description>
8205 …<description>6 system clocks flash access time (for system clock rates up to 66 MHz).</description>
8210 …<description>7 system clocks flash access time (for system clock rates up to 77 MHz).</description>
8215 …<description>8 system clocks flash access time (for system clock rates up to 88 MHz).</description>
8220 …<description>9 system clocks flash access time (for system clock rates up to 100 MHz).</descriptio…
8225 …<description>10 system clocks flash access time (for system clock rates up to 115 MHz).</descripti…
8230 …<description>11 system clocks flash access time (for system clock rates up to 130 MHz).</descripti…
8235 …<description>12 system clocks flash access time (for system clock rates up to 150 MHz).</descripti…
8242 <description>ECC error abort enable</description>
8249 <description>CLKDIV; default value is 00.</description>
8256 <description>1 division</description>
8261 <description>2 division</description>
8266 <description>3 division</description>
8271 <description>4 division</description>
8280 <description>ROM wait state</description>
8289 <description>ROM waiting arm core and other masters.</description>
8298 <description>USB0-FS need clock control</description>
8307 <description>USB0-FS Device USB0_NEEDCLK signal control:.</description>
8314 <description>Under hardware control.</description>
8319 <description>Forced high.</description>
8326 …<description>USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:.</…
8333 <description>Falling edge of device USB0_NEEDCLK triggers wake-up.</description>
8338 <description>Rising edge of device USB0_NEEDCLK triggers wake-up.</description>
8345 <description>USB0-FS Host USB0_NEEDCLK signal control:.</description>
8352 <description>Under hardware control.</description>
8357 <description>Forced high.</description>
8364 …<description>USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:.</de…
8371 <description>Falling edge of device USB0_NEEDCLK triggers wake-up.</description>
8376 <description>Rising edge of device USB0_NEEDCLK triggers wake-up.</description>
8383 <description>Internal pull-up disable control.</description>
8390 <description>Internal pull-up enable.</description>
8395 <description>Internal pull-up disable.</description>
8404 <description>USB0-FS need clock status</description>
8413 <description>USB0-FS Device USB0_NEEDCLK signal status:.</description>
8420 <description>USB0-FS Device clock is low.</description>
8425 <description>USB0-FS Device clock is high.</description>
8432 <description>USB0-FS Host USB0_NEEDCLK signal status:.</description>
8439 <description>USB0-FS Host clock is low.</description>
8444 <description>USB0-FS Host clock is high.</description>
8453 <description>EZH interrupt hijack</description>
8462 <description>EZH interrupt hijack.</description>
8471 <description>FMC flush control</description>
8480 <description>Flush control</description>
8487 <description>No action.</description>
8492 <description>Flush the FMC buffer contents.</description>
8501 <description>MCLK control</description>
8510 <description>MCLK control.</description>
8517 <description>input mode.</description>
8522 <description>output mode.</description>
8531 <description>Flash Banks control</description>
8540 <description>Flash Bank0 control.</description>
8547 …<description>Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor…
8552 …<description>1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased…
8559 <description>Flash Bank1 control.</description>
8566 …<description>Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor…
8571 …<description>1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased…
8578 <description>Flash Bank2 control.</description>
8585 …<description>Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor…
8590 …<description>1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased…
8599 <description>ADC1 clock source select</description>
8608 <description>ADC clock source select.</description>
8615 <description>Main clock.</description>
8620 <description>PLL0 clock.</description>
8625 <description>FRO 96 MHz clock.</description>
8630 <description>FRO 1 MHz clock.</description>
8635 <description>No clock.</description>
8640 <description>No clock.</description>
8645 <description>No clock.</description>
8650 <description>No clock.</description>
8659 <description>ADC1 clock divider</description>
8668 <description>Clock divider value.</description>
8675 <description>Resets the divider counter.</description>
8682 <description>Divider is not reset.</description>
8687 <description>Divider is reset.</description>
8694 <description>Halts the divider counter.</description>
8701 <description>Divider clock is running.</description>
8706 <description>Divider clock is stopped.</description>
8713 <description>Divider status flag.</description>
8720 <description>Divider clock is stable.</description>
8725 <description>Clock frequency is not stable.</description>
8734 <description>Control RAM interleave integration.</description>
8743 <description>Control RAM access for RAMX0 and RAMX1.</description>
8750 <description>RAM access to RAMX0 and RAMX1 is consecutive.</description>
8755 …<description>RAM access to RAMX0 and RAMX1 is interleaved. This setting is need for PKC L0 memory …
8764 <description>Reserved for Niobe4mini.</description>
8773 <description>Reserved for Niobe4mini.</description>
8782 <description>Reserved for Niobe4mini.</description>
8791 <description>DAC0 functional clock selection</description>
8800 <description>DAC clock source select.</description>
8807 <description>Main clock.</description>
8812 <description>PLL0 clock.</description>
8817 <description>No clock.</description>
8822 <description>FRO_HF.</description>
8827 <description>FRO_12M.</description>
8832 <description>PLL1 clock.</description>
8837 <description>FRO_1M.</description>
8842 <description>No clock.</description>
8851 <description>DAC0 functional clock divider</description>
8860 <description>Clock divider value.</description>
8867 <description>Resets the divider counter.</description>
8874 <description>Divider is not reset.</description>
8879 <description>Divider is reset.</description>
8886 <description>Halts the divider counter.</description>
8893 <description>Divider clock is running.</description>
8898 <description>Divider clock is stopped.</description>
8905 <description>Divider status flag.</description>
8912 <description>Divider clock is stable.</description>
8917 <description>Clock frequency is not stable.</description>
8926 <description>DAC1 functional clock selection</description>
8935 <description>DAC clock source select.</description>
8942 <description>Main clock.</description>
8947 <description>PLL0 clock.</description>
8952 <description>No clock.</description>
8957 <description>FRO_HF.</description>
8962 <description>FRO_12M.</description>
8967 <description>PLL1 clock.</description>
8972 <description>FRO_1M.</description>
8977 <description>No clock.</description>
8986 <description>DAC1 functional clock divider</description>
8995 <description>Clock divider value.</description>
9002 <description>Resets the divider counter.</description>
9009 <description>Divider is not reset.</description>
9014 <description>Divider is reset.</description>
9021 <description>Halts the divider counter.</description>
9028 <description>Divider clock is running.</description>
9033 <description>Divider clock is stopped.</description>
9040 <description>Divider status flag.</description>
9047 <description>Divider clock is stable.</description>
9052 <description>Clock frequency is not stable.</description>
9061 <description>DAC2 functional clock selection</description>
9070 <description>DAC clock source select.</description>
9077 <description>Main clock.</description>
9082 <description>PLL0 clock.</description>
9087 <description>No clock.</description>
9092 <description>FRO_HF.</description>
9097 <description>FRO_12M.</description>
9102 <description>PLL1 clock.</description>
9107 <description>FRO_1M.</description>
9112 <description>No clock.</description>
9121 <description>DAC2 functional clock divider</description>
9130 <description>Clock divider value.</description>
9137 <description>Resets the divider counter.</description>
9144 <description>Divider is not reset.</description>
9149 <description>Divider is reset.</description>
9156 <description>Halts the divider counter.</description>
9163 <description>Divider clock is running.</description>
9168 <description>Divider clock is stopped.</description>
9175 <description>Divider status flag.</description>
9182 <description>Divider clock is stable.</description>
9187 <description>Clock frequency is not stable.</description>
9196 <description>FLEXSPI clock selection</description>
9205 <description>Flexspi clock select</description>
9212 <description>Main clock</description>
9217 <description>PLL0 clock</description>
9222 <description>No clock</description>
9227 <description>FRO_HF</description>
9232 <description>No clock</description>
9237 <description>PLL1 clock</description>
9242 <description>No clock</description>
9247 <description>No clock</description>
9252 <description>No clock</description>
9257 <description>No clock</description>
9262 <description>No clock</description>
9267 <description>No clock</description>
9272 <description>No clock</description>
9277 <description>No clock</description>
9282 <description>No clock</description>
9287 <description>No clock</description>
9296 <description>FLEXSPI clock divider</description>
9305 <description>Clock divider value.</description>
9312 <description>Resets the divider counter.</description>
9319 <description>Divider is not reset.</description>
9324 <description>Divider is reset.</description>
9331 <description>Halts the divider counter.</description>
9338 <description>Divider clock is running.</description>
9343 <description>Divider clock is stopped.</description>
9350 <description>Divider status flag.</description>
9357 <description>Divider clock is stable.</description>
9362 <description>Clock frequency is not stable.</description>
9371 <description>Enable protection</description>
9380 <description>Enable control</description>
9389 <description>Enable protection duplicate</description>
9398 <description>Enable control</description>
9407 <description>CDPA base address</description>
9416 <description>Specifies the size of CDPA in number of pages.</description>
9425 <description>Flash hiding lockout address</description>
9434 <description>while flash hiding is disabled, register write is locked.</description>
9443 <description>Flash hiding base address</description>
9452 <description>Base address for flash hiding</description>
9461 <description>Flash hiding base DP address</description>
9470 <description>Base address for flash hiding</description>
9479 <description>Hiding size address</description>
9488 <description>Size address for flash hiding</description>
9497 <description>Hiding size DP address</description>
9506 <description>Size address for flash hiding</description>
9515 <description>PLL clock divider clock selection</description>
9524 <description>Flexspi clock select</description>
9531 <description>PLL0 clock</description>
9536 <description>PLL1 clock</description>
9541 <description>No clock</description>
9546 <description>No clock</description>
9551 <description>No clock</description>
9556 <description>No clock</description>
9561 <description>No clock</description>
9566 <description>No clock</description>
9575 <description>I3C functional clock selection</description>
9584 <description>I3C clock select</description>
9591 <description>Main clock</description>
9596 <description>FRO_HF_DIV</description>
9601 <description>No clock</description>
9606 <description>No clock</description>
9611 <description>No clock</description>
9616 <description>No clock</description>
9621 <description>No clock</description>
9626 <description>No clock</description>
9635 <description>I3C FCLK_STC clock selection</description>
9644 <description>I3C FCLK_STC clock select</description>
9651 <description>I3CFCLK</description>
9656 <description>FRO_1M</description>
9661 <description>No clock</description>
9666 <description>No clock</description>
9671 <description>No clock</description>
9676 <description>No clock</description>
9681 <description>No clock</description>
9686 <description>No clock</description>
9695 <description>I3C FCLK_STC clock divider</description>
9704 <description>Clock divider value.</description>
9711 <description>Resets the divider counter.</description>
9718 <description>Divider is not reset.</description>
9723 <description>Divider is reset.</description>
9730 <description>Halts the divider counter.</description>
9737 <description>Divider clock is running.</description>
9742 <description>Divider clock is stopped.</description>
9749 <description>Divider status flag.</description>
9756 <description>Divider clock is stable.</description>
9761 <description>Clock frequency is not stable.</description>
9770 <description>I3C FCLKS clock divider</description>
9779 <description>Clock divider value.</description>
9786 <description>Resets the divider counter.</description>
9793 <description>Divider is not reset.</description>
9798 <description>Divider is reset.</description>
9805 <description>Halts the divider counter.</description>
9812 <description>Divider clock is running.</description>
9817 <description>Divider clock is stopped.</description>
9824 <description>Divider status flag.</description>
9831 <description>Divider clock is stable.</description>
9836 <description>Clock frequency is not stable.</description>
9845 <description>I3C FCLK divider</description>
9854 <description>Clock divider value.</description>
9861 <description>Resets the divider counter.</description>
9868 <description>Divider is not reset.</description>
9873 <description>Divider is reset.</description>
9880 <description>Halts the divider counter.</description>
9887 <description>Divider clock is running.</description>
9892 <description>Divider clock is stopped.</description>
9899 <description>Divider status flag.</description>
9906 <description>Divider clock is stable.</description>
9911 <description>Clock frequency is not stable.</description>
9920 <description>I3C FCLK_S selection</description>
9929 <description>I3C FCLK_S clock select</description>
9936 <description>FRO_1M</description>
9941 <description>No clock</description>
9946 <description>No clock</description>
9951 <description>No clock</description>
9956 <description>No clock</description>
9961 <description>No clock</description>
9966 <description>No clock</description>
9971 <description>No clock</description>
9980 <description>DMIC clock selection</description>
9989 <description>DMIC clock select</description>
9996 <description>Main clock</description>
10001 <description>PLL0 clock</description>
10006 <description>Clock in</description>
10011 <description>FRO_HF</description>
10016 <description>PLL1 clock</description>
10021 <description>MCLK in</description>
10026 <description>No clock</description>
10031 <description>No clock</description>
10040 <description>DMIC clock division</description>
10049 <description>Clock divider value.</description>
10056 <description>Resets the divider counter.</description>
10063 <description>Divider is not reset.</description>
10068 <description>Divider is reset.</description>
10075 <description>Halts the divider counter.</description>
10082 <description>Divider clock is running.</description>
10087 <description>Divider clock is stopped.</description>
10094 <description>Divider status flag.</description>
10101 <description>Divider clock is stable.</description>
10106 <description>Clock frequency is not stable.</description>
10115 <description>PLL1 550m control</description>
10124 <description>Bandwidth select R value.</description>
10131 <description>Bandwidth select I value.</description>
10138 <description>Bandwidth select P value.</description>
10145 … <description>Bypass PLL input clock is sent directly to the PLL output (default).</description>
10152 <description>use PLL.</description>
10157 <description>PLL input clock is sent directly to the PLL output.</description>
10164 <description>bypass of the divide-by-2 divider in the post-divider.</description>
10171 <description>use the divide-by-2 divider in the post-divider.</description>
10176 <description>bypass of the divide-by-2 divider in the post-divider.</description>
10183 … <description>limup_off = 1 in spread spectrum and fractional PLL applications.</description>
10190 <description>control of the bandwidth of the PLL.</description>
10197 … <description>the bandwidth is changed synchronously with the feedback-divider.</description>
10202 <description>modify the bandwidth of the PLL directly.</description>
10209 <description>bypass of the pre-divider.</description>
10216 <description>use the pre-divider.</description>
10221 <description>bypass of the pre-divider.</description>
10228 <description>bypass of the post-divider.</description>
10235 <description>use the post-divider.</description>
10240 <description>bypass of the post-divider.</description>
10247 <description>enable the output clock.</description>
10254 <description>Disable the output clock.</description>
10259 <description>Enable the output clock.</description>
10266 <description>1: free running mode.</description>
10273 …<description>free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL o…
10280 <description>Skew mode.</description>
10287 <description>skewmode is disable.</description>
10292 <description>skewmode is enable.</description>
10301 <description>PLL1 550m status</description>
10310 …<description>lock detector output (active high) Warning: The lock signal is only reliable between …
10317 <description>pre-divider ratio change acknowledge.</description>
10324 <description>feedback divider ratio change acknowledge.</description>
10331 <description>post-divider ratio change acknowledge.</description>
10338 <description>free running detector output (active high).</description>
10347 <description>PLL1 550m N divider</description>
10356 <description>pre-divider divider ratio (N-divider).</description>
10363 <description>pre-divider ratio change request.</description>
10372 <description>PLL1 550m M divider</description>
10381 <description>feedback divider divider ratio (M-divider).</description>
10388 <description>feedback ratio change request.</description>
10397 <description>PLL1 550m P divider</description>
10406 <description>post-divider divider ratio (P-divider)</description>
10413 <description>feedback ratio change request.</description>
10422 <description>PLL1 550m functional test control</description>
10431 <description>input to functional test the pre-divider (N-divider).</description>
10438 <description>input to functional test the feedback-divider (M-divider).</description>
10445 <description>input to functional test the post-divider (P-divider).</description>
10454 <description>PLL1 550m functional test status</description>
10463 <description>output to observe the functional pre-divider test.</description>
10470 <description>output to observe the functional feedback-divider test.</description>
10477 <description>output to observe the functional post-divider test.</description>
10486 <description>PLL0 550m control</description>
10495 <description>Bandwidth select R value.</description>
10502 <description>Bandwidth select I value.</description>
10509 <description>Bandwidth select P value.</description>
10516 … <description>Bypass PLL input clock is sent directly to the PLL output (default).</description>
10523 <description>use PLL.</description>
10528 … <description>Bypass PLL input clock is sent directly to the PLL output.</description>
10535 <description>bypass of the divide-by-2 divider in the post-divider.</description>
10542 <description>use the divide-by-2 divider in the post-divider.</description>
10547 <description>bypass of the divide-by-2 divider in the post-divider.</description>
10554 … <description>limup_off = 1 in spread spectrum and fractional PLL applications.</description>
10561 <description>Control of the bandwidth of the PLL.</description>
10568 … <description>the bandwidth is changed synchronously with the feedback-divider.</description>
10573 <description>modify the bandwidth of the PLL directly.</description>
10580 <description>bypass of the pre-divider.</description>
10587 <description>use the pre-divider.</description>
10592 <description>bypass of the pre-divider.</description>
10599 <description>bypass of the post-divider.</description>
10606 <description>use the post-divider.</description>
10611 <description>bypass of the post-divider.</description>
10618 <description>enable the output clock.</description>
10625 <description>disable the output clock.</description>
10630 <description>enable the output clock.</description>
10637 <description>free running mode.</description>
10644 <description>free running mode is disable.</description>
10649 <description>free running mode is enable.</description>
10656 …<description>free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL ou…
10663 <description>skew mode.</description>
10670 <description>skew mode is disable.</description>
10675 <description>skew mode is enable.</description>
10684 <description>PLL0 550m status</description>
10693 …<description>lock detector output (active high) Warning: The lock signal is only reliable between …
10700 <description>pre-divider ratio change acknowledge.</description>
10707 <description>feedback divider ratio change acknowledge.</description>
10714 <description>post-divider ratio change acknowledge.</description>
10721 <description>free running detector output (active high).</description>
10730 <description>PLL0 550m N divider</description>
10739 <description>pre-divider divider ratio (N-divider).</description>
10746 <description>pre-divider ratio change request.</description>
10755 <description>PLL0 550m P divider</description>
10764 <description>post-divider divider ratio (P-divider)</description>
10771 <description>feedback ratio change request.</description>
10780 <description>PLL0 Spread Spectrum control 0</description>
10789 <description>input word of the wrapper bit 31 to 0.</description>
10798 <description>PLL0 Spread Spectrum control 1</description>
10807 <description>input word of the wrapper bit 32.</description>
10814 <description>md change request.</description>
10821 …<description>programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3.<…
10828 …description>programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]d…
10835 …description>modulation waveform control Compensation for low pass filtering of the PLL to get a tr…
10842 <description>to select an external mdiv value.</description>
10849 <description>to select an external mreq value.</description>
10856 …description>dithering between two modulation frequencies in a random way or in a pseudo random way…
10863 …<description>to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : …
10872 <description>PLL0 550m functional test control</description>
10881 <description>input to functional test the pre-divider (N-divider).</description>
10888 <description>input to functional test the feedback-divider (M-divider).</description>
10895 <description>input to functional test the post-divider (P-divider).</description>
10904 <description>PLL0 550m functional test status</description>
10913 <description>output to observe the functional pre-divider test.</description>
10920 <description>output to observe the functional feedback-divider test.</description>
10927 <description>output to observe the functional post-divider test.</description>
10936 <description>eFUSE controller clock enable</description>
10945 <description>eFUSE controller clock enable.</description>
10954 <description>DAC Isolation Control</description>
10963 <description>DAC0 Isolation</description>
10970 <description>DAC0 isolation disabled</description>
10975 <description>DAC0 isolation enabled</description>
10982 <description>DAC1 Isolation</description>
10989 <description>DAC1 isolation disabled</description>
10994 <description>DAC1 isolation enabled</description>
11001 <description>DAC2 Isolation</description>
11008 <description>DAC2 isolation disabled</description>
11013 <description>DAC2 isolation enabled</description>
11024 <description>Fractional rate divider for flexcomm n</description>
11033 <description>Denominator of the fractional rate divider.</description>
11040 <description>Numerator of the fractional rate divider.</description>
11049 <description>Start logic wake-up enable</description>
11058 <description>SYS interrupt wake-up.</description>
11065 <description>Wake-up disabled.</description>
11070 <description>Wake-up enabled.</description>
11077 <description>SDMA0 interrupt wake-up.</description>
11084 <description>Wake-up disabled.</description>
11089 <description>Wake-up enabled.</description>
11096 <description>GINT0 interrupt wake-up.</description>
11103 <description>Wake-up disabled.</description>
11108 <description>Wake-up enabled.</description>
11115 <description>GINT1 interrupt wake-up.</description>
11122 <description>Wake-up disabled.</description>
11127 <description>Wake-up enabled.</description>
11134 <description>PIO_INT0 interrupt wake-up.</description>
11141 <description>Wake-up disabled.</description>
11146 <description>Wake-up enabled.</description>
11153 <description>PIO_INT1 interrupt wake-up.</description>
11160 <description>Wake-up disabled.</description>
11165 <description>Wake-up enabled.</description>
11172 <description>PIO_INT2 interrupt wake-up.</description>
11179 <description>Wake-up disabled.</description>
11184 <description>Wake-up enabled.</description>
11191 <description>PIO_INT3 interrupt wake-up.</description>
11198 <description>Wake-up disabled.</description>
11203 <description>Wake-up enabled.</description>
11210 <description>UTICK0 interrupt wake-up.</description>
11217 <description>Wake-up disabled.</description>
11222 <description>Wake-up enabled.</description>
11229 <description>MRT0 interrupt wake-up.</description>
11236 <description>Wake-up disabled.</description>
11241 <description>Wake-up enabled.</description>
11248 <description>CTIMER0 interrupt wake-up.</description>
11255 <description>Wake-up disabled.</description>
11260 <description>Wake-up enabled.</description>
11267 <description>CTIMER1 interrupt wake-up.</description>
11274 <description>Wake-up disabled.</description>
11279 <description>Wake-up enabled.</description>
11286 <description>SCT0 interrupt wake-up.</description>
11293 <description>Wake-up disabled.</description>
11298 <description>Wake-up enabled.</description>
11305 <description>CTIMER3 interrupt wake-up.</description>
11312 <description>Wake-up disabled.</description>
11317 <description>Wake-up enabled.</description>
11324 <description>FLEXINT0 interrupt wake-up.</description>
11331 <description>Wake-up disabled.</description>
11336 <description>Wake-up enabled.</description>
11343 <description>FLEXINT1 interrupt wake-up.</description>
11350 <description>Wake-up disabled.</description>
11355 <description>Wake-up enabled.</description>
11362 <description>FLEXINT2 interrupt wake-up.</description>
11369 <description>Wake-up disabled.</description>
11374 <description>Wake-up enabled.</description>
11381 <description>FLEXINT3 interrupt wake-up.</description>
11388 <description>Wake-up disabled.</description>
11393 <description>Wake-up enabled.</description>
11400 <description>FLEXINT4 interrupt wake-up.</description>
11407 <description>Wake-up disabled.</description>
11412 <description>Wake-up enabled.</description>
11419 <description>FLEXINT5 interrupt wake-up.</description>
11426 <description>Wake-up disabled.</description>
11431 <description>Wake-up enabled.</description>
11438 <description>FLEXINT6 interrupt wake-up.</description>
11445 <description>Wake-up disabled.</description>
11450 <description>Wake-up enabled.</description>
11457 <description>FLEXINT7 interrupt wake-up.</description>
11464 <description>Wake-up disabled.</description>
11469 <description>Wake-up enabled.</description>
11476 <description>ADC0 interrupt wake-up.</description>
11483 <description>Wake-up disabled.</description>
11488 <description>Wake-up enabled.</description>
11495 <description>ADC1 interrupt wake-up.</description>
11502 <description>Wake-up disabled.</description>
11507 <description>Wake-up enabled.</description>
11514 <description>ACMP_OVR interrupt wake-up.</description>
11521 <description>Wake-up disabled.</description>
11526 <description>Wake-up enabled.</description>
11533 <description>DMIC interrupt wake-up.</description>
11540 <description>Wake-up disabled.</description>
11545 <description>Wake-up enabled.</description>
11552 <description>USB0_NEEDCLK interrupt wake-up.</description>
11559 <description>Wake-up disabled.</description>
11564 <description>Wake-up enabled.</description>
11571 <description>USB0-FS interrupt wake-up.</description>
11578 <description>Wake-up disabled.</description>
11583 <description>Wake-up enabled.</description>
11590 <description>RTC_LITE0 interrupt wake-up.</description>
11597 <description>Wake-up disabled.</description>
11602 <description>Wake-up enabled.</description>
11609 <description>EZH_ARCH_B0 interrupt wake-up.</description>
11616 <description>Wake-up disabled.</description>
11621 <description>Wake-up enabled.</description>
11628 <description>WAKEUP_MAILBOX0 interrupt wake-up.</description>
11635 <description>Wake-up disabled.</description>
11640 <description>Wake-up enabled.</description>
11649 <description>Start logic wake-up enable</description>
11658 <description>GPIO_INT04 interrupt wake-up.</description>
11665 <description>Wake-up disabled.</description>
11670 <description>Wake-up enabled.</description>
11677 <description>GPIO_INT05 interrupt wake-up.</description>
11684 <description>Wake-up disabled.</description>
11689 <description>Wake-up enabled.</description>
11696 <description>GPIO_INT06 interrupt wake-up.</description>
11703 <description>Wake-up disabled.</description>
11708 <description>Wake-up enabled.</description>
11715 <description>GPIO_INT07 interrupt wake-up.</description>
11722 <description>Wake-up disabled.</description>
11727 <description>Wake-up enabled.</description>
11734 <description>CTIMER2 interrupt wake-up.</description>
11741 <description>Wake-up disabled.</description>
11746 <description>Wake-up enabled.</description>
11753 <description>CTIMER4 interrupt wake-up.</description>
11760 <description>Wake-up disabled.</description>
11765 <description>Wake-up enabled.</description>
11772 <description>OS_EVENT interrupt wake-up.</description>
11779 <description>Wake-up disabled.</description>
11784 <description>Wake-up enabled.</description>
11791 <description>FLEXSPI interrupt wake-up.</description>
11798 <description>Wake-up disabled.</description>
11803 <description>Wake-up enabled.</description>
11810 <description>SDIO interrupt wake-up.</description>
11817 <description>Wake-up disabled.</description>
11822 <description>Wake-up enabled.</description>
11829 <description>SEC_HYPERVISOR_CALL interrupt wake-up.</description>
11836 <description>Wake-up disabled.</description>
11841 <description>Wake-up enabled.</description>
11848 <description>SEC_GPIO_INT00 interrupt wake-up.</description>
11855 <description>Wake-up disabled.</description>
11860 <description>Wake-up enabled.</description>
11867 <description>SEC_GPIO_INT01 interrupt wake-up.</description>
11874 <description>Wake-up disabled.</description>
11879 <description>Wake-up enabled.</description>
11886 <description>FREQME interrupt wake-up.</description>
11893 <description>Wake-up disabled.</description>
11898 <description>Wake-up enabled.</description>
11905 <description>SEC_VIO interrupt wake-up.</description>
11912 <description>Wake-up disabled.</description>
11917 <description>Wake-up enabled.</description>
11924 <description>SHA interrupt wake-up.</description>
11931 <description>Wake-up disabled.</description>
11936 <description>Wake-up enabled.</description>
11943 <description>PKC interrupt wake-up.</description>
11950 <description>Wake-up disabled.</description>
11955 <description>Wake-up enabled.</description>
11962 <description>QDDKEY interrupt wake-up.</description>
11969 <description>Wake-up disabled.</description>
11974 <description>Wake-up enabled.</description>
11981 <description>PQ interrupt wake-up.</description>
11988 <description>Wake-up disabled.</description>
11993 <description>Wake-up enabled.</description>
12000 <description>SDMA1 interrupt wake-up.</description>
12007 <description>Wake-up disabled.</description>
12012 <description>Wake-up enabled.</description>
12019 <description>LSPI_HS interrupt wake-up.</description>
12026 <description>Wake-up disabled.</description>
12031 <description>Wake-up enabled.</description>
12038 <description>CODE WDG0 interrupt wake-up.</description>
12045 <description>Wake-up disabled.</description>
12050 <description>Wake-up enabled.</description>
12057 <description>I3C0 interrupt wake-up.</description>
12064 <description>Wake-up disabled.</description>
12069 <description>Wake-up enabled.</description>
12078 <description>Start logic wake-up enable</description>
12087 <description>CSS_IRQ1 (Digital Glitch Detect)</description>
12094 <description>Wake-up disabled.</description>
12099 <description>Wake-up enabled.</description>
12106 <description>Tamper interrupt wake-up.</description>
12113 <description>Wake-up disabled.</description>
12118 <description>Wake-up enabled.</description>
12125 <description>Analog glitch detect.</description>
12132 <description>Wake-up disabled.</description>
12137 <description>Wake-up enabled.</description>
12144 <description>DAC0 interrupt wake-up.</description>
12151 <description>Wake-up disabled.</description>
12156 <description>Wake-up enabled.</description>
12163 <description>DAC1 interrupt wake-up.</description>
12170 <description>Wake-up disabled.</description>
12175 <description>Wake-up enabled.</description>
12182 <description>DAC2 interrupt wake-up.</description>
12189 <description>Wake-up disabled.</description>
12194 <description>Wake-up enabled.</description>
12201 <description>HS_CMP0 interrupt wake-up.</description>
12208 <description>Wake-up disabled.</description>
12213 <description>Wake-up enabled.</description>
12220 <description>HS_CMP1 interrupt wake-up.</description>
12227 <description>Wake-up disabled.</description>
12232 <description>Wake-up enabled.</description>
12239 <description>HS_CMP2 interrupt wake-up.</description>
12246 <description>Wake-up disabled.</description>
12251 <description>Wake-up enabled.</description>
12258 <description>FlexPWM0 capture interrupt wake-up.</description>
12265 <description>Wake-up disabled.</description>
12270 <description>Wake-up enabled.</description>
12277 <description>FlexPWM0 fault interrupt wake-up.</description>
12284 <description>Wake-up disabled.</description>
12289 <description>Wake-up enabled.</description>
12296 <description>FlexPWM0 reload error interrupt wake-up.</description>
12303 <description>Wake-up disabled.</description>
12308 <description>Wake-up enabled.</description>
12315 <description>FlexPWM0 compare interrupt wake-up.</description>
12322 <description>Wake-up disabled.</description>
12327 <description>Wake-up enabled.</description>
12334 <description>FlexPWM0 reload interrupt wake-up.</description>
12341 <description>Wake-up disabled.</description>
12346 <description>Wake-up enabled.</description>
12353 <description>FlexPWM0 compare interrupt wake-up.</description>
12360 <description>Wake-up disabled.</description>
12365 <description>Wake-up enabled.</description>
12372 <description>FlexPWM0 reload interrupt wake-up.</description>
12379 <description>Wake-up disabled.</description>
12384 <description>Wake-up enabled.</description>
12391 <description>FlexPWM0 compare interrupt wake-up.</description>
12398 <description>Wake-up disabled.</description>
12403 <description>Wake-up enabled.</description>
12410 <description>FlexPWM0 reload interrupt wake-up.</description>
12417 <description>Wake-up disabled.</description>
12422 <description>Wake-up enabled.</description>
12429 <description>FlexPWM0 compare interrupt wake-up.</description>
12436 <description>Wake-up disabled.</description>
12441 <description>Wake-up enabled.</description>
12448 <description>FlexPWM0 reload interrupt wake-up.</description>
12455 <description>Wake-up disabled.</description>
12460 <description>Wake-up enabled.</description>
12467 <description>FlexPWM1 capture interrupt wake-up.</description>
12474 <description>Wake-up disabled.</description>
12479 <description>Wake-up enabled.</description>
12486 <description>FlexPWM1 fault interrupt wake-up.</description>
12493 <description>Wake-up disabled.</description>
12498 <description>Wake-up enabled.</description>
12505 <description>FlexPWM1 reload error interrupt wake-up.</description>
12512 <description>Wake-up disabled.</description>
12517 <description>Wake-up enabled.</description>
12524 <description>FlexPWM1 compare interrupt wake-up.</description>
12531 <description>Wake-up disabled.</description>
12536 <description>Wake-up enabled.</description>
12543 <description>FlexPWM1 reload interrupt wake-up.</description>
12550 <description>Wake-up disabled.</description>
12555 <description>Wake-up enabled.</description>
12564 <description>Start logic wake-up enable</description>
12573 <description>FlexPWM1 compare interrupt wake-up.</description>
12580 <description>Wake-up disabled.</description>
12585 <description>Wake-up enabled.</description>
12592 <description>FlexPWM1 reload interrupt wake-up.</description>
12599 <description>Wake-up disabled.</description>
12604 <description>Wake-up enabled.</description>
12611 <description>FlexPWM1 compare interrupt wake-up.</description>
12618 <description>Wake-up disabled.</description>
12623 <description>Wake-up enabled.</description>
12630 <description>FlexPWM1 reload interrupt wake-up.</description>
12637 <description>Wake-up disabled.</description>
12642 <description>Wake-up enabled.</description>
12649 <description>FlexPWM1 compare interrupt wake-up.</description>
12656 <description>Wake-up disabled.</description>
12661 <description>Wake-up enabled.</description>
12668 <description>FlexPWM1 reload interrupt wake-up.</description>
12675 <description>Wake-up disabled.</description>
12680 <description>Wake-up enabled.</description>
12687 <description>ENC0 compare interrupt wake-up.</description>
12694 <description>Wake-up disabled.</description>
12699 <description>Wake-up enabled.</description>
12706 <description>ENC0 home interrupt wake-up.</description>
12713 <description>Wake-up disabled.</description>
12718 <description>Wake-up enabled.</description>
12725 <description>ENC0 WDOG interrupt wake-up.</description>
12732 <description>Wake-up disabled.</description>
12737 <description>Wake-up enabled.</description>
12744 <description>ENC0 IDX interrupt wake-up.</description>
12751 <description>Wake-up disabled.</description>
12756 <description>Wake-up enabled.</description>
12763 <description>ENC1 compare interrupt wake-up.</description>
12770 <description>Wake-up disabled.</description>
12775 <description>Wake-up enabled.</description>
12782 <description>ENC1 home interrupt wake-up.</description>
12789 <description>Wake-up disabled.</description>
12794 <description>Wake-up enabled.</description>
12801 <description>ENC1 WDOG interrupt wake-up.</description>
12808 <description>Wake-up disabled.</description>
12813 <description>Wake-up enabled.</description>
12820 <description>ENC1 IDX interrupt wake-up.</description>
12827 <description>Wake-up disabled.</description>
12832 <description>Wake-up enabled.</description>
12839 <description>ITRC interrupt wake-up.</description>
12846 <description>Wake-up disabled.</description>
12851 <description>Wake-up enabled.</description>
12858 <description>CSSv2 error interrupt wake-up.</description>
12865 <description>Wake-up disabled.</description>
12870 <description>Wake-up enabled.</description>
12877 <description>PKC error interrupt wake-up.</description>
12884 <description>Wake-up disabled.</description>
12889 <description>Wake-up enabled.</description>
12896 <description>PVTVF0 amber interrupt wake-up.</description>
12903 <description>Wake-up disabled.</description>
12908 <description>Wake-up enabled.</description>
12915 <description>PVTVF0 red interrupt wake-up.</description>
12922 <description>Wake-up disabled.</description>
12927 <description>Wake-up enabled.</description>
12934 <description>PVTVF1 amber interrupt wake-up.</description>
12941 <description>Wake-up disabled.</description>
12946 <description>Wake-up enabled.</description>
12953 <description>PVTVF1 red interrupt wake-up.</description>
12960 <description>Wake-up disabled.</description>
12965 <description>Wake-up enabled.</description>
12974 <description>Set bits in STARTER</description>
12983 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
12990 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
12997 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13004 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13011 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13018 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13025 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13032 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13039 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13046 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13053 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13060 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13067 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13074 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13081 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13088 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13095 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13102 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13109 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13116 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13123 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13130 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13137 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13144 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13151 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13158 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13165 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13172 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13179 …<description>Writing ones to this register sets the corresponding bit in the STARTER0 register.</d…
13188 <description>Set bits in STARTER</description>
13197 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13204 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13211 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13218 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13225 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13232 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13239 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13246 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13253 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13260 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13267 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13274 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13281 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13288 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13295 …<description>Writing ones to this register sets the corresponding bit in the STARTER1 register.</d…
13304 <description>Set bits in STARTER</description>
13313 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13320 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13327 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13334 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13341 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13348 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13355 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13362 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13369 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13376 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13383 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13390 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13397 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13404 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13411 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13418 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13425 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13432 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13439 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13446 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13453 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13460 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13467 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13474 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13481 …<description>Writing ones to this register sets the corresponding bit in the STARTER2 register.</d…
13490 <description>Set bits in STARTER</description>
13499 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13506 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13513 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13520 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13527 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13534 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13541 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13548 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13555 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13562 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13569 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13576 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13583 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13590 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13597 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13604 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13611 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13618 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13625 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13632 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13639 …<description>Writing ones to this register sets the corresponding bit in the STARTER3 register.</d…
13648 <description>Clear bits in STARTER</description>
13657 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13664 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13671 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13678 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13685 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13692 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13699 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13706 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13713 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13720 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13727 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13734 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13741 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13748 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13755 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13762 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13769 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13776 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13783 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13790 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13797 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13804 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13811 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13818 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13825 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13832 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13839 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13846 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13853 …<description>Writing ones to this register clears the corresponding bit in the STARTER0 register.<…
13862 <description>Clear bits in STARTER</description>
13871 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13878 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13885 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13892 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13899 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13906 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13913 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13920 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13927 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13934 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13941 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13948 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13955 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13962 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13969 …<description>Writing ones to this register clears the corresponding bit in the STARTER1 register.<…
13978 <description>Functional retention control</description>
13987 <description>functional retention in power down only.</description>
13994 <description>disable functional retention.</description>
13999 <description>enable functional retention.</description>
14006 <description>Start address divided by 4 inside SRAMX bank.</description>
14013 <description>lenth of Scan chains to save.</description>
14022 <description>Override some powerdown control signals (for debug purposes)</description>
14031 …<description>Overrides the fro_is_dead' signal in Sleepcon module, in case this doesn't work on si…
14040 <description>Main clock is enable after MAINCLKSAFETY cycle</description>
14049 <description>main clock is enable after MAINCLKSAFETY cycle.</description>
14058 <description>Hardware Sleep control</description>
14067 …<description>Force peripheral clocking to stay on during Deep Sleep and Power-down modes.</descrip…
14074 <description>Wake for Flexcomms.</description>
14081 <description>Wake for DMIC.</description>
14088 <description>Wake for DMA0.</description>
14095 <description>Wake for DMA1.</description>
14102 <description>Wake for DAC0/1/2.</description>
14109 <description>Set this bit if FRO192M is diabled.</description>
14118 <description>Coprocessor Stack Address</description>
14127 <description>Coprocessor Stack Address. -- NOT USED</description>
14136 <description>CPU Status</description>
14145 <description>The CPU0 sleeping state.</description>
14152 <description>the CPU is not sleeping.</description>
14157 <description>the CPU is sleeping.</description>
14164 <description>The CPU0 lockup state.</description>
14171 <description>the CPU is not in lockup.</description>
14176 <description>the CPU is in lockup.</description>
14185 <description>LPCAC control</description>
14194 <description>Disable/enable cache function. Default value is 1.</description>
14201 <description>Enable</description>
14206 <description>Disable</description>
14213 <description>Clear cache function. Default value is 0.</description>
14220 <description>Unclear cache</description>
14225 <description>Clear cache</description>
14232 <description>Force no allocation. Default value is 0.</description>
14239 <description>Force allocation</description>
14244 <description>Force no allocation</description>
14251 <description>Enable parity miss. Default value is 0.</description>
14258 <description>Disable</description>
14263 <description>Enable parity, miss on parity error</description>
14272 <description>Flexcomm 32K clock select</description>
14281 <description>Flexcomm 32K clock select</description>
14288 <description>FRO32K</description>
14293 <description>XTAL 32K</description>
14304 <description>FRG Clock Source Select</description>
14313 <description>FRG clock source select</description>
14320 <description>main clock</description>
14325 <description>PLL clock</description>
14330 <description>fro_div_hf</description>
14335 <description>None</description>
14340 <description>None</description>
14345 <description>None</description>
14350 <description>None</description>
14355 <description>None</description>
14366 <description>Flexcomm clock divider</description>
14375 <description>Clock divider value:</description>
14382 <description>Reset</description>
14389 <description>Divider is not reset</description>
14394 <description>Divider is reset</description>
14401 <description>Reset</description>
14408 <description>Divider clock is running</description>
14413 <description>Divider clock has stopped</description>
14420 <description>Reset</description>
14427 <description>Divider clock is stable</description>
14432 <description>Clock frequency is not stable</description>
14441 <description>Life cycle state register written by Boot-ROM</description>
14450 <description>OTP life cycle state</description>
14459 … <description>Life cycle state register written by Boot-ROM - duplicated version</description>
14468 <description>OTP life cycle state</description>
14477 <description>CSS temporal state</description>
14486 <description>Temporal state</description>
14495 <description>Key derivation function mask</description>
14504 <description>Key derivation function mask.</description>
14513 <description>CSS command feature</description>
14522 <description>CSS command feature bit.</description>
14531 <description>CSS command feature</description>
14540 <description>CSS command feature bit.</description>
14549 <description>CSS command feature - duplicate version</description>
14558 <description>CSS command feature bit.</description>
14567 <description>CSS command feature - duplicate version</description>
14576 <description>CSS command feature bit.</description>
14585 <description>CSS debug enable</description>
14594 <description>Debug enable bit.</description>
14603 <description>CSS boot retry counter</description>
14612 <description>Boot retry counter bit.</description>
14621 <description>CSS boot state</description>
14630 <description>Boot state record bit.</description>
14639 <description>CSS boot state lock down</description>
14648 <description>Boot state lock down bit.</description>
14657 <description>CSS clock control</description>
14666 <description>GDET reference clock enable bit.</description>
14673 <description>DTRNG reference clock enable bit.</description>
14682 <description>CSS clock control set</description>
14691 <description>GDET reference clock enable set bit.</description>
14698 <description>DTRNG reference clock enable set bit.</description>
14707 <description>CSS clock control clear</description>
14716 <description>GDET reference clock enable clear bit.</description>
14723 <description>DTRNG reference clock enable clear bit.</description>
14732 <description>CSS clock select</description>
14741 <description>GDET reference clock select bit.</description>
14748 <description>FRO 12 MHz</description>
14753 <description>FRO 48 MHz/2 (24 MHz)</description>
14758 <description>FRO 48 MHz</description>
14763 <description>FRO 96 MHz</description>
14772 <description>CSS AS configuration</description>
14781 <description>LC state configuration bit.</description>
14788 <description>FRO 12 MHz</description>
14793 <description>FRO 48 MHz/2 (24 MHz)</description>
14798 <description>FRO 48 MHz</description>
14803 <description>FRO 96 MHz</description>
14810 …<description>When BOD VBAT analog detector is turned on and BOD VBAT reset is enabled, this bit in…
14817 …<description>When BOD CORE analog detector is turned on and BOD CORE reset is enabled, this bit in…
14824 …<description>When BOD VBAT analog detector is turned on and BOD VBAT IRQ is enabled, this bit indi…
14831 … <description>When WatchDog Timer is activated, this bit indicates state 1.</description>
14838 … <description>When Code WatchDog Timer is activated, this bit indicates state 1.</description>
14845 …<description>When CSS GDET is enabled (CSS "o_gdet_enabled" output = 1), this bit indica…
14852 <description>When ANALOG GDET is enabled, this bit indicates state 1.</description>
14859 … <description>When tamper detector is enabled in RTC, this bit indicates state 1.</description>
14866 …<description>When FLASHREMAP_OFFSET register (0x4000_0448) is not equal to 0x0000_0000, this bit i…
14873 …<description>When FLASHREMAP_OFFSET_DP register (0x4000_044C) is not equal to 0x0000_0000, this bi…
14880 …<description>The state of FLASHBANK_ENABLE0 register (0x4000_0450) reflects to this register as be…
14887 …<description>The state of FLASHBANK_ENABLE1 register (0x4000_0454) reflects to this register as be…
14894 …<description>When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state…
14901 …<description>When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1…
14910 <description>CSS AS configuration1</description>
14919 …description>When "CFG_SEC_ENA_SEC_CHK" indicates state 0 or when "DISABLE_STRICT_MO…
14926 …description>When "DISABLE_VIOLATION_ABORT" bits in "MISC_CTRL_REG" and "M…
14933 …description>When "ENABLE_NS_PRIV_CHECK" bits in "MISC_CTRL_REG" and "MISC…
14940 …description>When "ENABLE_S_PRIV_CHECK" bits in "MISC_CTRL_REG" and "MISC_…
14947 …description>When "ENABLE_SECURE_CHECKING" bits in "MISC_CTRL_REG" and "MI…
14954 …description>When "IDAU_ALL_NS" bits in "MISC_CTRL_REG" and "MISC_CTRL_DP_…
14961 …description>When "LOCK_NS_MPU" bits in "CPU0_LOCK_REG" on AHB secure controlle…
14968 …description>When "LOCK_NS_VTOR" bits in "CPU0_LOCK_REG" on AHB secure controll…
14975 …description>When "LOCK_S_MPU" bits in "CPU0_LOCK_REG" on AHB secure controller…
14982 …description>When "LOCK_S_VTAIRCR" bits in "CPU0_LOCK_REG" on AHB secure contro…
14989 …description>When "LOCK_SAU" bits in "CPU0_LOCK_REG" on AHB secure controller a…
14998 <description>CSS AS configuration2</description>
15007 <description>CSS configuration command enable bit.</description>
15016 <description>CSS AS state register</description>
15025 …<description>"TEMPORAL_STATE[3:0]" on "CSS_TEMPORAL_STATE" register reflects t…
15032 …<description>When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1.</des…
15039 …<description>When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1.</des…
15046 …<description>When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1.</de…
15053 …<description>When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1.</d…
15060 …<description>When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1.<…
15067 …<description>When CSS uCode code fetch out of AHB for debug is enabled, this bit indicates state 1…
15074 … <description>When JTAG TAP access is allowed, this bit indicates state 1.</description>
15081 …<description>When XO32K oscillation fail flag is state 1 in PMC register block, this bit indicates…
15090 <description>CSS AS state1</description>
15099 …<description>These register bits indicate the state of "qk_puf_score[3:0]" outputs from …
15106 …<description>This register bit indicates the state of "qk_zeroized" output from QK PUF b…
15113 …<description>When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN…
15120 …<description>VOUT[3:0] setting on DCDC0 register in PMC block will reflect to this register.</desc…
15127 …<description>BOOTMODE[1:0] status on STATUS register in PMC block will reflect to this register.</…
15134 …<description>"BOOT_RETRY_CNT[3:0]" on "CSS_BOOT_RETRY_CNT" register reflects t…
15143 <description>CSS AS state2</description>
15152 …<description>"BOOT_STATE[31:0]" on "CSS_BOOT_STATE" register reflects this reg…
15161 <description>CSS AS flag0</description>
15170 …<description>This flag bit is set 1 when DAP enables AP0 for CPU0 (CM33) debug access. The registe…
15177 …description>This flag bit is set 1 when BOD VBAT reset is enabled and BOD VBAT analog detector is …
15184 …description>This flag bit is set 1 when BOD CORE reset is enabled and BOD CORE analog detector is …
15191 …description>This flag bit is set 1 when BOD VBAT IRQ is enabled and BOD VBAT analog detector is tr…
15198 …description>This flag bit is set 1 when BOD CORE IRQ is enabled and BOD CORE analog detector is tr…
15205 …description>This flag bit is set 1 when WatchDog Timer reset is enabled and reset event is trigger…
15212 …description>This flag bit is set 1 when Code WatchDog Timer reset is enabled and reset event is tr…
15219 …description>This flag register is set 1 when WatchDog Timer IRQ is enabled and IRQ event is trigge…
15226 …description>This flag bit is set 1 when Code WatchDog Timer IRQ is enabled and IRQ event is trigge…
15233 …<description>This flag bit is set 1 when QK_ERROR is flagged from QK PUF block. This register is c…
15240 …<description>This flag bit is set 1 when GDET error is flagged from CSS. This register is cleared …
15247 …<description>This flag bit is set 1 when ANALOG GDET error is flagged in SYSCON block. This regist…
15254 …description>This flag bit is set 1 when tamper event is flagged from RTC. This register is cleared…
15261 …<description>This flag bit is set 1 when FLASH controller indicates ECC error. This register is cl…
15268 …<description>This flag bit is set 1 when security violation is indicated from FLASH sub-system or …
15275 …<description>This flag bit is set 1 when CPU0 (CM33) makes non-secure code transactions. This regi…
15282 …description>This flag register is set 1 when CPU0 (CM33) makes non-secure data transactions. This …
15291 <description>Clock Control</description>
15300 <description>Enable Flash 48 MHz clock.</description>
15307 <description>The clock is not enabled.</description>
15312 <description>The clock is enabled.</description>
15319 <description>Enable XTAL32MHz clock for Frequency Measure module.</description>
15326 <description>The clock is not enabled.</description>
15331 <description>The clock is enabled.</description>
15338 … <description>Enable FRO 1MHz clock for Frequency Measure module and for UTICK.</description>
15345 <description>The clock is not enabled.</description>
15350 <description>The clock is enabled.</description>
15357 <description>Enable FRO 12MHz clock for Frequency Measure module.</description>
15364 <description>The clock is not enabled.</description>
15369 <description>The clock is enabled.</description>
15376 <description>Enable FRO 96MHz clock for Frequency Measure module.</description>
15383 <description>The clock is not enabled.</description>
15388 <description>The clock is enabled.</description>
15395 <description>Enable clock_in clock for clock module.</description>
15402 <description>The clock is not enabled.</description>
15407 <description>The clock is enabled.</description>
15414 <description>Enable FRO 1MHz clock for clock muxing in clock gen.</description>
15421 <description>The clock is not enabled.</description>
15426 <description>The clock is enabled.</description>
15433 … <description>Enable FRO 12MHz clock for analog control of the FRO 192MHz.</description>
15440 <description>The clock is not enabled.</description>
15445 <description>The clock is enabled.</description>
15452 <description>Enable clock for crystal oscillator calibration</description>
15459 <description>The clock is not enabled.</description>
15464 <description>The clock is enabled.</description>
15473 <description>Comparator Interrupt control</description>
15482 <description>Analog Comparator interrupt enable control:.</description>
15489 <description>interrupt disable.</description>
15494 <description>interrupt enable.</description>
15501 <description>Analog Comparator interrupt clear.</description>
15508 <description>No effect.</description>
15513 <description>Clear the interrupt. Self-cleared bit.</description>
15520 <description>Comparator interrupt type selector:.</description>
15527 … <description>The analog comparator interrupt edge sensitive is disabled.</description>
15532 … <description>The analog comparator interrupt level sensitive is disabled.</description>
15537 <description>analog comparator interrupt is rising edge sensitive.</description>
15542 <description>Analog Comparator interrupt is high level sensitive.</description>
15547 <description>analog comparator interrupt is falling edge sensitive.</description>
15552 <description>Analog Comparator interrupt is low level sensitive.</description>
15557 … <description>analog comparator interrupt is rising and falling edge sensitive.</description>
15562 … <description>The analog comparator interrupt level sensitive is disabled.</description>
15569 …<description>Select which Analog comparator output (filtered our un-filtered) is used for interrup…
15576 …<description>Select Analog Comparator filtered output as input for interrupt detection.</descripti…
15581 …description>Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Mus…
15590 <description>Comparator Interrupt status</description>
15599 <description>Interrupt status BEFORE Interrupt Enable.</description>
15606 <description>No interrupt pending.</description>
15611 <description>Interrupt pending.</description>
15618 <description>Interrupt status AFTER Interrupt Enable.</description>
15625 <description>no interrupt pending.</description>
15630 <description>interrupt pending.</description>
15637 <description>comparator analog output.</description>
15644 <description>P+ is smaller than P-.</description>
15649 <description>P+ is greater than P-.</description>
15660 <description>Analog Glitch Control</description>
15669 <description>Analog Glitch Control</description>
15678 <description>Analog Glitch Interrupt Enable Status</description>
15687 <description>Enable interrupt when ANA_GLITCHSENS_STAT is set.</description>
15694 <description>Disabled.</description>
15699 <description>Enabled</description>
15706 …<description>It is set when analog glitch sensor is triggered. It's cleared by software writing 1 …
15713 <description>analog glitch sensor is not triggered.</description>
15718 <description>analog glitch sensor is triggered.</description>
15727 <description>Analog Glitch Test Trigger</description>
15736 <description>Analog glitch test trigger</description>
15743 <description>Test trigger deassertion</description>
15748 <description>Test trigger assertion</description>
15757 <description>Control automatic clock gating</description>
15766 <description>Control automatic clock gating of ROM controller.</description>
15773 <description>Automatic clock gating is not overridden.</description>
15778 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15785 <description>Control automatic clock gating of RAMX controller.</description>
15792 <description>Automatic clock gating is not overridden.</description>
15797 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15804 <description>Control automatic clock gating of RAM0 controller.</description>
15811 <description>Automatic clock gating is not overridden.</description>
15816 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15823 <description>Control automatic clock gating of RAM1 controller.</description>
15830 <description>Automatic clock gating is not overridden.</description>
15835 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15842 <description>Control automatic clock gating of RAM2 controller.</description>
15849 <description>Automatic clock gating is not overridden.</description>
15854 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15861 <description>Control automatic clock gating of RAM3 controller.</description>
15868 <description>Automatic clock gating is not overridden.</description>
15873 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15880 <description>Control automatic clock gating of RAM4 controller.</description>
15887 <description>Automatic clock gating is not overridden.</description>
15892 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15899 … <description>Control automatic clock gating of synchronous bridge controller 0.</description>
15906 <description>Automatic clock gating is not overridden.</description>
15911 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15918 … <description>Control automatic clock gating of synchronous bridge controller 1.</description>
15925 <description>Automatic clock gating is not overridden.</description>
15930 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15937 <description>Control automatic clock gating of FLASH controller.</description>
15944 <description>Automatic clock gating is not overridden.</description>
15949 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15956 <description>Control automatic clock gating of FMC controller.</description>
15963 <description>Automatic clock gating is not overridden.</description>
15968 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15975 <description>Control automatic clock gating of CRCGEN controller.</description>
15982 <description>Automatic clock gating is not overridden.</description>
15987 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
15994 <description>Control automatic clock gating of DMA0 controller.</description>
16001 <description>Automatic clock gating is not overridden.</description>
16006 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
16013 <description>Control automatic clock gating of DMA1 controller.</description>
16020 <description>Automatic clock gating is not overridden.</description>
16025 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
16032 <description>Control automatic clock gating of USB controller.</description>
16039 <description>Automatic clock gating is not overridden.</description>
16044 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
16051 …<description>Control automatic clock gating of synchronous system controller registers bank.</desc…
16058 <description>Automatic clock gating is not overridden.</description>
16063 … <description>Automatic clock gating is overridden (Clock gating is disabled).</description>
16070 …<description>The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to …
16077 <description>Bit Fields 0 - 15 of this register are not updated</description>
16082 <description>Bit Fields 0 - 15 of this register are updated</description>
16091 <description>GPIO Synchronization</description>
16100 …<description>Enable bypass of the first stage of synchronization inside GPIO_INT module.</descript…
16107 … <description>Use the first stage of synchronization inside GPIO_INT module.</description>
16112 … <description>Bypass of the first stage of synchronization inside GPIO_INT module.</description>
16121 <description>Invert Main clock</description>
16130 <description>Invert main_clock (AHB system clock).</description>
16139 <description>Control automatic clock gating</description>
16148 <description>DAC0</description>
16155 <description>DAC1</description>
16162 <description>DAC2</description>
16169 <description>OPAMP0</description>
16176 <description>OPAMP1</description>
16183 <description>OPAMP2</description>
16190 <description>HSCMP0</description>
16197 <description>HSCMP0</description>
16204 <description>HSCMP2</description>
16211 <description>VREF</description>
16218 <description>PWM0</description>
16225 <description>PWM1</description>
16234 <description>Memory parity ECC enable</description>
16243 <description>Enable RAMx parity error check</description>
16250 <description>Disabled</description>
16255 <description>Enabled</description>
16262 <description>Enable RAM00 parity error check</description>
16269 <description>Disabled</description>
16274 <description>Enabled</description>
16281 <description>Enable RAM01 parity error check</description>
16288 <description>Disabled</description>
16293 <description>Enabled</description>
16300 <description>Enable RAMx02 parity error check</description>
16307 <description>Disabled</description>
16312 <description>Enabled</description>
16319 <description>Enable RAM03 parity error check</description>
16326 <description>Disabled</description>
16331 <description>Enabled</description>
16338 <description>Enable RAM1 ECC mbit error check</description>
16345 <description>Disabled</description>
16350 <description>Enabled</description>
16357 <description>Enable RAM1 ECC sbit error check</description>
16364 <description>Disabled</description>
16369 <description>Enabled</description>
16376 <description>Enable RAM2 parity error check</description>
16383 <description>Disabled</description>
16388 <description>Enabled</description>
16395 <description>Enable RAM3 parity error check</description>
16402 <description>Disabled</description>
16407 <description>Enabled</description>
16414 <description>Enable RAM40 parity error check</description>
16421 <description>Disabled</description>
16426 <description>Enabled</description>
16433 <description>Enable RAM41 parity error check</description>
16440 <description>Disabled</description>
16445 <description>Enabled</description>
16452 <description>Enable RAM42 parity error check</description>
16459 <description>Disabled</description>
16464 <description>Enabled</description>
16471 <description>Enable RAM43 parity error check</description>
16478 <description>Disabled</description>
16483 <description>Enabled</description>
16490 <description>Interrupt enable for RAMX parity error</description>
16497 <description>Disable.</description>
16502 … <description>Enable RAM error interrupt when RAMX parity error status flag is set.</description>
16509 <description>Interrupt enable for RAMA parity error</description>
16516 <description>Disable.</description>
16521 … <description>Enable RAM error interrupt when RAMA parity error status flag is set.</description>
16528 <description>Interrupt enable for RAMB ECC mbit_err</description>
16535 <description>Disable.</description>
16540 … <description>Enable RAM error interrupt when RAMB ECC mbit_err status flag is set.</description>
16547 <description>Interrupt enable for RAMB ECC sbit_err</description>
16554 <description>Disable.</description>
16559 … <description>Enable RAM error interrupt when RAMB ECC sbit_err status flag is set.</description>
16566 <description>Interrupt enable for RAMC parity error</description>
16573 <description>Disable.</description>
16578 … <description>Enable RAM error interrupt when RAMC parity error status flag is set.</description>
16585 <description>Interrupt enable for RAMD parity error</description>
16592 <description>Disable.</description>
16597 … <description>Enable RAM error interrupt when RAMD parity error status flag is set.</description>
16604 <description>Interrupt enable for RAME parity error</description>
16611 <description>Disable.</description>
16616 … <description>Enable RAM error interrupt when RAME parity error status flag is set.</description>
16625 <description>Memory parity ECC error flag</description>
16634 <description>RAMx parity error detected</description>
16641 <description>No error detected</description>
16646 <description>Error detected</description>
16653 <description>RAM0 parity error detected</description>
16660 <description>No error detected</description>
16665 <description>Error detected</description>
16672 <description>RAM1 ECC mbit error detected</description>
16679 <description>No error detected</description>
16684 <description>Error detected</description>
16691 <description>RAM1 ECC sbit error detected</description>
16698 <description>No error detected</description>
16703 <description>Error detected</description>
16710 <description>RAM2 parity error detected</description>
16717 <description>No error detected</description>
16722 <description>Error detected</description>
16729 <description>RAM3 parity error detected</description>
16736 <description>No error detected</description>
16741 <description>Error detected</description>
16748 <description>RAM4 parity error detected</description>
16755 <description>No error detected</description>
16760 <description>Error detected</description>
16769 <description>PWM0 submodule control</description>
16778 <description>PWM0 SUB Clock0 enable</description>
16785 <description>PWM0 SUB Clock1 enable</description>
16792 <description>PWM0 SUB Clock2 enable</description>
16799 <description>PWM0 SUB Clock3 enable</description>
16806 <description>PWM0 submodule 0 DMA Compare Value Done Mask</description>
16813 <description>PWM0 submodule 1 DMA Compare Value Done Mask</description>
16820 <description>PWM0 submodule 2 DMA Compare Value Done Mask</description>
16827 <description>PWM0 submodule 3 DMA Compare Value Done Mask</description>
16836 <description>PWM1 submodule control</description>
16845 <description>PWM1 SUB Clock0 enable</description>
16852 <description>PWM1 SUB Clock1 enable</description>
16859 <description>PWM1 SUB Clock2 enable</description>
16866 <description>PWM1 SUB Clock3 enable</description>
16873 <description>PWM1 submodule 0 DMA Compare Value Done Mask</description>
16880 <description>PWM1 submodule 1 DMA Compare Value Done Mask</description>
16887 <description>PWM1 submodule 2 DMA Compare Value Done Mask</description>
16894 <description>PWM1 submodule 3 DMA Compare Value Done Mask</description>
16903 <description>CTIMER global start enable</description>
16912 <description>CTIMER0 function clock enable</description>
16919 <description>CTIMER1 function clock enable</description>
16926 <description>CTIMER2 function clock enable</description>
16933 <description>CTIMER3 function clock enable</description>
16940 <description>CTIMER4 function clock enable</description>
16949 <description>Control write access to security</description>
16958 <description>Control write access to security registers.</description>
16965 … <description>Any other value than b1010: disable write access to all registers.</description>
16970 <description>1010: Enable write access to all registers.</description>
16979 <description>Cortex debug features control</description>
16988 <description>CPU0 Invasive Debug Control</description>
16995 <description>Disable debug</description>
17000 <description>Enable debug</description>
17007 <description>CPU0 Non Invasive Debug Control</description>
17014 <description>Disable debug</description>
17019 <description>Enable debug</description>
17026 <description>CPU0 Secure Privileged Invasive Debug Control</description>
17033 <description>Disable debug</description>
17038 <description>Enable debug</description>
17045 <description>CPU0 Secure Privileged Non Invasive Debug Control</description>
17052 <description>Disable debug</description>
17057 <description>Enable debug</description>
17066 <description>Cortex debug features control (duplicate)</description>
17075 <description>CPU0 Invasive Debug Control</description>
17082 <description>Disable debug</description>
17087 <description>Enable debug</description>
17094 <description>CPU0 Non Invasive Debug Control</description>
17101 <description>Disable debug</description>
17106 <description>Enable debug</description>
17113 <description>CPU0 Secure Privileged Invasive Debug Control</description>
17120 <description>Disable debug</description>
17125 <description>Enable debug</description>
17132 <description>CPU0 Secure Privileged Non Invasive Debug Control</description>
17139 <description>Disable debug</description>
17144 <description>Enable debug</description>
17153 <description>Security code to allow test (Design for Testability) access.</description>
17162 <description>Security code to allow test access : 0x12345678.</description>
17169 <description>test access is not allowed.</description>
17174 <description>Security code to allow test access.</description>
17183 <description>CPU0 Software Debug Access</description>
17192 <description>CPU0 SWD-AP: 0x12345678.</description>
17199 … <description>CPU0 DAP is not allowed. Reading back register will be read as 0x5.</description>
17204 …<description>Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA.<…
17213 <description>Key block</description>
17222 <description>Write a value to block PUF all index.</description>
17231 <description>Debug authentication BEACON</description>
17240 …description>Set by the debug authentication code in ROM to pass the debug beacons (Credential Beac…
17249 <description>DSP Software Debug Access</description>
17258 <description>DSP SWD-AP: 0x12345678.</description>
17265 … <description>DSP DAP is not allowed. Reading back register will be read as 0x5.</description>
17270 …<description>Value to write to enable DSP SWD access. Reading back register will be read as 0xA.</…
17279 <description>Flash size configuration</description>
17288 <description>Flash_size.</description>
17295 <description>128KB when 8'b00000000.</description>
17300 <description>256KB when 8'b00000001.</description>
17305 <description>512KB when 8'b00000010.</description>
17310 <description>640KB when others.</description>
17317 <description>Flash start address.</description>
17324 <description>Private flash start 32kB before last address.</description>
17329 <description>Private flash start 64kB before last address.</description>
17338 <description>Disable write access to FLASHSIZECFG, SRAMSIZECFG, CPUCFG.</description>
17347 …<description>Disable write access to FLASHSIZECFG, SRAMSIZECFG, DEVICE_ID0 and DEVICE_ID1.</descri…
17354 …<description>Enable write access to FLASHSIZECFG, SRAMSIZECFG, DEVICE_ID0 and DEVICE_ID1.</descrip…
17359 …<description>Disable write access to FLASHSIZECFG, SRAMSIZECFG, DEVICE_ID0 and DEVICE_ID1.</descri…
17366 <description>Disable write access to scratch lock.</description>
17373 <description>Enable write access to scratch lock.</description>
17378 <description>Disable write access to scratch lock.</description>
17385 <description>Disable write access to FLASHBENKENABLE.</description>
17392 <description>Enable write access to FLASHBENKENABLE.</description>
17397 <description>Disable write access to FLASHBENKENABLE.</description>
17404 <description>Disable write access to FLASHBENKENABLE.</description>
17411 <description>Enable write access to FLASHBENKENABLE.</description>
17416 <description>Disable write access to FLASHBENKENABLE.</description>
17423 <description>Disable write access to FLASHBENKENABLE.</description>
17430 <description>Enable write access to FLASHBENKENABLE.</description>
17435 <description>Disable write access to FLASHBENKENABLE.</description>
17442 <description>Disable write access to FLASHBENKENABLE.</description>
17449 <description>Enable write access to FLASHBENKENABLE.</description>
17454 <description>Disable write access to FLASHBENKENABLE.</description>
17461 <description>Disable write access to FLASHBENKENABLE.</description>
17468 <description>Enable write access to FLASHBENKENABLE.</description>
17473 <description>Disable write access to FLASHBENKENABLE.</description>
17480 <description>Disable write access to FLASHBENKENABLE.</description>
17487 <description>Enable write access to FLASHBENKENABLE.</description>
17492 <description>Disable write access to FLASHBENKENABLE.</description>
17499 <description>Disable write access to FLASHBENKENABLE.</description>
17506 <description>Enable write access to FLASHBENKENABLE.</description>
17511 <description>Disable write access to FLASHBENKENABLE.</description>
17518 <description>Disable write access to FLASHBENKENABLE.</description>
17525 <description>Enable write access to FLASHBENKENABLE.</description>
17530 <description>Disable write access to FLASHBENKENABLE.</description>
17539 <description>RAM size</description>
17548 <description>RAMX size:.</description>
17555 <description>RAMX size is 0 KByte.</description>
17560 <description>RAMX size is 16 KByte.</description>
17565 <description>RAMX size is 32 KByte.</description>
17572 <description>RAM0 size:.</description>
17579 <description>RAM0 size is 0 KByte.</description>
17584 <description>RAM0 size is 32 Kbyte.</description>
17589 <description>RAM0 size is 64 Kbyte.</description>
17596 <description>RAM1 size:.</description>
17603 <description>RAM1 size is 0 KByte.</description>
17608 <description>RAM1 size is 32 Kbyte.</description>
17613 <description>RAM1 size is 64 Kbyte.</description>
17620 <description>RAM2 size:.</description>
17627 <description>RAM2 size is 0 KByte.</description>
17632 <description>RAM2 size is 32 Kbyte.</description>
17637 <description>RAM2 size is 64 Kbyte.</description>
17644 <description>RAM3 size:.</description>
17651 <description>RAM3 size is 0 KByte.</description>
17656 <description>RAM3 size is 32 Kbyte.</description>
17661 <description>RAM3 size is 64 Kbyte.</description>
17668 <description>RAM4 size:.</description>
17675 <description>RAM4 size is 0 KByte.</description>
17680 <description>RAM4 size is 8 Kbyte.</description>
17685 <description>RAM4 size is 16 Kbyte.</description>
17694 <description>peripheral enable configuration</description>
17703 <description>SCT enable.</description>
17710 <description>peripheral is disable.</description>
17715 <description>peripheral is enable.</description>
17722 <description>ADC enable.</description>
17729 <description>peripheral is disable.</description>
17734 <description>peripheral is enable.</description>
17741 <description>USB0 enable.</description>
17748 <description>peripheral is disable.</description>
17753 <description>peripheral is enable.</description>
17760 <description>Puff enable.</description>
17767 <description>peripheral is disable.</description>
17772 <description>peripheral is enable.</description>
17779 <description>USB1-HS enable.</description>
17786 <description>peripheral is disable.</description>
17791 <description>peripheral is enable.</description>
17798 <description>SDIO enable.</description>
17805 <description>peripheral is disable.</description>
17810 <description>peripheral is enable.</description>
17817 <description>HASH enable.</description>
17824 <description>peripheral is disable.</description>
17829 <description>peripheral is enable.</description>
17836 <description>PRINCE enable.</description>
17843 <description>peripheral is disable.</description>
17848 <description>peripheral is enable.</description>
17857 <description>Device type</description>
17866 <description>Device ID</description>
17875 <description>Device type number. (E.g : LPC5569 stored as 69 decimal)</description>
17882 <description>Security device type</description>
17889 <description>SRAM size</description>
17896 <description>Flash size</description>
17903 <description>ROM revision.</description>
17910 <description>Model number extention</description>
17919 <description>Chip revision ID and Number</description>
17928 <description>Chip Metal Revision ID.</description>
17935 <description>Chip Number 0x426B.</description>
17946 <description>IOCON</description>
17957 <description>Analog/Digital I/O control for port</description>
17966 <description>Signal(function) select</description>
17973 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
17980 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
17985 <description>Pull-down. Pull-down resistor enabled.</description>
17990 <description>Pull-up. Pull-up resistor enabled.</description>
17995 <description>Repeater. Repeater mode.</description>
18002 <description>Driver slew rate</description>
18009 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18014 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18021 <description>Invert polarity of input signal</description>
18028 <description>Don't invert the signal.</description>
18033 <description>Invert the signal.</description>
18040 <description>Select Digital mode</description>
18047 <description>Disable digital mode. Digital input set to 0.</description>
18052 <description>Enable Digital mode. Digital input is enabled.</description>
18059 <description>Controls open-drain mode</description>
18066 <description>Normal. Normal push-pull output</description>
18071 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18078 <description>Analog switch input control</description>
18085 <description>Analog switch is open. (disable)</description>
18090 <description>Analog switch is closed. (enable)</description>
18099 <description>Analog/Digital I/O control for port</description>
18108 <description>Signal(function) select</description>
18115 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18122 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18127 <description>Pull-down. Pull-down resistor enabled.</description>
18132 <description>Pull-up. Pull-up resistor enabled.</description>
18137 <description>Repeater. Repeater mode.</description>
18144 <description>Driver slew rate</description>
18151 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18156 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18163 <description>Invert polarity of input signal</description>
18170 <description>Don't invert the signal.</description>
18175 <description>Invert the signal.</description>
18182 <description>Select Digital mode</description>
18189 <description>Disable digital mode. Digital input set to 0.</description>
18194 <description>Enable Digital mode. Digital input is enabled.</description>
18201 <description>Controls open-drain mode</description>
18208 <description>Normal. Normal push-pull output</description>
18213 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18222 <description>Digital I/O control for port</description>
18231 <description>Signal(function) select</description>
18238 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18245 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18250 <description>Pull-down. Pull-down resistor enabled.</description>
18255 <description>Pull-up. Pull-up resistor enabled.</description>
18260 <description>Repeater. Repeater mode.</description>
18267 <description>Driver slew rate</description>
18274 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18279 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18286 <description>Invert polarity of input signal</description>
18293 <description>Don't invert the signal.</description>
18298 <description>Invert the signal.</description>
18305 <description>Select Digital mode</description>
18312 <description>Disable digital mode. Digital input set to 0.</description>
18317 <description>Enable Digital mode. Digital input is enabled.</description>
18324 <description>Controls open-drain mode</description>
18331 <description>Normal. Normal push-pull output</description>
18336 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18345 <description>Digital I/O control for port</description>
18354 <description>Signal(function) select</description>
18361 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18368 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18373 <description>Pull-down. Pull-down resistor enabled.</description>
18378 <description>Pull-up. Pull-up resistor enabled.</description>
18383 <description>Repeater. Repeater mode.</description>
18390 <description>Driver slew rate</description>
18397 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18402 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18409 <description>Invert polarity of input signal</description>
18416 <description>Don't invert the signal.</description>
18421 <description>Invert the signal.</description>
18428 <description>Select Digital mode</description>
18435 <description>Disable digital mode. Digital input set to 0.</description>
18440 <description>Enable Digital mode. Digital input is enabled.</description>
18447 <description>Controls open-drain mode</description>
18454 <description>Normal. Normal push-pull output</description>
18459 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18468 <description>Digital I/O control for port</description>
18477 <description>Signal(function) select</description>
18484 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18491 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18496 <description>Pull-down. Pull-down resistor enabled.</description>
18501 <description>Pull-up. Pull-up resistor enabled.</description>
18506 <description>Repeater. Repeater mode.</description>
18513 <description>Driver slew rate</description>
18520 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18525 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18532 <description>Invert polarity of input signal</description>
18539 <description>Don't invert the signal.</description>
18544 <description>Invert the signal.</description>
18551 <description>Select Digital mode</description>
18558 <description>Disable digital mode. Digital input set to 0.</description>
18563 <description>Enable Digital mode. Digital input is enabled.</description>
18570 <description>Controls open-drain mode</description>
18577 <description>Normal. Normal push-pull output</description>
18582 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18591 <description>Digital I/O control for port</description>
18600 <description>Signal(function) select</description>
18607 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18614 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18619 <description>Pull-down. Pull-down resistor enabled.</description>
18624 <description>Pull-up. Pull-up resistor enabled.</description>
18629 <description>Repeater. Repeater mode.</description>
18636 <description>Driver slew rate</description>
18643 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18648 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18655 <description>Invert polarity of input signal</description>
18662 <description>Don't invert the signal.</description>
18667 <description>Invert the signal.</description>
18674 <description>Select Digital mode</description>
18681 <description>Disable digital mode. Digital input set to 0.</description>
18686 <description>Enable Digital mode. Digital input is enabled.</description>
18693 <description>Controls open-drain mode</description>
18700 <description>Normal. Normal push-pull output</description>
18705 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18714 <description>Digital I/O control for port</description>
18723 <description>Signal(function) select</description>
18730 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18737 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18742 <description>Pull-down. Pull-down resistor enabled.</description>
18747 <description>Pull-up. Pull-up resistor enabled.</description>
18752 <description>Repeater. Repeater mode.</description>
18759 <description>Driver slew rate</description>
18766 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18771 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18778 <description>Invert polarity of input signal</description>
18785 <description>Don't invert the signal.</description>
18790 <description>Invert the signal.</description>
18797 <description>Select Digital mode</description>
18804 <description>Disable digital mode. Digital input set to 0.</description>
18809 <description>Enable Digital mode. Digital input is enabled.</description>
18816 <description>Controls open-drain mode</description>
18823 <description>Normal. Normal push-pull output</description>
18828 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18837 <description>Analog/Digital I/O control for port</description>
18846 <description>Signal(function) select</description>
18853 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
18860 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
18865 <description>Pull-down. Pull-down resistor enabled.</description>
18870 <description>Pull-up. Pull-up resistor enabled.</description>
18875 <description>Repeater. Repeater mode.</description>
18882 <description>Driver slew rate</description>
18889 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
18894 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
18901 <description>Invert polarity of input signal</description>
18908 <description>Don't invert the signal.</description>
18913 <description>Invert the signal.</description>
18920 <description>Select Digital mode</description>
18927 <description>Disable digital mode. Digital input set to 0.</description>
18932 <description>Enable Digital mode. Digital input is enabled.</description>
18939 <description>Controls open-drain mode</description>
18946 <description>Normal. Normal push-pull output</description>
18951 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
18958 <description>Analog switch input control</description>
18965 <description>Analog switch is open. (disable)</description>
18970 <description>Analog switch is closed. (enable)</description>
18979 <description>Analog/Digital I/O control for port</description>
18988 <description>Signal(function) select</description>
18995 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19002 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19007 <description>Pull-down. Pull-down resistor enabled.</description>
19012 <description>Pull-up. Pull-up resistor enabled.</description>
19017 <description>Repeater. Repeater mode.</description>
19024 <description>Driver slew rate</description>
19031 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19036 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19043 <description>Invert polarity of input signal</description>
19050 <description>Don't invert the signal.</description>
19055 <description>Invert the signal.</description>
19062 <description>Select Digital mode</description>
19069 <description>Disable digital mode. Digital input set to 0.</description>
19074 <description>Enable Digital mode. Digital input is enabled.</description>
19081 <description>Controls open-drain mode</description>
19088 <description>Normal. Normal push-pull output</description>
19093 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19102 <description>Analog/Digital I/O control for port</description>
19111 <description>Signal(function) select</description>
19118 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19125 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19130 <description>Pull-down. Pull-down resistor enabled.</description>
19135 <description>Pull-up. Pull-up resistor enabled.</description>
19140 <description>Repeater. Repeater mode.</description>
19147 <description>Driver slew rate</description>
19154 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19159 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19166 <description>Invert polarity of input signal</description>
19173 <description>Don't invert the signal.</description>
19178 <description>Invert the signal.</description>
19185 <description>Select Digital mode</description>
19192 <description>Disable digital mode. Digital input set to 0.</description>
19197 <description>Enable Digital mode. Digital input is enabled.</description>
19204 <description>Controls open-drain mode</description>
19211 <description>Normal. Normal push-pull output</description>
19216 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19223 <description>Analog switch input control</description>
19230 <description>Analog switch is open. (disable)</description>
19235 <description>Analog switch is closed. (enable)</description>
19244 <description>Analog/Digital I/O control for port</description>
19253 <description>Signal(function) select</description>
19260 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19267 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19272 <description>Pull-down. Pull-down resistor enabled.</description>
19277 <description>Pull-up. Pull-up resistor enabled.</description>
19282 <description>Repeater. Repeater mode.</description>
19289 <description>Driver slew rate</description>
19296 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19301 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19308 <description>Invert polarity of input signal</description>
19315 <description>Don't invert the signal.</description>
19320 <description>Invert the signal.</description>
19327 <description>Select Digital mode</description>
19334 <description>Disable digital mode. Digital input set to 0.</description>
19339 <description>Enable Digital mode. Digital input is enabled.</description>
19346 <description>Controls open-drain mode</description>
19353 <description>Normal. Normal push-pull output</description>
19358 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19367 <description>Analog/Digital I/O control for port</description>
19376 <description>Signal(function) select</description>
19383 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19390 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19395 <description>Pull-down. Pull-down resistor enabled.</description>
19400 <description>Pull-up. Pull-up resistor enabled.</description>
19405 <description>Repeater. Repeater mode.</description>
19412 <description>Driver slew rate</description>
19419 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19424 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19431 <description>Invert polarity of input signal</description>
19438 <description>Don't invert the signal.</description>
19443 <description>Invert the signal.</description>
19450 <description>Select Digital mode</description>
19457 <description>Disable digital mode. Digital input set to 0.</description>
19462 <description>Enable Digital mode. Digital input is enabled.</description>
19469 <description>Controls open-drain mode</description>
19476 <description>Normal. Normal push-pull output</description>
19481 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19490 <description>Analog/Digital I/O control for port</description>
19499 <description>Signal(function) select</description>
19506 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19513 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19518 <description>Pull-down. Pull-down resistor enabled.</description>
19523 <description>Pull-up. Pull-up resistor enabled.</description>
19528 <description>Repeater. Repeater mode.</description>
19535 <description>Driver slew rate</description>
19542 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19547 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19554 <description>Invert polarity of input signal</description>
19561 <description>Don't invert the signal.</description>
19566 <description>Invert the signal.</description>
19573 <description>Select Digital mode</description>
19580 <description>Disable digital mode. Digital input set to 0.</description>
19585 <description>Enable Digital mode. Digital input is enabled.</description>
19592 <description>Controls open-drain mode</description>
19599 <description>Normal. Normal push-pull output</description>
19604 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19613 <description>I2C control for port</description>
19622 <description>Signal(function) select</description>
19629 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19636 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19641 <description>Pull-down. Pull-down resistor enabled.</description>
19646 <description>Pull-up. Pull-up resistor enabled.</description>
19651 <description>Repeater. Repeater mode.</description>
19658 <description>Driver slew rate</description>
19665 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19670 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19677 <description>Invert polarity of input signal</description>
19684 <description>Don't invert the signal.</description>
19689 <description>Invert the signal.</description>
19696 <description>Select Digital mode</description>
19703 <description>Disable digital mode. Digital input set to 0.</description>
19708 <description>Enable Digital mode. Digital input is enabled.</description>
19715 <description>Controls open-drain mode</description>
19722 <description>Normal. Normal push-pull output</description>
19727 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19734 <description>Supply Selection bit.</description>
19741 <description>3V3 Signaling in I2C Mode.</description>
19746 <description>1V8 Signaling in I2C Mode.</description>
19753 <description>Controls input glitch filter</description>
19760 <description>Filter enabled.</description>
19765 <description>Filter disabled.</description>
19772 <description>Pull-up current source enable in I2C mode</description>
19779 <description>Disabled. IO is in open drain cell.</description>
19784 <description>Enabled. Pull resistor is conencted.</description>
19791 <description>Switch between GPIO mode and I2C mode</description>
19798 <description>I2C mode</description>
19803 <description>GPIO mode.</description>
19810 …<description>Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation an…
19817 …<description>I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast…
19822 …<description>I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C.</description>
19831 <description>I2C control for port</description>
19840 <description>Signal(function) select</description>
19847 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
19854 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
19859 <description>Pull-down. Pull-down resistor enabled.</description>
19864 <description>Pull-up. Pull-up resistor enabled.</description>
19869 <description>Repeater. Repeater mode.</description>
19876 <description>Driver slew rate</description>
19883 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
19888 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
19895 <description>Invert polarity of input signal</description>
19902 <description>Don't invert the signal.</description>
19907 <description>Invert the signal.</description>
19914 <description>Select Digital mode</description>
19921 <description>Disable digital mode. Digital input set to 0.</description>
19926 <description>Enable Digital mode. Digital input is enabled.</description>
19933 <description>Controls open-drain mode</description>
19940 <description>Normal. Normal push-pull output</description>
19945 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
19952 <description>Supply Selection bit.</description>
19959 <description>3V3 Signaling in I2C Mode.</description>
19964 <description>1V8 Signaling in I2C Mode.</description>
19971 <description>Controls input glitch filter</description>
19978 <description>Filter enabled.</description>
19983 <description>Filter disabled.</description>
19990 <description>Pull-up current source enable in I2C mode</description>
19997 <description>Disabled. IO is in open drain cell.</description>
20002 <description>Enabled. Pull resistor is conencted.</description>
20009 <description>Switch between GPIO mode and I2C mode</description>
20016 <description>I2C mode</description>
20021 <description>GPIO mode.</description>
20028 …<description>Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation an…
20035 …<description>I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast…
20040 …<description>I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C.</description>
20049 <description>Analog/Digital I/O control for port</description>
20058 <description>Signal(function) select</description>
20065 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20072 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20077 <description>Pull-down. Pull-down resistor enabled.</description>
20082 <description>Pull-up. Pull-up resistor enabled.</description>
20087 <description>Repeater. Repeater mode.</description>
20094 <description>Driver slew rate</description>
20101 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20106 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20113 <description>Invert polarity of input signal</description>
20120 <description>Don't invert the signal.</description>
20125 <description>Invert the signal.</description>
20132 <description>Select Digital mode</description>
20139 <description>Disable digital mode. Digital input set to 0.</description>
20144 <description>Enable Digital mode. Digital input is enabled.</description>
20151 <description>Controls open-drain mode</description>
20158 <description>Normal. Normal push-pull output</description>
20163 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20172 <description>Analog/Digital I/O control for port</description>
20181 <description>Signal(function) select</description>
20188 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20195 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20200 <description>Pull-down. Pull-down resistor enabled.</description>
20205 <description>Pull-up. Pull-up resistor enabled.</description>
20210 <description>Repeater. Repeater mode.</description>
20217 <description>Driver slew rate</description>
20224 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20229 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20236 <description>Invert polarity of input signal</description>
20243 <description>Don't invert the signal.</description>
20248 <description>Invert the signal.</description>
20255 <description>Select Digital mode</description>
20262 <description>Disable digital mode. Digital input set to 0.</description>
20267 <description>Enable Digital mode. Digital input is enabled.</description>
20274 <description>Controls open-drain mode</description>
20281 <description>Normal. Normal push-pull output</description>
20286 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20295 <description>Analog/Digital I/O control for port</description>
20304 <description>Signal(function) select</description>
20311 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20318 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20323 <description>Pull-down. Pull-down resistor enabled.</description>
20328 <description>Pull-up. Pull-up resistor enabled.</description>
20333 <description>Repeater. Repeater mode.</description>
20340 <description>Driver slew rate</description>
20347 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20352 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20359 <description>Invert polarity of input signal</description>
20366 <description>Don't invert the signal.</description>
20371 <description>Invert the signal.</description>
20378 <description>Select Digital mode</description>
20385 <description>Disable digital mode. Digital input set to 0.</description>
20390 <description>Enable Digital mode. Digital input is enabled.</description>
20397 <description>Controls open-drain mode</description>
20404 <description>Normal. Normal push-pull output</description>
20409 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20416 <description>Analog switch input control</description>
20423 <description>Analog switch is open. (disable)</description>
20428 <description>Analog switch is closed. (enable)</description>
20437 <description>Analog/Digital I/O control for port</description>
20446 <description>Signal(function) select</description>
20453 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20460 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20465 <description>Pull-down. Pull-down resistor enabled.</description>
20470 <description>Pull-up. Pull-up resistor enabled.</description>
20475 <description>Repeater. Repeater mode.</description>
20482 <description>Driver slew rate</description>
20489 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20494 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20501 <description>Invert polarity of input signal</description>
20508 <description>Don't invert the signal.</description>
20513 <description>Invert the signal.</description>
20520 <description>Select Digital mode</description>
20527 <description>Disable digital mode. Digital input set to 0.</description>
20532 <description>Enable Digital mode. Digital input is enabled.</description>
20539 <description>Controls open-drain mode</description>
20546 <description>Normal. Normal push-pull output</description>
20551 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20558 <description>Analog switch input control</description>
20565 <description>Analog switch is open. (disable)</description>
20570 <description>Analog switch is closed. (enable)</description>
20579 <description>Digital I/O control for port</description>
20588 <description>Signal(function) select</description>
20595 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20602 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20607 <description>Pull-down. Pull-down resistor enabled.</description>
20612 <description>Pull-up. Pull-up resistor enabled.</description>
20617 <description>Repeater. Repeater mode.</description>
20624 <description>Driver slew rate</description>
20631 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20636 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20643 <description>Invert polarity of input signal</description>
20650 <description>Don't invert the signal.</description>
20655 <description>Invert the signal.</description>
20662 <description>Select Digital mode</description>
20669 <description>Disable digital mode. Digital input set to 0.</description>
20674 <description>Enable Digital mode. Digital input is enabled.</description>
20681 <description>Controls open-drain mode</description>
20688 <description>Normal. Normal push-pull output</description>
20693 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20702 <description>Digital I/O control for port</description>
20711 <description>Signal(function) select</description>
20718 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20725 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20730 <description>Pull-down. Pull-down resistor enabled.</description>
20735 <description>Pull-up. Pull-up resistor enabled.</description>
20740 <description>Repeater. Repeater mode.</description>
20747 <description>Driver slew rate</description>
20754 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20759 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20766 <description>Invert polarity of input signal</description>
20773 <description>Don't invert the signal.</description>
20778 <description>Invert the signal.</description>
20785 <description>Select Digital mode</description>
20792 <description>Disable digital mode. Digital input set to 0.</description>
20797 <description>Enable Digital mode. Digital input is enabled.</description>
20804 <description>Controls open-drain mode</description>
20811 <description>Normal. Normal push-pull output</description>
20816 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20825 <description>Digital I/O control for port</description>
20834 <description>Signal(function) select</description>
20841 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20848 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20853 <description>Pull-down. Pull-down resistor enabled.</description>
20858 <description>Pull-up. Pull-up resistor enabled.</description>
20863 <description>Repeater. Repeater mode.</description>
20870 <description>Driver slew rate</description>
20877 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
20882 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
20889 <description>Invert polarity of input signal</description>
20896 <description>Don't invert the signal.</description>
20901 <description>Invert the signal.</description>
20908 <description>Select Digital mode</description>
20915 <description>Disable digital mode. Digital input set to 0.</description>
20920 <description>Enable Digital mode. Digital input is enabled.</description>
20927 <description>Controls open-drain mode</description>
20934 <description>Normal. Normal push-pull output</description>
20939 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
20948 <description>Digital I/O control for port</description>
20957 <description>Signal(function) select</description>
20964 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
20971 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
20976 <description>Pull-down. Pull-down resistor enabled.</description>
20981 <description>Pull-up. Pull-up resistor enabled.</description>
20986 <description>Repeater. Repeater mode.</description>
20993 <description>Driver slew rate</description>
21000 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21005 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21012 <description>Invert polarity of input signal</description>
21019 <description>Don't invert the signal.</description>
21024 <description>Invert the signal.</description>
21031 <description>Select Digital mode</description>
21038 <description>Disable digital mode. Digital input set to 0.</description>
21043 <description>Enable Digital mode. Digital input is enabled.</description>
21050 <description>Controls open-drain mode</description>
21057 <description>Normal. Normal push-pull output</description>
21062 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21071 <description>Analog/Digital I/O control for port</description>
21080 <description>Signal(function) select</description>
21087 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21094 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21099 <description>Pull-down. Pull-down resistor enabled.</description>
21104 <description>Pull-up. Pull-up resistor enabled.</description>
21109 <description>Repeater. Repeater mode.</description>
21116 <description>Driver slew rate</description>
21123 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21128 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21135 <description>Invert polarity of input signal</description>
21142 <description>Don't invert the signal.</description>
21147 <description>Invert the signal.</description>
21154 <description>Select Digital mode</description>
21161 <description>Disable digital mode. Digital input set to 0.</description>
21166 <description>Enable Digital mode. Digital input is enabled.</description>
21173 <description>Controls open-drain mode</description>
21180 <description>Normal. Normal push-pull output</description>
21185 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21192 <description>Analog switch input control</description>
21199 <description>Analog switch is open. (disable)</description>
21204 <description>Analog switch is closed. (enable)</description>
21213 <description>Analog/Digital I/O control for port</description>
21222 <description>Signal(function) select</description>
21229 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21236 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21241 <description>Pull-down. Pull-down resistor enabled.</description>
21246 <description>Pull-up. Pull-up resistor enabled.</description>
21251 <description>Repeater. Repeater mode.</description>
21258 <description>Driver slew rate</description>
21265 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21270 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21277 <description>Invert polarity of input signal</description>
21284 <description>Don't invert the signal.</description>
21289 <description>Invert the signal.</description>
21296 <description>Select Digital mode</description>
21303 <description>Disable digital mode. Digital input set to 0.</description>
21308 <description>Enable Digital mode. Digital input is enabled.</description>
21315 <description>Controls open-drain mode</description>
21322 <description>Normal. Normal push-pull output</description>
21327 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21334 <description>Analog switch input control</description>
21341 <description>Analog switch is open. (disable)</description>
21346 <description>Analog switch is closed. (enable)</description>
21355 <description>Digital I/O control for port</description>
21364 <description>Signal(function) select</description>
21371 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21378 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21383 <description>Pull-down. Pull-down resistor enabled.</description>
21388 <description>Pull-up. Pull-up resistor enabled.</description>
21393 <description>Repeater. Repeater mode.</description>
21400 <description>Driver slew rate</description>
21407 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21412 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21419 <description>Invert polarity of input signal</description>
21426 <description>Don't invert the signal.</description>
21431 <description>Invert the signal.</description>
21438 <description>Select Digital mode</description>
21445 <description>Disable digital mode. Digital input set to 0.</description>
21450 <description>Enable Digital mode. Digital input is enabled.</description>
21457 <description>Controls open-drain mode</description>
21464 <description>Normal. Normal push-pull output</description>
21469 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21478 <description>Digital I/O control for port</description>
21487 <description>Signal(function) select</description>
21494 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21501 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21506 <description>Pull-down. Pull-down resistor enabled.</description>
21511 <description>Pull-up. Pull-up resistor enabled.</description>
21516 <description>Repeater. Repeater mode.</description>
21523 <description>Driver slew rate</description>
21530 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21535 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21542 <description>Invert polarity of input signal</description>
21549 <description>Don't invert the signal.</description>
21554 <description>Invert the signal.</description>
21561 <description>Select Digital mode</description>
21568 <description>Disable digital mode. Digital input set to 0.</description>
21573 <description>Enable Digital mode. Digital input is enabled.</description>
21580 <description>Controls open-drain mode</description>
21587 <description>Normal. Normal push-pull output</description>
21592 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21601 <description>Analog/Digital I/O control for port</description>
21610 <description>Signal(function) select</description>
21617 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21624 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21629 <description>Pull-down. Pull-down resistor enabled.</description>
21634 <description>Pull-up. Pull-up resistor enabled.</description>
21639 <description>Repeater. Repeater mode.</description>
21646 <description>Driver slew rate</description>
21653 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21658 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21665 <description>Invert polarity of input signal</description>
21672 <description>Don't invert the signal.</description>
21677 <description>Invert the signal.</description>
21684 <description>Select Digital mode</description>
21691 <description>Disable digital mode. Digital input set to 0.</description>
21696 <description>Enable Digital mode. Digital input is enabled.</description>
21703 <description>Controls open-drain mode</description>
21710 <description>Normal. Normal push-pull output</description>
21715 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21724 <description>Digital I/O control for port</description>
21733 <description>Signal(function) select</description>
21740 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21747 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21752 <description>Pull-down. Pull-down resistor enabled.</description>
21757 <description>Pull-up. Pull-up resistor enabled.</description>
21762 <description>Repeater. Repeater mode.</description>
21769 <description>Driver slew rate</description>
21776 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21781 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21788 <description>Invert polarity of input signal</description>
21795 <description>Don't invert the signal.</description>
21800 <description>Invert the signal.</description>
21807 <description>Select Digital mode</description>
21814 <description>Disable digital mode. Digital input set to 0.</description>
21819 <description>Enable Digital mode. Digital input is enabled.</description>
21826 <description>Controls open-drain mode</description>
21833 <description>Normal. Normal push-pull output</description>
21838 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21847 <description>Digital I/O control for port</description>
21856 <description>Signal(function) select</description>
21863 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21870 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21875 <description>Pull-down. Pull-down resistor enabled.</description>
21880 <description>Pull-up. Pull-up resistor enabled.</description>
21885 <description>Repeater. Repeater mode.</description>
21892 <description>Driver slew rate</description>
21899 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
21904 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
21911 <description>Invert polarity of input signal</description>
21918 <description>Don't invert the signal.</description>
21923 <description>Invert the signal.</description>
21930 <description>Select Digital mode</description>
21937 <description>Disable digital mode. Digital input set to 0.</description>
21942 <description>Enable Digital mode. Digital input is enabled.</description>
21949 <description>Controls open-drain mode</description>
21956 <description>Normal. Normal push-pull output</description>
21961 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
21970 <description>Digital I/O control for port</description>
21979 <description>Signal(function) select</description>
21986 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
21993 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
21998 <description>Pull-down. Pull-down resistor enabled.</description>
22003 <description>Pull-up. Pull-up resistor enabled.</description>
22008 <description>Repeater. Repeater mode.</description>
22015 <description>Driver slew rate</description>
22022 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22027 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22034 <description>Invert polarity of input signal</description>
22041 <description>Don't invert the signal.</description>
22046 <description>Invert the signal.</description>
22053 <description>Select Digital mode</description>
22060 <description>Disable digital mode. Digital input set to 0.</description>
22065 <description>Enable Digital mode. Digital input is enabled.</description>
22072 <description>Controls open-drain mode</description>
22079 <description>Normal. Normal push-pull output</description>
22084 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22093 <description>Analog/Digital I/O control for port</description>
22102 <description>Signal(function) select</description>
22109 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22116 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22121 <description>Pull-down. Pull-down resistor enabled.</description>
22126 <description>Pull-up. Pull-up resistor enabled.</description>
22131 <description>Repeater. Repeater mode.</description>
22138 <description>Driver slew rate</description>
22145 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22150 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22157 <description>Invert polarity of input signal</description>
22164 <description>Don't invert the signal.</description>
22169 <description>Invert the signal.</description>
22176 <description>Select Digital mode</description>
22183 <description>Disable digital mode. Digital input set to 0.</description>
22188 <description>Enable Digital mode. Digital input is enabled.</description>
22195 <description>Controls open-drain mode</description>
22202 <description>Normal. Normal push-pull output</description>
22207 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22214 <description>Analog switch input control</description>
22221 <description>Analog switch is open. (disable)</description>
22226 <description>Analog switch is closed. (enable)</description>
22235 <description>Digital I/O control for port</description>
22244 <description>Signal(function) select</description>
22251 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22258 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22263 <description>Pull-down. Pull-down resistor enabled.</description>
22268 <description>Pull-up. Pull-up resistor enabled.</description>
22273 <description>Repeater. Repeater mode.</description>
22280 <description>Driver slew rate</description>
22287 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22292 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22299 <description>Invert polarity of input signal</description>
22306 <description>Don't invert the signal.</description>
22311 <description>Invert the signal.</description>
22318 <description>Select Digital mode</description>
22325 <description>Disable digital mode. Digital input set to 0.</description>
22330 <description>Enable Digital mode. Digital input is enabled.</description>
22337 <description>Controls open-drain mode</description>
22344 <description>Normal. Normal push-pull output</description>
22349 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22358 <description>Digital I/O control for port</description>
22367 <description>Signal(function) select</description>
22374 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22381 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22386 <description>Pull-down. Pull-down resistor enabled.</description>
22391 <description>Pull-up. Pull-up resistor enabled.</description>
22396 <description>Repeater. Repeater mode.</description>
22403 <description>Driver slew rate</description>
22410 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22415 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22422 <description>Invert polarity of input signal</description>
22429 <description>Don't invert the signal.</description>
22434 <description>Invert the signal.</description>
22441 <description>Select Digital mode</description>
22448 <description>Disable digital mode. Digital input set to 0.</description>
22453 <description>Enable Digital mode. Digital input is enabled.</description>
22460 <description>Controls open-drain mode</description>
22467 <description>Normal. Normal push-pull output</description>
22472 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22481 <description>Digital I/O control for port</description>
22490 <description>Signal(function) select</description>
22497 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22504 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22509 <description>Pull-down. Pull-down resistor enabled.</description>
22514 <description>Pull-up. Pull-up resistor enabled.</description>
22519 <description>Repeater. Repeater mode.</description>
22526 <description>Driver slew rate</description>
22533 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22538 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22545 <description>Invert polarity of input signal</description>
22552 <description>Don't invert the signal.</description>
22557 <description>Invert the signal.</description>
22564 <description>Select Digital mode</description>
22571 <description>Disable digital mode. Digital input set to 0.</description>
22576 <description>Enable Digital mode. Digital input is enabled.</description>
22583 <description>Controls open-drain mode</description>
22590 <description>Normal. Normal push-pull output</description>
22595 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22604 <description>Digital I/O control for port</description>
22613 <description>Signal(function) select</description>
22620 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22627 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22632 <description>Pull-down. Pull-down resistor enabled.</description>
22637 <description>Pull-up. Pull-up resistor enabled.</description>
22642 <description>Repeater. Repeater mode.</description>
22649 <description>Driver slew rate</description>
22656 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22661 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22668 <description>Invert polarity of input signal</description>
22675 <description>Don't invert the signal.</description>
22680 <description>Invert the signal.</description>
22687 <description>Select Digital mode</description>
22694 <description>Disable digital mode. Digital input set to 0.</description>
22699 <description>Enable Digital mode. Digital input is enabled.</description>
22706 <description>Controls open-drain mode</description>
22713 <description>Normal. Normal push-pull output</description>
22718 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22727 <description>Digital I/O control for port</description>
22736 <description>Signal(function) select</description>
22743 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22750 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22755 <description>Pull-down. Pull-down resistor enabled.</description>
22760 <description>Pull-up. Pull-up resistor enabled.</description>
22765 <description>Repeater. Repeater mode.</description>
22772 <description>Driver slew rate</description>
22779 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22784 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22791 <description>Invert polarity of input signal</description>
22798 <description>Don't invert the signal.</description>
22803 <description>Invert the signal.</description>
22810 <description>Select Digital mode</description>
22817 <description>Disable digital mode. Digital input set to 0.</description>
22822 <description>Enable Digital mode. Digital input is enabled.</description>
22829 <description>Controls open-drain mode</description>
22836 <description>Normal. Normal push-pull output</description>
22841 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22850 <description>Analog/Digital I/O control for port</description>
22859 <description>Signal(function) select</description>
22866 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
22873 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
22878 <description>Pull-down. Pull-down resistor enabled.</description>
22883 <description>Pull-up. Pull-up resistor enabled.</description>
22888 <description>Repeater. Repeater mode.</description>
22895 <description>Driver slew rate</description>
22902 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
22907 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
22914 <description>Invert polarity of input signal</description>
22921 <description>Don't invert the signal.</description>
22926 <description>Invert the signal.</description>
22933 <description>Select Digital mode</description>
22940 <description>Disable digital mode. Digital input set to 0.</description>
22945 <description>Enable Digital mode. Digital input is enabled.</description>
22952 <description>Controls open-drain mode</description>
22959 <description>Normal. Normal push-pull output</description>
22964 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
22971 <description>Analog switch input control</description>
22978 <description>Analog switch is open. (disable)</description>
22983 <description>Analog switch is closed. (enable)</description>
22992 <description>Digital I/O control for port</description>
23001 <description>Signal(function) select</description>
23008 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23015 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23020 <description>Pull-down. Pull-down resistor enabled.</description>
23025 <description>Pull-up. Pull-up resistor enabled.</description>
23030 <description>Repeater. Repeater mode.</description>
23037 <description>Driver slew rate</description>
23044 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23049 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23056 <description>Invert polarity of input signal</description>
23063 <description>Don't invert the signal.</description>
23068 <description>Invert the signal.</description>
23075 <description>Select Digital mode</description>
23082 <description>Disable digital mode. Digital input set to 0.</description>
23087 <description>Enable Digital mode. Digital input is enabled.</description>
23094 <description>Controls open-drain mode</description>
23101 <description>Normal. Normal push-pull output</description>
23106 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23115 <description>Analog/Digital I/O control for port</description>
23124 <description>Signal(function) select</description>
23131 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23138 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23143 <description>Pull-down. Pull-down resistor enabled.</description>
23148 <description>Pull-up. Pull-up resistor enabled.</description>
23153 <description>Repeater. Repeater mode.</description>
23160 <description>Driver slew rate</description>
23167 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23172 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23179 <description>Invert polarity of input signal</description>
23186 <description>Don't invert the signal.</description>
23191 <description>Invert the signal.</description>
23198 <description>Select Digital mode</description>
23205 <description>Disable digital mode. Digital input set to 0.</description>
23210 <description>Enable Digital mode. Digital input is enabled.</description>
23217 <description>Controls open-drain mode</description>
23224 <description>Normal. Normal push-pull output</description>
23229 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23238 <description>Digital I/O control for port</description>
23247 <description>Signal(function) select</description>
23254 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23261 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23266 <description>Pull-down. Pull-down resistor enabled.</description>
23271 <description>Pull-up. Pull-up resistor enabled.</description>
23276 <description>Repeater. Repeater mode.</description>
23283 <description>Driver slew rate</description>
23290 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23295 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23302 <description>Invert polarity of input signal</description>
23309 <description>Don't invert the signal.</description>
23314 <description>Invert the signal.</description>
23321 <description>Select Digital mode</description>
23328 <description>Disable digital mode. Digital input set to 0.</description>
23333 <description>Enable Digital mode. Digital input is enabled.</description>
23340 <description>Controls open-drain mode</description>
23347 <description>Normal. Normal push-pull output</description>
23352 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23361 <description>Analog/Digital I/O control for port</description>
23370 <description>Signal(function) select</description>
23377 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23384 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23389 <description>Pull-down. Pull-down resistor enabled.</description>
23394 <description>Pull-up. Pull-up resistor enabled.</description>
23399 <description>Repeater. Repeater mode.</description>
23406 <description>Driver slew rate</description>
23413 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23418 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23425 <description>Invert polarity of input signal</description>
23432 <description>Don't invert the signal.</description>
23437 <description>Invert the signal.</description>
23444 <description>Select Digital mode</description>
23451 <description>Disable digital mode. Digital input set to 0.</description>
23456 <description>Enable Digital mode. Digital input is enabled.</description>
23463 <description>Controls open-drain mode</description>
23470 <description>Normal. Normal push-pull output</description>
23475 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23482 <description>Analog switch input control</description>
23489 <description>Analog switch is open. (disable)</description>
23494 <description>Analog switch is closed. (enable)</description>
23503 <description>Analog/Digital I/O control for port</description>
23512 <description>Signal(function) select</description>
23519 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23526 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23531 <description>Pull-down. Pull-down resistor enabled.</description>
23536 <description>Pull-up. Pull-up resistor enabled.</description>
23541 <description>Repeater. Repeater mode.</description>
23548 <description>Driver slew rate</description>
23555 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23560 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23567 <description>Invert polarity of input signal</description>
23574 <description>Don't invert the signal.</description>
23579 <description>Invert the signal.</description>
23586 <description>Select Digital mode</description>
23593 <description>Disable digital mode. Digital input set to 0.</description>
23598 <description>Enable Digital mode. Digital input is enabled.</description>
23605 <description>Controls open-drain mode</description>
23612 <description>Normal. Normal push-pull output</description>
23617 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23624 <description>Analog switch input control</description>
23631 <description>Analog switch is open. (disable)</description>
23636 <description>Analog switch is closed. (enable)</description>
23645 <description>Digital I/O control for port</description>
23654 <description>Signal(function) select</description>
23661 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23668 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23673 <description>Pull-down. Pull-down resistor enabled.</description>
23678 <description>Pull-up. Pull-up resistor enabled.</description>
23683 <description>Repeater. Repeater mode.</description>
23690 <description>Driver slew rate</description>
23697 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23702 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23709 <description>Invert polarity of input signal</description>
23716 <description>Don't invert the signal.</description>
23721 <description>Invert the signal.</description>
23728 <description>Select Digital mode</description>
23735 <description>Disable digital mode. Digital input set to 0.</description>
23740 <description>Enable Digital mode. Digital input is enabled.</description>
23747 <description>Controls open-drain mode</description>
23754 <description>Normal. Normal push-pull output</description>
23759 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23768 <description>Analog/Digital I/O control for port</description>
23777 <description>Signal(function) select</description>
23784 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23791 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23796 <description>Pull-down. Pull-down resistor enabled.</description>
23801 <description>Pull-up. Pull-up resistor enabled.</description>
23806 <description>Repeater. Repeater mode.</description>
23813 <description>Driver slew rate</description>
23820 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23825 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23832 <description>Invert polarity of input signal</description>
23839 <description>Don't invert the signal.</description>
23844 <description>Invert the signal.</description>
23851 <description>Select Digital mode</description>
23858 <description>Disable digital mode. Digital input set to 0.</description>
23863 <description>Enable Digital mode. Digital input is enabled.</description>
23870 <description>Controls open-drain mode</description>
23877 <description>Normal. Normal push-pull output</description>
23882 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
23889 <description>Analog switch input control</description>
23896 <description>Analog switch is open. (disable)</description>
23901 <description>Analog switch is closed. (enable)</description>
23910 <description>Analog/Digital I/O control for port</description>
23919 <description>Signal(function) select</description>
23926 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
23933 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
23938 <description>Pull-down. Pull-down resistor enabled.</description>
23943 <description>Pull-up. Pull-up resistor enabled.</description>
23948 <description>Repeater. Repeater mode.</description>
23955 <description>Driver slew rate</description>
23962 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
23967 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
23974 <description>Invert polarity of input signal</description>
23981 <description>Don't invert the signal.</description>
23986 <description>Invert the signal.</description>
23993 <description>Select Digital mode</description>
24000 <description>Disable digital mode. Digital input set to 0.</description>
24005 <description>Enable Digital mode. Digital input is enabled.</description>
24012 <description>Controls open-drain mode</description>
24019 <description>Normal. Normal push-pull output</description>
24024 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24031 <description>Analog switch input control</description>
24038 <description>Analog switch is open. (disable)</description>
24043 <description>Analog switch is closed. (enable)</description>
24052 <description>Analog/Digital I/O control for port</description>
24061 <description>Signal(function) select</description>
24068 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24075 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24080 <description>Pull-down. Pull-down resistor enabled.</description>
24085 <description>Pull-up. Pull-up resistor enabled.</description>
24090 <description>Repeater. Repeater mode.</description>
24097 <description>Driver slew rate</description>
24104 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24109 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24116 <description>Invert polarity of input signal</description>
24123 <description>Don't invert the signal.</description>
24128 <description>Invert the signal.</description>
24135 <description>Select Digital mode</description>
24142 <description>Disable digital mode. Digital input set to 0.</description>
24147 <description>Enable Digital mode. Digital input is enabled.</description>
24154 <description>Controls open-drain mode</description>
24161 <description>Normal. Normal push-pull output</description>
24166 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24173 <description>Analog switch input control</description>
24180 <description>Analog switch is open. (disable)</description>
24185 <description>Analog switch is closed. (enable)</description>
24194 <description>Digital I/O control for port</description>
24203 <description>Signal(function) select</description>
24210 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24217 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24222 <description>Pull-down. Pull-down resistor enabled.</description>
24227 <description>Pull-up. Pull-up resistor enabled.</description>
24232 <description>Repeater. Repeater mode.</description>
24239 <description>Driver slew rate</description>
24246 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24251 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24258 <description>Invert polarity of input signal</description>
24265 <description>Don't invert the signal.</description>
24270 <description>Invert the signal.</description>
24277 <description>Select Digital mode</description>
24284 <description>Disable digital mode. Digital input set to 0.</description>
24289 <description>Enable Digital mode. Digital input is enabled.</description>
24296 <description>Controls open-drain mode</description>
24303 <description>Normal. Normal push-pull output</description>
24308 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24317 <description>Digital I/O control for port</description>
24326 <description>Signal(function) select</description>
24333 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24340 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24345 <description>Pull-down. Pull-down resistor enabled.</description>
24350 <description>Pull-up. Pull-up resistor enabled.</description>
24355 <description>Repeater. Repeater mode.</description>
24362 <description>Driver slew rate</description>
24369 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24374 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24381 <description>Invert polarity of input signal</description>
24388 <description>Don't invert the signal.</description>
24393 <description>Invert the signal.</description>
24400 <description>Select Digital mode</description>
24407 <description>Disable digital mode. Digital input set to 0.</description>
24412 <description>Enable Digital mode. Digital input is enabled.</description>
24419 <description>Controls open-drain mode</description>
24426 <description>Normal. Normal push-pull output</description>
24431 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24440 <description>Digital I/O control for port</description>
24449 <description>Signal(function) select</description>
24456 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24463 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24468 <description>Pull-down. Pull-down resistor enabled.</description>
24473 <description>Pull-up. Pull-up resistor enabled.</description>
24478 <description>Repeater. Repeater mode.</description>
24485 <description>Driver slew rate</description>
24492 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24497 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24504 <description>Invert polarity of input signal</description>
24511 <description>Don't invert the signal.</description>
24516 <description>Invert the signal.</description>
24523 <description>Select Digital mode</description>
24530 <description>Disable digital mode. Digital input set to 0.</description>
24535 <description>Enable Digital mode. Digital input is enabled.</description>
24542 <description>Controls open-drain mode</description>
24549 <description>Normal. Normal push-pull output</description>
24554 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24563 <description>Digital I/O control for port</description>
24572 <description>Signal(function) select</description>
24579 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24586 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24591 <description>Pull-down. Pull-down resistor enabled.</description>
24596 <description>Pull-up. Pull-up resistor enabled.</description>
24601 <description>Repeater. Repeater mode.</description>
24608 <description>Driver slew rate</description>
24615 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24620 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24627 <description>Invert polarity of input signal</description>
24634 <description>Don't invert the signal.</description>
24639 <description>Invert the signal.</description>
24646 <description>Select Digital mode</description>
24653 <description>Disable digital mode. Digital input set to 0.</description>
24658 <description>Enable Digital mode. Digital input is enabled.</description>
24665 <description>Controls open-drain mode</description>
24672 <description>Normal. Normal push-pull output</description>
24677 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24686 <description>Analog/Digital I/O control for port</description>
24695 <description>Signal(function) select</description>
24702 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24709 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24714 <description>Pull-down. Pull-down resistor enabled.</description>
24719 <description>Pull-up. Pull-up resistor enabled.</description>
24724 <description>Repeater. Repeater mode.</description>
24731 <description>Driver slew rate</description>
24738 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24743 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24750 <description>Invert polarity of input signal</description>
24757 <description>Don't invert the signal.</description>
24762 <description>Invert the signal.</description>
24769 <description>Select Digital mode</description>
24776 <description>Disable digital mode. Digital input set to 0.</description>
24781 <description>Enable Digital mode. Digital input is enabled.</description>
24788 <description>Controls open-drain mode</description>
24795 <description>Normal. Normal push-pull output</description>
24800 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24809 <description>Analog/Digital I/O control for port</description>
24818 <description>Signal(function) select</description>
24825 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24832 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24837 <description>Pull-down. Pull-down resistor enabled.</description>
24842 <description>Pull-up. Pull-up resistor enabled.</description>
24847 <description>Repeater. Repeater mode.</description>
24854 <description>Driver slew rate</description>
24861 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
24866 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
24873 <description>Invert polarity of input signal</description>
24880 <description>Don't invert the signal.</description>
24885 <description>Invert the signal.</description>
24892 <description>Select Digital mode</description>
24899 <description>Disable digital mode. Digital input set to 0.</description>
24904 <description>Enable Digital mode. Digital input is enabled.</description>
24911 <description>Controls open-drain mode</description>
24918 <description>Normal. Normal push-pull output</description>
24923 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
24930 <description>Analog switch input control</description>
24937 <description>Analog switch is open. (disable)</description>
24942 <description>Analog switch is closed. (enable)</description>
24951 <description>Digital I/O control for port</description>
24960 <description>Signal(function) select</description>
24967 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
24974 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
24979 <description>Pull-down. Pull-down resistor enabled.</description>
24984 <description>Pull-up. Pull-up resistor enabled.</description>
24989 <description>Repeater. Repeater mode.</description>
24996 <description>Driver slew rate</description>
25003 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25008 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25015 <description>Invert polarity of input signal</description>
25022 <description>Don't invert the signal.</description>
25027 <description>Invert the signal.</description>
25034 <description>Select Digital mode</description>
25041 <description>Disable digital mode. Digital input set to 0.</description>
25046 <description>Enable Digital mode. Digital input is enabled.</description>
25053 <description>Controls open-drain mode</description>
25060 <description>Normal. Normal push-pull output</description>
25065 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25074 <description>Analog/Digital I/O control for port</description>
25083 <description>Signal(function) select</description>
25090 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25097 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25102 <description>Pull-down. Pull-down resistor enabled.</description>
25107 <description>Pull-up. Pull-up resistor enabled.</description>
25112 <description>Repeater. Repeater mode.</description>
25119 <description>Driver slew rate</description>
25126 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25131 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25138 <description>Invert polarity of input signal</description>
25145 <description>Don't invert the signal.</description>
25150 <description>Invert the signal.</description>
25157 <description>Select Digital mode</description>
25164 <description>Disable digital mode. Digital input set to 0.</description>
25169 <description>Enable Digital mode. Digital input is enabled.</description>
25176 <description>Controls open-drain mode</description>
25183 <description>Normal. Normal push-pull output</description>
25188 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25195 <description>Analog switch input control</description>
25202 <description>Analog switch is open. (disable)</description>
25207 <description>Analog switch is closed. (enable)</description>
25214 <description>Analog switch input control</description>
25221 <description>Analog switch is open. (disable)</description>
25226 <description>Analog switch is closed. (enable)</description>
25235 <description>Analog/Digital I/O control for port</description>
25244 <description>Signal(function) select</description>
25251 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25258 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25263 <description>Pull-down. Pull-down resistor enabled.</description>
25268 <description>Pull-up. Pull-up resistor enabled.</description>
25273 <description>Repeater. Repeater mode.</description>
25280 <description>Driver slew rate</description>
25287 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25292 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25299 <description>Invert polarity of input signal</description>
25306 <description>Don't invert the signal.</description>
25311 <description>Invert the signal.</description>
25318 <description>Select Digital mode</description>
25325 <description>Disable digital mode. Digital input set to 0.</description>
25330 <description>Enable Digital mode. Digital input is enabled.</description>
25337 <description>Controls open-drain mode</description>
25344 <description>Normal. Normal push-pull output</description>
25349 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25356 <description>Analog switch input control</description>
25363 <description>Analog switch is open. (disable)</description>
25368 <description>Analog switch is closed. (enable)</description>
25377 <description>Analog/Digital I/O control for port</description>
25386 <description>Signal(function) select</description>
25393 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25400 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25405 <description>Pull-down. Pull-down resistor enabled.</description>
25410 <description>Pull-up. Pull-up resistor enabled.</description>
25415 <description>Repeater. Repeater mode.</description>
25422 <description>Driver slew rate</description>
25429 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25434 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25441 <description>Invert polarity of input signal</description>
25448 <description>Don't invert the signal.</description>
25453 <description>Invert the signal.</description>
25460 <description>Select Digital mode</description>
25467 <description>Disable digital mode. Digital input set to 0.</description>
25472 <description>Enable Digital mode. Digital input is enabled.</description>
25479 <description>Controls open-drain mode</description>
25486 <description>Normal. Normal push-pull output</description>
25491 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25498 <description>Analog switch input control</description>
25505 <description>Analog switch is open. (disable)</description>
25510 <description>Analog switch is closed. (enable)</description>
25519 <description>Digital I/O control for port</description>
25528 <description>Signal(function) select</description>
25535 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25542 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25547 <description>Pull-down. Pull-down resistor enabled.</description>
25552 <description>Pull-up. Pull-up resistor enabled.</description>
25557 <description>Repeater. Repeater mode.</description>
25564 <description>Driver slew rate</description>
25571 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25576 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25583 <description>Invert polarity of input signal</description>
25590 <description>Don't invert the signal.</description>
25595 <description>Invert the signal.</description>
25602 <description>Select Digital mode</description>
25609 <description>Disable digital mode. Digital input set to 0.</description>
25614 <description>Enable Digital mode. Digital input is enabled.</description>
25621 <description>Controls open-drain mode</description>
25628 <description>Normal. Normal push-pull output</description>
25633 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25642 <description>Digital I/O control for port</description>
25651 <description>Signal(function) select</description>
25658 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25665 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25670 <description>Pull-down. Pull-down resistor enabled.</description>
25675 <description>Pull-up. Pull-up resistor enabled.</description>
25680 <description>Repeater. Repeater mode.</description>
25687 <description>Driver slew rate</description>
25694 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25699 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25706 <description>Invert polarity of input signal</description>
25713 <description>Don't invert the signal.</description>
25718 <description>Invert the signal.</description>
25725 <description>Select Digital mode</description>
25732 <description>Disable digital mode. Digital input set to 0.</description>
25737 <description>Enable Digital mode. Digital input is enabled.</description>
25744 <description>Controls open-drain mode</description>
25751 <description>Normal. Normal push-pull output</description>
25756 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25765 <description>Digital I/O control for port</description>
25774 <description>Signal(function) select</description>
25781 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25788 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25793 <description>Pull-down. Pull-down resistor enabled.</description>
25798 <description>Pull-up. Pull-up resistor enabled.</description>
25803 <description>Repeater. Repeater mode.</description>
25810 <description>Driver slew rate</description>
25817 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25822 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25829 <description>Invert polarity of input signal</description>
25836 <description>Don't invert the signal.</description>
25841 <description>Invert the signal.</description>
25848 <description>Select Digital mode</description>
25855 <description>Disable digital mode. Digital input set to 0.</description>
25860 <description>Enable Digital mode. Digital input is enabled.</description>
25867 <description>Controls open-drain mode</description>
25874 <description>Normal. Normal push-pull output</description>
25879 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
25888 <description>Digital I/O control for port</description>
25897 <description>Signal(function) select</description>
25904 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
25911 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
25916 <description>Pull-down. Pull-down resistor enabled.</description>
25921 <description>Pull-up. Pull-up resistor enabled.</description>
25926 <description>Repeater. Repeater mode.</description>
25933 <description>Driver slew rate</description>
25940 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
25945 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
25952 <description>Invert polarity of input signal</description>
25959 <description>Don't invert the signal.</description>
25964 <description>Invert the signal.</description>
25971 <description>Select Digital mode</description>
25978 <description>Disable digital mode. Digital input set to 0.</description>
25983 <description>Enable Digital mode. Digital input is enabled.</description>
25990 <description>Controls open-drain mode</description>
25997 <description>Normal. Normal push-pull output</description>
26002 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26011 <description>Digital I/O control for port</description>
26020 <description>Signal(function) select</description>
26027 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26034 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26039 <description>Pull-down. Pull-down resistor enabled.</description>
26044 <description>Pull-up. Pull-up resistor enabled.</description>
26049 <description>Repeater. Repeater mode.</description>
26056 <description>Driver slew rate</description>
26063 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26068 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26075 <description>Invert polarity of input signal</description>
26082 <description>Don't invert the signal.</description>
26087 <description>Invert the signal.</description>
26094 <description>Select Digital mode</description>
26101 <description>Disable digital mode. Digital input set to 0.</description>
26106 <description>Enable Digital mode. Digital input is enabled.</description>
26113 <description>Controls open-drain mode</description>
26120 <description>Normal. Normal push-pull output</description>
26125 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26134 <description>Digital I/O control for port</description>
26143 <description>Signal(function) select</description>
26150 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26157 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26162 <description>Pull-down. Pull-down resistor enabled.</description>
26167 <description>Pull-up. Pull-up resistor enabled.</description>
26172 <description>Repeater. Repeater mode.</description>
26179 <description>Driver slew rate</description>
26186 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26191 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26198 <description>Invert polarity of input signal</description>
26205 <description>Don't invert the signal.</description>
26210 <description>Invert the signal.</description>
26217 <description>Select Digital mode</description>
26224 <description>Disable digital mode. Digital input set to 0.</description>
26229 <description>Enable Digital mode. Digital input is enabled.</description>
26236 <description>Controls open-drain mode</description>
26243 <description>Normal. Normal push-pull output</description>
26248 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26257 <description>Digital I/O control for port</description>
26266 <description>Signal(function) select</description>
26273 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26280 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26285 <description>Pull-down. Pull-down resistor enabled.</description>
26290 <description>Pull-up. Pull-up resistor enabled.</description>
26295 <description>Repeater. Repeater mode.</description>
26302 <description>Driver slew rate</description>
26309 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26314 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26321 <description>Invert polarity of input signal</description>
26328 <description>Don't invert the signal.</description>
26333 <description>Invert the signal.</description>
26340 <description>Select Digital mode</description>
26347 <description>Disable digital mode. Digital input set to 0.</description>
26352 <description>Enable Digital mode. Digital input is enabled.</description>
26359 <description>Controls open-drain mode</description>
26366 <description>Normal. Normal push-pull output</description>
26371 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26380 <description>Analog/Digital I/O control for port</description>
26389 <description>Signal(function) select</description>
26396 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26403 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26408 <description>Pull-down. Pull-down resistor enabled.</description>
26413 <description>Pull-up. Pull-up resistor enabled.</description>
26418 <description>Repeater. Repeater mode.</description>
26425 <description>Driver slew rate</description>
26432 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26437 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26444 <description>Invert polarity of input signal</description>
26451 <description>Don't invert the signal.</description>
26456 <description>Invert the signal.</description>
26463 <description>Select Digital mode</description>
26470 <description>Disable digital mode. Digital input set to 0.</description>
26475 <description>Enable Digital mode. Digital input is enabled.</description>
26482 <description>Controls open-drain mode</description>
26489 <description>Normal. Normal push-pull output</description>
26494 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26501 <description>Analog switch input control</description>
26508 <description>Analog switch is open. (disable)</description>
26513 <description>Analog switch is closed. (enable)</description>
26522 <description>Analog/Digital I/O control for port</description>
26531 <description>Signal(function) select</description>
26538 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26545 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26550 <description>Pull-down. Pull-down resistor enabled.</description>
26555 <description>Pull-up. Pull-up resistor enabled.</description>
26560 <description>Repeater. Repeater mode.</description>
26567 <description>Driver slew rate</description>
26574 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26579 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26586 <description>Invert polarity of input signal</description>
26593 <description>Don't invert the signal.</description>
26598 <description>Invert the signal.</description>
26605 <description>Select Digital mode</description>
26612 <description>Disable digital mode. Digital input set to 0.</description>
26617 <description>Enable Digital mode. Digital input is enabled.</description>
26624 <description>Controls open-drain mode</description>
26631 <description>Normal. Normal push-pull output</description>
26636 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26645 <description>Analog/Digital I/O control for port</description>
26654 <description>Signal(function) select</description>
26661 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26668 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26673 <description>Pull-down. Pull-down resistor enabled.</description>
26678 <description>Pull-up. Pull-up resistor enabled.</description>
26683 <description>Repeater. Repeater mode.</description>
26690 <description>Driver slew rate</description>
26697 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26702 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26709 <description>Invert polarity of input signal</description>
26716 <description>Don't invert the signal.</description>
26721 <description>Invert the signal.</description>
26728 <description>Select Digital mode</description>
26735 <description>Disable digital mode. Digital input set to 0.</description>
26740 <description>Enable Digital mode. Digital input is enabled.</description>
26747 <description>Controls open-drain mode</description>
26754 <description>Normal. Normal push-pull output</description>
26759 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26766 <description>Analog switch input control</description>
26773 <description>Analog switch is open. (disable)</description>
26778 <description>Analog switch is closed. (enable)</description>
26787 <description>Digital I/O control for port</description>
26796 <description>Signal(function) select</description>
26803 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26810 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26815 <description>Pull-down. Pull-down resistor enabled.</description>
26820 <description>Pull-up. Pull-up resistor enabled.</description>
26825 <description>Repeater. Repeater mode.</description>
26832 <description>Driver slew rate</description>
26839 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26844 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26851 <description>Invert polarity of input signal</description>
26858 <description>Don't invert the signal.</description>
26863 <description>Invert the signal.</description>
26870 <description>Select Digital mode</description>
26877 <description>Disable digital mode. Digital input set to 0.</description>
26882 <description>Enable Digital mode. Digital input is enabled.</description>
26889 <description>Controls open-drain mode</description>
26896 <description>Normal. Normal push-pull output</description>
26901 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
26910 <description>Analog/Digital I/O control for port</description>
26919 <description>Signal(function) select</description>
26926 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
26933 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
26938 <description>Pull-down. Pull-down resistor enabled.</description>
26943 <description>Pull-up. Pull-up resistor enabled.</description>
26948 <description>Repeater. Repeater mode.</description>
26955 <description>Driver slew rate</description>
26962 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
26967 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
26974 <description>Invert polarity of input signal</description>
26981 <description>Don't invert the signal.</description>
26986 <description>Invert the signal.</description>
26993 <description>Select Digital mode</description>
27000 <description>Disable digital mode. Digital input set to 0.</description>
27005 <description>Enable Digital mode. Digital input is enabled.</description>
27012 <description>Controls open-drain mode</description>
27019 <description>Normal. Normal push-pull output</description>
27024 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27033 <description>Analog/Digital I/O control for port</description>
27042 <description>Signal(function) select</description>
27049 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27056 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27061 <description>Pull-down. Pull-down resistor enabled.</description>
27066 <description>Pull-up. Pull-up resistor enabled.</description>
27071 <description>Repeater. Repeater mode.</description>
27078 <description>Driver slew rate</description>
27085 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27090 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27097 <description>Invert polarity of input signal</description>
27104 <description>Don't invert the signal.</description>
27109 <description>Invert the signal.</description>
27116 <description>Select Digital mode</description>
27123 <description>Disable digital mode. Digital input set to 0.</description>
27128 <description>Enable Digital mode. Digital input is enabled.</description>
27135 <description>Controls open-drain mode</description>
27142 <description>Normal. Normal push-pull output</description>
27147 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27154 <description>Analog switch input control</description>
27161 <description>Analog switch is open. (disable)</description>
27166 <description>Analog switch is closed. (enable)</description>
27175 <description>Analog/Digital I/O control for port</description>
27184 <description>Signal(function) select</description>
27191 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27198 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27203 <description>Pull-down. Pull-down resistor enabled.</description>
27208 <description>Pull-up. Pull-up resistor enabled.</description>
27213 <description>Repeater. Repeater mode.</description>
27220 <description>Driver slew rate</description>
27227 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27232 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27239 <description>Invert polarity of input signal</description>
27246 <description>Don't invert the signal.</description>
27251 <description>Invert the signal.</description>
27258 <description>Select Digital mode</description>
27265 <description>Disable digital mode. Digital input set to 0.</description>
27270 <description>Enable Digital mode. Digital input is enabled.</description>
27277 <description>Controls open-drain mode</description>
27284 <description>Normal. Normal push-pull output</description>
27289 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27296 <description>Analog switch input control</description>
27303 <description>Analog switch is open. (disable)</description>
27308 <description>Analog switch is closed. (enable)</description>
27317 <description>Digital I/O control for port</description>
27326 <description>Signal(function) select</description>
27333 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27340 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27345 <description>Pull-down. Pull-down resistor enabled.</description>
27350 <description>Pull-up. Pull-up resistor enabled.</description>
27355 <description>Repeater. Repeater mode.</description>
27362 <description>Driver slew rate</description>
27369 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27374 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27381 <description>Invert polarity of input signal</description>
27388 <description>Don't invert the signal.</description>
27393 <description>Invert the signal.</description>
27400 <description>Select Digital mode</description>
27407 <description>Disable digital mode. Digital input set to 0.</description>
27412 <description>Enable Digital mode. Digital input is enabled.</description>
27419 <description>Controls open-drain mode</description>
27426 <description>Normal. Normal push-pull output</description>
27431 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27440 <description>Analog/Digital I/O control for port</description>
27449 <description>Signal(function) select</description>
27456 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27463 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27468 <description>Pull-down. Pull-down resistor enabled.</description>
27473 <description>Pull-up. Pull-up resistor enabled.</description>
27478 <description>Repeater. Repeater mode.</description>
27485 <description>Driver slew rate</description>
27492 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27497 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27504 <description>Invert polarity of input signal</description>
27511 <description>Don't invert the signal.</description>
27516 <description>Invert the signal.</description>
27523 <description>Select Digital mode</description>
27530 <description>Disable digital mode. Digital input set to 0.</description>
27535 <description>Enable Digital mode. Digital input is enabled.</description>
27542 <description>Controls open-drain mode</description>
27549 <description>Normal. Normal push-pull output</description>
27554 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27561 <description>Analog switch input control</description>
27568 <description>Analog switch is open. (disable)</description>
27573 <description>Analog switch is closed. (enable)</description>
27582 <description>Digital I/O control for port</description>
27591 <description>Signal(function) select</description>
27598 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27605 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27610 <description>Pull-down. Pull-down resistor enabled.</description>
27615 <description>Pull-up. Pull-up resistor enabled.</description>
27620 <description>Repeater. Repeater mode.</description>
27627 <description>Driver slew rate</description>
27634 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27639 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27646 <description>Invert polarity of input signal</description>
27653 <description>Don't invert the signal.</description>
27658 <description>Invert the signal.</description>
27665 <description>Select Digital mode</description>
27672 <description>Disable digital mode. Digital input set to 0.</description>
27677 <description>Enable Digital mode. Digital input is enabled.</description>
27684 <description>Controls open-drain mode</description>
27691 <description>Normal. Normal push-pull output</description>
27696 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27705 <description>Digital I/O control for port</description>
27714 <description>Signal(function) select</description>
27721 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27728 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27733 <description>Pull-down. Pull-down resistor enabled.</description>
27738 <description>Pull-up. Pull-up resistor enabled.</description>
27743 <description>Repeater. Repeater mode.</description>
27750 <description>Driver slew rate</description>
27757 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27762 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27769 <description>Invert polarity of input signal</description>
27776 <description>Don't invert the signal.</description>
27781 <description>Invert the signal.</description>
27788 <description>Select Digital mode</description>
27795 <description>Disable digital mode. Digital input set to 0.</description>
27800 <description>Enable Digital mode. Digital input is enabled.</description>
27807 <description>Controls open-drain mode</description>
27814 <description>Normal. Normal push-pull output</description>
27819 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27828 <description>Analog/Digital I/O control for port</description>
27837 <description>Signal(function) select</description>
27844 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27851 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27856 <description>Pull-down. Pull-down resistor enabled.</description>
27861 <description>Pull-up. Pull-up resistor enabled.</description>
27866 <description>Repeater. Repeater mode.</description>
27873 <description>Driver slew rate</description>
27880 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
27885 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
27892 <description>Invert polarity of input signal</description>
27899 <description>Don't invert the signal.</description>
27904 <description>Invert the signal.</description>
27911 <description>Select Digital mode</description>
27918 <description>Disable digital mode. Digital input set to 0.</description>
27923 <description>Enable Digital mode. Digital input is enabled.</description>
27930 <description>Controls open-drain mode</description>
27937 <description>Normal. Normal push-pull output</description>
27942 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
27949 <description>Analog switch input control</description>
27956 <description>Analog switch is open. (disable)</description>
27961 <description>Analog switch is closed. (enable)</description>
27970 <description>Analog/Digital I/O control for port</description>
27979 <description>Signal(function) select</description>
27986 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
27993 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
27998 <description>Pull-down. Pull-down resistor enabled.</description>
28003 <description>Pull-up. Pull-up resistor enabled.</description>
28008 <description>Repeater. Repeater mode.</description>
28015 <description>Driver slew rate</description>
28022 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28027 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28034 <description>Invert polarity of input signal</description>
28041 <description>Don't invert the signal.</description>
28046 <description>Invert the signal.</description>
28053 <description>Select Digital mode</description>
28060 <description>Disable digital mode. Digital input set to 0.</description>
28065 <description>Enable Digital mode. Digital input is enabled.</description>
28072 <description>Controls open-drain mode</description>
28079 <description>Normal. Normal push-pull output</description>
28084 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28091 <description>Analog switch input control</description>
28098 <description>Analog switch is open. (disable)</description>
28103 <description>Analog switch is closed. (enable)</description>
28112 <description>Analog/Digital I/O control for port</description>
28121 <description>Signal(function) select</description>
28128 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28135 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28140 <description>Pull-down. Pull-down resistor enabled.</description>
28145 <description>Pull-up. Pull-up resistor enabled.</description>
28150 <description>Repeater. Repeater mode.</description>
28157 <description>Driver slew rate</description>
28164 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28169 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28176 <description>Invert polarity of input signal</description>
28183 <description>Don't invert the signal.</description>
28188 <description>Invert the signal.</description>
28195 <description>Select Digital mode</description>
28202 <description>Disable digital mode. Digital input set to 0.</description>
28207 <description>Enable Digital mode. Digital input is enabled.</description>
28214 <description>Controls open-drain mode</description>
28221 <description>Normal. Normal push-pull output</description>
28226 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28233 <description>Analog switch input control</description>
28240 <description>Analog switch is open. (disable)</description>
28245 <description>Analog switch is closed. (enable)</description>
28254 <description>Analog/Digital I/O control for port</description>
28263 <description>Signal(function) select</description>
28270 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28277 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28282 <description>Pull-down. Pull-down resistor enabled.</description>
28287 <description>Pull-up. Pull-up resistor enabled.</description>
28292 <description>Repeater. Repeater mode.</description>
28299 <description>Driver slew rate</description>
28306 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28311 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28318 <description>Invert polarity of input signal</description>
28325 <description>Don't invert the signal.</description>
28330 <description>Invert the signal.</description>
28337 <description>Select Digital mode</description>
28344 <description>Disable digital mode. Digital input set to 0.</description>
28349 <description>Enable Digital mode. Digital input is enabled.</description>
28356 <description>Controls open-drain mode</description>
28363 <description>Normal. Normal push-pull output</description>
28368 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28375 <description>Analog switch input control</description>
28382 <description>Analog switch is open. (disable)</description>
28387 <description>Analog switch is closed. (enable)</description>
28396 <description>Digital I/O control for port</description>
28405 <description>Signal(function) select</description>
28412 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28419 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28424 <description>Pull-down. Pull-down resistor enabled.</description>
28429 <description>Pull-up. Pull-up resistor enabled.</description>
28434 <description>Repeater. Repeater mode.</description>
28441 <description>Driver slew rate</description>
28448 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28453 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28460 <description>Invert polarity of input signal</description>
28467 <description>Don't invert the signal.</description>
28472 <description>Invert the signal.</description>
28479 <description>Select Digital mode</description>
28486 <description>Disable digital mode. Digital input set to 0.</description>
28491 <description>Enable Digital mode. Digital input is enabled.</description>
28498 <description>Controls open-drain mode</description>
28505 <description>Normal. Normal push-pull output</description>
28510 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28519 <description>Digital I/O control for port</description>
28528 <description>Signal(function) select</description>
28535 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28542 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28547 <description>Pull-down. Pull-down resistor enabled.</description>
28552 <description>Pull-up. Pull-up resistor enabled.</description>
28557 <description>Repeater. Repeater mode.</description>
28564 <description>Driver slew rate</description>
28571 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28576 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28583 <description>Invert polarity of input signal</description>
28590 <description>Don't invert the signal.</description>
28595 <description>Invert the signal.</description>
28602 <description>Select Digital mode</description>
28609 <description>Disable digital mode. Digital input set to 0.</description>
28614 <description>Enable Digital mode. Digital input is enabled.</description>
28621 <description>Controls open-drain mode</description>
28628 <description>Normal. Normal push-pull output</description>
28633 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28642 <description>Digital I/O control for port</description>
28651 <description>Signal(function) select</description>
28658 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28665 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28670 <description>Pull-down. Pull-down resistor enabled.</description>
28675 <description>Pull-up. Pull-up resistor enabled.</description>
28680 <description>Repeater. Repeater mode.</description>
28687 <description>Driver slew rate</description>
28694 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28699 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28706 <description>Invert polarity of input signal</description>
28713 <description>Don't invert the signal.</description>
28718 <description>Invert the signal.</description>
28725 <description>Select Digital mode</description>
28732 <description>Disable digital mode. Digital input set to 0.</description>
28737 <description>Enable Digital mode. Digital input is enabled.</description>
28744 <description>Controls open-drain mode</description>
28751 <description>Normal. Normal push-pull output</description>
28756 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28765 <description>Digital I/O control for port</description>
28774 <description>Signal(function) select</description>
28781 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28788 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28793 <description>Pull-down. Pull-down resistor enabled.</description>
28798 <description>Pull-up. Pull-up resistor enabled.</description>
28803 <description>Repeater. Repeater mode.</description>
28810 <description>Driver slew rate</description>
28817 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28822 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28829 <description>Invert polarity of input signal</description>
28836 <description>Don't invert the signal.</description>
28841 <description>Invert the signal.</description>
28848 <description>Select Digital mode</description>
28855 <description>Disable digital mode. Digital input set to 0.</description>
28860 <description>Enable Digital mode. Digital input is enabled.</description>
28867 <description>Controls open-drain mode</description>
28874 <description>Normal. Normal push-pull output</description>
28879 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
28888 <description>Analog/Digital I/O control for port</description>
28897 <description>Signal(function) select</description>
28904 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
28911 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
28916 <description>Pull-down. Pull-down resistor enabled.</description>
28921 <description>Pull-up. Pull-up resistor enabled.</description>
28926 <description>Repeater. Repeater mode.</description>
28933 <description>Driver slew rate</description>
28940 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
28945 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
28952 <description>Invert polarity of input signal</description>
28959 <description>Don't invert the signal.</description>
28964 <description>Invert the signal.</description>
28971 <description>Select Digital mode</description>
28978 <description>Disable digital mode. Digital input set to 0.</description>
28983 <description>Enable Digital mode. Digital input is enabled.</description>
28990 <description>Controls open-drain mode</description>
28997 <description>Normal. Normal push-pull output</description>
29002 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29009 <description>Analog switch input control</description>
29016 <description>Analog switch is open. (disable)</description>
29021 <description>Analog switch is closed. (enable)</description>
29030 <description>Analog/Digital I/O control for port</description>
29039 <description>Signal(function) select</description>
29046 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29053 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29058 <description>Pull-down. Pull-down resistor enabled.</description>
29063 <description>Pull-up. Pull-up resistor enabled.</description>
29068 <description>Repeater. Repeater mode.</description>
29075 <description>Driver slew rate</description>
29082 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29087 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29094 <description>Invert polarity of input signal</description>
29101 <description>Don't invert the signal.</description>
29106 <description>Invert the signal.</description>
29113 <description>Select Digital mode</description>
29120 <description>Disable digital mode. Digital input set to 0.</description>
29125 <description>Enable Digital mode. Digital input is enabled.</description>
29132 <description>Controls open-drain mode</description>
29139 <description>Normal. Normal push-pull output</description>
29144 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29151 <description>Analog switch input control</description>
29158 <description>Analog switch is open. (disable)</description>
29163 <description>Analog switch is closed. (enable)</description>
29172 <description>Digital I/O control for port</description>
29181 <description>Signal(function) select</description>
29188 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29195 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29200 <description>Pull-down. Pull-down resistor enabled.</description>
29205 <description>Pull-up. Pull-up resistor enabled.</description>
29210 <description>Repeater. Repeater mode.</description>
29217 <description>Driver slew rate</description>
29224 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29229 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29236 <description>Invert polarity of input signal</description>
29243 <description>Don't invert the signal.</description>
29248 <description>Invert the signal.</description>
29255 <description>Select Digital mode</description>
29262 <description>Disable digital mode. Digital input set to 0.</description>
29267 <description>Enable Digital mode. Digital input is enabled.</description>
29274 <description>Controls open-drain mode</description>
29281 <description>Normal. Normal push-pull output</description>
29286 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29295 <description>Digital I/O control for port</description>
29304 <description>Signal(function) select</description>
29311 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29318 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29323 <description>Pull-down. Pull-down resistor enabled.</description>
29328 <description>Pull-up. Pull-up resistor enabled.</description>
29333 <description>Repeater. Repeater mode.</description>
29340 <description>Driver slew rate</description>
29347 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29352 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29359 <description>Invert polarity of input signal</description>
29366 <description>Don't invert the signal.</description>
29371 <description>Invert the signal.</description>
29378 <description>Select Digital mode</description>
29385 <description>Disable digital mode. Digital input set to 0.</description>
29390 <description>Enable Digital mode. Digital input is enabled.</description>
29397 <description>Controls open-drain mode</description>
29404 <description>Normal. Normal push-pull output</description>
29409 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29418 <description>Analog/Digital I/O control for port</description>
29427 <description>Signal(function) select</description>
29434 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29441 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29446 <description>Pull-down. Pull-down resistor enabled.</description>
29451 <description>Pull-up. Pull-up resistor enabled.</description>
29456 <description>Repeater. Repeater mode.</description>
29463 <description>Driver slew rate</description>
29470 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29475 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29482 <description>Invert polarity of input signal</description>
29489 <description>Don't invert the signal.</description>
29494 <description>Invert the signal.</description>
29501 <description>Select Digital mode</description>
29508 <description>Disable digital mode. Digital input set to 0.</description>
29513 <description>Enable Digital mode. Digital input is enabled.</description>
29520 <description>Controls open-drain mode</description>
29527 <description>Normal. Normal push-pull output</description>
29532 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29539 <description>Analog switch input control</description>
29546 <description>Analog switch is open. (disable)</description>
29551 <description>Analog switch is closed. (enable)</description>
29560 <description>Analog/Digital I/O control for port</description>
29569 <description>Signal(function) select</description>
29576 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29583 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29588 <description>Pull-down. Pull-down resistor enabled.</description>
29593 <description>Pull-up. Pull-up resistor enabled.</description>
29598 <description>Repeater. Repeater mode.</description>
29605 <description>Driver slew rate</description>
29612 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29617 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29624 <description>Invert polarity of input signal</description>
29631 <description>Don't invert the signal.</description>
29636 <description>Invert the signal.</description>
29643 <description>Select Digital mode</description>
29650 <description>Disable digital mode. Digital input set to 0.</description>
29655 <description>Enable Digital mode. Digital input is enabled.</description>
29662 <description>Controls open-drain mode</description>
29669 <description>Normal. Normal push-pull output</description>
29674 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29681 <description>Analog switch input control</description>
29688 <description>Analog switch is open. (disable)</description>
29693 <description>Analog switch is closed. (enable)</description>
29702 <description>Digital I/O control for port</description>
29711 <description>Signal(function) select</description>
29718 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29725 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29730 <description>Pull-down. Pull-down resistor enabled.</description>
29735 <description>Pull-up. Pull-up resistor enabled.</description>
29740 <description>Repeater. Repeater mode.</description>
29747 <description>Driver slew rate</description>
29754 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29759 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29766 <description>Invert polarity of input signal</description>
29773 <description>Don't invert the signal.</description>
29778 <description>Invert the signal.</description>
29785 <description>Select Digital mode</description>
29792 <description>Disable digital mode. Digital input set to 0.</description>
29797 <description>Enable Digital mode. Digital input is enabled.</description>
29804 <description>Controls open-drain mode</description>
29811 <description>Normal. Normal push-pull output</description>
29816 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29825 <description>Digital I/O control for port</description>
29834 <description>Signal(function) select</description>
29841 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29848 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29853 <description>Pull-down. Pull-down resistor enabled.</description>
29858 <description>Pull-up. Pull-up resistor enabled.</description>
29863 <description>Repeater. Repeater mode.</description>
29870 <description>Driver slew rate</description>
29877 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
29882 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
29889 <description>Invert polarity of input signal</description>
29896 <description>Don't invert the signal.</description>
29901 <description>Invert the signal.</description>
29908 <description>Select Digital mode</description>
29915 <description>Disable digital mode. Digital input set to 0.</description>
29920 <description>Enable Digital mode. Digital input is enabled.</description>
29927 <description>Controls open-drain mode</description>
29934 <description>Normal. Normal push-pull output</description>
29939 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
29948 <description>Digital I/O control for port</description>
29957 <description>Signal(function) select</description>
29964 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
29971 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
29976 <description>Pull-down. Pull-down resistor enabled.</description>
29981 <description>Pull-up. Pull-up resistor enabled.</description>
29986 <description>Repeater. Repeater mode.</description>
29993 <description>Driver slew rate</description>
30000 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30005 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30012 <description>Invert polarity of input signal</description>
30019 <description>Don't invert the signal.</description>
30024 <description>Invert the signal.</description>
30031 <description>Select Digital mode</description>
30038 <description>Disable digital mode. Digital input set to 0.</description>
30043 <description>Enable Digital mode. Digital input is enabled.</description>
30050 <description>Controls open-drain mode</description>
30057 <description>Normal. Normal push-pull output</description>
30062 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30071 <description>Digital I/O control for port</description>
30080 <description>Signal(function) select</description>
30087 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30094 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30099 <description>Pull-down. Pull-down resistor enabled.</description>
30104 <description>Pull-up. Pull-up resistor enabled.</description>
30109 <description>Repeater. Repeater mode.</description>
30116 <description>Driver slew rate</description>
30123 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30128 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30135 <description>Invert polarity of input signal</description>
30142 <description>Don't invert the signal.</description>
30147 <description>Invert the signal.</description>
30154 <description>Select Digital mode</description>
30161 <description>Disable digital mode. Digital input set to 0.</description>
30166 <description>Enable Digital mode. Digital input is enabled.</description>
30173 <description>Controls open-drain mode</description>
30180 <description>Normal. Normal push-pull output</description>
30185 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30194 <description>Digital I/O control for port</description>
30203 <description>Signal(function) select</description>
30210 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30217 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30222 <description>Pull-down. Pull-down resistor enabled.</description>
30227 <description>Pull-up. Pull-up resistor enabled.</description>
30232 <description>Repeater. Repeater mode.</description>
30239 <description>Driver slew rate</description>
30246 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30251 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30258 <description>Invert polarity of input signal</description>
30265 <description>Don't invert the signal.</description>
30270 <description>Invert the signal.</description>
30277 <description>Select Digital mode</description>
30284 <description>Disable digital mode. Digital input set to 0.</description>
30289 <description>Enable Digital mode. Digital input is enabled.</description>
30296 <description>Controls open-drain mode</description>
30303 <description>Normal. Normal push-pull output</description>
30308 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30317 <description>Digital I/O control for port</description>
30326 <description>Signal(function) select</description>
30333 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30340 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30345 <description>Pull-down. Pull-down resistor enabled.</description>
30350 <description>Pull-up. Pull-up resistor enabled.</description>
30355 <description>Repeater. Repeater mode.</description>
30362 <description>Driver slew rate</description>
30369 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30374 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30381 <description>Invert polarity of input signal</description>
30388 <description>Don't invert the signal.</description>
30393 <description>Invert the signal.</description>
30400 <description>Select Digital mode</description>
30407 <description>Disable digital mode. Digital input set to 0.</description>
30412 <description>Enable Digital mode. Digital input is enabled.</description>
30419 <description>Controls open-drain mode</description>
30426 <description>Normal. Normal push-pull output</description>
30431 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30440 <description>Digital I/O control for port</description>
30449 <description>Signal(function) select</description>
30456 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30463 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30468 <description>Pull-down. Pull-down resistor enabled.</description>
30473 <description>Pull-up. Pull-up resistor enabled.</description>
30478 <description>Repeater. Repeater mode.</description>
30485 <description>Driver slew rate</description>
30492 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30497 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30504 <description>Invert polarity of input signal</description>
30511 <description>Don't invert the signal.</description>
30516 <description>Invert the signal.</description>
30523 <description>Select Digital mode</description>
30530 <description>Disable digital mode. Digital input set to 0.</description>
30535 <description>Enable Digital mode. Digital input is enabled.</description>
30542 <description>Controls open-drain mode</description>
30549 <description>Normal. Normal push-pull output</description>
30554 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30563 <description>Digital I/O control for port</description>
30572 <description>Signal(function) select</description>
30579 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30586 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30591 <description>Pull-down. Pull-down resistor enabled.</description>
30596 <description>Pull-up. Pull-up resistor enabled.</description>
30601 <description>Repeater. Repeater mode.</description>
30608 <description>Driver slew rate</description>
30615 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30620 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30627 <description>Invert polarity of input signal</description>
30634 <description>Don't invert the signal.</description>
30639 <description>Invert the signal.</description>
30646 <description>Select Digital mode</description>
30653 <description>Disable digital mode. Digital input set to 0.</description>
30658 <description>Enable Digital mode. Digital input is enabled.</description>
30665 <description>Controls open-drain mode</description>
30672 <description>Normal. Normal push-pull output</description>
30677 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30686 <description>Digital I/O control for port</description>
30695 <description>Signal(function) select</description>
30702 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30709 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30714 <description>Pull-down. Pull-down resistor enabled.</description>
30719 <description>Pull-up. Pull-up resistor enabled.</description>
30724 <description>Repeater. Repeater mode.</description>
30731 <description>Driver slew rate</description>
30738 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30743 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30750 <description>Invert polarity of input signal</description>
30757 <description>Don't invert the signal.</description>
30762 <description>Invert the signal.</description>
30769 <description>Select Digital mode</description>
30776 <description>Disable digital mode. Digital input set to 0.</description>
30781 <description>Enable Digital mode. Digital input is enabled.</description>
30788 <description>Controls open-drain mode</description>
30795 <description>Normal. Normal push-pull output</description>
30800 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30809 <description>Digital I/O control for port</description>
30818 <description>Signal(function) select</description>
30825 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30832 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30837 <description>Pull-down. Pull-down resistor enabled.</description>
30842 <description>Pull-up. Pull-up resistor enabled.</description>
30847 <description>Repeater. Repeater mode.</description>
30854 <description>Driver slew rate</description>
30861 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30866 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30873 <description>Invert polarity of input signal</description>
30880 <description>Don't invert the signal.</description>
30885 <description>Invert the signal.</description>
30892 <description>Select Digital mode</description>
30899 <description>Disable digital mode. Digital input set to 0.</description>
30904 <description>Enable Digital mode. Digital input is enabled.</description>
30911 <description>Controls open-drain mode</description>
30918 <description>Normal. Normal push-pull output</description>
30923 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
30932 <description>Digital I/O control for port</description>
30941 <description>Signal(function) select</description>
30948 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
30955 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
30960 <description>Pull-down. Pull-down resistor enabled.</description>
30965 <description>Pull-up. Pull-up resistor enabled.</description>
30970 <description>Repeater. Repeater mode.</description>
30977 <description>Driver slew rate</description>
30984 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
30989 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
30996 <description>Invert polarity of input signal</description>
31003 <description>Don't invert the signal.</description>
31008 <description>Invert the signal.</description>
31015 <description>Select Digital mode</description>
31022 <description>Disable digital mode. Digital input set to 0.</description>
31027 <description>Enable Digital mode. Digital input is enabled.</description>
31034 <description>Controls open-drain mode</description>
31041 <description>Normal. Normal push-pull output</description>
31046 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31055 <description>Digital I/O control for port</description>
31064 <description>Signal(function) select</description>
31071 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31078 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31083 <description>Pull-down. Pull-down resistor enabled.</description>
31088 <description>Pull-up. Pull-up resistor enabled.</description>
31093 <description>Repeater. Repeater mode.</description>
31100 <description>Driver slew rate</description>
31107 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31112 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31119 <description>Invert polarity of input signal</description>
31126 <description>Don't invert the signal.</description>
31131 <description>Invert the signal.</description>
31138 <description>Select Digital mode</description>
31145 <description>Disable digital mode. Digital input set to 0.</description>
31150 <description>Enable Digital mode. Digital input is enabled.</description>
31157 <description>Controls open-drain mode</description>
31164 <description>Normal. Normal push-pull output</description>
31169 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31178 <description>Digital I/O control for port</description>
31187 <description>Signal(function) select</description>
31194 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31201 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31206 <description>Pull-down. Pull-down resistor enabled.</description>
31211 <description>Pull-up. Pull-up resistor enabled.</description>
31216 <description>Repeater. Repeater mode.</description>
31223 <description>Driver slew rate</description>
31230 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31235 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31242 <description>Invert polarity of input signal</description>
31249 <description>Don't invert the signal.</description>
31254 <description>Invert the signal.</description>
31261 <description>Select Digital mode</description>
31268 <description>Disable digital mode. Digital input set to 0.</description>
31273 <description>Enable Digital mode. Digital input is enabled.</description>
31280 <description>Controls open-drain mode</description>
31287 <description>Normal. Normal push-pull output</description>
31292 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31301 <description>Digital I/O control for port</description>
31310 <description>Signal(function) select</description>
31317 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31324 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31329 <description>Pull-down. Pull-down resistor enabled.</description>
31334 <description>Pull-up. Pull-up resistor enabled.</description>
31339 <description>Repeater. Repeater mode.</description>
31346 <description>Driver slew rate</description>
31353 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31358 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31365 <description>Invert polarity of input signal</description>
31372 <description>Don't invert the signal.</description>
31377 <description>Invert the signal.</description>
31384 <description>Select Digital mode</description>
31391 <description>Disable digital mode. Digital input set to 0.</description>
31396 <description>Enable Digital mode. Digital input is enabled.</description>
31403 <description>Controls open-drain mode</description>
31410 <description>Normal. Normal push-pull output</description>
31415 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31424 <description>Digital I/O control for port</description>
31433 <description>Signal(function) select</description>
31440 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31447 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31452 <description>Pull-down. Pull-down resistor enabled.</description>
31457 <description>Pull-up. Pull-up resistor enabled.</description>
31462 <description>Repeater. Repeater mode.</description>
31469 <description>Driver slew rate</description>
31476 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31481 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31488 <description>Invert polarity of input signal</description>
31495 <description>Don't invert the signal.</description>
31500 <description>Invert the signal.</description>
31507 <description>Select Digital mode</description>
31514 <description>Disable digital mode. Digital input set to 0.</description>
31519 <description>Enable Digital mode. Digital input is enabled.</description>
31526 <description>Controls open-drain mode</description>
31533 <description>Normal. Normal push-pull output</description>
31538 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31547 <description>Digital I/O control for port</description>
31556 <description>Signal(function) select</description>
31563 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31570 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31575 <description>Pull-down. Pull-down resistor enabled.</description>
31580 <description>Pull-up. Pull-up resistor enabled.</description>
31585 <description>Repeater. Repeater mode.</description>
31592 <description>Driver slew rate</description>
31599 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31604 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31611 <description>Invert polarity of input signal</description>
31618 <description>Don't invert the signal.</description>
31623 <description>Invert the signal.</description>
31630 <description>Select Digital mode</description>
31637 <description>Disable digital mode. Digital input set to 0.</description>
31642 <description>Enable Digital mode. Digital input is enabled.</description>
31649 <description>Controls open-drain mode</description>
31656 <description>Normal. Normal push-pull output</description>
31661 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31670 <description>Digital I/O control for port</description>
31679 <description>Signal(function) select</description>
31686 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31693 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31698 <description>Pull-down. Pull-down resistor enabled.</description>
31703 <description>Pull-up. Pull-up resistor enabled.</description>
31708 <description>Repeater. Repeater mode.</description>
31715 <description>Driver slew rate</description>
31722 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31727 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31734 <description>Invert polarity of input signal</description>
31741 <description>Don't invert the signal.</description>
31746 <description>Invert the signal.</description>
31753 <description>Select Digital mode</description>
31760 <description>Disable digital mode. Digital input set to 0.</description>
31765 <description>Enable Digital mode. Digital input is enabled.</description>
31772 <description>Controls open-drain mode</description>
31779 <description>Normal. Normal push-pull output</description>
31784 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31793 <description>Digital I/O control for port</description>
31802 <description>Signal(function) select</description>
31809 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31816 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31821 <description>Pull-down. Pull-down resistor enabled.</description>
31826 <description>Pull-up. Pull-up resistor enabled.</description>
31831 <description>Repeater. Repeater mode.</description>
31838 <description>Driver slew rate</description>
31845 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31850 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31857 <description>Invert polarity of input signal</description>
31864 <description>Don't invert the signal.</description>
31869 <description>Invert the signal.</description>
31876 <description>Select Digital mode</description>
31883 <description>Disable digital mode. Digital input set to 0.</description>
31888 <description>Enable Digital mode. Digital input is enabled.</description>
31895 <description>Controls open-drain mode</description>
31902 <description>Normal. Normal push-pull output</description>
31907 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
31916 <description>Digital I/O control for port</description>
31925 <description>Signal(function) select</description>
31932 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
31939 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
31944 <description>Pull-down. Pull-down resistor enabled.</description>
31949 <description>Pull-up. Pull-up resistor enabled.</description>
31954 <description>Repeater. Repeater mode.</description>
31961 <description>Driver slew rate</description>
31968 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
31973 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
31980 <description>Invert polarity of input signal</description>
31987 <description>Don't invert the signal.</description>
31992 <description>Invert the signal.</description>
31999 <description>Select Digital mode</description>
32006 <description>Disable digital mode. Digital input set to 0.</description>
32011 <description>Enable Digital mode. Digital input is enabled.</description>
32018 <description>Controls open-drain mode</description>
32025 <description>Normal. Normal push-pull output</description>
32030 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32039 <description>Digital I/O control for port</description>
32048 <description>Signal(function) select</description>
32055 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32062 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32067 <description>Pull-down. Pull-down resistor enabled.</description>
32072 <description>Pull-up. Pull-up resistor enabled.</description>
32077 <description>Repeater. Repeater mode.</description>
32084 <description>Driver slew rate</description>
32091 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32096 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32103 <description>Invert polarity of input signal</description>
32110 <description>Don't invert the signal.</description>
32115 <description>Invert the signal.</description>
32122 <description>Select Digital mode</description>
32129 <description>Disable digital mode. Digital input set to 0.</description>
32134 <description>Enable Digital mode. Digital input is enabled.</description>
32141 <description>Controls open-drain mode</description>
32148 <description>Normal. Normal push-pull output</description>
32153 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32162 <description>Digital I/O control for port</description>
32171 <description>Signal(function) select</description>
32178 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32185 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32190 <description>Pull-down. Pull-down resistor enabled.</description>
32195 <description>Pull-up. Pull-up resistor enabled.</description>
32200 <description>Repeater. Repeater mode.</description>
32207 <description>Driver slew rate</description>
32214 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32219 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32226 <description>Invert polarity of input signal</description>
32233 <description>Don't invert the signal.</description>
32238 <description>Invert the signal.</description>
32245 <description>Select Digital mode</description>
32252 <description>Disable digital mode. Digital input set to 0.</description>
32257 <description>Enable Digital mode. Digital input is enabled.</description>
32264 <description>Controls open-drain mode</description>
32271 <description>Normal. Normal push-pull output</description>
32276 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32285 <description>Digital I/O control for port</description>
32294 <description>Signal(function) select</description>
32301 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32308 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32313 <description>Pull-down. Pull-down resistor enabled.</description>
32318 <description>Pull-up. Pull-up resistor enabled.</description>
32323 <description>Repeater. Repeater mode.</description>
32330 <description>Driver slew rate</description>
32337 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32342 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32349 <description>Invert polarity of input signal</description>
32356 <description>Don't invert the signal.</description>
32361 <description>Invert the signal.</description>
32368 <description>Select Digital mode</description>
32375 <description>Disable digital mode. Digital input set to 0.</description>
32380 <description>Enable Digital mode. Digital input is enabled.</description>
32387 <description>Controls open-drain mode</description>
32394 <description>Normal. Normal push-pull output</description>
32399 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32408 <description>Digital I/O control for port</description>
32417 <description>Signal(function) select</description>
32424 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32431 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32436 <description>Pull-down. Pull-down resistor enabled.</description>
32441 <description>Pull-up. Pull-up resistor enabled.</description>
32446 <description>Repeater. Repeater mode.</description>
32453 <description>Driver slew rate</description>
32460 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32465 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32472 <description>Invert polarity of input signal</description>
32479 <description>Don't invert the signal.</description>
32484 <description>Invert the signal.</description>
32491 <description>Select Digital mode</description>
32498 <description>Disable digital mode. Digital input set to 0.</description>
32503 <description>Enable Digital mode. Digital input is enabled.</description>
32510 <description>Controls open-drain mode</description>
32517 <description>Normal. Normal push-pull output</description>
32522 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32531 <description>Digital I/O control for port</description>
32540 <description>Signal(function) select</description>
32547 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32554 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32559 <description>Pull-down. Pull-down resistor enabled.</description>
32564 <description>Pull-up. Pull-up resistor enabled.</description>
32569 <description>Repeater. Repeater mode.</description>
32576 <description>Driver slew rate</description>
32583 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32588 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32595 <description>Invert polarity of input signal</description>
32602 <description>Don't invert the signal.</description>
32607 <description>Invert the signal.</description>
32614 <description>Select Digital mode</description>
32621 <description>Disable digital mode. Digital input set to 0.</description>
32626 <description>Enable Digital mode. Digital input is enabled.</description>
32633 <description>Controls open-drain mode</description>
32640 <description>Normal. Normal push-pull output</description>
32645 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32654 <description>Digital I/O control for port</description>
32663 <description>Signal(function) select</description>
32670 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32677 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32682 <description>Pull-down. Pull-down resistor enabled.</description>
32687 <description>Pull-up. Pull-up resistor enabled.</description>
32692 <description>Repeater. Repeater mode.</description>
32699 <description>Driver slew rate</description>
32706 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32711 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32718 <description>Invert polarity of input signal</description>
32725 <description>Don't invert the signal.</description>
32730 <description>Invert the signal.</description>
32737 <description>Select Digital mode</description>
32744 <description>Disable digital mode. Digital input set to 0.</description>
32749 <description>Enable Digital mode. Digital input is enabled.</description>
32756 <description>Controls open-drain mode</description>
32763 <description>Normal. Normal push-pull output</description>
32768 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32777 <description>Digital I/O control for port</description>
32786 <description>Signal(function) select</description>
32793 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32800 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32805 <description>Pull-down. Pull-down resistor enabled.</description>
32810 <description>Pull-up. Pull-up resistor enabled.</description>
32815 <description>Repeater. Repeater mode.</description>
32822 <description>Driver slew rate</description>
32829 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32834 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32841 <description>Invert polarity of input signal</description>
32848 <description>Don't invert the signal.</description>
32853 <description>Invert the signal.</description>
32860 <description>Select Digital mode</description>
32867 <description>Disable digital mode. Digital input set to 0.</description>
32872 <description>Enable Digital mode. Digital input is enabled.</description>
32879 <description>Controls open-drain mode</description>
32886 <description>Normal. Normal push-pull output</description>
32891 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
32900 <description>Digital I/O control for port</description>
32909 <description>Signal(function) select</description>
32916 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
32923 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
32928 <description>Pull-down. Pull-down resistor enabled.</description>
32933 <description>Pull-up. Pull-up resistor enabled.</description>
32938 <description>Repeater. Repeater mode.</description>
32945 <description>Driver slew rate</description>
32952 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
32957 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
32964 <description>Invert polarity of input signal</description>
32971 <description>Don't invert the signal.</description>
32976 <description>Invert the signal.</description>
32983 <description>Select Digital mode</description>
32990 <description>Disable digital mode. Digital input set to 0.</description>
32995 <description>Enable Digital mode. Digital input is enabled.</description>
33002 <description>Controls open-drain mode</description>
33009 <description>Normal. Normal push-pull output</description>
33014 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33023 <description>Digital I/O control for port</description>
33032 <description>Signal(function) select</description>
33039 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33046 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33051 <description>Pull-down. Pull-down resistor enabled.</description>
33056 <description>Pull-up. Pull-up resistor enabled.</description>
33061 <description>Repeater. Repeater mode.</description>
33068 <description>Driver slew rate</description>
33075 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33080 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33087 <description>Invert polarity of input signal</description>
33094 <description>Don't invert the signal.</description>
33099 <description>Invert the signal.</description>
33106 <description>Select Digital mode</description>
33113 <description>Disable digital mode. Digital input set to 0.</description>
33118 <description>Enable Digital mode. Digital input is enabled.</description>
33125 <description>Controls open-drain mode</description>
33132 <description>Normal. Normal push-pull output</description>
33137 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33146 <description>Digital I/O control for port</description>
33155 <description>Signal(function) select</description>
33162 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33169 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33174 <description>Pull-down. Pull-down resistor enabled.</description>
33179 <description>Pull-up. Pull-up resistor enabled.</description>
33184 <description>Repeater. Repeater mode.</description>
33191 <description>Driver slew rate</description>
33198 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33203 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33210 <description>Invert polarity of input signal</description>
33217 <description>Don't invert the signal.</description>
33222 <description>Invert the signal.</description>
33229 <description>Select Digital mode</description>
33236 <description>Disable digital mode. Digital input set to 0.</description>
33241 <description>Enable Digital mode. Digital input is enabled.</description>
33248 <description>Controls open-drain mode</description>
33255 <description>Normal. Normal push-pull output</description>
33260 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33269 <description>Digital I/O control for port</description>
33278 <description>Signal(function) select</description>
33285 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33292 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33297 <description>Pull-down. Pull-down resistor enabled.</description>
33302 <description>Pull-up. Pull-up resistor enabled.</description>
33307 <description>Repeater. Repeater mode.</description>
33314 <description>Driver slew rate</description>
33321 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33326 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33333 <description>Invert polarity of input signal</description>
33340 <description>Don't invert the signal.</description>
33345 <description>Invert the signal.</description>
33352 <description>Select Digital mode</description>
33359 <description>Disable digital mode. Digital input set to 0.</description>
33364 <description>Enable Digital mode. Digital input is enabled.</description>
33371 <description>Controls open-drain mode</description>
33378 <description>Normal. Normal push-pull output</description>
33383 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33392 <description>Digital I/O control for port</description>
33401 <description>Signal(function) select</description>
33408 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33415 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33420 <description>Pull-down. Pull-down resistor enabled.</description>
33425 <description>Pull-up. Pull-up resistor enabled.</description>
33430 <description>Repeater. Repeater mode.</description>
33437 <description>Driver slew rate</description>
33444 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33449 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33456 <description>Invert polarity of input signal</description>
33463 <description>Don't invert the signal.</description>
33468 <description>Invert the signal.</description>
33475 <description>Select Digital mode</description>
33482 <description>Disable digital mode. Digital input set to 0.</description>
33487 <description>Enable Digital mode. Digital input is enabled.</description>
33494 <description>Controls open-drain mode</description>
33501 <description>Normal. Normal push-pull output</description>
33506 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33515 <description>Digital I/O control for port</description>
33524 <description>Signal(function) select</description>
33531 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33538 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33543 <description>Pull-down. Pull-down resistor enabled.</description>
33548 <description>Pull-up. Pull-up resistor enabled.</description>
33553 <description>Repeater. Repeater mode.</description>
33560 <description>Driver slew rate</description>
33567 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33572 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33579 <description>Invert polarity of input signal</description>
33586 <description>Don't invert the signal.</description>
33591 <description>Invert the signal.</description>
33598 <description>Select Digital mode</description>
33605 <description>Disable digital mode. Digital input set to 0.</description>
33610 <description>Enable Digital mode. Digital input is enabled.</description>
33617 <description>Controls open-drain mode</description>
33624 <description>Normal. Normal push-pull output</description>
33629 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33638 <description>Digital I/O control for port</description>
33647 <description>Signal(function) select</description>
33654 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33661 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33666 <description>Pull-down. Pull-down resistor enabled.</description>
33671 <description>Pull-up. Pull-up resistor enabled.</description>
33676 <description>Repeater. Repeater mode.</description>
33683 <description>Driver slew rate</description>
33690 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33695 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33702 <description>Invert polarity of input signal</description>
33709 <description>Don't invert the signal.</description>
33714 <description>Invert the signal.</description>
33721 <description>Select Digital mode</description>
33728 <description>Disable digital mode. Digital input set to 0.</description>
33733 <description>Enable Digital mode. Digital input is enabled.</description>
33740 <description>Controls open-drain mode</description>
33747 <description>Normal. Normal push-pull output</description>
33752 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33761 <description>Digital I/O control for port</description>
33770 <description>Signal(function) select</description>
33777 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33784 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33789 <description>Pull-down. Pull-down resistor enabled.</description>
33794 <description>Pull-up. Pull-up resistor enabled.</description>
33799 <description>Repeater. Repeater mode.</description>
33806 <description>Driver slew rate</description>
33813 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33818 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33825 <description>Invert polarity of input signal</description>
33832 <description>Don't invert the signal.</description>
33837 <description>Invert the signal.</description>
33844 <description>Select Digital mode</description>
33851 <description>Disable digital mode. Digital input set to 0.</description>
33856 <description>Enable Digital mode. Digital input is enabled.</description>
33863 <description>Controls open-drain mode</description>
33870 <description>Normal. Normal push-pull output</description>
33875 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
33884 <description>Digital I/O control for port</description>
33893 <description>Signal(function) select</description>
33900 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
33907 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
33912 <description>Pull-down. Pull-down resistor enabled.</description>
33917 <description>Pull-up. Pull-up resistor enabled.</description>
33922 <description>Repeater. Repeater mode.</description>
33929 <description>Driver slew rate</description>
33936 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
33941 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
33948 <description>Invert polarity of input signal</description>
33955 <description>Don't invert the signal.</description>
33960 <description>Invert the signal.</description>
33967 <description>Select Digital mode</description>
33974 <description>Disable digital mode. Digital input set to 0.</description>
33979 <description>Enable Digital mode. Digital input is enabled.</description>
33986 <description>Controls open-drain mode</description>
33993 <description>Normal. Normal push-pull output</description>
33998 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
34007 <description>Digital I/O control for port</description>
34016 <description>Signal(function) select</description>
34023 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
34030 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
34035 <description>Pull-down. Pull-down resistor enabled.</description>
34040 <description>Pull-up. Pull-up resistor enabled.</description>
34045 <description>Repeater. Repeater mode.</description>
34052 <description>Driver slew rate</description>
34059 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
34064 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
34071 <description>Invert polarity of input signal</description>
34078 <description>Don't invert the signal.</description>
34083 <description>Invert the signal.</description>
34090 <description>Select Digital mode</description>
34097 <description>Disable digital mode. Digital input set to 0.</description>
34102 <description>Enable Digital mode. Digital input is enabled.</description>
34109 <description>Controls open-drain mode</description>
34116 <description>Normal. Normal push-pull output</description>
34121 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
34130 <description>Digital I/O control for port</description>
34139 <description>Signal(function) select</description>
34146 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
34153 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
34158 <description>Pull-down. Pull-down resistor enabled.</description>
34163 <description>Pull-up. Pull-up resistor enabled.</description>
34168 <description>Repeater. Repeater mode.</description>
34175 <description>Driver slew rate</description>
34182 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
34187 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
34194 <description>Invert polarity of input signal</description>
34201 <description>Don't invert the signal.</description>
34206 <description>Invert the signal.</description>
34213 <description>Select Digital mode</description>
34220 <description>Disable digital mode. Digital input set to 0.</description>
34225 <description>Enable Digital mode. Digital input is enabled.</description>
34232 <description>Controls open-drain mode</description>
34239 <description>Normal. Normal push-pull output</description>
34244 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
34253 <description>Digital I/O control for port</description>
34262 <description>Signal(function) select</description>
34269 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
34276 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
34281 <description>Pull-down. Pull-down resistor enabled.</description>
34286 <description>Pull-up. Pull-up resistor enabled.</description>
34291 <description>Repeater. Repeater mode.</description>
34298 <description>Driver slew rate</description>
34305 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
34310 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
34317 <description>Invert polarity of input signal</description>
34324 <description>Don't invert the signal.</description>
34329 <description>Invert the signal.</description>
34336 <description>Select Digital mode</description>
34343 <description>Disable digital mode. Digital input set to 0.</description>
34348 <description>Enable Digital mode. Digital input is enabled.</description>
34355 <description>Controls open-drain mode</description>
34362 <description>Normal. Normal push-pull output</description>
34367 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
34376 <description>Digital I/O control for port</description>
34385 <description>Signal(function) select</description>
34392 <description>Mode select (on-chip pull-up/pull-down resistor control)</description>
34399 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
34404 <description>Pull-down. Pull-down resistor enabled.</description>
34409 <description>Pull-up. Pull-up resistor enabled.</description>
34414 <description>Repeater. Repeater mode.</description>
34421 <description>Driver slew rate</description>
34428 …<description>Standard-mode, output slew rate is slower. More outputs can be switched simultaneousl…
34433 …<description>Fast-mode, output slew rate is faster. Refer to the appropriate specific device data …
34440 <description>Invert polarity of input signal</description>
34447 <description>Don't invert the signal.</description>
34452 <description>Invert the signal.</description>
34459 <description>Select Digital mode</description>
34466 <description>Disable digital mode. Digital input set to 0.</description>
34471 <description>Enable Digital mode. Digital input is enabled.</description>
34478 <description>Controls open-drain mode</description>
34485 <description>Normal. Normal push-pull output</description>
34490 … <description>Open-drain. Simulated open-drain output (high drive disabled).</description>
34501 <description>Group GPIO input interrupt (GINT0/1)</description>
34517 <description>GPIO grouped interrupt control</description>
34526 <description>Group interrupt status</description>
34534 <description>No interrupt request is pending.</description>
34539 <description>Interrupt request is pending.</description>
34546 <description>Combine enabled inputs for group interrupt</description>
34553 <description>OR functionality</description>
34558 <description>AND functionality</description>
34565 <description>Group interrupt trigger</description>
34572 <description>Edge-triggered</description>
34577 <description>Level-triggered</description>
34588 <description>Port polarity</description>
34597 <description>Polarity of pin n of the port</description>
34604 <description>Pin is active LOW</description>
34609 <description>Pin is active HIGH</description>
34616 <description>Polarity of pin n of the port</description>
34623 <description>Pin is active LOW</description>
34628 <description>Pin is active HIGH</description>
34635 <description>Polarity of pin n of the port</description>
34642 <description>Pin is active LOW</description>
34647 <description>Pin is active HIGH</description>
34654 <description>Polarity of pin n of the port</description>
34661 <description>Pin is active LOW</description>
34666 <description>Pin is active HIGH</description>
34673 <description>Polarity of pin n of the port</description>
34680 <description>Pin is active LOW</description>
34685 <description>Pin is active HIGH</description>
34692 <description>Polarity of pin n of the port</description>
34699 <description>Pin is active LOW</description>
34704 <description>Pin is active HIGH</description>
34711 <description>Polarity of pin n of the port</description>
34718 <description>Pin is active LOW</description>
34723 <description>Pin is active HIGH</description>
34730 <description>Polarity of pin n of the port</description>
34737 <description>Pin is active LOW</description>
34742 <description>Pin is active HIGH</description>
34749 <description>Polarity of pin n of the port</description>
34756 <description>Pin is active LOW</description>
34761 <description>Pin is active HIGH</description>
34768 <description>Polarity of pin n of the port</description>
34775 <description>Pin is active LOW</description>
34780 <description>Pin is active HIGH</description>
34787 <description>Polarity of pin n of the port</description>
34794 <description>Pin is active LOW</description>
34799 <description>Pin is active HIGH</description>
34806 <description>Polarity of pin n of the port</description>
34813 <description>Pin is active LOW</description>
34818 <description>Pin is active HIGH</description>
34825 <description>Polarity of pin n of the port</description>
34832 <description>Pin is active LOW</description>
34837 <description>Pin is active HIGH</description>
34844 <description>Polarity of pin n of the port</description>
34851 <description>Pin is active LOW</description>
34856 <description>Pin is active HIGH</description>
34863 <description>Polarity of pin n of the port</description>
34870 <description>Pin is active LOW</description>
34875 <description>Pin is active HIGH</description>
34882 <description>Polarity of pin n of the port</description>
34889 <description>Pin is active LOW</description>
34894 <description>Pin is active HIGH</description>
34901 <description>Polarity of pin n of the port</description>
34908 <description>Pin is active LOW</description>
34913 <description>Pin is active HIGH</description>
34920 <description>Polarity of pin n of the port</description>
34927 <description>Pin is active LOW</description>
34932 <description>Pin is active HIGH</description>
34939 <description>Polarity of pin n of the port</description>
34946 <description>Pin is active LOW</description>
34951 <description>Pin is active HIGH</description>
34958 <description>Polarity of pin n of the port</description>
34965 <description>Pin is active LOW</description>
34970 <description>Pin is active HIGH</description>
34977 <description>Polarity of pin n of the port</description>
34984 <description>Pin is active LOW</description>
34989 <description>Pin is active HIGH</description>
34996 <description>Polarity of pin n of the port</description>
35003 <description>Pin is active LOW</description>
35008 <description>Pin is active HIGH</description>
35015 <description>Polarity of pin n of the port</description>
35022 <description>Pin is active LOW</description>
35027 <description>Pin is active HIGH</description>
35034 <description>Polarity of pin n of the port</description>
35041 <description>Pin is active LOW</description>
35046 <description>Pin is active HIGH</description>
35053 <description>Polarity of pin n of the port</description>
35060 <description>Pin is active LOW</description>
35065 <description>Pin is active HIGH</description>
35072 <description>Polarity of pin n of the port</description>
35079 <description>Pin is active LOW</description>
35084 <description>Pin is active HIGH</description>
35091 <description>Polarity of pin n of the port</description>
35098 <description>Pin is active LOW</description>
35103 <description>Pin is active HIGH</description>
35110 <description>Polarity of pin n of the port</description>
35117 <description>Pin is active LOW</description>
35122 <description>Pin is active HIGH</description>
35129 <description>Polarity of pin n of the port</description>
35136 <description>Pin is active LOW</description>
35141 <description>Pin is active HIGH</description>
35148 <description>Polarity of pin n of the port</description>
35155 <description>Pin is active LOW</description>
35160 <description>Pin is active HIGH</description>
35167 <description>Polarity of pin n of the port</description>
35174 <description>Pin is active LOW</description>
35179 <description>Pin is active HIGH</description>
35186 <description>Polarity of pin n of the port</description>
35193 <description>Pin is active LOW</description>
35198 <description>Pin is active HIGH</description>
35209 <description>GPIO grouped interrupt port 0 enable register</description>
35218 <description>Enables port pin n to contribute to the group interrupt</description>
35225 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35230 <description>Pin is enabled and contributes to the grouped interrupt</description>
35237 <description>Enables port pin n to contribute to the group interrupt</description>
35244 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35249 <description>Pin is enabled and contributes to the grouped interrupt</description>
35256 <description>Enables port pin n to contribute to the group interrupt</description>
35263 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35268 <description>Pin is enabled and contributes to the grouped interrupt</description>
35275 <description>Enables port pin n to contribute to the group interrupt</description>
35282 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35287 <description>Pin is enabled and contributes to the grouped interrupt</description>
35294 <description>Enables port pin n to contribute to the group interrupt</description>
35301 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35306 <description>Pin is enabled and contributes to the grouped interrupt</description>
35313 <description>Enables port pin n to contribute to the group interrupt</description>
35320 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35325 <description>Pin is enabled and contributes to the grouped interrupt</description>
35332 <description>Enables port pin n to contribute to the group interrupt</description>
35339 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35344 <description>Pin is enabled and contributes to the grouped interrupt</description>
35351 <description>Enables port pin n to contribute to the group interrupt</description>
35358 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35363 <description>Pin is enabled and contributes to the grouped interrupt</description>
35370 <description>Enables port pin n to contribute to the group interrupt</description>
35377 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35382 <description>Pin is enabled and contributes to the grouped interrupt</description>
35389 <description>Enables port pin n to contribute to the group interrupt</description>
35396 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35401 <description>Pin is enabled and contributes to the grouped interrupt</description>
35408 <description>Enables port pin n to contribute to the group interrupt</description>
35415 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35420 <description>Pin is enabled and contributes to the grouped interrupt</description>
35427 <description>Enables port pin n to contribute to the group interrupt</description>
35434 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35439 <description>Pin is enabled and contributes to the grouped interrupt</description>
35446 <description>Enables port pin n to contribute to the group interrupt</description>
35453 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35458 <description>Pin is enabled and contributes to the grouped interrupt</description>
35465 <description>Enables port pin n to contribute to the group interrupt</description>
35472 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35477 <description>Pin is enabled and contributes to the grouped interrupt</description>
35484 <description>Enables port pin n to contribute to the group interrupt</description>
35491 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35496 <description>Pin is enabled and contributes to the grouped interrupt</description>
35503 <description>Enables port pin n to contribute to the group interrupt</description>
35510 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35515 <description>Pin is enabled and contributes to the grouped interrupt</description>
35522 <description>Enables port pin n to contribute to the group interrupt</description>
35529 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35534 <description>Pin is enabled and contributes to the grouped interrupt</description>
35541 <description>Enables port pin n to contribute to the group interrupt</description>
35548 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35553 <description>Pin is enabled and contributes to the grouped interrupt</description>
35560 <description>Enables port pin n to contribute to the group interrupt</description>
35567 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35572 <description>Pin is enabled and contributes to the grouped interrupt</description>
35579 <description>Enables port pin n to contribute to the group interrupt</description>
35586 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35591 <description>Pin is enabled and contributes to the grouped interrupt</description>
35598 <description>Enables port pin n to contribute to the group interrupt</description>
35605 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35610 <description>Pin is enabled and contributes to the grouped interrupt</description>
35617 <description>Enables port pin n to contribute to the group interrupt</description>
35624 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35629 <description>Pin is enabled and contributes to the grouped interrupt</description>
35636 <description>Enables port pin n to contribute to the group interrupt</description>
35643 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35648 <description>Pin is enabled and contributes to the grouped interrupt</description>
35655 <description>Enables port pin n to contribute to the group interrupt</description>
35662 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35667 <description>Pin is enabled and contributes to the grouped interrupt</description>
35674 <description>Enables port pin n to contribute to the group interrupt</description>
35681 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35686 <description>Pin is enabled and contributes to the grouped interrupt</description>
35693 <description>Enables port pin n to contribute to the group interrupt</description>
35700 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35705 <description>Pin is enabled and contributes to the grouped interrupt</description>
35712 <description>Enables port pin n to contribute to the group interrupt</description>
35719 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35724 <description>Pin is enabled and contributes to the grouped interrupt</description>
35731 <description>Enables port pin n to contribute to the group interrupt</description>
35738 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35743 <description>Pin is enabled and contributes to the grouped interrupt</description>
35750 <description>Enables port pin n to contribute to the group interrupt</description>
35757 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35762 <description>Pin is enabled and contributes to the grouped interrupt</description>
35769 <description>Enables port pin n to contribute to the group interrupt</description>
35776 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35781 <description>Pin is enabled and contributes to the grouped interrupt</description>
35788 <description>Enables port pin n to contribute to the group interrupt</description>
35795 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35800 <description>Pin is enabled and contributes to the grouped interrupt</description>
35807 <description>Enables port pin n to contribute to the group interrupt</description>
35814 … <description>Pin is disabled and does not contribute to the grouped interrupt</description>
35819 <description>Pin is enabled and contributes to the grouped interrupt</description>
35830 <description>Group GPIO input interrupt (GINT0/1)</description>
35845 <description>Pin Interrupts and Pattern Match</description>
35889 <description>Pin Interrupt Mode</description>
35898 <description>Interrupt mode</description>
35905 <description>Edge-sensitive</description>
35910 <description>Level-sensitive</description>
35919 <description>Pin Interrupt Level or Rising Edge Interrupt Enable</description>
35928 <description>Enable Interrupt</description>
35935 <description>Disable rising edge or level interrupt</description>
35940 <description>Enable rising edge or level interrupt</description>
35949 <description>Pin Interrupt Level or Rising Edge Interrupt Set</description>
35958 <description>Set bits in the IENR</description>
35966 <description>No operation</description>
35971 <description>Enable rising edge or level interrupt</description>
35980 <description>Pin Interrupt Level (Rising Edge Interrupt) Clear</description>
35989 <description>Clear bits in the IENR</description>
35997 <description>No operation</description>
36002 <description>Disable rising edge or level interrupt</description>
36011 <description>Pin Interrupt Active Level or Falling Edge Interrupt Enable</description>
36020 <description>Enable Interrupt</description>
36027 … <description>Disable falling edge interrupt or set active interrupt level LOW</description>
36032 …<description>Enable falling edge interrupt enabled or set active interrupt level HIGH</description>
36041 <description>Pin Interrupt Active Level or Falling Edge Interrupt Set</description>
36050 <description>Set bits in the IENF</description>
36058 <description>No operation</description>
36063 … <description>Select HIGH-active interrupt or enable falling edge interrupt</description>
36072 <description>Pin Interrupt Active Level or Falling Edge Interrupt Clear</description>
36081 <description>Clear bits in the IENF</description>
36088 <description>No operation</description>
36093 … <description>LOW-active interrupt selected or falling edge interrupt disabled</description>
36102 <description>Pin Interrupt Rising Edge</description>
36111 <description>Rising edge detect</description>
36118 …description>Read 0- No rising edge has been detected on this pin since Reset or the last time a on…
36123 …description>Read 1- a rising edge has been detected since Reset or the last time a one was written…
36132 <description>Pin Interrupt Falling Edge</description>
36141 <description>Falling edge detect</description>
36148 …description>Read 0- No falling edge has been detected on this pin since Reset or the last time a o…
36153 …description>Read 1- a falling edge has been detected since Reset or the last time a one was writte…
36162 <description>Pin Interrupt Status</description>
36171 <description>Pin interrupt status</description>
36178 …<description>Read 0- interrupt is not being requested for this pin, Write 0- no operation.</descri…
36183 …description>Read 1- interrupt is being requested for this pin, Write 1 (edge-sensitive)- clear ris…
36192 <description>Pattern Match Interrupt Control</description>
36201 …<description>Specifies whether the pin interrupts are controlled by the pin interrupt function or …
36208 …<description>Pin interrupt- interrupts are driven in response to the standard pin interrupt functi…
36213 … <description>Pattern match- interrupts are driven in response to pattern matches.</description>
36220 …<description>Enables the RXEV output to the CPU and/or to a GPIO output, when the specified boolea…
36227 <description>Disabled- RXEV output to the CPU is disabled.</description>
36232 <description>Enabled- RXEV output to the CPU is enabled.</description>
36239 <description>Pattern Matches</description>
36246 …<description>The corresponding product term is matched by the current state of the appropriate inp…
36255 <description>Pattern Match Interrupt Bit-Slice Source</description>
36264 <description>Selects the input source for bit slice 0</description>
36271 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36276 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36281 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36286 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36291 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36296 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36301 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36306 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36313 <description>Selects the input source for bit slice 1</description>
36320 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36325 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36330 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36335 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36340 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36345 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36350 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36355 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36362 <description>Selects the input source for bit slice 2</description>
36369 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36374 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36379 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36384 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36389 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36394 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36399 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36404 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36411 <description>Selects the input source for bit slice 3</description>
36418 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36423 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36428 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36433 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36438 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36443 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36448 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36453 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36460 <description>Selects the input source for bit slice 4</description>
36467 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36472 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36477 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36482 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36487 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36492 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36497 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36502 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36509 <description>Selects the input source for bit slice 5</description>
36516 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36521 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36526 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36531 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36536 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36541 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36546 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36551 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36558 <description>Selects the input source for bit slice 6</description>
36565 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36570 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36575 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36580 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36585 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36590 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36595 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36600 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36607 <description>Selects the input source for bit slice 7</description>
36614 …<description>Input 0. Selects the pin selected in the PINT_SEL0 register as the source to bit slic…
36619 …<description>Input 1. Selects the pin selected in the PINT_SEL1 register as the source to bit slic…
36624 …<description>Input 2. Selects the pin selected in the PINT_SEL2 register as the source to bit slic…
36629 …<description>Input 3. Selects the pin selected in the PINT_SEL3 register as the source to bit slic…
36634 …<description>Input 4. Selects the pin selected in the PINT_SEL4 register as the source to bit slic…
36639 …<description>Input 5. Selects the pin selected in the PINT_SEL5 register as the source to bit slic…
36644 …<description>Input 6. Selects the pin selected in the PINT_SEL6 register as the source to bit slic…
36649 …<description>Input 7. Selects the pin selected in the PINT_SEL7 register as the source to bit slic…
36658 <description>Pattern Match Interrupt Bit Slice Configuration</description>
36667 <description>Determines whether slice 0 is an endpoint.</description>
36674 <description>No effect. Slice 0 is not an endpoint.</description>
36679 …description>Endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the …
36686 <description>Determines whether slice 1 is an endpoint.</description>
36693 <description>No effect. Slice 1 is not an endpoint.</description>
36698 …description>Endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the …
36705 <description>Determines whether slice 2 is an endpoint.</description>
36712 <description>No effect. Slice 2 is not an endpoint.</description>
36717 …description>Endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the …
36724 <description>Determines whether slice 3 is an endpoint.</description>
36731 <description>No effect. Slice 3 is not an endpoint.</description>
36736 …description>Endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the …
36743 <description>Determines whether slice 4 is an endpoint.</description>
36750 <description>No effect. Slice 4 is not an endpoint.</description>
36755 …description>Endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the …
36762 <description>Determines whether slice 5 is an endpoint.</description>
36769 <description>No effect. Slice 5 is not an endpoint.</description>
36774 …description>Endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the …
36781 <description>Determines whether slice 6 is an endpoint.</description>
36788 <description>No effect. Slice 6 is not an endpoint.</description>
36793 …description>Endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the …
36800 <description>Specifies the match contribution condition for bit slice 0.</description>
36807 <description>Constant HIGH</description>
36812 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
36817 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
36822 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
36827 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
36832 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
36837 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
36842 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
36849 <description>Specifies the match contribution condition for bit slice 1.</description>
36856 <description>Constant HIGH</description>
36861 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
36866 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
36871 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
36876 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
36881 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
36886 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
36891 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
36898 <description>Specifies the match contribution condition for bit slice 2.</description>
36905 <description>Constant HIGH</description>
36910 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
36915 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
36920 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
36925 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
36930 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
36935 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
36940 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
36947 <description>Specifies the match contribution condition for bit slice 3.</description>
36954 <description>Constant HIGH</description>
36959 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
36964 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
36969 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
36974 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
36979 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
36984 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
36989 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
36996 <description>Specifies the match contribution condition for bit slice 4.</description>
37003 <description>Constant HIGH</description>
37008 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
37013 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
37018 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
37023 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
37028 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
37033 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
37038 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
37045 <description>Specifies the match contribution condition for bit slice 5.</description>
37052 <description>Constant HIGH</description>
37057 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
37062 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
37067 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
37072 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
37077 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
37082 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
37087 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
37094 <description>Specifies the match contribution condition for bit slice 6.</description>
37101 <description>Constant HIGH</description>
37106 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
37111 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
37116 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
37121 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
37126 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
37131 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
37136 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
37143 <description>Specifies the match contribution condition for bit slice 7.</description>
37150 <description>Constant HIGH</description>
37155 …description>Sticky rising edge. Match occurs if a rising edge on the specified input has occurred …
37160 …description>Sticky falling edge. Match occurs if a falling edge on the specified input has occurre…
37165 …description>Sticky rising or falling edge. Match occurs if either a rising or falling edge on the …
37170 …description>High level. Match (for this bit slice) occurs when there is a high level on the input …
37175 …<description>Low level. Match occurs when there is a low level on the specified input.</descriptio…
37180 …<description>Constant 0. This bit slice never contributes to a match (should be used to disable an…
37185 …description>Event. Non-sticky rising or falling edge. Match occurs on an event when either a risin…
37196 <description>Pin Interrupts and Pattern Match</description>
37215 <description>Input multiplexing (INPUTMUX)</description>
37228 <description>Inputmux register for SCT0 input</description>
37237 <description>Input number to SCT0 inputs 0 to 6.</description>
37244 <description>SCT_GPIO_IN_A function selected from IOCON register</description>
37249 <description>SCT_GPIO_IN_B function selected from IOCON register</description>
37254 <description>SCT_GPIO_IN_C function selected from IOCON register</description>
37259 <description>SCT_GPIO_IN_D function selected from IOCON register</description>
37264 <description>SCT_GPIO_IN_E function selected from IOCON register</description>
37269 <description>SCT_GPIO_IN_F function selected from IOCON register</description>
37274 <description>SCT_GPIO_IN_G function selected from IOCON register</description>
37279 <description>SCT_GPIO_IN_H function selected from IOCON register</description>
37284 <description>T0_MAT0 ctimer 0 match[0] output</description>
37289 <description>T1_MAT0 ctimer 1 match[0] output</description>
37294 <description>T2_MAT0 ctimer 2 match[0] output</description>
37299 <description>T3_MAT0 ctimer 3 match[0] output</description>
37304 <description>T4_MAT0 ctimer 4 match[0] output</description>
37309 <description>ADC0_IRQ interrupt request from ADC0</description>
37314 <description>GPIOINT_BMATCH</description>
37319 <description>USB0_FRAME_TOGGLE</description>
37324 <description>COMP0_OUT from analog comparator</description>
37329 <description>SHARED_I2S_SCLK0 output from I2S pin sharing</description>
37334 <description>SHARED_I2S_SCLK1 output from I2S pin sharing</description>
37339 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
37344 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
37349 <description>ARM_TXEV interrupt event from CPU0</description>
37354 <description>DEBUG_HALTED from CPU0</description>
37359 <description>ADC1_IRQ interrupt request from ADC1</description>
37364 <description>ADC0_tcomp[0]</description>
37369 <description>ADC0_tcomp[1]</description>
37374 <description>ADC0_tcomp[2]</description>
37379 <description>ADC0_tcomp[3]</description>
37384 <description>ADC1_tcomp[0]</description>
37389 <description>ADC1_tcomp[1]</description>
37394 <description>ADC1_tcomp[2]</description>
37399 <description>ADC1_tcomp[3]</description>
37404 <description>HSCMP0_OUT</description>
37409 <description>HSCMP1_OUT</description>
37414 <description>HSCMP2_OUT</description>
37419 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
37424 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
37429 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
37434 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
37439 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
37444 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
37449 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
37454 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
37459 <description>ENC0_CMP/POS_MATCH</description>
37464 <description>ENC1_CMP/POS_MATCH</description>
37469 <description>AOI0_OUT0</description>
37474 <description>AOI0_OUT1</description>
37479 <description>AOI0_OUT2</description>
37484 <description>AOI0_OUT3</description>
37489 <description>AOI1_OUT0</description>
37494 <description>AOI1_OUT1</description>
37499 <description>AOI1_OUT2</description>
37504 <description>AOI1_OUT3</description>
37509 <description>FC3_SCK</description>
37514 <description>FC3_RXD_SDA_MOSI_DATA</description>
37519 <description>FC3_TXD_SCL_MISO_WS</description>
37524 <description>FC3_CTS_DSA_SSEL0</description>
37529 <description>TMPR_OUT</description>
37534 <description>None</description>
37539 <description>None</description>
37544 <description>None</description>
37549 <description>None</description>
37554 <description>None</description>
37565 <description>Capture select register for TIMER0 inputs</description>
37574 <description>Input number to TIMER0 capture inputs 0 to 5</description>
37581 <description>CT_INP0 function selected from IOCON register</description>
37586 <description>CT_INP1 function selected from IOCON register</description>
37591 <description>CT_INP2 function selected from IOCON register</description>
37596 <description>CT_INP3 function selected from IOCON register</description>
37601 <description>CT_INP4 function selected from IOCON register</description>
37606 <description>CT_INP5 function selected from IOCON register</description>
37611 <description>CT_INP6 function selected from IOCON register</description>
37616 <description>CT_INP7 function selected from IOCON register</description>
37621 <description>CT_INP8 function selected from IOCON register</description>
37626 <description>CT_INP9 function selected from IOCON register</description>
37631 <description>CT_INP10 function selected from IOCON register</description>
37636 <description>CT_INP11 function selected from IOCON register</description>
37641 <description>CT_INP12 function selected from IOCON register</description>
37646 <description>CT_INP13 function selected from IOCON register</description>
37651 <description>CT_INP14 function selected from IOCON register</description>
37656 <description>CT_INP15 function selected from IOCON register</description>
37661 <description>CT_INP16 function selected from IOCON register</description>
37666 <description>CT_INP17 function selected from IOCON register</description>
37671 <description>CT_INP18 function selected from IOCON register</description>
37676 <description>CT_INP19 function selected from IOCON register</description>
37681 <description>USB0_FRAME_TOGGLE</description>
37686 <description>COMP0_OUT from analog comparator</description>
37691 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
37696 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
37701 <description>ADC0_IRQ</description>
37706 <description>ADC1_IRQ</description>
37711 <description>HSCMP0_OUT</description>
37716 <description>HSCMP1_OUT</description>
37721 <description>HSCMP2_OUT</description>
37726 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
37731 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
37736 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
37741 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
37746 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
37751 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
37756 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
37761 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
37766 <description>ENC0_CMP/POS_MATCH</description>
37771 <description>ENC1_CMP/POS_MATCH</description>
37776 <description>AOI0_OUT0</description>
37781 <description>AOI0_OUT1</description>
37786 <description>AOI0_OUT2</description>
37791 <description>AOI0_OUT3</description>
37796 <description>AOI1_OUT0</description>
37801 <description>AOI1_OUT1</description>
37806 <description>AOI1_OUT2</description>
37811 <description>AOI1_OUT3</description>
37816 <description>TMPR_OUT</description>
37821 <description>None</description>
37826 <description>None</description>
37831 <description>None</description>
37836 <description>None</description>
37841 <description>None</description>
37846 <description>None</description>
37851 <description>None</description>
37856 <description>None</description>
37861 <description>None</description>
37866 <description>None</description>
37871 <description>None</description>
37876 <description>None</description>
37881 <description>None</description>
37886 <description>None</description>
37891 <description>None</description>
37900 <description>Trigger register for TIMER0</description>
37909 <description>Input number to TIMER0 trigger inputs</description>
37916 <description>CT_INP0 function selected from IOCON register</description>
37921 <description>CT_INP1 function selected from IOCON register</description>
37926 <description>CT_INP2 function selected from IOCON register</description>
37931 <description>CT_INP3 function selected from IOCON register</description>
37936 <description>CT_INP4 function selected from IOCON register</description>
37941 <description>CT_INP5 function selected from IOCON register</description>
37946 <description>CT_INP6 function selected from IOCON register</description>
37951 <description>CT_INP7 function selected from IOCON register</description>
37956 <description>CT_INP8 function selected from IOCON register</description>
37961 <description>CT_INP9 function selected from IOCON register</description>
37966 <description>CT_INP10 function selected from IOCON register</description>
37971 <description>CT_INP11 function selected from IOCON register</description>
37976 <description>CT_INP12 function selected from IOCON register</description>
37981 <description>CT_INP13 function selected from IOCON register</description>
37986 <description>CT_INP14 function selected from IOCON register</description>
37991 <description>CT_INP15 function selected from IOCON register</description>
37996 <description>CT_INP16 function selected from IOCON register</description>
38001 <description>CT_INP17 function selected from IOCON register</description>
38006 <description>CT_INP18 function selected from IOCON register</description>
38011 <description>CT_INP19 function selected from IOCON register</description>
38016 <description>USB0_FRAME_TOGGLE</description>
38021 <description>COMP0_OUT from analog comparator</description>
38026 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
38031 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
38036 <description>ADC0_IRQ</description>
38041 <description>ADC1_IRQ</description>
38046 <description>HSCMP0_OUT</description>
38051 <description>HSCMP1_OUT</description>
38056 <description>HSCMP2_OUT</description>
38061 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
38066 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
38071 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
38076 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
38081 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
38086 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
38091 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
38096 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
38101 <description>ENC0_CMP/POS_MATCH</description>
38106 <description>ENC1_CMP/POS_MATCH</description>
38111 <description>AOI0_OUT0</description>
38116 <description>AOI0_OUT1</description>
38121 <description>AOI0_OUT2</description>
38126 <description>AOI0_OUT3</description>
38131 <description>AOI1_OUT0</description>
38136 <description>AOI1_OUT1</description>
38141 <description>AOI1_OUT2</description>
38146 <description>AOI1_OUT3</description>
38151 <description>TMPR_OUT</description>
38156 <description>None</description>
38161 <description>None</description>
38166 <description>None</description>
38171 <description>None</description>
38176 <description>None</description>
38181 <description>None</description>
38186 <description>None</description>
38191 <description>None</description>
38196 <description>None</description>
38201 <description>None</description>
38206 <description>None</description>
38211 <description>None</description>
38216 <description>None</description>
38221 <description>None</description>
38226 <description>None</description>
38237 <description>Capture select register for TIMER1 inputs</description>
38246 <description>Input number to TIMER1 capture inputs 0 to 5</description>
38253 <description>CT_INP0 function selected from IOCON register</description>
38258 <description>CT_INP1 function selected from IOCON register</description>
38263 <description>CT_INP2 function selected from IOCON register</description>
38268 <description>CT_INP3 function selected from IOCON register</description>
38273 <description>CT_INP4 function selected from IOCON register</description>
38278 <description>CT_INP5 function selected from IOCON register</description>
38283 <description>CT_INP6 function selected from IOCON register</description>
38288 <description>CT_INP7 function selected from IOCON register</description>
38293 <description>CT_INP8 function selected from IOCON register</description>
38298 <description>CT_INP9 function selected from IOCON register</description>
38303 <description>CT_INP10 function selected from IOCON register</description>
38308 <description>CT_INP11 function selected from IOCON register</description>
38313 <description>CT_INP12 function selected from IOCON register</description>
38318 <description>CT_INP13 function selected from IOCON register</description>
38323 <description>CT_INP14 function selected from IOCON register</description>
38328 <description>CT_INP15 function selected from IOCON register</description>
38333 <description>CT_INP16 function selected from IOCON register</description>
38338 <description>CT_INP17 function selected from IOCON register</description>
38343 <description>CT_INP18 function selected from IOCON register</description>
38348 <description>CT_INP19 function selected from IOCON register</description>
38353 <description>USB0_FRAME_TOGGLE</description>
38358 <description>COMP0_OUT from analog comparator</description>
38363 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
38368 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
38373 <description>ADC0_IRQ</description>
38378 <description>ADC1_IRQ</description>
38383 <description>HSCMP0_OUT</description>
38388 <description>HSCMP1_OUT</description>
38393 <description>HSCMP2_OUT</description>
38398 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
38403 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
38408 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
38413 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
38418 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
38423 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
38428 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
38433 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
38438 <description>ENC0_CMP/POS_MATCH</description>
38443 <description>ENC1_CMP/POS_MATCH</description>
38448 <description>AOI0_OUT0</description>
38453 <description>AOI0_OUT1</description>
38458 <description>AOI0_OUT2</description>
38463 <description>AOI0_OUT3</description>
38468 <description>AOI1_OUT0</description>
38473 <description>AOI1_OUT1</description>
38478 <description>AOI1_OUT2</description>
38483 <description>AOI1_OUT3</description>
38488 <description>TMPR_OUT</description>
38493 <description>None</description>
38498 <description>None</description>
38503 <description>None</description>
38508 <description>None</description>
38513 <description>None</description>
38518 <description>None</description>
38523 <description>None</description>
38528 <description>None</description>
38533 <description>None</description>
38538 <description>None</description>
38543 <description>None</description>
38548 <description>None</description>
38553 <description>None</description>
38558 <description>None</description>
38563 <description>None</description>
38572 <description>Trigger register for TIMER1</description>
38581 <description>Input number to TIMER1 trigger inputs</description>
38588 <description>CT_INP0 function selected from IOCON register</description>
38593 <description>CT_INP1 function selected from IOCON register</description>
38598 <description>CT_INP2 function selected from IOCON register</description>
38603 <description>CT_INP3 function selected from IOCON register</description>
38608 <description>CT_INP4 function selected from IOCON register</description>
38613 <description>CT_INP5 function selected from IOCON register</description>
38618 <description>CT_INP6 function selected from IOCON register</description>
38623 <description>CT_INP7 function selected from IOCON register</description>
38628 <description>CT_INP8 function selected from IOCON register</description>
38633 <description>CT_INP9 function selected from IOCON register</description>
38638 <description>CT_INP10 function selected from IOCON register</description>
38643 <description>CT_INP11 function selected from IOCON register</description>
38648 <description>CT_INP12 function selected from IOCON register</description>
38653 <description>CT_INP13 function selected from IOCON register</description>
38658 <description>CT_INP14 function selected from IOCON register</description>
38663 <description>CT_INP15 function selected from IOCON register</description>
38668 <description>CT_INP16 function selected from IOCON register</description>
38673 <description>CT_INP17 function selected from IOCON register</description>
38678 <description>CT_INP18 function selected from IOCON register</description>
38683 <description>CT_INP19 function selected from IOCON register</description>
38688 <description>USB0_FRAME_TOGGLE</description>
38693 <description>COMP0_OUT from analog comparator</description>
38698 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
38703 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
38708 <description>ADC0_IRQ</description>
38713 <description>ADC1_IRQ</description>
38718 <description>HSCMP0_OUT</description>
38723 <description>HSCMP1_OUT</description>
38728 <description>HSCMP2_OUT</description>
38733 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
38738 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
38743 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
38748 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
38753 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
38758 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
38763 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
38768 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
38773 <description>ENC0_CMP/POS_MATCH</description>
38778 <description>ENC1_CMP/POS_MATCH</description>
38783 <description>AOI0_OUT0</description>
38788 <description>AOI0_OUT1</description>
38793 <description>AOI0_OUT2</description>
38798 <description>AOI0_OUT3</description>
38803 <description>AOI1_OUT0</description>
38808 <description>AOI1_OUT1</description>
38813 <description>AOI1_OUT2</description>
38818 <description>AOI1_OUT3</description>
38823 <description>TMPR_OUT</description>
38828 <description>None</description>
38833 <description>None</description>
38838 <description>None</description>
38843 <description>None</description>
38848 <description>None</description>
38853 <description>None</description>
38858 <description>None</description>
38863 <description>None</description>
38868 <description>None</description>
38873 <description>None</description>
38878 <description>None</description>
38883 <description>None</description>
38888 <description>None</description>
38893 <description>None</description>
38898 <description>None</description>
38909 <description>Capture select register for TIMER2 inputs</description>
38918 <description>Input number to TIMER2 capture inputs 0 to 5</description>
38925 <description>CT_INP0 function selected from IOCON register</description>
38930 <description>CT_INP1 function selected from IOCON register</description>
38935 <description>CT_INP2 function selected from IOCON register</description>
38940 <description>CT_INP3 function selected from IOCON register</description>
38945 <description>CT_INP4 function selected from IOCON register</description>
38950 <description>CT_INP5 function selected from IOCON register</description>
38955 <description>CT_INP6 function selected from IOCON register</description>
38960 <description>CT_INP7 function selected from IOCON register</description>
38965 <description>CT_INP8 function selected from IOCON register</description>
38970 <description>CT_INP9 function selected from IOCON register</description>
38975 <description>CT_INP10 function selected from IOCON register</description>
38980 <description>CT_INP11 function selected from IOCON register</description>
38985 <description>CT_INP12 function selected from IOCON register</description>
38990 <description>CT_INP13 function selected from IOCON register</description>
38995 <description>CT_INP14 function selected from IOCON register</description>
39000 <description>CT_INP15 function selected from IOCON register</description>
39005 <description>CT_INP16 function selected from IOCON register</description>
39010 <description>CT_INP17 function selected from IOCON register</description>
39015 <description>CT_INP18 function selected from IOCON register</description>
39020 <description>CT_INP19 function selected from IOCON register</description>
39025 <description>USB0_FRAME_TOGGLE</description>
39030 <description>COMP0_OUT from analog comparator</description>
39035 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
39040 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
39045 <description>ADC0_IRQ</description>
39050 <description>ADC1_IRQ</description>
39055 <description>HSCMP0_OUT</description>
39060 <description>HSCMP1_OUT</description>
39065 <description>HSCMP2_OUT</description>
39070 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
39075 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
39080 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
39085 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
39090 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
39095 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
39100 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
39105 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
39110 <description>ENC0_CMP/POS_MATCH</description>
39115 <description>ENC1_CMP/POS_MATCH</description>
39120 <description>AOI0_OUT0</description>
39125 <description>AOI0_OUT1</description>
39130 <description>AOI0_OUT2</description>
39135 <description>AOI0_OUT3</description>
39140 <description>AOI1_OUT0</description>
39145 <description>AOI1_OUT1</description>
39150 <description>AOI1_OUT2</description>
39155 <description>AOI1_OUT3</description>
39160 <description>TMPR_OUT</description>
39165 <description>None</description>
39170 <description>None</description>
39175 <description>None</description>
39180 <description>None</description>
39185 <description>None</description>
39190 <description>None</description>
39195 <description>None</description>
39200 <description>None</description>
39205 <description>None</description>
39210 <description>None</description>
39215 <description>None</description>
39220 <description>None</description>
39225 <description>None</description>
39230 <description>None</description>
39235 <description>None</description>
39244 <description>Trigger register for TIMER2</description>
39253 <description>Input number to TIMER2 trigger inputs</description>
39260 <description>CT_INP0 function selected from IOCON register</description>
39265 <description>CT_INP1 function selected from IOCON register</description>
39270 <description>CT_INP2 function selected from IOCON register</description>
39275 <description>CT_INP3 function selected from IOCON register</description>
39280 <description>CT_INP4 function selected from IOCON register</description>
39285 <description>CT_INP5 function selected from IOCON register</description>
39290 <description>CT_INP6 function selected from IOCON register</description>
39295 <description>CT_INP7 function selected from IOCON register</description>
39300 <description>CT_INP8 function selected from IOCON register</description>
39305 <description>CT_INP9 function selected from IOCON register</description>
39310 <description>CT_INP10 function selected from IOCON register</description>
39315 <description>CT_INP11 function selected from IOCON register</description>
39320 <description>CT_INP12 function selected from IOCON register</description>
39325 <description>CT_INP13 function selected from IOCON register</description>
39330 <description>CT_INP14 function selected from IOCON register</description>
39335 <description>CT_INP15 function selected from IOCON register</description>
39340 <description>CT_INP16 function selected from IOCON register</description>
39345 <description>CT_INP17 function selected from IOCON register</description>
39350 <description>CT_INP18 function selected from IOCON register</description>
39355 <description>CT_INP19 function selected from IOCON register</description>
39360 <description>USB0_FRAME_TOGGLE</description>
39365 <description>COMP0_OUT from analog comparator</description>
39370 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
39375 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
39380 <description>ADC0_IRQ</description>
39385 <description>ADC1_IRQ</description>
39390 <description>HSCMP0_OUT</description>
39395 <description>HSCMP1_OUT</description>
39400 <description>HSCMP2_OUT</description>
39405 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
39410 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
39415 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
39420 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
39425 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
39430 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
39435 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
39440 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
39445 <description>ENC0_CMP/POS_MATCH</description>
39450 <description>ENC1_CMP/POS_MATCH</description>
39455 <description>AOI0_OUT0</description>
39460 <description>AOI0_OUT1</description>
39465 <description>AOI0_OUT2</description>
39470 <description>AOI0_OUT3</description>
39475 <description>AOI1_OUT0</description>
39480 <description>AOI1_OUT1</description>
39485 <description>AOI1_OUT2</description>
39490 <description>AOI1_OUT3</description>
39495 <description>TMPR_OUT</description>
39500 <description>None</description>
39505 <description>None</description>
39510 <description>None</description>
39515 <description>None</description>
39520 <description>None</description>
39525 <description>None</description>
39530 <description>None</description>
39535 <description>None</description>
39540 <description>None</description>
39545 <description>None</description>
39550 <description>None</description>
39555 <description>None</description>
39560 <description>None</description>
39565 <description>None</description>
39570 <description>None</description>
39581 <description>Inputmux register for EZH arch B inputs</description>
39590 <description>Input number select to EZHARCHB input</description>
39597 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39602 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39607 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39612 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39617 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39622 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39627 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39632 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39637 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39642 …<description>GPI00_0 to GPIO0_15 functions synced to system clock, selected from IOCON register</d…
39647 <description>SCT0_OUT8 output from SCTimer, synced to system clock</description>
39652 <description>SCT0_OUT9 output from SCTimer, synced to system clock</description>
39657 <description>T1_OUT2 ctimer 1 match[2] output</description>
39662 … <description>UTICK0_IRQ_SYNC Micro-tick timer interrupt, synced to system clock</description>
39667 <description>MRT_IRQ0 Multi-rate timer interrupt request 0</description>
39672 <description>MRT_IRQ1 Multi-rate timer interrupt request 1</description>
39677 <description>T4_OUT3 ctimer 4 match[3] output</description>
39682 <description>T4_OUT2 ctimer 4 match[2] output</description>
39687 <description>T3_OUT3 ctimer 3 match[3] output</description>
39692 <description>T3_OUT2 ctimer 3 match[2] output</description>
39697 … <description>FLEXCOMM5_IRQ Flexcomm5 interrupt synced to system clock</description>
39702 … <description>FLEXCOMM4_IRQ Flexcomm4 interrupt synced to system clock</description>
39707 … <description>FLEXCOMM3_IRQ Flexcomm3 interrupt synced to system clock</description>
39712 … <description>FLEXCOMM2_IRQ Flexcomm2 interrupt synced to system clock</description>
39717 … <description>FLEXCOMM1_IRQ Flexcomm1 interrupt synced to system clock</description>
39722 … <description>FLEXCOMM0_IRQ Flexcomm0 interrupt synced to system clock</description>
39727 <description>DMA0_IRQ DMA0 interrupt request</description>
39732 <description>DMA1_IRQ DMA1 interrupt request</description>
39737 …description>SYS_SYNC_IRQ combined WDT_INT Watchdog Timer interrupt request | FLASH_IRQ Flash inter…
39742 … <description>RTC_IRQ Real Time Clock Combined Alarm | Wake-up interrupt request</description>
39747 <description>ARM_TXEV interrupt event from CPU0</description>
39752 <description>GPIOINT_BMATCH GPIO_INT boolean pattern match output</description>
39757 <description>COMP_OUTPUT output from analog comparator</description>
39762 <description>USB0_FRAME_TOGGLE</description>
39767 <description>OSTIMER_IRQ OS Timer interrupt request</description>
39772 <description>None</description>
39777 <description>None</description>
39782 <description>None</description>
39787 <description>None</description>
39792 <description>None</description>
39797 <description>None</description>
39802 <description>None</description>
39807 <description>None</description>
39812 <description>None</description>
39817 <description>None</description>
39822 <description>None</description>
39827 <description>None</description>
39832 <description>None</description>
39837 <description>None</description>
39842 <description>None</description>
39847 <description>None</description>
39852 <description>None</description>
39857 <description>None</description>
39862 <description>None</description>
39867 <description>None</description>
39872 <description>None</description>
39877 <description>None</description>
39882 <description>None</description>
39887 <description>None</description>
39892 <description>None</description>
39897 <description>None</description>
39908 <description>Pin interrupt select</description>
39917 …description>Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN …
39928 <description>Trigger select for DMA0 channel</description>
39937 … <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 31).</description>
39944 <description>FlexSPI_RX</description>
39949 <description>FlexSPI_TX</description>
39954 <description>GPIO_INT0</description>
39959 <description>GPIO_INT1</description>
39964 <description>GPIO_INT2</description>
39969 <description>GPIO_INT3</description>
39974 <description>T0_DMAREQ_M0</description>
39979 <description>T0_DMAREQ_M1</description>
39984 <description>T1_DMAREQ_M0</description>
39989 <description>T1_DMAREQ_M1</description>
39994 <description>T2_DMAREQ_M0</description>
39999 <description>T2_DMAREQ_M1</description>
40004 <description>T3_DMAREQ_M0</description>
40009 <description>T3_DMAREQ_M1</description>
40014 <description>T4_DMAREQ_M0</description>
40019 <description>T4_DMAREQ_M1</description>
40024 <description>COMP0_OUT</description>
40029 <description>SDMA0_TRIGOUT_A</description>
40034 <description>SDMA0_TRIGOUT_B</description>
40039 <description>SDMA0_TRIGOUT_C</description>
40044 <description>SDMA0_TRIGOUT_D</description>
40049 <description>SCT_DMA0</description>
40054 <description>SCT_DMA1</description>
40059 <description>ADC0_tcomp[0]</description>
40064 <description>ADC1_tcomp[0]</description>
40069 <description>HSCMP0</description>
40074 <description>HSCMP1</description>
40079 <description>HSCMP2</description>
40084 <description>AOI0_OUT0</description>
40089 <description>AOI0_OUT1</description>
40094 <description>AOI0_OUT2</description>
40099 <description>AOI0_OUT3</description>
40104 <description>AOI1_OUT0</description>
40109 <description>AOI1_OUT1</description>
40114 <description>AOI1_OUT2</description>
40119 <description>AOI1_OUT3</description>
40124 <description>FlexPWM0_req_capt0</description>
40129 <description>FlexPWM0_req_capt1</description>
40134 <description>FlexPWM0_req_capt2</description>
40139 <description>FlexPWM0_req_capt3</description>
40144 <description>FlexPWM0_req_val0</description>
40149 <description>FlexPWM0_req_val1</description>
40154 <description>FlexPWM0_req_val2</description>
40159 <description>FlexPWM0_req_val3</description>
40164 <description>FlexPWM1_req_capt0</description>
40169 <description>FlexPWM1_req_capt1</description>
40174 <description>FlexPWM1_req_capt2</description>
40179 <description>FlexPWM1_req_capt3</description>
40184 <description>FlexPWM1_req_val0</description>
40189 <description>FlexPWM1_req_val1</description>
40194 <description>FlexPWM1_req_val2</description>
40199 <description>FlexPWM1_req_val3</description>
40204 <description>TMPR_OUT</description>
40215 <description>DMA0 output trigger selection for DMA0 input trigger</description>
40224 …<description>DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22).</descripti…
40233 <description>Selection for frequency measurement reference clock</description>
40242 …description>Clock source number (decimal value) for frequency measure function target clock: 0 = C…
40251 <description>Selection for frequency measurement target clock</description>
40260 …description>Clock source number (decimal value) for frequency measure function target clock: 0 = C…
40271 <description>Capture select register for TIMER3 inputs</description>
40280 <description>Input number to TIMER3 capture inputs 0 to 5</description>
40287 <description>CT_INP0 function selected from IOCON register</description>
40292 <description>CT_INP1 function selected from IOCON register</description>
40297 <description>CT_INP2 function selected from IOCON register</description>
40302 <description>CT_INP3 function selected from IOCON register</description>
40307 <description>CT_INP4 function selected from IOCON register</description>
40312 <description>CT_INP5 function selected from IOCON register</description>
40317 <description>CT_INP6 function selected from IOCON register</description>
40322 <description>CT_INP7 function selected from IOCON register</description>
40327 <description>CT_INP8 function selected from IOCON register</description>
40332 <description>CT_INP9 function selected from IOCON register</description>
40337 <description>CT_INP10 function selected from IOCON register</description>
40342 <description>CT_INP11 function selected from IOCON register</description>
40347 <description>CT_INP12 function selected from IOCON register</description>
40352 <description>CT_INP13 function selected from IOCON register</description>
40357 <description>CT_INP14 function selected from IOCON register</description>
40362 <description>CT_INP15 function selected from IOCON register</description>
40367 <description>CT_INP16 function selected from IOCON register</description>
40372 <description>CT_INP17 function selected from IOCON register</description>
40377 <description>CT_INP18 function selected from IOCON register</description>
40382 <description>CT_INP19 function selected from IOCON register</description>
40387 <description>USB0_FRAME_TOGGLE</description>
40392 <description>COMP0_OUT from analog comparator</description>
40397 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
40402 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
40407 <description>ADC0_IRQ</description>
40412 <description>ADC1_IRQ</description>
40417 <description>HSCMP0_OUT</description>
40422 <description>HSCMP1_OUT</description>
40427 <description>HSCMP2_OUT</description>
40432 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
40437 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
40442 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
40447 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
40452 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
40457 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
40462 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
40467 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
40472 <description>ENC0_CMP/POS_MATCH</description>
40477 <description>ENC1_CMP/POS_MATCH</description>
40482 <description>AOI0_OUT0</description>
40487 <description>AOI0_OUT1</description>
40492 <description>AOI0_OUT2</description>
40497 <description>AOI0_OUT3</description>
40502 <description>AOI1_OUT0</description>
40507 <description>AOI1_OUT1</description>
40512 <description>AOI1_OUT2</description>
40517 <description>AOI1_OUT3</description>
40522 <description>TMPR_OUT</description>
40527 <description>None</description>
40532 <description>None</description>
40537 <description>None</description>
40542 <description>None</description>
40547 <description>None</description>
40552 <description>None</description>
40557 <description>None</description>
40562 <description>None</description>
40567 <description>None</description>
40572 <description>None</description>
40577 <description>None</description>
40582 <description>None</description>
40587 <description>None</description>
40592 <description>None</description>
40597 <description>None</description>
40606 <description>Trigger register for TIMER3</description>
40615 <description>Input number to TIMER3 trigger inputs</description>
40622 <description>CT_INP0 function selected from IOCON register</description>
40627 <description>CT_INP1 function selected from IOCON register</description>
40632 <description>CT_INP2 function selected from IOCON register</description>
40637 <description>CT_INP3 function selected from IOCON register</description>
40642 <description>CT_INP4 function selected from IOCON register</description>
40647 <description>CT_INP5 function selected from IOCON register</description>
40652 <description>CT_INP6 function selected from IOCON register</description>
40657 <description>CT_INP7 function selected from IOCON register</description>
40662 <description>CT_INP8 function selected from IOCON register</description>
40667 <description>CT_INP9 function selected from IOCON register</description>
40672 <description>CT_INP10 function selected from IOCON register</description>
40677 <description>CT_INP11 function selected from IOCON register</description>
40682 <description>CT_INP12 function selected from IOCON register</description>
40687 <description>CT_INP13 function selected from IOCON register</description>
40692 <description>CT_INP14 function selected from IOCON register</description>
40697 <description>CT_INP15 function selected from IOCON register</description>
40702 <description>CT_INP16 function selected from IOCON register</description>
40707 <description>CT_INP17 function selected from IOCON register</description>
40712 <description>CT_INP18 function selected from IOCON register</description>
40717 <description>CT_INP19 function selected from IOCON register</description>
40722 <description>USB0_FRAME_TOGGLE</description>
40727 <description>COMP0_OUT from analog comparator</description>
40732 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
40737 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
40742 <description>ADC0_IRQ</description>
40747 <description>ADC1_IRQ</description>
40752 <description>HSCMP0_OUT</description>
40757 <description>HSCMP1_OUT</description>
40762 <description>HSCMP2_OUT</description>
40767 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
40772 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
40777 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
40782 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
40787 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
40792 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
40797 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
40802 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
40807 <description>ENC0_CMP/POS_MATCH</description>
40812 <description>ENC1_CMP/POS_MATCH</description>
40817 <description>AOI0_OUT0</description>
40822 <description>AOI0_OUT1</description>
40827 <description>AOI0_OUT2</description>
40832 <description>AOI0_OUT3</description>
40837 <description>AOI1_OUT0</description>
40842 <description>AOI1_OUT1</description>
40847 <description>AOI1_OUT2</description>
40852 <description>AOI1_OUT3</description>
40857 <description>TMPR_OUT</description>
40862 <description>None</description>
40867 <description>None</description>
40872 <description>None</description>
40877 <description>None</description>
40882 <description>None</description>
40887 <description>None</description>
40892 <description>None</description>
40897 <description>None</description>
40902 <description>None</description>
40907 <description>None</description>
40912 <description>None</description>
40917 <description>None</description>
40922 <description>None</description>
40927 <description>None</description>
40932 <description>None</description>
40943 <description>Capture select register for TIMER4 inputs</description>
40952 <description>Input number to TIMER4 capture inputs 0 to 5</description>
40959 <description>CT_INP0 function selected from IOCON register</description>
40964 <description>CT_INP1 function selected from IOCON register</description>
40969 <description>CT_INP2 function selected from IOCON register</description>
40974 <description>CT_INP3 function selected from IOCON register</description>
40979 <description>CT_INP4 function selected from IOCON register</description>
40984 <description>CT_INP5 function selected from IOCON register</description>
40989 <description>CT_INP6 function selected from IOCON register</description>
40994 <description>CT_INP7 function selected from IOCON register</description>
40999 <description>CT_INP8 function selected from IOCON register</description>
41004 <description>CT_INP9 function selected from IOCON register</description>
41009 <description>CT_INP10 function selected from IOCON register</description>
41014 <description>CT_INP11 function selected from IOCON register</description>
41019 <description>CT_INP12 function selected from IOCON register</description>
41024 <description>CT_INP13 function selected from IOCON register</description>
41029 <description>CT_INP14 function selected from IOCON register</description>
41034 <description>CT_INP15 function selected from IOCON register</description>
41039 <description>CT_INP16 function selected from IOCON register</description>
41044 <description>CT_INP17 function selected from IOCON register</description>
41049 <description>CT_INP18 function selected from IOCON register</description>
41054 <description>CT_INP19 function selected from IOCON register</description>
41059 <description>USB0_FRAME_TOGGLE</description>
41064 <description>COMP0_OUT from analog comparator</description>
41069 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
41074 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
41079 <description>ADC0_IRQ</description>
41084 <description>ADC1_IRQ</description>
41089 <description>HSCMP0_OUT</description>
41094 <description>HSCMP1_OUT</description>
41099 <description>HSCMP2_OUT</description>
41104 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
41109 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
41114 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
41119 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
41124 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
41129 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
41134 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
41139 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
41144 <description>ENC0_CMP/POS_MATCH</description>
41149 <description>ENC1_CMP/POS_MATCH</description>
41154 <description>AOI0_OUT0</description>
41159 <description>AOI0_OUT1</description>
41164 <description>AOI0_OUT2</description>
41169 <description>AOI0_OUT3</description>
41174 <description>AOI1_OUT0</description>
41179 <description>AOI1_OUT1</description>
41184 <description>AOI1_OUT2</description>
41189 <description>AOI1_OUT3</description>
41194 <description>TMPR_OUT</description>
41199 <description>None</description>
41204 <description>None</description>
41209 <description>None</description>
41214 <description>None</description>
41219 <description>None</description>
41224 <description>None</description>
41229 <description>None</description>
41234 <description>None</description>
41239 <description>None</description>
41244 <description>None</description>
41249 <description>None</description>
41254 <description>None</description>
41259 <description>None</description>
41264 <description>None</description>
41269 <description>None</description>
41278 <description>Trigger register for TIMER4</description>
41287 <description>Input number to TIMER4 trigger inputs</description>
41294 <description>CT_INP0 function selected from IOCON register</description>
41299 <description>CT_INP1 function selected from IOCON register</description>
41304 <description>CT_INP2 function selected from IOCON register</description>
41309 <description>CT_INP3 function selected from IOCON register</description>
41314 <description>CT_INP4 function selected from IOCON register</description>
41319 <description>CT_INP5 function selected from IOCON register</description>
41324 <description>CT_INP6 function selected from IOCON register</description>
41329 <description>CT_INP7 function selected from IOCON register</description>
41334 <description>CT_INP8 function selected from IOCON register</description>
41339 <description>CT_INP9 function selected from IOCON register</description>
41344 <description>CT_INP10 function selected from IOCON register</description>
41349 <description>CT_INP11 function selected from IOCON register</description>
41354 <description>CT_INP12 function selected from IOCON register</description>
41359 <description>CT_INP13 function selected from IOCON register</description>
41364 <description>CT_INP14 function selected from IOCON register</description>
41369 <description>CT_INP15 function selected from IOCON register</description>
41374 <description>CT_INP16 function selected from IOCON register</description>
41379 <description>CT_INP17 function selected from IOCON register</description>
41384 <description>CT_INP18 function selected from IOCON register</description>
41389 <description>CT_INP19 function selected from IOCON register</description>
41394 <description>USB0_FRAME_TOGGLE</description>
41399 <description>COMP0_OUT from analog comparator</description>
41404 <description>SHARED_I2S_WS0 output from I2S pin sharing</description>
41409 <description>SHARED_I2S_WS1 output from I2S pin sharing</description>
41414 <description>ADC0_IRQ</description>
41419 <description>ADC1_IRQ</description>
41424 <description>HSCMP0_OUT</description>
41429 <description>HSCMP1_OUT</description>
41434 <description>HSCMP2_OUT</description>
41439 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
41444 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
41449 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
41454 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
41459 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
41464 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
41469 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
41474 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
41479 <description>ENC0_CMP/POS_MATCH</description>
41484 <description>ENC1_CMP/POS_MATCH</description>
41489 <description>AOI0_OUT0</description>
41494 <description>AOI0_OUT1</description>
41499 <description>AOI0_OUT2</description>
41504 <description>AOI0_OUT3</description>
41509 <description>AOI1_OUT0</description>
41514 <description>AOI1_OUT1</description>
41519 <description>AOI1_OUT2</description>
41524 <description>AOI1_OUT3</description>
41529 <description>TMPR_OUT</description>
41534 <description>None</description>
41539 <description>None</description>
41544 <description>None</description>
41549 <description>None</description>
41554 <description>None</description>
41559 <description>None</description>
41564 <description>None</description>
41569 <description>None</description>
41574 <description>None</description>
41579 <description>None</description>
41584 <description>None</description>
41589 <description>None</description>
41594 <description>None</description>
41599 <description>None</description>
41604 <description>None</description>
41615 <description>Pin interrupt secure select</description>
41624 …description>Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: …
41635 <description>Trigger select for DMA1 channel</description>
41644 … <description>Trigger input number (decimal value) for DMA channel n (n = 0 to 14).</description>
41651 <description>Pin interrupt 0 (GPIO_INT0)</description>
41656 <description>Pin interrupt 1 (GPIO_INT1)</description>
41661 <description>Pin interrupt 2 (GPIO_INT2)</description>
41666 <description>Pin interrupt 3 (GPIO_INT3)</description>
41671 <description>Timer CTIMER0 Match 0 (T0_DMAREQ_M0)</description>
41676 <description>Timer CTIMER0 Match 1 (T0_DMAREQ_M1)</description>
41681 <description>Timer CTIMER2 Match 0 (T2_DMAREQ_M0)</description>
41686 <description>Timer CTIMER4 Match 0 (T4_DMAREQ_M0)</description>
41691 <description>SDMA1_TRIGOUT_A</description>
41696 <description>SDMA1_TRIGOUT_B</description>
41701 <description>SDMA1_TRIGOUT_C</description>
41706 <description>SDMA1_TRIGOUT_D</description>
41711 <description>SCT_DMA_REQ0</description>
41716 <description>SCT_DMA_REQ1</description>
41721 <description>FlexSPI_RX</description>
41726 <description>FlexSPI_TX</description>
41731 <description>AOI0_OUT0</description>
41736 <description>AOI0_OUT1</description>
41741 <description>AOI0_OUT2</description>
41746 <description>AOI0_OUT3</description>
41751 <description>AOI1_OUT0</description>
41756 <description>AOI1_OUT1</description>
41761 <description>AOI1_OUT2</description>
41766 <description>AOI1_OUT3</description>
41771 <description>TMPR_OUT</description>
41782 <description>DMA1 output trigger selection for DMA1 input trigger</description>
41791 …<description>DMA trigger output number (decimal value) for DMA channel n (n = 0 to 13).</descripti…
41798 <description>SDMA1_CH0_TRIGOUT</description>
41803 <description>SDMA1_CH1_TRIGOUT</description>
41808 <description>SDMA1_CH2_TRIGOUT</description>
41813 <description>SDMA1_CH3_TRIGOUT</description>
41818 <description>SDMA1_CH4_TRIGOUT</description>
41823 <description>SDMA1_CH5_TRIGOUT</description>
41828 <description>SDMA1_CH6_TRIGOUT</description>
41833 <description>SDMA1_CH7_TRIGOUT</description>
41838 <description>SDMA1_CH8_TRIGOUT</description>
41843 <description>SDMA1_CH9_TRIGOUT</description>
41848 <description>SDMA1_CH10_TRIGOUT</description>
41853 <description>SDMA1_CH11_TRIGOUT</description>
41858 <description>SDMA1_CH12_TRIGOUT</description>
41863 <description>SDMA1_CH13_TRIGOUT</description>
41872 <description>Input connections for HSCMP0</description>
41881 <description>CMP0 input trigger</description>
41888 <description>PIN_INT0</description>
41893 <description>PIN_INT6</description>
41898 <description>SCT_OUT4</description>
41903 <description>SCT_OUT5</description>
41908 <description>SCT_OUT6</description>
41913 <description>T0_MAT3</description>
41918 <description>T1_MAT3</description>
41923 <description>T2_MAT3</description>
41928 <description>T0_MAT0</description>
41933 <description>T4_MAT0</description>
41938 <description>ARM_TXEV</description>
41943 <description>GPIOINT_BMATCH</description>
41948 <description>ADC0_tcomp[0]</description>
41953 <description>ADC1_tcomp[0]</description>
41958 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
41963 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
41968 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
41973 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
41978 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
41983 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
41988 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
41993 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
41998 <description>ENC0_CMP/POS_MATCH</description>
42003 <description>ENC1_CMP/POS_MATCH</description>
42008 <description>AOI0_OUT0</description>
42013 <description>AOI0_OUT1</description>
42018 <description>AOI0_OUT2</description>
42023 <description>AOI0_OUT3</description>
42028 <description>AOI1_OUT0</description>
42033 <description>AOI1_OUT1</description>
42038 <description>AOI1_OUT2</description>
42043 <description>AOI1_OUT3</description>
42048 <description>DMA0_TRIGOUT0</description>
42053 <description>DMA0_TRIGOUT1</description>
42058 <description>DMA0_TRIGOUT2</description>
42069 <description>ADC0 Trigger input connections</description>
42078 <description>ADC0 trigger inputs</description>
42085 <description>PIN_INT0</description>
42090 <description>PIN_INT1</description>
42095 <description>SCT_OUT4</description>
42100 <description>SCT_OUT5</description>
42105 <description>SCT_OUT9</description>
42110 <description>T0_MAT3</description>
42115 <description>T1_MAT3</description>
42120 <description>T2_MAT3</description>
42125 <description>T3_MAT3</description>
42130 <description>T4_MAT3</description>
42135 <description>COMP0_OUT</description>
42140 <description>ARM_TXEV</description>
42145 <description>GPIOINT_BMATCH</description>
42150 <description>ADC0_tcomp[0]</description>
42155 <description>ADC0_tcomp[1]</description>
42160 <description>ADC0_tcomp[2]</description>
42165 <description>ADC0_tcomp[3]</description>
42170 <description>ADC1_tcomp[0]</description>
42175 <description>ADC1_tcomp[1]</description>
42180 <description>ADC1_tcomp[2]</description>
42185 <description>ADC1_tcomp[3]</description>
42190 <description>HSCMP0_OUT</description>
42195 <description>HSCMP1_OUT</description>
42200 <description>HSCMP2_OUT</description>
42205 <description>PWM0_SM0_MUX_TRIG0</description>
42210 <description>PWM0_SM0_MUX_TRIG1</description>
42215 <description>PWM0_SM1_MUX_TRIG0</description>
42220 <description>PWM0_SM1_MUX_TRIG1</description>
42225 <description>PWM0_SM2_MUX_TRIG0</description>
42230 <description>PWM0_SM2_MUX_TRIG1</description>
42235 <description>PWM0_SM3_MUX_TRIG0</description>
42240 <description>PWM0_SM3_MUX_TRIG1</description>
42245 <description>PWM1_SM0_MUX_TRIG0</description>
42250 <description>PWM1_SM0_MUX_TRIG1</description>
42255 <description>PWM1_SM0_MUX_TRIG0</description>
42260 <description>PWM1_SM1_MUX_TRIG1</description>
42265 <description>PWM1_SM2_MUX_TRIG0</description>
42270 <description>PWM1_SM2_MUX_TRIG1</description>
42275 <description>PWM1_SM3_MUX_TRIG0</description>
42280 <description>PWM1_SM3_MUX_TRIG1</description>
42285 <description>ENC0_CMP/POS_MATCH</description>
42290 <description>ENC1_CMP/POS_MATCH</description>
42295 <description>AOI0_OUT0</description>
42300 <description>AOI0_OUT1</description>
42305 <description>AOI0_OUT2</description>
42310 <description>AOI0_OUT3</description>
42315 <description>AOI1_OUT0</description>
42320 <description>AOI1_OUT1</description>
42325 <description>AOI1_OUT2</description>
42330 <description>AOI1_OUT3</description>
42335 <description>DMA0_TRIGOUT0</description>
42340 <description>DMA0_TRIGOUT1</description>
42345 <description>DMA0_TRIGOUT2</description>
42350 <description>None</description>
42355 <description>None</description>
42360 <description>None</description>
42365 <description>None</description>
42370 <description>None</description>
42375 <description>None</description>
42380 <description>None</description>
42385 <description>None</description>
42390 <description>None</description>
42395 <description>None</description>
42400 <description>None</description>
42411 <description>ADC1 Trigger input connections</description>
42420 <description>ADC1 trigger inputs</description>
42427 <description>PIN_INT0</description>
42432 <description>PIN_INT2</description>
42437 <description>SCT_OUT4</description>
42442 <description>SCT_OUT5</description>
42447 <description>SCT_OUT3</description>
42452 <description>T0_MAT3</description>
42457 <description>T1_MAT3</description>
42462 <description>T2_MAT3</description>
42467 <description>T3_MAT2</description>
42472 <description>T4_MAT1</description>
42477 <description>COMP0_OUT</description>
42482 <description>ARM_TXEV</description>
42487 <description>GPIOINT_BMATCH</description>
42492 <description>ADC0_tcomp[0]</description>
42497 <description>ADC0_tcomp[1]</description>
42502 <description>ADC0_tcomp[2]</description>
42507 <description>ADC0_tcomp[3]</description>
42512 <description>ADC1_tcomp[0]</description>
42517 <description>ADC1_tcomp[1]</description>
42522 <description>ADC1_tcomp[2]</description>
42527 <description>ADC1_tcomp[3]</description>
42532 <description>HSCMP0_OUT</description>
42537 <description>HSCMP1_OUT</description>
42542 <description>HSCMP2_OUT</description>
42547 <description>PWM0_SM0_MUX_TRIG0</description>
42552 <description>PWM0_SM0_MUX_TRIG1</description>
42557 <description>PWM0_SM1_MUX_TRIG0</description>
42562 <description>PWM0_SM1_MUX_TRIG1</description>
42567 <description>PWM0_SM2_MUX_TRIG0</description>
42572 <description>PWM0_SM2_MUX_TRIG1</description>
42577 <description>PWM0_SM3_MUX_TRIG0</description>
42582 <description>PWM0_SM3_MUX_TRIG1</description>
42587 <description>PWM1_SM0_MUX_TRIG0</description>
42592 <description>PWM1_SM0_MUX_TRIG1</description>
42597 <description>PWM1_SM0_MUX_TRIG0</description>
42602 <description>PWM1_SM1_MUX_TRIG1</description>
42607 <description>PWM1_SM2_MUX_TRIG0</description>
42612 <description>PWM1_SM2_MUX_TRIG1</description>
42617 <description>PWM1_SM3_MUX_TRIG0</description>
42622 <description>PWM1_SM3_MUX_TRIG1</description>
42627 <description>ENC0_CMP/POS_MATCH</description>
42632 <description>ENC1_CMP/POS_MATCH</description>
42637 <description>AOI0_OUT0</description>
42642 <description>AOI0_OUT1</description>
42647 <description>AOI0_OUT2</description>
42652 <description>AOI0_OUT3</description>
42657 <description>AOI1_OUT0</description>
42662 <description>AOI1_OUT1</description>
42667 <description>AOI1_OUT2</description>
42672 <description>AOI1_OUT3</description>
42677 <description>DMA0_TRIGOUT0</description>
42682 <description>DMA0_TRIGOUT1</description>
42687 <description>DMA0_TRIGOUT2</description>
42692 <description>None</description>
42697 <description>None</description>
42702 <description>None</description>
42707 <description>None</description>
42712 <description>None</description>
42717 <description>None</description>
42722 <description>None</description>
42727 <description>None</description>
42732 <description>None</description>
42737 <description>None</description>
42742 <description>None</description>
42751 <description>DAC0 Trigger Inputs</description>
42760 <description>DAC0 trigger input</description>
42767 <description>PIN_INT0</description>
42772 <description>PIN_INT3</description>
42777 <description>SCT_OUT4</description>
42782 <description>SCT_OUT5</description>
42787 <description>SCT_OUT0</description>
42792 <description>T0_MAT3</description>
42797 <description>T1_MAT3</description>
42802 <description>T2_MAT3</description>
42807 <description>T2_MAT0</description>
42812 <description>T3_MAT0</description>
42817 <description>COMP0_OUT</description>
42822 <description>ARM_TXEV</description>
42827 <description>GPIOINT_BMATCH</description>
42832 <description>ADC0_tcomp[0]</description>
42837 <description>ADC1_tcomp[0]</description>
42842 <description>HSCMP0_OUT</description>
42847 <description>HSCMP1_OUT</description>
42852 <description>HSCMP2_OUT</description>
42857 <description>AOI0_OUT0</description>
42862 <description>AOI0_OUT1</description>
42867 <description>AOI0_OUT2</description>
42872 <description>AOI0_OUT3</description>
42877 <description>AOI1_OUT0</description>
42882 <description>AOI1_OUT1</description>
42887 <description>AOI1_OUT2</description>
42892 <description>AOI1_OUT3</description>
42897 <description>DMA0_TRIGOUT0</description>
42902 <description>DMA0_TRIGOUT1</description>
42907 <description>DMA0_TRIGOUT2</description>
42916 <description>DAC1 Trigger Inputs</description>
42925 <description>DAC1 trigger input</description>
42932 <description>PIN_INT0</description>
42937 <description>PIN_INT4</description>
42942 <description>SCT_OUT4</description>
42947 <description>SCT_OUT5</description>
42952 <description>SCT_OUT1</description>
42957 <description>T0_MAT3</description>
42962 <description>T1_MAT3</description>
42967 <description>T2_MAT3</description>
42972 <description>T2_MAT1</description>
42977 <description>T3_MAT1</description>
42982 <description>COMP0_OUT</description>
42987 <description>ARM_TXEV</description>
42992 <description>GPIOINT_BMATCH</description>
42997 <description>ADC0_tcomp[1]</description>
43002 <description>ADC1_tcomp[1]</description>
43007 <description>HSCMP0_OUT</description>
43012 <description>HSCMP1_OUT</description>
43017 <description>HSCMP2_OUT</description>
43022 <description>AOI0_OUT0</description>
43027 <description>AOI0_OUT1</description>
43032 <description>AOI0_OUT2</description>
43037 <description>AOI0_OUT3</description>
43042 <description>AOI1_OUT0</description>
43047 <description>AOI1_OUT1</description>
43052 <description>AOI1_OUT2</description>
43057 <description>AOI1_OUT3</description>
43062 <description>DMA0_TRIGOUT0</description>
43067 <description>DMA0_TRIGOUT1</description>
43072 <description>DMA0_TRIGOUT2</description>
43081 <description>DAC2 Trigger Inputs</description>
43090 <description>DAC2 trigger input</description>
43097 <description>PIN_INT0</description>
43102 <description>PIN_INT5</description>
43107 <description>SCT_OUT4</description>
43112 <description>SCT_OUT5</description>
43117 <description>SCT_OUT2</description>
43122 <description>T0_MAT3</description>
43127 <description>T1_MAT3</description>
43132 <description>T2_MAT3</description>
43137 <description>T2_MAT2</description>
43142 <description>T3_MAT2</description>
43147 <description>COMP0_OUT</description>
43152 <description>ARM_TXEV</description>
43157 <description>GPIOINT_BMATCH</description>
43162 <description>ADC0_tcomp[2]</description>
43167 <description>ADC1_tcomp[2]</description>
43172 <description>HSCMP0_OUT</description>
43177 <description>HSCMP1_OUT</description>
43182 <description>HSCMP2_OUT</description>
43187 <description>AOI0_OUT0</description>
43192 <description>AOI0_OUT1</description>
43197 <description>AOI0_OUT2</description>
43202 <description>AOI0_OUT3</description>
43207 <description>AOI1_OUT0</description>
43212 <description>AOI1_OUT1</description>
43217 <description>AOI1_OUT2</description>
43222 <description>AOI1_OUT3</description>
43227 <description>DMA0_TRIGOUT0</description>
43232 <description>DMA0_TRIGOUT1</description>
43237 <description>DMA0_TRIGOUT2</description>
43246 <description>ENC0 Trigger Input Connections</description>
43255 <description>ENC0 input trigger</description>
43262 <description>PIN_INT0</description>
43267 <description>PIN_INT4</description>
43272 <description>SCT_OUT4</description>
43277 <description>SCT_OUT5</description>
43282 <description>SCT_OUT1</description>
43287 <description>T0_MAT3</description>
43292 <description>T1_MAT3</description>
43297 <description>T2_MAT3</description>
43302 <description>T1_MAT0</description>
43307 <description>T3_MAT0</description>
43312 <description>COMP0_OUT</description>
43317 <description>ARM_TXEV</description>
43322 <description>GPIOINT_BMATCH</description>
43327 <description>ADC0_tcomp[0]</description>
43332 <description>ADC0_tcomp[1]</description>
43337 <description>ADC0_tcomp[2]</description>
43342 <description>ADC0_tcomp[3]</description>
43347 <description>ADC1_tcomp[0]</description>
43352 <description>ADC1_tcomp[1]</description>
43357 <description>ADC1_tcomp[2]</description>
43362 <description>ADC1_tcomp[3]</description>
43367 <description>HSCMP0_OUT</description>
43372 <description>HSCMP1_OUT</description>
43377 <description>HSCMP2_OUT</description>
43382 <description>PWM1_SM0_MUX_TRIG0</description>
43387 <description>PWM1_SM0_MUX_TRIG1</description>
43392 <description>PWM1_SM0_MUX_TRIG0</description>
43397 <description>PWM1_SM1_MUX_TRIG1</description>
43402 <description>PWM1_SM2_MUX_TRIG0</description>
43407 <description>PWM1_SM2_MUX_TRIG1</description>
43412 <description>PWM1_SM3_MUX_TRIG0</description>
43417 <description>PWM1_SM3_MUX_TRIG1</description>
43422 <description>ENC0_CMP/POS_MATCH</description>
43427 <description>ENC1_CMP/POS_MATCH</description>
43432 <description>AOI0_OUT0</description>
43437 <description>AOI0_OUT1</description>
43442 <description>AOI0_OUT2</description>
43447 <description>AOI0_OUT3</description>
43452 <description>AOI1_OUT0</description>
43457 <description>AOI1_OUT1</description>
43462 <description>AOI1_OUT2</description>
43467 <description>AOI1_OUT3</description>
43472 <description>EXTTRIG_IN0</description>
43477 <description>EXTTRIG_IN1</description>
43482 <description>EXTTRIG_IN2</description>
43487 <description>EXTTRIG_IN3</description>
43492 <description>EXTTRIG_IN4</description>
43497 <description>EXTTRIG_IN5</description>
43502 <description>EXTTRIG_IN6</description>
43507 <description>EXTTRIG_IN7</description>
43512 <description>EXTTRIG_IN8</description>
43517 <description>EXTTRIG_IN9</description>
43522 <description>DMA0_TRIGOUT0</description>
43527 <description>DMA0_TRIGOUT1</description>
43532 <description>DMA0_TRIGOUT2</description>
43541 <description>ENC0 Input Connections</description>
43550 <description>ENC0 Input Connections</description>
43557 <description>PIN_INT0</description>
43562 <description>PIN_INT4</description>
43567 <description>SCT_OUT4</description>
43572 <description>SCT_OUT5</description>
43577 <description>SCT_OUT1</description>
43582 <description>T0_MAT3</description>
43587 <description>T1_MAT3</description>
43592 <description>T2_MAT3</description>
43597 <description>T1_MAT0</description>
43602 <description>T3_MAT0</description>
43607 <description>COMP0_OUT</description>
43612 <description>ARM_TXEV</description>
43617 <description>GPIOINT_BMATCH</description>
43622 <description>ADC0_tcomp[0]</description>
43627 <description>ADC0_tcomp[1]</description>
43632 <description>ADC0_tcomp[2]</description>
43637 <description>ADC0_tcomp[3]</description>
43642 <description>ADC1_tcomp[0]</description>
43647 <description>ADC1_tcomp[1]</description>
43652 <description>ADC1_tcomp[2]</description>
43657 <description>ADC1_tcomp[3]</description>
43662 <description>HSCMP0_OUT</description>
43667 <description>HSCMP1_OUT</description>
43672 <description>HSCMP2_OUT</description>
43677 <description>PWM1_SM0_MUX_TRIG0</description>
43682 <description>PWM1_SM0_MUX_TRIG1</description>
43687 <description>PWM1_SM0_MUX_TRIG0</description>
43692 <description>PWM1_SM1_MUX_TRIG1</description>
43697 <description>PWM1_SM2_MUX_TRIG0</description>
43702 <description>PWM1_SM2_MUX_TRIG1</description>
43707 <description>PWM1_SM3_MUX_TRIG0</description>
43712 <description>PWM1_SM3_MUX_TRIG1</description>
43717 <description>ENC0_CMP/POS_MATCH</description>
43722 <description>ENC1_CMP/POS_MATCH</description>
43727 <description>AOI0_OUT0</description>
43732 <description>AOI0_OUT1</description>
43737 <description>AOI0_OUT2</description>
43742 <description>AOI0_OUT3</description>
43747 <description>AOI1_OUT0</description>
43752 <description>AOI1_OUT1</description>
43757 <description>AOI1_OUT2</description>
43762 <description>AOI1_OUT3</description>
43767 <description>EXTTRIG_IN0</description>
43772 <description>EXTTRIG_IN1</description>
43777 <description>EXTTRIG_IN2</description>
43782 <description>EXTTRIG_IN3</description>
43787 <description>EXTTRIG_IN4</description>
43792 <description>EXTTRIG_IN5</description>
43797 <description>EXTTRIG_IN6</description>
43802 <description>EXTTRIG_IN7</description>
43807 <description>EXTTRIG_IN8</description>
43812 <description>EXTTRIG_IN9</description>
43817 <description>DMA0_TRIGOUT0</description>
43822 <description>DMA0_TRIGOUT1</description>
43827 <description>DMA0_TRIGOUT2</description>
43836 <description>ENC0 Input Connections</description>
43845 <description>ENC0 Input Connections</description>
43852 <description>PIN_INT0</description>
43857 <description>PIN_INT4</description>
43862 <description>SCT_OUT4</description>
43867 <description>SCT_OUT5</description>
43872 <description>SCT_OUT1</description>
43877 <description>T0_MAT3</description>
43882 <description>T1_MAT3</description>
43887 <description>T2_MAT3</description>
43892 <description>T1_MAT0</description>
43897 <description>T3_MAT0</description>
43902 <description>COMP0_OUT</description>
43907 <description>ARM_TXEV</description>
43912 <description>GPIOINT_BMATCH</description>
43917 <description>ADC0_tcomp[0]</description>
43922 <description>ADC0_tcomp[1]</description>
43927 <description>ADC0_tcomp[2]</description>
43932 <description>ADC0_tcomp[3]</description>
43937 <description>ADC1_tcomp[0]</description>
43942 <description>ADC1_tcomp[1]</description>
43947 <description>ADC1_tcomp[2]</description>
43952 <description>ADC1_tcomp[3]</description>
43957 <description>HSCMP0_OUT</description>
43962 <description>HSCMP1_OUT</description>
43967 <description>HSCMP2_OUT</description>
43972 <description>PWM1_SM0_MUX_TRIG0</description>
43977 <description>PWM1_SM0_MUX_TRIG1</description>
43982 <description>PWM1_SM0_MUX_TRIG0</description>
43987 <description>PWM1_SM1_MUX_TRIG1</description>
43992 <description>PWM1_SM2_MUX_TRIG0</description>
43997 <description>PWM1_SM2_MUX_TRIG1</description>
44002 <description>PWM1_SM3_MUX_TRIG0</description>
44007 <description>PWM1_SM3_MUX_TRIG1</description>
44012 <description>ENC0_CMP/POS_MATCH</description>
44017 <description>ENC1_CMP/POS_MATCH</description>
44022 <description>AOI0_OUT0</description>
44027 <description>AOI0_OUT1</description>
44032 <description>AOI0_OUT2</description>
44037 <description>AOI0_OUT3</description>
44042 <description>AOI1_OUT0</description>
44047 <description>AOI1_OUT1</description>
44052 <description>AOI1_OUT2</description>
44057 <description>AOI1_OUT3</description>
44062 <description>EXTTRIG_IN0</description>
44067 <description>EXTTRIG_IN1</description>
44072 <description>EXTTRIG_IN2</description>
44077 <description>EXTTRIG_IN3</description>
44082 <description>EXTTRIG_IN4</description>
44087 <description>EXTTRIG_IN5</description>
44092 <description>EXTTRIG_IN6</description>
44097 <description>EXTTRIG_IN7</description>
44102 <description>EXTTRIG_IN8</description>
44107 <description>EXTTRIG_IN9</description>
44112 <description>DMA0_TRIGOUT0</description>
44117 <description>DMA0_TRIGOUT1</description>
44122 <description>DMA0_TRIGOUT2</description>
44131 <description>ENC0 Input Connections</description>
44140 <description>ENC0 Input Connections</description>
44147 <description>PIN_INT0</description>
44152 <description>PIN_INT4</description>
44157 <description>SCT_OUT4</description>
44162 <description>SCT_OUT5</description>
44167 <description>SCT_OUT1</description>
44172 <description>T0_MAT3</description>
44177 <description>T1_MAT3</description>
44182 <description>T2_MAT3</description>
44187 <description>T1_MAT0</description>
44192 <description>T3_MAT0</description>
44197 <description>COMP0_OUT</description>
44202 <description>ARM_TXEV</description>
44207 <description>GPIOINT_BMATCH</description>
44212 <description>ADC0_tcomp[0]</description>
44217 <description>ADC0_tcomp[1]</description>
44222 <description>ADC0_tcomp[2]</description>
44227 <description>ADC0_tcomp[3]</description>
44232 <description>ADC1_tcomp[0]</description>
44237 <description>ADC1_tcomp[1]</description>
44242 <description>ADC1_tcomp[2]</description>
44247 <description>ADC1_tcomp[3]</description>
44252 <description>HSCMP0_OUT</description>
44257 <description>HSCMP1_OUT</description>
44262 <description>HSCMP2_OUT</description>
44267 <description>PWM1_SM0_MUX_TRIG0</description>
44272 <description>PWM1_SM0_MUX_TRIG1</description>
44277 <description>PWM1_SM0_MUX_TRIG0</description>
44282 <description>PWM1_SM1_MUX_TRIG1</description>
44287 <description>PWM1_SM2_MUX_TRIG0</description>
44292 <description>PWM1_SM2_MUX_TRIG1</description>
44297 <description>PWM1_SM3_MUX_TRIG0</description>
44302 <description>PWM1_SM3_MUX_TRIG1</description>
44307 <description>ENC0_CMP/POS_MATCH</description>
44312 <description>ENC1_CMP/POS_MATCH</description>
44317 <description>AOI0_OUT0</description>
44322 <description>AOI0_OUT1</description>
44327 <description>AOI0_OUT2</description>
44332 <description>AOI0_OUT3</description>
44337 <description>AOI1_OUT0</description>
44342 <description>AOI1_OUT1</description>
44347 <description>AOI1_OUT2</description>
44352 <description>AOI1_OUT3</description>
44357 <description>EXTTRIG_IN0</description>
44362 <description>EXTTRIG_IN1</description>
44367 <description>EXTTRIG_IN2</description>
44372 <description>EXTTRIG_IN3</description>
44377 <description>EXTTRIG_IN4</description>
44382 <description>EXTTRIG_IN5</description>
44387 <description>EXTTRIG_IN6</description>
44392 <description>EXTTRIG_IN7</description>
44397 <description>EXTTRIG_IN8</description>
44402 <description>EXTTRIG_IN9</description>
44407 <description>DMA0_TRIGOUT0</description>
44412 <description>DMA0_TRIGOUT1</description>
44417 <description>DMA0_TRIGOUT2</description>
44426 <description>ENC0 Input Connections</description>
44435 <description>ENC0 Input Connections</description>
44442 <description>PIN_INT0</description>
44447 <description>PIN_INT4</description>
44452 <description>SCT_OUT4</description>
44457 <description>SCT_OUT5</description>
44462 <description>SCT_OUT1</description>
44467 <description>T0_MAT3</description>
44472 <description>T1_MAT3</description>
44477 <description>T2_MAT3</description>
44482 <description>T1_MAT0</description>
44487 <description>T3_MAT0</description>
44492 <description>COMP0_OUT</description>
44497 <description>ARM_TXEV</description>
44502 <description>GPIOINT_BMATCH</description>
44507 <description>ADC0_tcomp[0]</description>
44512 <description>ADC0_tcomp[1]</description>
44517 <description>ADC0_tcomp[2]</description>
44522 <description>ADC0_tcomp[3]</description>
44527 <description>ADC1_tcomp[0]</description>
44532 <description>ADC1_tcomp[1]</description>
44537 <description>ADC1_tcomp[2]</description>
44542 <description>ADC1_tcomp[3]</description>
44547 <description>HSCMP0_OUT</description>
44552 <description>HSCMP1_OUT</description>
44557 <description>HSCMP2_OUT</description>
44562 <description>PWM1_SM0_MUX_TRIG0</description>
44567 <description>PWM1_SM0_MUX_TRIG1</description>
44572 <description>PWM1_SM0_MUX_TRIG0</description>
44577 <description>PWM1_SM1_MUX_TRIG1</description>
44582 <description>PWM1_SM2_MUX_TRIG0</description>
44587 <description>PWM1_SM2_MUX_TRIG1</description>
44592 <description>PWM1_SM3_MUX_TRIG0</description>
44597 <description>PWM1_SM3_MUX_TRIG1</description>
44602 <description>ENC0_CMP/POS_MATCH</description>
44607 <description>ENC1_CMP/POS_MATCH</description>
44612 <description>AOI0_OUT0</description>
44617 <description>AOI0_OUT1</description>
44622 <description>AOI0_OUT2</description>
44627 <description>AOI0_OUT3</description>
44632 <description>AOI1_OUT0</description>
44637 <description>AOI1_OUT1</description>
44642 <description>AOI1_OUT2</description>
44647 <description>AOI1_OUT3</description>
44652 <description>EXTTRIG_IN0</description>
44657 <description>EXTTRIG_IN1</description>
44662 <description>EXTTRIG_IN2</description>
44667 <description>EXTTRIG_IN3</description>
44672 <description>EXTTRIG_IN4</description>
44677 <description>EXTTRIG_IN5</description>
44682 <description>EXTTRIG_IN6</description>
44687 <description>EXTTRIG_IN7</description>
44692 <description>EXTTRIG_IN8</description>
44697 <description>EXTTRIG_IN9</description>
44702 <description>DMA0_TRIGOUT0</description>
44707 <description>DMA0_TRIGOUT1</description>
44712 <description>DMA0_TRIGOUT2</description>
44721 <description>ENC1 Trigger Input Connections</description>
44730 <description>ENC1 input trigger</description>
44737 <description>PIN_INT0</description>
44742 <description>PIN_INT5</description>
44747 <description>SCT_OUT4</description>
44752 <description>SCT_OUT5</description>
44757 <description>SCT_OUT7</description>
44762 <description>T0_MAT3</description>
44767 <description>T1_MAT3</description>
44772 <description>T2_MAT3</description>
44777 <description>T1_MAT1</description>
44782 <description>T3_MAT1</description>
44787 <description>COMP0_OUT</description>
44792 <description>ARM_TXEV</description>
44797 <description>GPIOINT_BMATCH</description>
44802 <description>ADC0_tcomp[0]</description>
44807 <description>ADC0_tcomp[1]</description>
44812 <description>ADC0_tcomp[2]</description>
44817 <description>ADC0_tcomp[3]</description>
44822 <description>ADC1_tcomp[0]</description>
44827 <description>ADC1_tcomp[1]</description>
44832 <description>ADC1_tcomp[2]</description>
44837 <description>ADC1_tcomp[3]</description>
44842 <description>HSCMP0_OUT</description>
44847 <description>HSCMP1_OUT</description>
44852 <description>HSCMP2_OUT</description>
44857 <description>PWM1_SM0_MUX_TRIG0</description>
44862 <description>PWM1_SM0_MUX_TRIG1</description>
44867 <description>PWM1_SM0_MUX_TRIG0</description>
44872 <description>PWM1_SM1_MUX_TRIG1</description>
44877 <description>PWM1_SM2_MUX_TRIG0</description>
44882 <description>PWM1_SM2_MUX_TRIG1</description>
44887 <description>PWM1_SM3_MUX_TRIG0</description>
44892 <description>PWM1_SM3_MUX_TRIG1</description>
44897 <description>ENC0_CMP/POS_MATCH</description>
44902 <description>ENC1_CMP/POS_MATCH</description>
44907 <description>AOI0_OUT0</description>
44912 <description>AOI0_OUT1</description>
44917 <description>AOI0_OUT2</description>
44922 <description>AOI0_OUT3</description>
44927 <description>AOI1_OUT0</description>
44932 <description>AOI1_OUT1</description>
44937 <description>AOI1_OUT2</description>
44942 <description>AOI1_OUT3</description>
44947 <description>EXTTRIG_IN0</description>
44952 <description>EXTTRIG_IN1</description>
44957 <description>EXTTRIG_IN2</description>
44962 <description>EXTTRIG_IN3</description>
44967 <description>EXTTRIG_IN4</description>
44972 <description>EXTTRIG_IN5</description>
44977 <description>EXTTRIG_IN6</description>
44982 <description>EXTTRIG_IN7</description>
44987 <description>EXTTRIG_IN8</description>
44992 <description>EXTTRIG_IN9</description>
44997 <description>DMA0_TRIGOUT0</description>
45002 <description>DMA0_TRIGOUT1</description>
45007 <description>DMA0_TRIGOUT2</description>
45016 <description>ENC1 Input Connections</description>
45025 <description>ENC1 input trigger</description>
45032 <description>PIN_INT0</description>
45037 <description>PIN_INT5</description>
45042 <description>SCT_OUT4</description>
45047 <description>SCT_OUT5</description>
45052 <description>SCT_OUT7</description>
45057 <description>T0_MAT3</description>
45062 <description>T1_MAT3</description>
45067 <description>T2_MAT3</description>
45072 <description>T1_MAT1</description>
45077 <description>T3_MAT1</description>
45082 <description>COMP0_OUT</description>
45087 <description>ARM_TXEV</description>
45092 <description>GPIOINT_BMATCH</description>
45097 <description>ADC0_tcomp[0]</description>
45102 <description>ADC0_tcomp[1]</description>
45107 <description>ADC0_tcomp[2]</description>
45112 <description>ADC0_tcomp[3]</description>
45117 <description>ADC1_tcomp[0]</description>
45122 <description>ADC1_tcomp[1]</description>
45127 <description>ADC1_tcomp[2]</description>
45132 <description>ADC1_tcomp[3]</description>
45137 <description>HSCMP0_OUT</description>
45142 <description>HSCMP1_OUT</description>
45147 <description>HSCMP2_OUT</description>
45152 <description>PWM1_SM0_MUX_TRIG0</description>
45157 <description>PWM1_SM0_MUX_TRIG1</description>
45162 <description>PWM1_SM0_MUX_TRIG0</description>
45167 <description>PWM1_SM1_MUX_TRIG1</description>
45172 <description>PWM1_SM2_MUX_TRIG0</description>
45177 <description>PWM1_SM2_MUX_TRIG1</description>
45182 <description>PWM1_SM3_MUX_TRIG0</description>
45187 <description>PWM1_SM3_MUX_TRIG1</description>
45192 <description>ENC0_CMP/POS_MATCH</description>
45197 <description>ENC1_CMP/POS_MATCH</description>
45202 <description>AOI0_OUT0</description>
45207 <description>AOI0_OUT1</description>
45212 <description>AOI0_OUT2</description>
45217 <description>AOI0_OUT3</description>
45222 <description>AOI1_OUT0</description>
45227 <description>AOI1_OUT1</description>
45232 <description>AOI1_OUT2</description>
45237 <description>AOI1_OUT3</description>
45242 <description>EXTTRIG_IN0</description>
45247 <description>EXTTRIG_IN1</description>
45252 <description>EXTTRIG_IN2</description>
45257 <description>EXTTRIG_IN3</description>
45262 <description>EXTTRIG_IN4</description>
45267 <description>EXTTRIG_IN5</description>
45272 <description>EXTTRIG_IN6</description>
45277 <description>EXTTRIG_IN7</description>
45282 <description>EXTTRIG_IN8</description>
45287 <description>EXTTRIG_IN9</description>
45292 <description>DMA0_TRIGOUT0</description>
45297 <description>DMA0_TRIGOUT1</description>
45302 <description>DMA0_TRIGOUT2</description>
45311 <description>ENC1 Input Connections</description>
45320 <description>ENC1 input trigger</description>
45327 <description>PIN_INT0</description>
45332 <description>PIN_INT5</description>
45337 <description>SCT_OUT4</description>
45342 <description>SCT_OUT5</description>
45347 <description>SCT_OUT7</description>
45352 <description>T0_MAT3</description>
45357 <description>T1_MAT3</description>
45362 <description>T2_MAT3</description>
45367 <description>T1_MAT1</description>
45372 <description>T3_MAT1</description>
45377 <description>COMP0_OUT</description>
45382 <description>ARM_TXEV</description>
45387 <description>GPIOINT_BMATCH</description>
45392 <description>ADC0_tcomp[0]</description>
45397 <description>ADC0_tcomp[1]</description>
45402 <description>ADC0_tcomp[2]</description>
45407 <description>ADC0_tcomp[3]</description>
45412 <description>ADC1_tcomp[0]</description>
45417 <description>ADC1_tcomp[1]</description>
45422 <description>ADC1_tcomp[2]</description>
45427 <description>ADC1_tcomp[3]</description>
45432 <description>HSCMP0_OUT</description>
45437 <description>HSCMP1_OUT</description>
45442 <description>HSCMP2_OUT</description>
45447 <description>PWM1_SM0_MUX_TRIG0</description>
45452 <description>PWM1_SM0_MUX_TRIG1</description>
45457 <description>PWM1_SM0_MUX_TRIG0</description>
45462 <description>PWM1_SM1_MUX_TRIG1</description>
45467 <description>PWM1_SM2_MUX_TRIG0</description>
45472 <description>PWM1_SM2_MUX_TRIG1</description>
45477 <description>PWM1_SM3_MUX_TRIG0</description>
45482 <description>PWM1_SM3_MUX_TRIG1</description>
45487 <description>ENC0_CMP/POS_MATCH</description>
45492 <description>ENC1_CMP/POS_MATCH</description>
45497 <description>AOI0_OUT0</description>
45502 <description>AOI0_OUT1</description>
45507 <description>AOI0_OUT2</description>
45512 <description>AOI0_OUT3</description>
45517 <description>AOI1_OUT0</description>
45522 <description>AOI1_OUT1</description>
45527 <description>AOI1_OUT2</description>
45532 <description>AOI1_OUT3</description>
45537 <description>EXTTRIG_IN0</description>
45542 <description>EXTTRIG_IN1</description>
45547 <description>EXTTRIG_IN2</description>
45552 <description>EXTTRIG_IN3</description>
45557 <description>EXTTRIG_IN4</description>
45562 <description>EXTTRIG_IN5</description>
45567 <description>EXTTRIG_IN6</description>
45572 <description>EXTTRIG_IN7</description>
45577 <description>EXTTRIG_IN8</description>
45582 <description>EXTTRIG_IN9</description>
45587 <description>DMA0_TRIGOUT0</description>
45592 <description>DMA0_TRIGOUT1</description>
45597 <description>DMA0_TRIGOUT2</description>
45606 <description>ENC1 Input Connections</description>
45615 <description>ENC1 input trigger</description>
45622 <description>PIN_INT0</description>
45627 <description>PIN_INT5</description>
45632 <description>SCT_OUT4</description>
45637 <description>SCT_OUT5</description>
45642 <description>SCT_OUT7</description>
45647 <description>T0_MAT3</description>
45652 <description>T1_MAT3</description>
45657 <description>T2_MAT3</description>
45662 <description>T1_MAT1</description>
45667 <description>T3_MAT1</description>
45672 <description>COMP0_OUT</description>
45677 <description>ARM_TXEV</description>
45682 <description>GPIOINT_BMATCH</description>
45687 <description>ADC0_tcomp[0]</description>
45692 <description>ADC0_tcomp[1]</description>
45697 <description>ADC0_tcomp[2]</description>
45702 <description>ADC0_tcomp[3]</description>
45707 <description>ADC1_tcomp[0]</description>
45712 <description>ADC1_tcomp[1]</description>
45717 <description>ADC1_tcomp[2]</description>
45722 <description>ADC1_tcomp[3]</description>
45727 <description>HSCMP0_OUT</description>
45732 <description>HSCMP1_OUT</description>
45737 <description>HSCMP2_OUT</description>
45742 <description>PWM1_SM0_MUX_TRIG0</description>
45747 <description>PWM1_SM0_MUX_TRIG1</description>
45752 <description>PWM1_SM0_MUX_TRIG0</description>
45757 <description>PWM1_SM1_MUX_TRIG1</description>
45762 <description>PWM1_SM2_MUX_TRIG0</description>
45767 <description>PWM1_SM2_MUX_TRIG1</description>
45772 <description>PWM1_SM3_MUX_TRIG0</description>
45777 <description>PWM1_SM3_MUX_TRIG1</description>
45782 <description>ENC0_CMP/POS_MATCH</description>
45787 <description>ENC1_CMP/POS_MATCH</description>
45792 <description>AOI0_OUT0</description>
45797 <description>AOI0_OUT1</description>
45802 <description>AOI0_OUT2</description>
45807 <description>AOI0_OUT3</description>
45812 <description>AOI1_OUT0</description>
45817 <description>AOI1_OUT1</description>
45822 <description>AOI1_OUT2</description>
45827 <description>AOI1_OUT3</description>
45832 <description>EXTTRIG_IN0</description>
45837 <description>EXTTRIG_IN1</description>
45842 <description>EXTTRIG_IN2</description>
45847 <description>EXTTRIG_IN3</description>
45852 <description>EXTTRIG_IN4</description>
45857 <description>EXTTRIG_IN5</description>
45862 <description>EXTTRIG_IN6</description>
45867 <description>EXTTRIG_IN7</description>
45872 <description>EXTTRIG_IN8</description>
45877 <description>EXTTRIG_IN9</description>
45882 <description>DMA0_TRIGOUT0</description>
45887 <description>DMA0_TRIGOUT1</description>
45892 <description>DMA0_TRIGOUT2</description>
45901 <description>ENC1 Input Connections</description>
45910 <description>ENC1 input trigger</description>
45917 <description>PIN_INT0</description>
45922 <description>PIN_INT5</description>
45927 <description>SCT_OUT4</description>
45932 <description>SCT_OUT5</description>
45937 <description>SCT_OUT7</description>
45942 <description>T0_MAT3</description>
45947 <description>T1_MAT3</description>
45952 <description>T2_MAT3</description>
45957 <description>T1_MAT1</description>
45962 <description>T3_MAT1</description>
45967 <description>COMP0_OUT</description>
45972 <description>ARM_TXEV</description>
45977 <description>GPIOINT_BMATCH</description>
45982 <description>ADC0_tcomp[0]</description>
45987 <description>ADC0_tcomp[1]</description>
45992 <description>ADC0_tcomp[2]</description>
45997 <description>ADC0_tcomp[3]</description>
46002 <description>ADC1_tcomp[0]</description>
46007 <description>ADC1_tcomp[1]</description>
46012 <description>ADC1_tcomp[2]</description>
46017 <description>ADC1_tcomp[3]</description>
46022 <description>HSCMP0_OUT</description>
46027 <description>HSCMP1_OUT</description>
46032 <description>HSCMP2_OUT</description>
46037 <description>PWM1_SM0_MUX_TRIG0</description>
46042 <description>PWM1_SM0_MUX_TRIG1</description>
46047 <description>PWM1_SM0_MUX_TRIG0</description>
46052 <description>PWM1_SM1_MUX_TRIG1</description>
46057 <description>PWM1_SM2_MUX_TRIG0</description>
46062 <description>PWM1_SM2_MUX_TRIG1</description>
46067 <description>PWM1_SM3_MUX_TRIG0</description>
46072 <description>PWM1_SM3_MUX_TRIG1</description>
46077 <description>ENC0_CMP/POS_MATCH</description>
46082 <description>ENC1_CMP/POS_MATCH</description>
46087 <description>AOI0_OUT0</description>
46092 <description>AOI0_OUT1</description>
46097 <description>AOI0_OUT2</description>
46102 <description>AOI0_OUT3</description>
46107 <description>AOI1_OUT0</description>
46112 <description>AOI1_OUT1</description>
46117 <description>AOI1_OUT2</description>
46122 <description>AOI1_OUT3</description>
46127 <description>EXTTRIG_IN0</description>
46132 <description>EXTTRIG_IN1</description>
46137 <description>EXTTRIG_IN2</description>
46142 <description>EXTTRIG_IN3</description>
46147 <description>EXTTRIG_IN4</description>
46152 <description>EXTTRIG_IN5</description>
46157 <description>EXTTRIG_IN6</description>
46162 <description>EXTTRIG_IN7</description>
46167 <description>EXTTRIG_IN8</description>
46172 <description>EXTTRIG_IN9</description>
46177 <description>DMA0_TRIGOUT0</description>
46182 <description>DMA0_TRIGOUT1</description>
46187 <description>DMA0_TRIGOUT2</description>
46198 <description>PWM0 external synchronization</description>
46207 <description>Trigger input connections for PWM0</description>
46214 <description>PIN_INT0</description>
46219 <description>PIN_INT5</description>
46224 <description>SCT_OUT4</description>
46229 <description>SCT_OUT5</description>
46234 <description>SCT_OUT2</description>
46239 <description>T0_MAT3</description>
46244 <description>T1_MAT3</description>
46249 <description>T2_MAT3</description>
46254 <description>T2_MAT0</description>
46259 <description>T4_MAT0</description>
46264 <description>COMP0_OUT</description>
46269 <description>ARM_TXEV</description>
46274 <description>GPIOINT_BMATCH</description>
46279 <description>ADC0_tcomp[0]</description>
46284 <description>ADC0_tcomp[1]</description>
46289 <description>ADC0_tcomp[2]</description>
46294 <description>ADC0_tcomp[3]</description>
46299 <description>ADC1_tcomp[0]</description>
46304 <description>ADC1_tcomp[1]</description>
46309 <description>ADC1_tcomp[2]</description>
46314 <description>ADC1_tcomp[3]</description>
46319 <description>HSCMP0_OUT</description>
46324 <description>HSCMP1_OUT</description>
46329 <description>HSCMP2_OUT</description>
46334 <description>PWM1_SM0_MUX_TRIG0</description>
46339 <description>PWM1_SM0_MUX_TRIG1</description>
46344 <description>PWM1_SM0_MUX_TRIG0</description>
46349 <description>PWM1_SM1_MUX_TRIG1</description>
46354 <description>PWM1_SM2_MUX_TRIG0</description>
46359 <description>PWM1_SM2_MUX_TRIG1</description>
46364 <description>PWM1_SM3_MUX_TRIG0</description>
46369 <description>PWM1_SM3_MUX_TRIG1</description>
46374 <description>ENC0_CMP/POS_MATCH</description>
46379 <description>ENC1_CMP/POS_MATCH</description>
46384 <description>AOI0_OUT0</description>
46389 <description>AOI0_OUT1</description>
46394 <description>AOI0_OUT2</description>
46399 <description>AOI0_OUT3</description>
46404 <description>AOI1_OUT0</description>
46409 <description>AOI1_OUT1</description>
46414 <description>AOI1_OUT2</description>
46419 <description>AOI1_OUT3</description>
46424 <description>EXTTRIG_IN0</description>
46429 <description>EXTTRIG_IN1</description>
46434 <description>EXTTRIG_IN2</description>
46439 <description>EXTTRIG_IN3</description>
46444 <description>EXTTRIG_IN4</description>
46449 <description>EXTTRIG_IN5</description>
46454 <description>EXTTRIG_IN6</description>
46459 <description>EXTTRIG_IN7</description>
46464 <description>EXTTRIG_IN8</description>
46469 <description>EXTTRIG_IN9</description>
46474 <description>DMA0_TRIGOUT0</description>
46479 <description>DMA0_TRIGOUT1</description>
46484 <description>DMA0_TRIGOUT2</description>
46495 <description>PWM0 input trigger connections</description>
46504 <description>Trigger input connections for PWM0</description>
46511 <description>PIN_INT0</description>
46516 <description>PIN_INT5</description>
46521 <description>SCT_OUT4</description>
46526 <description>SCT_OUT5</description>
46531 <description>SCT_OUT2</description>
46536 <description>T0_MAT3</description>
46541 <description>T1_MAT3</description>
46546 <description>T2_MAT3</description>
46551 <description>T2_MAT0</description>
46556 <description>T4_MAT0</description>
46561 <description>COMP0_OUT</description>
46566 <description>ARM_TXEV</description>
46571 <description>GPIOINT_BMATCH</description>
46576 <description>ADC0_tcomp[0]</description>
46581 <description>ADC0_tcomp[1]</description>
46586 <description>ADC0_tcomp[2]</description>
46591 <description>ADC0_tcomp[3]</description>
46596 <description>ADC1_tcomp[0]</description>
46601 <description>ADC1_tcomp[1]</description>
46606 <description>ADC1_tcomp[2]</description>
46611 <description>ADC1_tcomp[3]</description>
46616 <description>HSCMP0_OUT</description>
46621 <description>HSCMP1_OUT</description>
46626 <description>HSCMP2_OUT</description>
46631 <description>PWM1_SM0_MUX_TRIG0</description>
46636 <description>PWM1_SM0_MUX_TRIG1</description>
46641 <description>PWM1_SM0_MUX_TRIG0</description>
46646 <description>PWM1_SM1_MUX_TRIG1</description>
46651 <description>PWM1_SM2_MUX_TRIG0</description>
46656 <description>PWM1_SM2_MUX_TRIG1</description>
46661 <description>PWM1_SM3_MUX_TRIG0</description>
46666 <description>PWM1_SM3_MUX_TRIG1</description>
46671 <description>ENC0_CMP/POS_MATCH</description>
46676 <description>ENC1_CMP/POS_MATCH</description>
46681 <description>AOI0_OUT0</description>
46686 <description>AOI0_OUT1</description>
46691 <description>AOI0_OUT2</description>
46696 <description>AOI0_OUT3</description>
46701 <description>AOI1_OUT0</description>
46706 <description>AOI1_OUT1</description>
46711 <description>AOI1_OUT2</description>
46716 <description>AOI1_OUT3</description>
46721 <description>EXTTRIG_IN0</description>
46726 <description>EXTTRIG_IN1</description>
46731 <description>EXTTRIG_IN2</description>
46736 <description>EXTTRIG_IN3</description>
46741 <description>EXTTRIG_IN4</description>
46746 <description>EXTTRIG_IN5</description>
46751 <description>EXTTRIG_IN6</description>
46756 <description>EXTTRIG_IN7</description>
46761 <description>EXTTRIG_IN8</description>
46766 <description>EXTTRIG_IN9</description>
46771 <description>DMA0_TRIGOUT0</description>
46776 <description>DMA0_TRIGOUT1</description>
46781 <description>DMA0_TRIGOUT2</description>
46790 <description>PWM0 external force trigger connections</description>
46799 <description>Trigger input connections for PWM0</description>
46806 <description>PIN_INT0</description>
46811 <description>PIN_INT5</description>
46816 <description>SCT_OUT4</description>
46821 <description>SCT_OUT5</description>
46826 <description>SCT_OUT2</description>
46831 <description>T0_MAT3</description>
46836 <description>T1_MAT3</description>
46841 <description>T2_MAT3</description>
46846 <description>T2_MAT0</description>
46851 <description>T4_MAT0</description>
46856 <description>COMP0_OUT</description>
46861 <description>ARM_TXEV</description>
46866 <description>GPIOINT_BMATCH</description>
46871 <description>ADC0_tcomp[0]</description>
46876 <description>ADC0_tcomp[1]</description>
46881 <description>ADC0_tcomp[2]</description>
46886 <description>ADC0_tcomp[3]</description>
46891 <description>ADC1_tcomp[0]</description>
46896 <description>ADC1_tcomp[1]</description>
46901 <description>ADC1_tcomp[2]</description>
46906 <description>ADC1_tcomp[3]</description>
46911 <description>HSCMP0_OUT</description>
46916 <description>HSCMP1_OUT</description>
46921 <description>HSCMP2_OUT</description>
46926 <description>PWM1_SM0_MUX_TRIG0</description>
46931 <description>PWM1_SM0_MUX_TRIG1</description>
46936 <description>PWM1_SM0_MUX_TRIG0</description>
46941 <description>PWM1_SM1_MUX_TRIG1</description>
46946 <description>PWM1_SM2_MUX_TRIG0</description>
46951 <description>PWM1_SM2_MUX_TRIG1</description>
46956 <description>PWM1_SM3_MUX_TRIG0</description>
46961 <description>PWM1_SM3_MUX_TRIG1</description>
46966 <description>ENC0_CMP/POS_MATCH</description>
46971 <description>ENC1_CMP/POS_MATCH</description>
46976 <description>AOI0_OUT0</description>
46981 <description>AOI0_OUT1</description>
46986 <description>AOI0_OUT2</description>
46991 <description>AOI0_OUT3</description>
46996 <description>AOI1_OUT0</description>
47001 <description>AOI1_OUT1</description>
47006 <description>AOI1_OUT2</description>
47011 <description>AOI1_OUT3</description>
47016 <description>EXTTRIG_IN0</description>
47021 <description>EXTTRIG_IN1</description>
47026 <description>EXTTRIG_IN2</description>
47031 <description>EXTTRIG_IN3</description>
47036 <description>EXTTRIG_IN4</description>
47041 <description>EXTTRIG_IN5</description>
47046 <description>EXTTRIG_IN6</description>
47051 <description>EXTTRIG_IN7</description>
47056 <description>EXTTRIG_IN8</description>
47061 <description>EXTTRIG_IN9</description>
47066 <description>DMA0_TRIGOUT0</description>
47071 <description>DMA0_TRIGOUT1</description>
47076 <description>DMA0_TRIGOUT2</description>
47087 <description>PWM0 fault input trigger connections</description>
47096 <description>Trigger input connections for PWM0</description>
47103 <description>PIN_INT0</description>
47108 <description>PIN_INT5</description>
47113 <description>SCT_OUT4</description>
47118 <description>SCT_OUT5</description>
47123 <description>SCT_OUT2</description>
47128 <description>T0_MAT3</description>
47133 <description>T1_MAT3</description>
47138 <description>T2_MAT3</description>
47143 <description>T2_MAT0</description>
47148 <description>T4_MAT0</description>
47153 <description>COMP0_OUT</description>
47158 <description>ARM_TXEV</description>
47163 <description>GPIOINT_BMATCH</description>
47168 <description>ADC0_tcomp[0]</description>
47173 <description>ADC0_tcomp[1]</description>
47178 <description>ADC0_tcomp[2]</description>
47183 <description>ADC0_tcomp[3]</description>
47188 <description>ADC1_tcomp[0]</description>
47193 <description>ADC1_tcomp[1]</description>
47198 <description>ADC1_tcomp[2]</description>
47203 <description>ADC1_tcomp[3]</description>
47208 <description>HSCMP0_OUT</description>
47213 <description>HSCMP1_OUT</description>
47218 <description>HSCMP2_OUT</description>
47223 <description>PWM1_SM0_MUX_TRIG0</description>
47228 <description>PWM1_SM0_MUX_TRIG1</description>
47233 <description>PWM1_SM0_MUX_TRIG0</description>
47238 <description>PWM1_SM1_MUX_TRIG1</description>
47243 <description>PWM1_SM2_MUX_TRIG0</description>
47248 <description>PWM1_SM2_MUX_TRIG1</description>
47253 <description>PWM1_SM3_MUX_TRIG0</description>
47258 <description>PWM1_SM3_MUX_TRIG1</description>
47263 <description>ENC0_CMP/POS_MATCH</description>
47268 <description>ENC1_CMP/POS_MATCH</description>
47273 <description>AOI0_OUT0</description>
47278 <description>AOI0_OUT1</description>
47283 <description>AOI0_OUT2</description>
47288 <description>AOI0_OUT3</description>
47293 <description>AOI1_OUT0</description>
47298 <description>AOI1_OUT1</description>
47303 <description>AOI1_OUT2</description>
47308 <description>AOI1_OUT3</description>
47313 <description>EXTTRIG_IN0</description>
47318 <description>EXTTRIG_IN1</description>
47323 <description>EXTTRIG_IN2</description>
47328 <description>EXTTRIG_IN3</description>
47333 <description>EXTTRIG_IN4</description>
47338 <description>EXTTRIG_IN5</description>
47343 <description>EXTTRIG_IN6</description>
47348 <description>EXTTRIG_IN7</description>
47353 <description>EXTTRIG_IN8</description>
47358 <description>EXTTRIG_IN9</description>
47363 <description>DMA0_TRIGOUT0</description>
47368 <description>DMA0_TRIGOUT1</description>
47373 <description>DMA0_TRIGOUT2</description>
47384 <description>PWM1 external synchronization</description>
47393 <description>Trigger input connections for PWM1</description>
47400 <description>PIN_INT0</description>
47405 <description>PIN_INT2</description>
47410 <description>SCT_OUT4</description>
47415 <description>SCT_OUT5</description>
47420 <description>SCT_OUT3</description>
47425 <description>T0_MAT3</description>
47430 <description>T1_MAT3</description>
47435 <description>T2_MAT3</description>
47440 <description>T2_MAT1</description>
47445 <description>T4_MAT1</description>
47450 <description>COMP0_OUT</description>
47455 <description>ARM_TXEV</description>
47460 <description>GPIOINT_BMATCH</description>
47465 <description>ADC0_tcomp[0]</description>
47470 <description>ADC0_tcomp[1]</description>
47475 <description>ADC0_tcomp[2]</description>
47480 <description>ADC0_tcomp[3]</description>
47485 <description>ADC1_tcomp[0]</description>
47490 <description>ADC1_tcomp[1]</description>
47495 <description>ADC1_tcomp[2]</description>
47500 <description>ADC1_tcomp[3]</description>
47505 <description>HSCMP0_OUT</description>
47510 <description>HSCMP1_OUT</description>
47515 <description>HSCMP2_OUT</description>
47520 <description>PWM0_SM0_MUX_TRIG0</description>
47525 <description>PWM0_SM0_MUX_TRIG1</description>
47530 <description>PWM0_SM1_MUX_TRIG0</description>
47535 <description>PWM0_SM1_MUX_TRIG1</description>
47540 <description>PWM0_SM2_MUX_TRIG0</description>
47545 <description>PWM0_SM2_MUX_TRIG1</description>
47550 <description>PWM0_SM3_MUX_TRIG0</description>
47555 <description>PWM0_SM3_MUX_TRIG1</description>
47560 <description>ENC0_CMP/POS_MATCH</description>
47565 <description>ENC1_CMP/POS_MATCH</description>
47570 <description>AOI0_OUT0</description>
47575 <description>AOI0_OUT1</description>
47580 <description>AOI0_OUT2</description>
47585 <description>AOI0_OUT3</description>
47590 <description>AOI1_OUT0</description>
47595 <description>AOI1_OUT1</description>
47600 <description>AOI1_OUT2</description>
47605 <description>AOI1_OUT3</description>
47610 <description>EXTTRIG_IN0</description>
47615 <description>EXTTRIG_IN1</description>
47620 <description>EXTTRIG_IN2</description>
47625 <description>EXTTRIG_IN3</description>
47630 <description>EXTTRIG_IN4</description>
47635 <description>EXTTRIG_IN5</description>
47640 <description>EXTTRIG_IN6</description>
47645 <description>EXTTRIG_IN7</description>
47650 <description>EXTTRIG_IN8</description>
47655 <description>EXTTRIG_IN9</description>
47660 <description>DMA0_TRIGOUT0</description>
47665 <description>DMA0_TRIGOUT1</description>
47670 <description>DMA0_TRIGOUT2</description>
47681 <description>PWM1 input trigger connections</description>
47690 <description>Trigger input connections for PWM1</description>
47697 <description>PIN_INT0</description>
47702 <description>PIN_INT2</description>
47707 <description>SCT_OUT4</description>
47712 <description>SCT_OUT5</description>
47717 <description>SCT_OUT3</description>
47722 <description>T0_MAT3</description>
47727 <description>T1_MAT3</description>
47732 <description>T2_MAT3</description>
47737 <description>T2_MAT1</description>
47742 <description>T4_MAT1</description>
47747 <description>COMP0_OUT</description>
47752 <description>ARM_TXEV</description>
47757 <description>GPIOINT_BMATCH</description>
47762 <description>ADC0_tcomp[0]</description>
47767 <description>ADC0_tcomp[1]</description>
47772 <description>ADC0_tcomp[2]</description>
47777 <description>ADC0_tcomp[3]</description>
47782 <description>ADC1_tcomp[0]</description>
47787 <description>ADC1_tcomp[1]</description>
47792 <description>ADC1_tcomp[2]</description>
47797 <description>ADC1_tcomp[3]</description>
47802 <description>HSCMP0_OUT</description>
47807 <description>HSCMP1_OUT</description>
47812 <description>HSCMP2_OUT</description>
47817 <description>PWM0_SM0_MUX_TRIG0</description>
47822 <description>PWM0_SM0_MUX_TRIG1</description>
47827 <description>PWM0_SM1_MUX_TRIG0</description>
47832 <description>PWM0_SM1_MUX_TRIG1</description>
47837 <description>PWM0_SM2_MUX_TRIG0</description>
47842 <description>PWM0_SM2_MUX_TRIG1</description>
47847 <description>PWM0_SM3_MUX_TRIG0</description>
47852 <description>PWM0_SM3_MUX_TRIG1</description>
47857 <description>ENC0_CMP/POS_MATCH</description>
47862 <description>ENC1_CMP/POS_MATCH</description>
47867 <description>AOI0_OUT0</description>
47872 <description>AOI0_OUT1</description>
47877 <description>AOI0_OUT2</description>
47882 <description>AOI0_OUT3</description>
47887 <description>AOI1_OUT0</description>
47892 <description>AOI1_OUT1</description>
47897 <description>AOI1_OUT2</description>
47902 <description>AOI1_OUT3</description>
47907 <description>EXTTRIG_IN0</description>
47912 <description>EXTTRIG_IN1</description>
47917 <description>EXTTRIG_IN2</description>
47922 <description>EXTTRIG_IN3</description>
47927 <description>EXTTRIG_IN4</description>
47932 <description>EXTTRIG_IN5</description>
47937 <description>EXTTRIG_IN6</description>
47942 <description>EXTTRIG_IN7</description>
47947 <description>EXTTRIG_IN8</description>
47952 <description>EXTTRIG_IN9</description>
47957 <description>DMA0_TRIGOUT0</description>
47962 <description>DMA0_TRIGOUT1</description>
47967 <description>DMA0_TRIGOUT2</description>
47976 <description>PWM1 external force trigger connections</description>
47985 <description>Trigger input connections for PWM1</description>
47992 <description>PIN_INT0</description>
47997 <description>PIN_INT2</description>
48002 <description>SCT_OUT4</description>
48007 <description>SCT_OUT5</description>
48012 <description>SCT_OUT3</description>
48017 <description>T0_MAT3</description>
48022 <description>T1_MAT3</description>
48027 <description>T2_MAT3</description>
48032 <description>T2_MAT1</description>
48037 <description>T4_MAT1</description>
48042 <description>COMP0_OUT</description>
48047 <description>ARM_TXEV</description>
48052 <description>GPIOINT_BMATCH</description>
48057 <description>ADC0_tcomp[0]</description>
48062 <description>ADC0_tcomp[1]</description>
48067 <description>ADC0_tcomp[2]</description>
48072 <description>ADC0_tcomp[3]</description>
48077 <description>ADC1_tcomp[0]</description>
48082 <description>ADC1_tcomp[1]</description>
48087 <description>ADC1_tcomp[2]</description>
48092 <description>ADC1_tcomp[3]</description>
48097 <description>HSCMP0_OUT</description>
48102 <description>HSCMP1_OUT</description>
48107 <description>HSCMP2_OUT</description>
48112 <description>PWM0_SM0_MUX_TRIG0</description>
48117 <description>PWM0_SM0_MUX_TRIG1</description>
48122 <description>PWM0_SM1_MUX_TRIG0</description>
48127 <description>PWM0_SM1_MUX_TRIG1</description>
48132 <description>PWM0_SM2_MUX_TRIG0</description>
48137 <description>PWM0_SM2_MUX_TRIG1</description>
48142 <description>PWM0_SM3_MUX_TRIG0</description>
48147 <description>PWM0_SM3_MUX_TRIG1</description>
48152 <description>ENC0_CMP/POS_MATCH</description>
48157 <description>ENC1_CMP/POS_MATCH</description>
48162 <description>AOI0_OUT0</description>
48167 <description>AOI0_OUT1</description>
48172 <description>AOI0_OUT2</description>
48177 <description>AOI0_OUT3</description>
48182 <description>AOI1_OUT0</description>
48187 <description>AOI1_OUT1</description>
48192 <description>AOI1_OUT2</description>
48197 <description>AOI1_OUT3</description>
48202 <description>EXTTRIG_IN0</description>
48207 <description>EXTTRIG_IN1</description>
48212 <description>EXTTRIG_IN2</description>
48217 <description>EXTTRIG_IN3</description>
48222 <description>EXTTRIG_IN4</description>
48227 <description>EXTTRIG_IN5</description>
48232 <description>EXTTRIG_IN6</description>
48237 <description>EXTTRIG_IN7</description>
48242 <description>EXTTRIG_IN8</description>
48247 <description>EXTTRIG_IN9</description>
48252 <description>DMA0_TRIGOUT0</description>
48257 <description>DMA0_TRIGOUT1</description>
48262 <description>DMA0_TRIGOUT2</description>
48273 <description>PWM1 fault input trigger connections</description>
48282 <description>Trigger input connections for PWM1</description>
48289 <description>PIN_INT0</description>
48294 <description>PIN_INT2</description>
48299 <description>SCT_OUT4</description>
48304 <description>SCT_OUT5</description>
48309 <description>SCT_OUT3</description>
48314 <description>T0_MAT3</description>
48319 <description>T1_MAT3</description>
48324 <description>T2_MAT3</description>
48329 <description>T2_MAT1</description>
48334 <description>T4_MAT1</description>
48339 <description>COMP0_OUT</description>
48344 <description>ARM_TXEV</description>
48349 <description>GPIOINT_BMATCH</description>
48354 <description>ADC0_tcomp[0]</description>
48359 <description>ADC0_tcomp[1]</description>
48364 <description>ADC0_tcomp[2]</description>
48369 <description>ADC0_tcomp[3]</description>
48374 <description>ADC1_tcomp[0]</description>
48379 <description>ADC1_tcomp[1]</description>
48384 <description>ADC1_tcomp[2]</description>
48389 <description>ADC1_tcomp[3]</description>
48394 <description>HSCMP0_OUT</description>
48399 <description>HSCMP1_OUT</description>
48404 <description>HSCMP2_OUT</description>
48409 <description>PWM0_SM0_MUX_TRIG0</description>
48414 <description>PWM0_SM0_MUX_TRIG1</description>
48419 <description>PWM0_SM1_MUX_TRIG0</description>
48424 <description>PWM0_SM1_MUX_TRIG1</description>
48429 <description>PWM0_SM2_MUX_TRIG0</description>
48434 <description>PWM0_SM2_MUX_TRIG1</description>
48439 <description>PWM0_SM3_MUX_TRIG0</description>
48444 <description>PWM0_SM3_MUX_TRIG1</description>
48449 <description>ENC0_CMP/POS_MATCH</description>
48454 <description>ENC1_CMP/POS_MATCH</description>
48459 <description>AOI0_OUT0</description>
48464 <description>AOI0_OUT1</description>
48469 <description>AOI0_OUT2</description>
48474 <description>AOI0_OUT3</description>
48479 <description>AOI1_OUT0</description>
48484 <description>AOI1_OUT1</description>
48489 <description>AOI1_OUT2</description>
48494 <description>AOI1_OUT3</description>
48499 <description>EXTTRIG_IN0</description>
48504 <description>EXTTRIG_IN1</description>
48509 <description>EXTTRIG_IN2</description>
48514 <description>EXTTRIG_IN3</description>
48519 <description>EXTTRIG_IN4</description>
48524 <description>EXTTRIG_IN5</description>
48529 <description>EXTTRIG_IN6</description>
48534 <description>EXTTRIG_IN7</description>
48539 <description>EXTTRIG_IN8</description>
48544 <description>EXTTRIG_IN9</description>
48549 <description>DMA0_TRIGOUT0</description>
48554 <description>DMA0_TRIGOUT1</description>
48559 <description>DMA0_TRIGOUT2</description>
48568 <description>PWM0 external clock trigger connections</description>
48577 <description>Trigger input connections for PWM0</description>
48584 <description>PIN_INT0</description>
48589 <description>PIN_INT5</description>
48594 <description>SCT_OUT4</description>
48599 <description>SCT_OUT5</description>
48604 <description>SCT_OUT2</description>
48609 <description>T0_MAT3</description>
48614 <description>T1_MAT3</description>
48619 <description>T2_MAT3</description>
48624 <description>T2_MAT0</description>
48629 <description>T4_MAT0</description>
48634 <description>COMP0_OUT</description>
48639 <description>ARM_TXEV</description>
48644 <description>GPIOINT_BMATCH</description>
48649 <description>ADC0_tcomp[0]</description>
48654 <description>ADC0_tcomp[1]</description>
48659 <description>ADC0_tcomp[2]</description>
48664 <description>ADC0_tcomp[3]</description>
48669 <description>ADC1_tcomp[0]</description>
48674 <description>ADC1_tcomp[1]</description>
48679 <description>ADC1_tcomp[2]</description>
48684 <description>ADC1_tcomp[3]</description>
48689 <description>HSCMP0_OUT</description>
48694 <description>HSCMP1_OUT</description>
48699 <description>HSCMP2_OUT</description>
48704 <description>PWM1_SM0_MUX_TRIG0</description>
48709 <description>PWM1_SM0_MUX_TRIG1</description>
48714 <description>PWM1_SM0_MUX_TRIG0</description>
48719 <description>PWM1_SM1_MUX_TRIG1</description>
48724 <description>PWM1_SM2_MUX_TRIG0</description>
48729 <description>PWM1_SM2_MUX_TRIG1</description>
48734 <description>PWM1_SM3_MUX_TRIG0</description>
48739 <description>PWM1_SM3_MUX_TRIG1</description>
48744 <description>ENC0_CMP/POS_MATCH</description>
48749 <description>ENC1_CMP/POS_MATCH</description>
48754 <description>AOI0_OUT0</description>
48759 <description>AOI0_OUT1</description>
48764 <description>AOI0_OUT2</description>
48769 <description>AOI0_OUT3</description>
48774 <description>AOI1_OUT0</description>
48779 <description>AOI1_OUT1</description>
48784 <description>AOI1_OUT2</description>
48789 <description>AOI1_OUT3</description>
48794 <description>EXTTRIG_IN0</description>
48799 <description>EXTTRIG_IN1</description>
48804 <description>EXTTRIG_IN2</description>
48809 <description>EXTTRIG_IN3</description>
48814 <description>EXTTRIG_IN4</description>
48819 <description>EXTTRIG_IN5</description>
48824 <description>EXTTRIG_IN6</description>
48829 <description>EXTTRIG_IN7</description>
48834 <description>EXTTRIG_IN8</description>
48839 <description>EXTTRIG_IN9</description>
48844 <description>DMA0_TRIGOUT0</description>
48849 <description>DMA0_TRIGOUT1</description>
48854 <description>DMA0_TRIGOUT2</description>
48863 <description>PWM1 external clock trigger connections</description>
48872 <description>Trigger input connections for PWM1</description>
48879 <description>PIN_INT0</description>
48884 <description>PIN_INT2</description>
48889 <description>SCT_OUT4</description>
48894 <description>SCT_OUT5</description>
48899 <description>SCT_OUT3</description>
48904 <description>T0_MAT3</description>
48909 <description>T1_MAT3</description>
48914 <description>T2_MAT3</description>
48919 <description>T2_MAT1</description>
48924 <description>T4_MAT1</description>
48929 <description>COMP0_OUT</description>
48934 <description>ARM_TXEV</description>
48939 <description>GPIOINT_BMATCH</description>
48944 <description>ADC0_tcomp[0]</description>
48949 <description>ADC0_tcomp[1]</description>
48954 <description>ADC0_tcomp[2]</description>
48959 <description>ADC0_tcomp[3]</description>
48964 <description>ADC1_tcomp[0]</description>
48969 <description>ADC1_tcomp[1]</description>
48974 <description>ADC1_tcomp[2]</description>
48979 <description>ADC1_tcomp[3]</description>
48984 <description>HSCMP0_OUT</description>
48989 <description>HSCMP1_OUT</description>
48994 <description>HSCMP2_OUT</description>
48999 <description>PWM0_SM0_MUX_TRIG0</description>
49004 <description>PWM0_SM0_MUX_TRIG1</description>
49009 <description>PWM0_SM1_MUX_TRIG0</description>
49014 <description>PWM0_SM1_MUX_TRIG1</description>
49019 <description>PWM0_SM2_MUX_TRIG0</description>
49024 <description>PWM0_SM2_MUX_TRIG1</description>
49029 <description>PWM0_SM3_MUX_TRIG0</description>
49034 <description>PWM0_SM3_MUX_TRIG1</description>
49039 <description>ENC0_CMP/POS_MATCH</description>
49044 <description>ENC1_CMP/POS_MATCH</description>
49049 <description>AOI0_OUT0</description>
49054 <description>AOI0_OUT1</description>
49059 <description>AOI0_OUT2</description>
49064 <description>AOI0_OUT3</description>
49069 <description>AOI1_OUT0</description>
49074 <description>AOI1_OUT1</description>
49079 <description>AOI1_OUT2</description>
49084 <description>AOI1_OUT3</description>
49089 <description>EXTTRIG_IN0</description>
49094 <description>EXTTRIG_IN1</description>
49099 <description>EXTTRIG_IN2</description>
49104 <description>EXTTRIG_IN3</description>
49109 <description>EXTTRIG_IN4</description>
49114 <description>EXTTRIG_IN5</description>
49119 <description>EXTTRIG_IN6</description>
49124 <description>EXTTRIG_IN7</description>
49129 <description>EXTTRIG_IN8</description>
49134 <description>EXTTRIG_IN9</description>
49139 <description>DMA0_TRIGOUT0</description>
49144 <description>DMA0_TRIGOUT1</description>
49149 <description>DMA0_TRIGOUT2</description>
49160 <description>no description available</description>
49166 <description>AOIn trigger inputs</description>
49175 <description>Input trigger assignments</description>
49182 <description>PIN_INT0</description>
49187 <description>PIN_INT1</description>
49192 <description>SCT_OUT0</description>
49197 <description>SCT_OUT1</description>
49202 <description>SCT_OUT2</description>
49207 <description>SCT_OUT3</description>
49212 <description>T0_MAT3</description>
49217 <description>T1_MAT3</description>
49222 <description>T2_MAT3</description>
49227 <description>T2_MAT2</description>
49232 <description>T3_MAT2</description>
49237 <description>T4_MAT2</description>
49242 <description>COMP0_OUT</description>
49247 <description>GPIOINT_BMATCH</description>
49252 <description>ADC0_IRQ</description>
49257 <description>ADC1_IRQ</description>
49262 <description>ADC0_tcomp[0]</description>
49267 <description>ADC0_tcomp[1]</description>
49272 <description>ADC0_tcomp[2]</description>
49277 <description>ADC0_tcomp[3]</description>
49282 <description>ADC1_tcomp[0]</description>
49287 <description>ADC1_tcomp[1]</description>
49292 <description>ADC1_tcomp[2]</description>
49297 <description>ADC1_tcomp[3]</description>
49302 <description>HSCMP0_OUT</description>
49307 <description>HSCMP1_OUT</description>
49312 <description>HSCMP2_OUT</description>
49317 <description>PWM0_SM0_MUX_TRIG0</description>
49322 <description>PWM0_SM0_MUX_TRIG1</description>
49327 <description>PWM0_SM1_MUX_TRIG0</description>
49332 <description>PWM0_SM1_MUX_TRIG1</description>
49337 <description>PWM0_SM2_MUX_TRIG0</description>
49342 <description>PWM0_SM2_MUX_TRIG1</description>
49347 <description>PWM0_SM3_MUX_TRIG0</description>
49352 <description>PWM0_SM3_MUX_TRIG1</description>
49357 <description>PWM1_SM0_MUX_TRIG0</description>
49362 <description>PWM1_SM0_MUX_TRIG1</description>
49367 <description>PWM1_SM0_MUX_TRIG0</description>
49372 <description>PWM1_SM1_MUX_TRIG1</description>
49377 <description>PWM1_SM2_MUX_TRIG0</description>
49382 <description>PWM1_SM2_MUX_TRIG1</description>
49387 <description>PWM1_SM3_MUX_TRIG0</description>
49392 <description>PWM1_SM3_MUX_TRIG1</description>
49397 <description>ENC0_CMP/POS_MATCH</description>
49402 <description>ENC1_CMP/POS_MATCH</description>
49407 <description>EXTTRIG_IN0</description>
49412 <description>EXTTRIG_IN1</description>
49417 <description>EXTTRIG_IN2</description>
49422 <description>EXTTRIG_IN2</description>
49427 <description>DMA0_TRIGOUT0</description>
49432 <description>DMA0_TRIGOUT1</description>
49437 <description>DMA0_TRIGOUT2</description>
49442 <description>DMA0_TRIGOUT3</description>
49447 <description>DMA0_TRIGOUT4</description>
49452 <description>DMA0_TRIGOUT5</description>
49457 <description>DMA0_TRIGOUT6</description>
49462 <description>DMA1_TRIGOUT0</description>
49467 <description>DMA1_TRIGOUT1</description>
49472 <description>DMA1_TRIGOUT2</description>
49484 <description>AOI External Trigger Inputs</description>
49493 <description>AOI external trigger inputs from 0 to 4.</description>
49500 <description>PIN_INT0</description>
49505 <description>PIN_INT1</description>
49510 <description>ADC0_IRQ</description>
49515 <description>ADC1_IRQ</description>
49520 <description>ADC0_tcomp[0]</description>
49525 <description>ADC1_tcomp[0]</description>
49530 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
49535 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
49540 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
49545 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
49550 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
49555 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
49560 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
49565 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
49570 <description>ENC0_CMP/POS_MATCH</description>
49575 <description>ENC1_CMP/POS_MATCH</description>
49580 <description>AOI0_OUT0</description>
49585 <description>AOI0_OUT1</description>
49590 <description>AOI0_OUT2</description>
49595 <description>AOI0_OUT3</description>
49600 <description>AOI1_OUT0</description>
49605 <description>AOI1_OUT1</description>
49610 <description>AOI1_OUT2</description>
49615 <description>AOI1_OUT3</description>
49620 <description>TMPR_OUT</description>
49625 <description>None</description>
49630 <description>None</description>
49635 <description>None</description>
49640 <description>None</description>
49645 <description>None</description>
49650 <description>None</description>
49655 <description>None</description>
49664 <description>Input connections for HSCMP1</description>
49673 <description>CMP1 input trigger</description>
49680 <description>PIN_INT0</description>
49685 <description>PIN_INT7</description>
49690 <description>SCT_OUT4</description>
49695 <description>SCT_OUT5</description>
49700 <description>SCT_OUT7</description>
49705 <description>T0_MAT3</description>
49710 <description>T1_MAT3</description>
49715 <description>T2_MAT3</description>
49720 <description>T0_MAT1</description>
49725 <description>T4_MAT1</description>
49730 <description>ARM_TXEV</description>
49735 <description>GPIOINT_BMATCH</description>
49740 <description>ADC0_tcomp[1]</description>
49745 <description>ADC1_tcomp[1]</description>
49750 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
49755 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
49760 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
49765 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
49770 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
49775 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
49780 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
49785 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
49790 <description>ENC0_CMP/POS_MATCH</description>
49795 <description>ENC1_CMP/POS_MATCH</description>
49800 <description>AOI0_OUT0</description>
49805 <description>AOI0_OUT1</description>
49810 <description>AOI0_OUT2</description>
49815 <description>AOI0_OUT3</description>
49820 <description>AOI1_OUT0</description>
49825 <description>AOI1_OUT1</description>
49830 <description>AOI1_OUT2</description>
49835 <description>AOI1_OUT3</description>
49840 <description>DMA0_TRIGOUT0</description>
49845 <description>DMA0_TRIGOUT1</description>
49850 <description>DMA0_TRIGOUT2</description>
49859 <description>Input connections for HSCMP2</description>
49868 <description>CMP2 input trigger</description>
49875 <description>PIN_INT0</description>
49880 <description>PIN_INT4</description>
49885 <description>SCT_OUT4</description>
49890 <description>SCT_OUT5</description>
49895 <description>SCT_OUT8</description>
49900 <description>T0_MAT3</description>
49905 <description>T1_MAT3</description>
49910 <description>T2_MAT3</description>
49915 <description>T0_MAT2</description>
49920 <description>T4_MAT2</description>
49925 <description>ARM_TXEV</description>
49930 <description>GPIOINT_BMATCH</description>
49935 <description>ADC0_tcomp[2]</description>
49940 <description>ADC1_tcomp[2]</description>
49945 <description>PWM0_SM0_MUX_TRIG0 | PWM0_SM0_MUX_TRIG1</description>
49950 <description>PWM0_SM1_MUX_TRIG0 | PWM0_SM1_MUX_TRIG1</description>
49955 <description>PWM0_SM2_MUX_TRIG0 | PWM0_SM2_MUX_TRIG1</description>
49960 <description>PWM0_SM3_MUX_TRIG0 | PWM0_SM3_MUX_TRIG1</description>
49965 <description>PWM1_SM0_MUX_TRIG0 | PWM1_SM0_MUX_TRIG1</description>
49970 <description>PWM1_SM1_MUX_TRIG0 | PWM1_SM1_MUX_TRIG1</description>
49975 <description>PWM1_SM2_MUX_TRIG0 | PWM1_SM2_MUX_TRIG1</description>
49980 <description>PWM1_SM3_MUX_TRIG0 | PWM1_SM3_MUX_TRIG1</description>
49985 <description>ENC0_CMP/POS_MATCH</description>
49990 <description>ENC1_CMP/POS_MATCH</description>
49995 <description>AOI0_OUT0</description>
50000 <description>AOI0_OUT1</description>
50005 <description>AOI0_OUT2</description>
50010 <description>AOI0_OUT3</description>
50015 <description>AOI1_OUT0</description>
50020 <description>AOI1_OUT1</description>
50025 <description>AOI1_OUT2</description>
50030 <description>AOI1_OUT3</description>
50035 <description>DMA0_TRIGOUT0</description>
50040 <description>DMA0_TRIGOUT1</description>
50045 <description>DMA0_TRIGOUT2</description>
50057 <description>Trigger select for DMA0 channel</description>
50066 … <description>Trigger input number (decimal value) for DMA channel n (n = 32 to 51).</description>
50073 <description>FlexSPI_RX</description>
50078 <description>FlexSPI_TX</description>
50083 <description>GPIO_INT0</description>
50088 <description>GPIO_INT1</description>
50093 <description>GPIO_INT2</description>
50098 <description>GPIO_INT3</description>
50103 <description>T0_DMAREQ_M0</description>
50108 <description>T0_DMAREQ_M1</description>
50113 <description>T1_DMAREQ_M0</description>
50118 <description>T1_DMAREQ_M1</description>
50123 <description>T2_DMAREQ_M0</description>
50128 <description>T2_DMAREQ_M1</description>
50133 <description>T3_DMAREQ_M0</description>
50138 <description>T3_DMAREQ_M1</description>
50143 <description>T4_DMAREQ_M0</description>
50148 <description>T4_DMAREQ_M1</description>
50153 <description>COMP0_OUT</description>
50158 <description>SDMA0_TRIGOUT_A</description>
50163 <description>SDMA0_TRIGOUT_B</description>
50168 <description>SDMA0_TRIGOUT_C</description>
50173 <description>SDMA0_TRIGOUT_D</description>
50178 <description>SCT_DMA0</description>
50183 <description>SCT_DMA1</description>
50188 <description>ADC0_tcomp[0]</description>
50193 <description>ADC1_tcomp[0]</description>
50198 <description>HSCMP0</description>
50203 <description>HSCMP1</description>
50208 <description>HSCMP2</description>
50213 <description>AOI0_OUT0</description>
50218 <description>AOI0_OUT1</description>
50223 <description>AOI0_OUT2</description>
50228 <description>AOI0_OUT3</description>
50233 <description>AOI1_OUT0</description>
50238 <description>AOI1_OUT1</description>
50243 <description>AOI1_OUT2</description>
50248 <description>AOI1_OUT3</description>
50253 <description>FlexPWM0_req_capt0</description>
50258 <description>FlexPWM0_req_capt1</description>
50263 <description>FlexPWM0_req_capt2</description>
50268 <description>FlexPWM0_req_capt3</description>
50273 <description>FlexPWM0_req_val0</description>
50278 <description>FlexPWM0_req_val1</description>
50283 <description>FlexPWM0_req_val2</description>
50288 <description>FlexPWM0_req_val3</description>
50293 <description>FlexPWM1_req_capt0</description>
50298 <description>FlexPWM1_req_capt1</description>
50303 <description>FlexPWM1_req_capt2</description>
50308 <description>FlexPWM1_req_capt3</description>
50313 <description>FlexPWM1_req_val0</description>
50318 <description>FlexPWM1_req_val1</description>
50323 <description>FlexPWM1_req_val2</description>
50328 <description>FlexPWM1_req_val3</description>
50333 <description>TMPR_OUT</description>
50342 <description>Enable DMA0 requests</description>
50351 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50358 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50365 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50372 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50379 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50386 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50393 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50400 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50407 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50414 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50421 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50428 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50435 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50442 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50449 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50456 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50463 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50470 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50477 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50484 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50491 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50498 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50505 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50512 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50519 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50526 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50533 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50540 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50547 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50554 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50561 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50568 …<description>Controls the first 32 request inputs of DMA0. If bit i is '1' the DMA request input #…
50577 <description>Enable DMA0 requests</description>
50586 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50593 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50600 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50607 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50614 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50621 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50628 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50635 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50642 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50649 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50656 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50663 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50670 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50677 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50684 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50691 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50698 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50705 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50712 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50719 …<description>Controls the remaining 20 request inputs of DMA0. If bit i is '1' the DMA request inp…
50728 <description>Set bits in DMA0_REQEN0 register</description>
50737 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50744 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50751 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50758 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50765 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50772 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50779 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50786 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50793 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50800 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50807 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50814 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50821 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50828 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50835 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50842 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50849 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50856 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50863 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50870 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50877 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50884 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50891 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50898 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50905 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50912 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50919 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50926 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50933 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50940 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50947 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50954 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is set to 1; if bit #i = 0, no …
50963 <description>DMA0 Request Eb</description>
50972 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
50979 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
50986 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
50993 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51000 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51007 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51014 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51021 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51028 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51035 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51042 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51049 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51056 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51063 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51070 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51077 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51084 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51091 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51098 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51105 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is set to 1; if bit #i = 0, no …
51114 <description>Clear bits in DMA0_REQEN0 register</description>
51123 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51130 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51137 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51144 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51151 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51158 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51165 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51172 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51179 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51186 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51193 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51200 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51207 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51214 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51221 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51228 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51235 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51242 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51249 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51256 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51263 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51270 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51277 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51284 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51291 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51298 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51305 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51312 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51319 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51326 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51333 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51340 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN0 register is reset to 0; if bit #i = 0 , …
51349 <description>Clear bits in DMA0_REQEN1 register</description>
51358 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51365 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51372 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51379 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51386 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51393 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51400 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51407 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51414 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51421 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51428 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51435 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51442 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51449 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51456 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51463 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51470 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51477 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51484 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51491 …<description>Write : If bit #i = 1, bit #i in DMA0_REQEN1 register is reset to 0; if bit #i = 0 , …
51500 <description>Enable DMA1 requests</description>
51509 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51516 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51523 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51530 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51537 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51544 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51551 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51558 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51565 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51572 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51579 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51586 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51593 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51600 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51607 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51614 …<description>Controls the 16 request inputs of DMA1. If bit i is '1' the DMA request input #i is e…
51623 <description>Set bits in DMA1_REQEN register</description>
51632 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51639 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51646 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51653 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51660 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51667 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51674 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51681 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51688 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51695 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51702 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51709 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51716 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51723 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51730 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51737 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is set to 1; if bit #i = 0 , no …
51746 <description>Clear bits in DMA1_REQEN register</description>
51755 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51762 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51769 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51776 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51783 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51790 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51797 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51804 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51811 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51818 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51825 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51832 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51839 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51846 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51853 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51860 …<description>Write : If bit #i = 1, bit #i in DMA1_REQEN register is reset to 0; if bit #i = 0 , n…
51869 <description>Enable DMA0 triggers</description>
51878 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51885 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51892 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51899 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51906 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51913 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51920 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51927 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51934 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51941 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51948 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51955 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51962 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51969 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51976 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51983 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51990 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
51997 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52004 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52011 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52018 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52025 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52032 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52039 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52046 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52053 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52060 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52067 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52074 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52081 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52088 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52095 …<description>Controls the 32 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is e…
52104 <description>Enable DMA0 triggers</description>
52113 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52120 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52127 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52134 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52141 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52148 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52155 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52162 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52169 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52176 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52183 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52190 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52197 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52204 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52211 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52218 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52225 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52232 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52239 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52246 …<description>Controls the remaining 20 trigger inputs of DMA0. If bit i is '1' the DMA trigger inp…
52255 <description>Set bits in DMA0_ITRIGEN0 register</description>
52264 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52271 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52278 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52285 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52292 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52299 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52306 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52313 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52320 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52327 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52334 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52341 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52348 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52355 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52362 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52369 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52376 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52383 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52390 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52397 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52404 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52411 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52418 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52425 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52432 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52439 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52446 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52453 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52460 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52467 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52474 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52481 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is set to 1; if bit #i = 0 , …
52490 <description>Set bits in DMA0_ITRIGEN1 register</description>
52499 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52506 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52513 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52520 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52527 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52534 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52541 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52548 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52555 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52562 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52569 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52576 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52583 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52590 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52597 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52604 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52611 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52618 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52625 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52632 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52639 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52646 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52653 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52660 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52667 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52674 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52681 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52688 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52695 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52702 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52709 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52716 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is set to 1; if bit #i = 0 , …
52725 <description>Clear bits in DMA0_ITRIGEN0 register</description>
52734 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52741 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52748 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52755 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52762 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52769 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52776 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52783 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52790 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52797 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52804 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52811 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52818 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52825 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52832 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52839 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52846 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52853 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52860 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52867 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52874 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52881 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52888 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52895 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52902 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52909 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52916 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52923 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52930 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52937 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52944 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52951 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN0 register is reset to 0; if bit #i = 0 …
52960 <description>Clear bits in DMA0_ITRIGEN1 register</description>
52969 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
52976 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
52983 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
52990 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
52997 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53004 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53011 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53018 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53025 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53032 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53039 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53046 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53053 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53060 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53067 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53074 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53081 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53088 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53095 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53102 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53109 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53116 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53123 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53130 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53137 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53144 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53151 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53158 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53165 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53172 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53179 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53186 …<description>Write : If bit #i = 1, bit #i in DMA0_ITRIGEN1 register is reset to 0; if bit #i = 0 …
53195 <description>Enable DMA1 triggers</description>
53204 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53211 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53218 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53225 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53232 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53239 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53246 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53253 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53260 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53267 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53274 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53281 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53288 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53295 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53302 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53309 …<description>Controls the 16 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is e…
53318 <description>Set bits in DMA1_ITRIGEN register</description>
53327 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53334 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53341 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53348 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53355 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53362 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53369 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53376 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53383 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53390 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53397 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53404 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53411 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53418 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53425 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53432 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is set to 1; if bit #i = 0 , n…
53441 <description>Clear bits in DMA1_ITRIGEN register</description>
53450 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53457 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53464 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53471 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53478 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53485 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53492 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53499 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53506 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53513 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53520 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53527 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53534 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53541 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53548 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53555 …<description>Write : If bit #i = 1, bit #i in DMA1_ITRIGEN register is reset to 0; if bit #i = 0 ,…
53566 <description>Frequency Measurement</description>
53577 <description>Frequency Measurement (in Read mode)</description>
53587 <description>Result</description>
53594 <description>Measure in Progress</description>
53601 …<description>Process complete. Measurement cycle is complete. The results are ready in the RESULT …
53606 <description>In Progress. Measurement cycle is in progress.</description>
53615 <description>Frequency Measurement (in Write mode)</description>
53625 <description>Reference Clock Scaling Factor</description>
53632 <description>Count cycle = 2 ^ 0 = 1</description>
53637 <description>Count cycle = 2 ^ 1 = 2</description>
53642 <description>Count cycle = 2 ^ 2 = 4</description>
53647 <description>Count cycle = 2 ^ 31 = 2,147,483,648</description>
53654 <description>Pulse Width Measurement mode select</description>
53661 …description>Frequency Measurement Mode. FREQMECTRL works in a Frequency Measurement mode. Once the…
53666 …description>Pulse Width Measurement mode. FREQMECTRL works in a Pulse Width Measurement mode, meas…
53673 <description>Pulse Polarity</description>
53680 …description>High Period. High period of reference clock is measured in Pulse Width Measurement mod…
53685 …description>Low Period. Low period of reference clock is measured in Pulse Width Measurement mode …
53692 <description>Less Than Minimum Interrupt Enable</description>
53699 <description>Disable</description>
53704 <description>Enable</description>
53711 <description>Greater Than Maximum Interrupt Enable</description>
53718 <description>Disable</description>
53723 <description>Enable</description>
53730 <description>Result Ready Interrupt Enable</description>
53737 <description>Disable</description>
53742 <description>Enable</description>
53749 <description>Continuous Mode Enable</description>
53756 <description>Disable</description>
53761 <description>Enable</description>
53768 <description>Measure in Progress</description>
53775 <description>Force Terminate</description>
53780 <description>Initiates Measurement Cycle</description>
53789 <description>Frequency Measurement Control Status</description>
53798 <description>Reference Scale Value</description>
53805 <description>Pulse Mode Status</description>
53812 <description>Pulse Polarity Status</description>
53819 <description>Less Than Minimum Interrupt Enable Status</description>
53826 <description>Greater Then Maximum Interrupt Enable Status</description>
53833 <description>Result Ready Interrupt Enable Status</description>
53840 <description>Less Than Minimum Results Status</description>
53848 <description>Greater Than Maximum Result Status</description>
53856 <description>Result Ready Status</description>
53864 <description>Continuous Mode Enable Status</description>
53871 <description>Measure in Progress Status</description>
53880 <description>Frequency Measurement Minimum</description>
53889 <description>Minumum Value</description>
53898 <description>Frequency Measurement Maximum</description>
53907 <description>Maximum Value</description>
53918 <description>Counter/Timer</description>
53934 <description>Interrupt Register.</description>
53943 <description>Interrupt flag for match channel 0</description>
53950 <description>Interrupt flag for match channel 1</description>
53957 <description>Interrupt flag for match channel 2</description>
53964 <description>Interrupt flag for match channel 3</description>
53971 <description>Interrupt flag for capture channel 0 event</description>
53978 <description>Interrupt flag for capture channel 1 event</description>
53985 <description>Interrupt flag for capture channel 2 event</description>
53992 <description>Interrupt flag for capture channel 3 event</description>
54001 <description>Timer Control Register</description>
54010 <description>Counter enable.</description>
54017 <description>Disabled. The counters are disabled.</description>
54022 …description>Enabled. The Timer Counter and Prescale Counter are enabled. When the timer is enabled…
54029 <description>Counter reset.</description>
54036 <description>Disabled. Do nothing.</description>
54041 <description>Enabled</description>
54048 <description>Allow Global Count Enable</description>
54055 <description>Not allowed</description>
54060 <description>Allow input global_enable=1 action to take effect</description>
54067 <description>Allow Trigger Count Enable</description>
54074 <description>Not allowed</description>
54079 <description>Allow input trigger_enable=1 action to take effect</description>
54088 <description>Timer Counter</description>
54097 <description>Timer counter value.</description>
54106 <description>Prescale Register</description>
54115 <description>Prescale reload value.</description>
54124 <description>Prescale Counter.</description>
54133 <description>Prescale counter value</description>
54142 <description>Match Control Register</description>
54151 <description>Interrupt on MR0</description>
54158 <description>Disabled</description>
54163 <description>Enabled</description>
54170 <description>Reset on MR0</description>
54177 <description>Disabled</description>
54182 <description>Enabled</description>
54189 <description>Stop on MR0</description>
54196 <description>Disabled</description>
54201 <description>Enabled</description>
54208 <description>Interrupt on MR1</description>
54215 <description>Disabled</description>
54220 <description>Enabled</description>
54227 <description>Reset on MR1</description>
54234 <description>Disabled</description>
54239 <description>Enabled</description>
54246 <description>Stop on MR1</description>
54253 <description>Disabled</description>
54258 <description>Enabled</description>
54265 <description>Interrupt on MR2</description>
54272 <description>Disabled</description>
54277 <description>Enabled</description>
54284 <description>Reset on MR2</description>
54291 <description>Disabled</description>
54296 <description>Enabled</description>
54303 <description>Stop on MR2</description>
54310 <description>Disabled</description>
54315 <description>Enabled</description>
54322 <description>Interrupt on MR3</description>
54329 <description>Disabled</description>
54334 <description>Enabled</description>
54341 <description>Reset on MR3</description>
54348 <description>Disabled</description>
54353 <description>Enabled</description>
54360 <description>Stop on MR3</description>
54367 <description>Disabled</description>
54372 <description>Enabled</description>
54379 <description>Reload MR0</description>
54386 <description>Disabled</description>
54391 <description>Enabled</description>
54398 <description>Reload MR1</description>
54405 <description>Disabled</description>
54410 <description>Enabled</description>
54417 <description>Reload MR2</description>
54424 <description>Disabled</description>
54429 <description>Enabled</description>
54436 <description>Reload MR3</description>
54443 <description>Disabled</description>
54448 <description>Enabled</description>
54459 <description>Match Register</description>
54468 <description>Timer counter match value</description>
54477 <description>Capture Control Register</description>
54486 …<description>Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with…
54493 <description>Disabled</description>
54498 <description>Enabled</description>
54505 …<description>Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded wit…
54512 <description>Disabled</description>
54517 <description>Enabled</description>
54524 …<description>Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.</de…
54531 <description>Disabled</description>
54536 <description>Enabled</description>
54543 …<description>Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with…
54550 <description>Disabled</description>
54555 <description>Enabled</description>
54562 …<description>Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded wit…
54569 <description>Disabled</description>
54574 <description>Enabled</description>
54581 …<description>Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.</de…
54588 <description>Disabled</description>
54593 <description>Enabled</description>
54600 …<description>Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with…
54607 <description>Disabled</description>
54612 <description>Enabled</description>
54619 …<description>Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded wit…
54626 <description>Disabled</description>
54631 <description>Enabled</description>
54638 …<description>Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.</de…
54645 <description>Disabled</description>
54650 <description>Enabled</description>
54657 …<description>Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with…
54664 <description>Disabled</description>
54669 <description>Enabled</description>
54676 …<description>Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded wit…
54683 <description>Disabled</description>
54688 <description>Enabled</description>
54695 …<description>Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.</de…
54702 <description>Disabled</description>
54707 <description>Enabled</description>
54718 <description>Capture Register</description>
54727 <description>Timer counter capture value.</description>
54736 <description>External Match Register</description>
54745 <description>External Match 0</description>
54752 <description>External Match 1</description>
54759 <description>External Match 2</description>
54766 <description>External Match 3</description>
54773 <description>External Match Control 0</description>
54780 <description>Do Nothing.</description>
54785 …<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pin…
54790 …<description>Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned…
54795 … <description>Toggle. Toggle the corresponding External Match bit/output.</description>
54802 <description>External Match Control 1</description>
54809 <description>Do Nothing</description>
54814 …<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pin…
54819 …<description>Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned…
54824 … <description>Toggle. Toggle the corresponding External Match bit/output.</description>
54831 <description>External Match Control 2</description>
54838 <description>Do Nothing.</description>
54843 …<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pin…
54848 …<description>Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned…
54853 … <description>Toggle. Toggle the corresponding External Match bit/output.</description>
54860 <description>External Match Control 3</description>
54867 <description>Do Nothing.</description>
54872 …<description>Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pin…
54877 …<description>Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned…
54882 … <description>Toggle. Toggle the corresponding External Match bit/output.</description>
54891 <description>Count Control Register</description>
54900 …description>The Count Control Register (CTCR) is used to select between Timer and Counter mode, an…
54907 <description>Timer Mode</description>
54912 <description>Counter Mode rising edge</description>
54917 <description>Counter Mode falling edge</description>
54922 <description>Counter Mode dual edge</description>
54929 <description>Count Input Select</description>
54936 <description>Channel 0. CAPn.0 for CTIMERn</description>
54941 <description>Channel 1. CAPn.1 for CTIMERn</description>
54946 <description>Channel 2. CAPn.2 for CTIMERn</description>
54951 <description>Channel 3. CAPn.3 for CTIMERn</description>
54958 …<description>Setting this bit to 1 enables clearing of the timer and the prescaler when the captur…
54965 <description>Edge select</description>
54972 …<description>Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the time…
54977 …<description>Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the ti…
54982 …<description>Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the time…
54987 …<description>Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the ti…
54992 …<description>Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the time…
54997 …<description>Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the ti…
55006 <description>PWM Control Register</description>
55015 <description>PWM mode enable for channel0.</description>
55022 <description>Match. CTIMERn_MAT0 is controlled by EM0.</description>
55027 <description>PWM. PWM mode is enabled for CTIMERn_MAT0.</description>
55034 <description>PWM mode enable for channel1.</description>
55041 <description>Match. CTIMERn_MAT01 is controlled by EM1.</description>
55046 <description>PWM. PWM mode is enabled for CTIMERn_MAT1.</description>
55053 <description>PWM mode enable for channel2.</description>
55060 <description>Match. CTIMERn_MAT2 is controlled by EM2.</description>
55065 <description>PWM. PWM mode is enabled for CTIMERn_MAT2.</description>
55072 …<description>PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set t…
55079 <description>Match. CTIMERn_MAT3 is controlled by EM3.</description>
55084 <description>PWM. PWM mode is enabled for CT132Bn_MAT3.</description>
55095 <description>Match Shadow Register</description>
55104 <description>Timer counter match shadow value.</description>
55115 <description>Counter/Timer</description>
55130 <description>Counter/Timer</description>
55145 <description>Counter/Timer</description>
55160 <description>Counter/Timer</description>
55175 <description>WWDT</description>
55190 <description>Mode</description>
55199 <description>Watchdog Enable</description>
55206 <description>Stop. The Watchdog timer is stopped.</description>
55211 <description>Run. The Watchdog timer is running.</description>
55218 <description>Watchdog Reset Enable</description>
55225 … <description>Interrupt. A Watchdog timeout will not cause a chip reset.</description>
55230 <description>Reset. A Watchdog timeout will cause a chip reset.</description>
55237 <description>Watchdog Timeout Flag</description>
55244 <description>Clear.</description>
55249 <description>Reset. Causes a chip reset if WDRESET = 1.</description>
55256 <description>Warning Interrupt Flag</description>
55264 <description>No flag.</description>
55269 …<description>Flag. The Watchdog interrupt flag is set when the Watchdog counter is no longer great…
55276 <description>Watchdog Update Mode</description>
55283 <description>Flexible</description>
55288 <description>Threshold</description>
55295 <description>Lock</description>
55302 <description>No Lock</description>
55307 <description>Lock</description>
55316 <description>Timer Constant</description>
55325 <description>Watchdog Timeout Value</description>
55334 <description>Feed Sequence</description>
55343 <description>Feed Value</description>
55352 <description>Timer Value</description>
55361 <description>Counter Timer Value</description>
55370 <description>Warning Interrupt Compare Value</description>
55379 <description>Watchdog Warning Interrupt Compare Value</description>
55388 <description>Window Compare Value</description>
55397 <description>Watchdog Window Value.</description>
55408 <description>Multi-Rate Timer (MRT)</description>
55425 <description>no description available</description>
55429 <description>Time Interval Value</description>
55438 <description>Time interval load value.</description>
55445 …<description>Determines how the timer interval value (IVALUE -1) is loaded into the TIMER n regist…
55452 <description>No force load.</description>
55457 <description>Force load. T</description>
55466 <description>Timer</description>
55475 <description>Holds the current timer value of the down-counter.</description>
55484 <description>Control</description>
55493 <description>Enable the TIMER n interrupt.</description>
55500 <description>Disabled. TIMER n interrupt is disabled.</description>
55505 <description>Enabled. TIMER n interrupt is enabled.</description>
55512 <description>Selects the timer mode</description>
55519 <description>Repeat interrupt mode</description>
55524 <description>One-shot interrupt mode</description>
55529 <description>One-shot stall mode</description>
55538 <description>Status</description>
55547 <description>Monitors the interrupt flag</description>
55554 … <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
55559 <description>Pending interrupt.</description>
55566 <description>Indicates the state of TIMER n. RUN bit is read-only.</description>
55573 <description>Idle state. TIMER n has stopped.</description>
55578 <description>Running. TIMER n is running.</description>
55585 <description>Channel-In-Use flag</description>
55593 <description>This timer channel is not in use.</description>
55598 …<description>This timer channel is in use. Writing a 1 to this bit clears the status.</description>
55608 <description>Module Configuration</description>
55617 …<description>Number Of Channels: identifies the number of channels in this MRT. (Minus 1 encoded)<…
55624 …<description>Number Of Bits: identifies the number of timer bits in this MRT. (24 bits on this dev…
55631 …<description>Selects the operating mode for the INUSE flags and the IDLE_CH register.</description>
55638 …<description>Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.</d…
55643 <description>Multi-task mode</description>
55652 <description>Idle Channel</description>
55661 <description>Idle channel.</description>
55670 <description>Global Interrupt Flag</description>
55679 <description>Monitors the interrupt flag of TIMER0.</description>
55686 … <description>No pending interrupt. Writing a zero is equivalent to no operation.</description>
55691 <description>Pending interrupt</description>
55698 … <description>Monitors the interrupt flag of TIMER1, and acts similarly to channel 0.</description>
55705 … <description>Monitors the interrupt flag of TIMER2, and acts similarly to channel 0.</description>
55712 … <description>Monitors the interrupt flag of TIMER3, and acts similarly to channel 0.</description>
55721 <description>Multi-Rate Timer ID code</description>
55730 <description>Multi-Rate Timer ID code</description>
55741 <description>UTICK</description>
55756 <description>Control</description>
55765 <description>Tick interval</description>
55772 <description>Repeat delay</description>
55779 <description>One-time delay</description>
55784 <description>Delay repeats continuously</description>
55793 <description>Status</description>
55802 <description>Interrupt flag</description>
55809 <description>No interrupt is pending</description>
55814 <description>An interrupt is pending</description>
55821 <description>Timer active flag</description>
55828 <description>The Micro-Tick Timer is not active (stopped)</description>
55833 <description>The Micro-Tick Timer is currently active</description>
55842 <description>Capture Configuration</description>
55851 <description>Enable Capture 0</description>
55858 <description>Disabled</description>
55863 <description>Enabled</description>
55870 <description>Enable Capture 1</description>
55877 <description>Disabled</description>
55882 <description>Enabled</description>
55889 <description>Enable Capture 2</description>
55896 <description>Disabled</description>
55901 <description>Enabled</description>
55908 <description>Enable Capture 3</description>
55915 <description>Disabled</description>
55920 <description>Enabled</description>
55927 <description>Capture Polarity 0</description>
55934 <description>Positive edge capture</description>
55939 <description>Negative edge capture</description>
55946 <description>Capture Polarity 1</description>
55953 <description>Positive edge capture</description>
55958 <description>Negative edge capture</description>
55965 <description>Capture Polarity 2</description>
55972 <description>Positive edge capture</description>
55977 <description>Negative edge capture</description>
55984 <description>Capture Polarity 3</description>
55991 <description>Positive edge capture</description>
55996 <description>Negative edge capture</description>
56005 <description>Capture Clear</description>
56014 <description>Clear capture 0</description>
56021 <description>Does nothing</description>
56026 <description>Write 1 to clear the CAP0 register value</description>
56033 <description>Clear capture 1</description>
56040 <description>Does nothing</description>
56045 <description>Write 1 to clear the CAP1 register value</description>
56052 <description>Clear capture 2</description>
56059 <description>Does nothing</description>
56064 <description>Write 1 to clear the CAP2 register value</description>
56071 <description>Clear capture 3</description>
56078 <description>Does nothing</description>
56083 <description>Write 1 to clear the CAP3 register value</description>
56094 <description>Capture</description>
56103 <description>Captured value for the related capture event</description>
56110 <description>Captured value is valid</description>
56117 <description>A valid value has been not been captured</description>
56122 …<description>A valid value has been captured, based on a transition of the related UTICK_CAPn pin<…
56133 <description>Intrusion and Tamper Response Controller</description>
56144 <description>Status register</description>
56153 <description>Digital glitch detector event occurred.</description>
56161 <description>Tamper pins logic detected an event.</description>
56169 <description>Code watchdog detected an code execution anomaly.</description>
56177 <description>Low voltage event (BoD) detected on VBAT rail.</description>
56185 <description>Low voltage event (BoD) detected on VDD_CORE rail.</description>
56193 <description>Watch Dog timer event occurred.</description>
56201 <description>Flash ECC mismatch event occurred.</description>
56209 <description>AHB secure bus checkers detected illegal access.</description>
56217 <description>CSS error event occurred.</description>
56225 <description>Analog glitch sensor event occurred.</description>
56233 <description>PKC module detected an error event.</description>
56241 <description>Software event 0 occurred.</description>
56249 <description>Software event 1 occurred.</description>
56257 <description>ITRC triggered ITRC_IRQ output.</description>
56265 <description>ITRC triggered CSS_RESET to clear CSS key store.</description>
56273 <description>ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM.</description>
56281 … <description>ITRC triggered RAM_ZEROIZE to clear retention and PKC RAM contents.</description>
56289 …<description>ITRC triggered CHIP_RESET to reset the chip after all other response process finished…
56297 …<description>ITRC triggered ITRC_TMPR_OUT internal signal connected to various on-chip multiplexer…
56307 <description>ITRC_IRQ Trigger source selector 0 register</description>
56316 <description>Selects digital glitch detector as a trigger source.</description>
56323 <description>Selects tamper pin event as a trigger source.</description>
56330 <description>Selects Code Watch Dog event as a trigger source.</description>
56337 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56344 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56351 <description>Selects Watch Dog timer event as a trigger source.</description>
56358 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56365 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56372 <description>Selects CSS error event as a trigger source.</description>
56379 <description>Selects analog glitch detector as a trigger source.</description>
56386 <description>Selects PKC error event as a trigger source.</description>
56393 <description>Selects software event 0 as a trigger source.</description>
56400 <description>Selects software event 1 as a trigger source.</description>
56409 <description>ITRC_IRQ Trigger source selector 1 register</description>
56418 <description>Selects digital glitch detector as a trigger source.</description>
56425 <description>Selects tamper pin event as a trigger source.</description>
56432 <description>Selects Code Watch Dog event as a trigger source.</description>
56439 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56446 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56453 <description>Selects Watch Dog timer event as a trigger source.</description>
56460 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56467 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56474 <description>Selects CSS error event as a trigger source.</description>
56481 <description>Selects analog glitch detector as a trigger source.</description>
56488 <description>Selects PKC error event as a trigger source.</description>
56495 <description>Selects software event 0 as a trigger source.</description>
56502 <description>Selects software event 1 as a trigger source.</description>
56511 <description>CSS_RESET Trigger source selector 0 register</description>
56520 <description>CSS_RESET Trigger source selector 0 register.</description>
56527 <description>Selects tamper pin event as a trigger source.</description>
56534 <description>Selects Code Watch Dog event as a trigger source.</description>
56541 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56548 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56555 <description>Selects Watch Dog timer event as a trigger source.</description>
56562 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56569 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56576 <description>Selects CSS error event as a trigger source.</description>
56583 <description>Selects analog glitch detector as a trigger source.</description>
56590 <description>Selects PKC error event as a trigger source.</description>
56597 <description>Selects software event 0 as a trigger source.</description>
56604 <description>Selects software event 1 as a trigger source.</description>
56613 <description>CSS_RESET Trigger source selector 1 register</description>
56622 <description>Selects digital glitch detector as a trigger source.</description>
56629 <description>Selects tamper pin event as a trigger source.</description>
56636 <description>Selects Code Watch Dog event as a trigger source.</description>
56643 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56650 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56657 <description>Selects Watch Dog timer event as a trigger source.</description>
56664 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56671 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56678 <description>Selects CSS error event as a trigger source.</description>
56685 <description>Selects analog glitch detector as a trigger source.</description>
56692 <description>Selects PKC error event as a trigger source.</description>
56699 <description>Selects software event 0 as a trigger source.</description>
56706 <description>Selects software event 1 as a trigger source.</description>
56715 <description>PUF_ZEROIZE Trigger source selector 0 register</description>
56724 <description>CSS_RESET Trigger source selector 0 register.</description>
56731 <description>Selects tamper pin event as a trigger source.</description>
56738 <description>Selects Code Watch Dog event as a trigger source.</description>
56745 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56752 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56759 <description>Selects Watch Dog timer event as a trigger source.</description>
56766 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56773 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56780 <description>Selects CSS error event as a trigger source.</description>
56787 <description>Selects analog glitch detector as a trigger source.</description>
56794 <description>Selects PKC error event as a trigger source.</description>
56801 <description>Selects software event 0 as a trigger source.</description>
56808 <description>Selects software event 1 as a trigger source.</description>
56817 <description>PUF_ZEROIZE Trigger source selector 1 register</description>
56826 <description>Selects digital glitch detector as a trigger source.</description>
56833 <description>Selects tamper pin event as a trigger source.</description>
56840 <description>Selects Code Watch Dog event as a trigger source.</description>
56847 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56854 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56861 <description>Selects Watch Dog timer event as a trigger source.</description>
56868 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56875 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56882 <description>Selects CSS error event as a trigger source.</description>
56889 <description>Selects analog glitch detector as a trigger source.</description>
56896 <description>Selects PKC error event as a trigger source.</description>
56903 <description>Selects software event 0 as a trigger source.</description>
56910 <description>Selects software event 1 as a trigger source.</description>
56919 <description>RAM_ZEROIZE Trigger source selector 0 register</description>
56928 <description>CSS_RESET Trigger source selector 0 register.</description>
56935 <description>Selects tamper pin event as a trigger source.</description>
56942 <description>Selects Code Watch Dog event as a trigger source.</description>
56949 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
56956 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
56963 <description>Selects Watch Dog timer event as a trigger source.</description>
56970 <description>Selects Flash ECC mismatch event as a trigger source.</description>
56977 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
56984 <description>Selects CSS error event as a trigger source.</description>
56991 <description>Selects analog glitch detector as a trigger source.</description>
56998 <description>Selects PKC error event as a trigger source.</description>
57005 <description>Selects software event 0 as a trigger source.</description>
57012 <description>Selects software event 1 as a trigger source.</description>
57021 <description>RAM_ZEROIZE Trigger source selector 1 register</description>
57030 <description>Selects digital glitch detector as a trigger source.</description>
57037 <description>Selects tamper pin event as a trigger source.</description>
57044 <description>Selects Code Watch Dog event as a trigger source.</description>
57051 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
57058 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
57065 <description>Selects Watch Dog timer event as a trigger source.</description>
57072 <description>Selects Flash ECC mismatch event as a trigger source.</description>
57079 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
57086 <description>Selects CSS error event as a trigger source.</description>
57093 <description>Selects analog glitch detector as a trigger source.</description>
57100 <description>Selects PKC error event as a trigger source.</description>
57107 <description>Selects software event 0 as a trigger source.</description>
57114 <description>Selects software event 1 as a trigger source.</description>
57123 <description>CHIP_RESET Trigger source selector 0 register</description>
57132 <description>CSS_RESET Trigger source selector 0 register.</description>
57139 <description>Selects tamper pin event as a trigger source.</description>
57146 <description>Selects Code Watch Dog event as a trigger source.</description>
57153 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
57160 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
57167 <description>Selects Watch Dog timer event as a trigger source.</description>
57174 <description>Selects Flash ECC mismatch event as a trigger source.</description>
57181 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
57188 <description>Selects CSS error event as a trigger source.</description>
57195 <description>Selects analog glitch detector as a trigger source.</description>
57202 <description>Selects PKC error event as a trigger source.</description>
57209 <description>Selects software event 0 as a trigger source.</description>
57216 <description>Selects software event 1 as a trigger source.</description>
57225 <description>CHIP_RESET Trigger source selector 1 register</description>
57234 <description>Selects digital glitch detector as a trigger source.</description>
57241 <description>Selects tamper pin event as a trigger source.</description>
57248 <description>Selects Code Watch Dog event as a trigger source.</description>
57255 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
57262 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
57269 <description>Selects Watch Dog timer event as a trigger source.</description>
57276 <description>Selects Flash ECC mismatch event as a trigger source.</description>
57283 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
57290 <description>Selects CSS error event as a trigger source.</description>
57297 <description>Selects analog glitch detector as a trigger source.</description>
57304 <description>Selects PKC error event as a trigger source.</description>
57311 <description>Selects software event 0 as a trigger source.</description>
57318 <description>Selects software event 1 as a trigger source.</description>
57327 <description>ITR_OUT Trigger source selector 0 register</description>
57336 <description>CSS_RESET Trigger source selector 0 register.</description>
57343 <description>Selects tamper pin event as a trigger source.</description>
57350 <description>Selects Code Watch Dog event as a trigger source.</description>
57357 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
57364 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
57371 <description>Selects Watch Dog timer event as a trigger source.</description>
57378 <description>Selects Flash ECC mismatch event as a trigger source.</description>
57385 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
57392 <description>Selects CSS error event as a trigger source.</description>
57399 <description>Selects analog glitch detector as a trigger source.</description>
57406 <description>Selects PKC error event as a trigger source.</description>
57413 <description>Selects software event 0 as a trigger source.</description>
57420 <description>Selects software event 1 as a trigger source.</description>
57429 <description>ITR_OUT Trigger source selector 1 register</description>
57438 <description>Selects digital glitch detector as a trigger source.</description>
57445 <description>Selects tamper pin event as a trigger source.</description>
57452 <description>Selects Code Watch Dog event as a trigger source.</description>
57459 <description>Selects low-voltage event on VBAT rail as a trigger source.</description>
57466 … <description>Selects low-voltage event on VDD_CORE rail as a trigger source.</description>
57473 <description>Selects Watch Dog timer event as a trigger source.</description>
57480 <description>Selects Flash ECC mismatch event as a trigger source.</description>
57487 … <description>Selects AHB secure bus illegal access event as a trigger source.</description>
57494 <description>Selects CSS error event as a trigger source.</description>
57501 <description>Selects analog glitch detector as a trigger source.</description>
57508 <description>Selects PKC error event as a trigger source.</description>
57515 <description>Selects software event 0 as a trigger source.</description>
57522 <description>Selects software event 1 as a trigger source.</description>
57531 <description>Software event 0</description>
57540 <description>Trigger software event 0.</description>
57549 <description>Software event 1</description>
57558 <description>Trigger software event 1.</description>
57569 <description>Analog Controller</description>
57580 …<description>Various Analog blocks configuration (like FRO 192MHz trimmings source ...)</descripti…
57589 <description>FRO192M trimming and 'Enable' source.</description>
57596 <description>FRO192M trimming and 'Enable' comes from eFUSE.</description>
57601 … <description>FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers.</description>
57610 <description>Analog Control and Status</description>
57619 … <description>Power Management Unit (PMU) Analog macro-bloc identification number : .</description>
57626 <description>Oscillators Analog macro-bloc identification number : .</description>
57633 <description>Flash Power Down status</description>
57640 <description>Not in power down mode.</description>
57645 <description>In power down mode.</description>
57652 <description>Flash initialization error status</description>
57659 <description>No error</description>
57664 <description>At least one error occurred</description>
57671 <description>Flash ECC Error Flag</description>
57678 <description>Flash Blank Status Flag</description>
57687 <description>192MHz Free Running Oscillator (FRO) Control</description>
57696 <description>Bias trimming bits (course frequency trimming).</description>
57703 <description>Temperature coefficient trimming bits.</description>
57710 <description>12 MHz clock control.</description>
57717 <description>Disable the 12 MHz clock.</description>
57722 <description>Enable the 12 MHz clock.</description>
57729 …<description>48 MHz clock control. Only 1 should be written. Writing zero prevents the Flash from …
57736 <description>48 MHz clock is enabled.</description>
57743 <description>Frequency trim.</description>
57750 …description>If USBCLKADJ bit is set and the USB peripheral is enabled for full speed device mode, …
57757 <description>USBCLKADJ mode trim change</description>
57764 <description>Analog Test Bus control.</description>
57771 <description>96 MHz clock control</description>
57778 <description>Disable the 96 MHz clock.</description>
57783 <description>Enable the 96 MHz clock.</description>
57790 … <description>This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields.</description>
57799 <description>192MHz Free Running Oscillator (FRO) Status</description>
57808 <description>Output clock valid.</description>
57815 …<description>No output clock available (None of 12 MHz, 48 MHz or 96 MHz clock is available).</des…
57820 …description>Output clock is available (12 MHz, 48 MHz or 96 MHz can be output if they are enable r…
57827 …description>CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses t…
57836 <description>General Purpose ADC VBAT Divider branch control</description>
57845 <description>Switch On/Off VBAT divider branch.</description>
57852 <description>VBAT divider branch is disabled.</description>
57857 <description>VBAT divider branch is enabled.</description>
57866 <description>High speed Crystal Oscillator Control register</description>
57875 <description>Gm value for Xo.</description>
57882 <description>Xo in slave mode.</description>
57889 <description>Amplitude selection , Min amp : 001, Max amp : 110.</description>
57896 <description>Tune capa banks of High speed Crystal Oscillator input pin</description>
57903 <description>Tune capa banks of High speed Crystal Oscillator output pin</description>
57910 <description>Bypass enable of XO AC buffer enable in PLL and top level.</description>
57917 <description>Disable the buffer bypass.</description>
57922 <description>Enable the buffer bypass.</description>
57929 <description>Enable High speed Crystal oscillator output to CPU system.</description>
57936 <description>Disable the oscillator.</description>
57941 <description>Enable the oscillator.</description>
57948 <description>Source selection for 'xo32k_captest_start' signal.</description>
57955 <description>Sourced from CAPTESTSTART.</description>
57960 <description>Sourced from calibration.</description>
57967 <description>1: Start CapTest.</description>
57974 <description>Enable signal for captest.</description>
57981 <description>Captest is disabled.</description>
57986 <description>Captest is enabled.</description>
57993 <description>Select the input for test.</description>
58000 <description>osc_out (Crystal oscillator output) pin.</description>
58005 <description>osc_in (Crystal oscillator input) pin.</description>
58014 <description>High speed Crystal Oscillator Status</description>
58023 <description>Crystal Oscillator Ready</description>
58030 <description>Frequency is not yet stable.</description>
58035 <description>Frequency is stable.</description>
58044 <description>Brown Out Detectors & DCDC interrupt control</description>
58053 <description>BOD VBAT interrupt control.</description>
58060 <description>Disable the interrupt.</description>
58065 <description>Enable the interrupt.</description>
58072 … <description>BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit.</description>
58079 <description>BOD CORE interrupt control.</description>
58086 <description>Disable the interrupt.</description>
58091 <description>Enable the interrupt.</description>
58098 … <description>BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit.</description>
58105 <description>DCDC interrupt control.</description>
58112 <description>Disable the interrupt.</description>
58117 <description>Enable the interrupt.</description>
58124 … <description>DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit.</description>
58133 <description>BoDs & DCDC interrupt status</description>
58142 <description>BOD VBAT Interrupt status before Interrupt Enable.</description>
58149 <description>No interrupt pending.</description>
58154 <description>Interrupt pending.</description>
58161 <description>BOD VBAT Interrupt status after Interrupt Enable.</description>
58168 <description>No interrupt pending.</description>
58173 <description>Interrupt pending.</description>
58180 <description>BOD VBAT power status</description>
58187 <description>Below the threshold.</description>
58192 <description>Above the threshold.</description>
58199 <description>BOD CORE Interrupt status before Interrupt Enable.</description>
58206 <description>No interrupt pending.</description>
58211 <description>Interrupt pending.</description>
58218 <description>BOD CORE Interrupt status after Interrupt Enable.</description>
58225 <description>No interrupt pending.</description>
58230 <description>Interrupt pending.</description>
58237 <description>BOD CORE power status</description>
58244 <description>Below the threshold.</description>
58249 <description>Above the threshold.</description>
58256 <description>DCDC Interrupt status before Interrupt Enable.</description>
58263 <description>No interrupt pending.</description>
58268 <description>Interrupt pending.</description>
58275 <description>DCDC Interrupt status after Interrupt Enable.</description>
58282 <description>No interrupt pending.</description>
58287 <description>Interrupt pending.</description>
58294 <description>DCDC power status</description>
58301 <description>Below the target.</description>
58306 <description>Above the target.</description>
58315 <description>First Ring Oscillator module control register.</description>
58324 <description>Select short or long ringo (for all ringos types).</description>
58331 <description>Select short ringo (few elements).</description>
58336 <description>Select long ringo (many elements).</description>
58343 <description>Ringo frequency output divider.</description>
58350 <description>High frequency output (frequency lower than 100 MHz).</description>
58355 <description>Low frequency output (frequency lower than 10 MHz).</description>
58362 … <description>PN-Ringos (P-Transistor and N-Transistor processing) control.</description>
58369 <description>Normal mode.</description>
58374 <description>P-Monitor mode. Measure with weak P transistor.</description>
58379 <description>P-Monitor mode. Measure with weak N transistor.</description>
58384 <description>Don't use.</description>
58391 <description>Ringo module Power control.</description>
58398 <description>The Ringo module is enabled.</description>
58403 <description>The Ringo module is disabled.</description>
58410 <description>First NAND2-based ringo control.</description>
58417 <description>First NAND2-based ringo is disabled.</description>
58422 <description>First NAND2-based ringo is enabled.</description>
58429 <description>Second NAND2-based ringo control.</description>
58436 <description>Second NAND2-based ringo is disabled.</description>
58441 <description>Second NAND2-based ringo is enabled.</description>
58448 <description>First NOR2-based ringo control.</description>
58455 <description>First NOR2-based ringo is disabled.</description>
58460 <description>First NOR2-based ringo is enabled.</description>
58467 <description>Second NOR2-based ringo control.</description>
58474 <description>Second NORD2-based ringo is disabled.</description>
58479 <description>Second NORD2-based ringo is enabled.</description>
58486 <description>First Inverter-based ringo control.</description>
58493 <description>First INV-based ringo is disabled.</description>
58498 <description>First INV-based ringo is enabled.</description>
58505 <description>Second Inverter-based ringo control.</description>
58512 <description>Second INV-based ringo is disabled.</description>
58517 <description>Second INV-based ringo is enabled.</description>
58524 … <description>First PN (P-Transistor and N-Transistor processing) monitor control.</description>
58531 <description>First PN-based ringo is disabled.</description>
58536 <description>First PN-based ringo is enabled.</description>
58543 … <description>Second PN (P-Transistor and N-Transistor processing) monitor control.</description>
58550 <description>Second PN-based ringo is disabled.</description>
58555 <description>Second PN-based ringo is enabled.</description>
58562 …<description>Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (min…
58569 …<description>Ringo clock out Divider status flag. Set when a change is made to the divider value, …
58578 <description>Second Ring Oscillator module control register.</description>
58587 <description>Select short or long ringo (for all ringos types).</description>
58594 <description>Select short ringo (few elements).</description>
58599 <description>Select long ringo (many elements).</description>
58606 <description>Ringo frequency output divider.</description>
58613 <description>High frequency output (frequency lower than 100 MHz).</description>
58618 <description>Low frequency output (frequency lower than 10 MHz).</description>
58625 <description>Ringo module Power control.</description>
58632 <description>The Ringo module is enabled.</description>
58637 <description>The Ringo module is disabled.</description>
58644 <description>.</description>
58651 <description>Ringo is disabled.</description>
58656 <description>Ringo is enabled.</description>
58663 <description>.</description>
58670 <description>Ringo is disabled.</description>
58675 <description>Ringo is enabled.</description>
58682 <description>Metal 2 (M2) monitor control.</description>
58689 <description>Ringo is disabled.</description>
58694 <description>Ringo is enabled.</description>
58701 <description>Metal 3 (M3) monitor control.</description>
58708 <description>Ringo is disabled.</description>
58713 <description>Ringo is enabled.</description>
58720 <description>Metal 4 (M4) monitor control.</description>
58727 <description>Ringo is disabled.</description>
58732 <description>Ringo is enabled.</description>
58739 <description>Metal 5 (M5) monitor control.</description>
58746 <description>Ringo is disabled.</description>
58751 <description>Ringo is enabled.</description>
58758 …<description>Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (min…
58765 …<description>Ringo clock out Divider status flag. Set when a change is made to the divider value, …
58774 <description>Third Ring Oscillator module control register.</description>
58783 <description>Select short or long ringo (for all ringos types).</description>
58790 <description>Select short ringo (few elements).</description>
58795 <description>Select long ringo (many elements).</description>
58802 <description>Ringo frequency output divider.</description>
58809 <description>High frequency output (frequency lower than 100 MHz).</description>
58814 <description>Low frequency output (frequency lower than 10 MHz).</description>
58821 <description>Ringo module Power control.</description>
58828 <description>The Ringo module is enabled.</description>
58833 <description>The Ringo module is disabled.</description>
58840 <description>.</description>
58847 <description>Ringo is disabled.</description>
58852 <description>Ringo is enabled.</description>
58859 <description>.</description>
58866 <description>Ringo is disabled.</description>
58871 <description>Ringo is enabled.</description>
58878 <description>Metal 2 (M2) monitor control.</description>
58885 <description>Ringo is disabled.</description>
58890 <description>Ringo is enabled.</description>
58897 <description>Metal 3 (M3) monitor control.</description>
58904 <description>Ringo is disabled.</description>
58909 <description>Ringo is enabled.</description>
58916 <description>Metal 4 (M4) monitor control.</description>
58923 <description>Ringo is disabled.</description>
58928 <description>Ringo is enabled.</description>
58935 <description>Metal 5 (M5) monitor control.</description>
58942 <description>Ringo is disabled.</description>
58947 <description>Ringo is enabled.</description>
58954 …<description>Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (min…
58961 …<description>Ringo clock out Divider status flag. Set when a change is made to the divider value, …
58970 …<description>High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control registe…
58979 <description>Activate LDO bypass.</description>
58986 <description>Disable bypass mode (for normal operations).</description>
58991 <description>Activate LDO bypass.</description>
58998 <description>.</description>
59005 <description>Output in High normal state.</description>
59010 <description>Output in High Impedance state.</description>
59017 <description>Sets the LDO output level.</description>
59024 <description>0.750 V.</description>
59029 <description>0.775 V.</description>
59034 <description>0.800 V.</description>
59039 <description>0.825 V.</description>
59044 <description>0.850 V.</description>
59049 <description>0.875 V.</description>
59054 <description>0.900 V.</description>
59059 <description>0.925 V.</description>
59066 <description>Adjust the biasing current.</description>
59073 <description>Stability configuration.</description>
59082 <description>AUX_BIAS</description>
59091 <description>Control output of 1V reference voltage.</description>
59098 <description>Output of 1V reference voltage buffer is bypassed.</description>
59103 <description>Output of 1V reference voltage is enabled.</description>
59110 <description>current trimming control word.</description>
59117 <description>current trimming control word for ptat current.</description>
59124 <description>voltage trimming control word.</description>
59131 <description>Control bit to configure trimming state of mirror.</description>
59138 <description>Control bit to configure trimming state of mirror.</description>
59145 <description>Control bit to configure trimming state of mirror.</description>
59154 …<description>All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibra…
59163 <description>Polarity of the externally applied START signal</description>
59170 <description>Override of the START signal.</description>
59177 <description>Override value of the START signal.</description>
59184 <description>Polarity of the STOP signal.</description>
59191 … <description>Generate the external DONE signal when the counter reaches its end.</description>
59198 …<description>When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal o…
59205 <description>High speed crystal oscillator (12 MHz- 32 MHz) is used</description>
59210 <description>32 kHz crystal oscillator calibration is used.</description>
59219 …<description>All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibra…
59228 <description>START signal for testing the state machine.</description>
59235 <description>STOP signal for testing the state machine.</description>
59242 …<description>Override instructing the state machine to use the START/STOP signals from this regist…
59251 …<description>All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibra…
59260 … <description>Value of the calibration counter (result of the calibration operation).</description>
59267 <description>Status of the calibration run. 1: Calibration is completed.</description>
59276 <description>Oscillators Analog Macrobloc ACBUS and DCBUS control</description>
59285 <description>.</description>
59292 <description>.</description>
59301 <description>Auxillary Analog modules ACBUS and DCBUS control</description>
59310 <description>.</description>
59317 <description>.</description>
59326 <description>Dummy Control bus to analog modules</description>
59335 <description>.</description>
59342 <description>Oscillator Analog Macrobloc dummy control interface.</description>
59351 <description>Dummy Status bus from analog modules</description>
59360 <description>.</description>
59367 <description>Oscillator Analog Macrobloc dummy control interface.</description>
59376 <description>USB High Speed Phy Control</description>
59385 <description>Override value for Vbus if using external detectors.</description>
59392 <description>Override value for ID if using external detectors.</description>
59399 <description>.</description>
59408 <description>USB High Speed Phy Trim values</description>
59417 … <description>Adjusts time constant of HS RX squelch (envelope) comparator.</description>
59424 <description>.</description>
59431 <description>.</description>
59438 <description>.</description>
59445 <description>.</description>
59452 <description>.</description>
59459 <description>.</description>
59468 <description>USB High Speed Phy Status</description>
59477 <description>pfd output is stable.</description>
59484 <description>Can be left disconnected if not using High volt interrupts.</description>
59491 <description>Same as utmi_sessend.</description>
59498 <description>Full speed single ended receiver for 1.</description>
59505 <description>Full speed single ended receiver for 1.</description>
59512 … <description>this is a proprietary mode described in the reference manual.</description>
59519 <description>ID value in the 1.</description>
59530 <description>I3C</description>
59541 <description>Master Configuration</description>
59550 <description>Master enable</description>
59557 <description>MASTER_OFF</description>
59562 <description>MASTER_ON</description>
59567 <description>MASTER_CAPABLE</description>
59574 <description>Disable Timeout</description>
59581 <description>High-Keeper</description>
59588 <description>NONE</description>
59593 <description>WIRED_IN</description>
59598 <description>PASSIVE_SDA</description>
59603 <description>PASSIVE_ON_SDA_SCL</description>
59610 <description>Open drain stop</description>
59617 <description>Push-pull baud rate</description>
59624 <description>Push-Pull low</description>
59631 <description>Open drain baud rate</description>
59638 <description>Open drain high push-pull</description>
59645 <description>Skew</description>
59652 <description>I2C baud rate</description>
59661 <description>Slave Configuration</description>
59670 <description>Slave enable</description>
59677 <description>Not acknowledge</description>
59684 <description>Match START or STOP</description>
59691 <description>S0/S1 errors ignore</description>
59698 <description>Double Data Rate OK</description>
59705 <description>ID random</description>
59712 <description>Offline</description>
59719 <description>Bus available match</description>
59726 <description>Static address</description>
59735 <description>Slave Status</description>
59744 <description>Status not stop</description>
59751 <description>Status message</description>
59758 <description>Status Common Command Code Handler</description>
59765 <description>Status request read</description>
59772 <description>Status request write</description>
59779 <description>Status Dynamic Address Assignment</description>
59786 <description>Status High Data Rate</description>
59793 <description>Start</description>
59801 <description>Matched</description>
59809 <description>Stop</description>
59817 <description>Received message pending</description>
59824 <description>Transmit buffer is not full</description>
59831 <description>DACHG</description>
59839 <description>Common Command Code</description>
59847 <description>Error warning</description>
59854 <description>High Data Rate command match</description>
59862 <description>Common Command Code handled</description>
59870 <description>Event</description>
59878 <description>Event details</description>
59885 <description>NONE</description>
59890 <description>NO_REQUEST</description>
59895 <description>NACKED</description>
59900 <description>ACKED</description>
59907 <description>In-Band Interrupts are disabled</description>
59914 <description>Master requests are disabled</description>
59921 <description>Hot-Join is disabled</description>
59928 <description>Activity state from Common Command Codes (CCC)</description>
59935 <description>NO_LATENCY</description>
59940 <description>LATENCY_1MS</description>
59945 <description>LATENCY_100MS</description>
59950 <description>LATENCY_10S</description>
59957 <description>Time control</description>
59964 <description>NO_TIME_CONTROL</description>
59969 <description>ASYNC_MODE</description>
59978 <description>Slave Control</description>
59987 <description>EVENT</description>
59994 <description>NORMAL_MODE</description>
59999 <description>IBI</description>
60004 <description>MASTER_REQUEST</description>
60009 <description>HOT_JOIN_REQUEST</description>
60016 <description>Extended Data</description>
60023 <description>In-Band Interrupt data</description>
60030 <description>Pending interrupt</description>
60037 <description>Activity state (of slave)</description>
60044 <description>Vendor information</description>
60053 <description>Slave Interrupt Set</description>
60062 <description>Start interrupt enable</description>
60070 <description>Match interrupt enable</description>
60078 <description>Stop interrupt enable</description>
60086 <description>Receive interrupt enable</description>
60094 <description>Transmit interrupt enable</description>
60102 <description>Dynamic address change interrupt enable</description>
60110 …<description>Common Command Code (CCC) (that was not handled by I3C module) interrupt enable</desc…
60118 <description>Error/warning interrupt enable</description>
60126 <description>Double Data Rate (DDR) interrupt enable</description>
60134 …<description>Common Command Code (CCC) (that was handled by I3C module) interrupt enable</descript…
60142 <description>Event interrupt enable</description>
60152 <description>Slave Interrupt Clear</description>
60161 <description>START interrupt enable clear</description>
60169 <description>MATCHED interrupt enable clear</description>
60177 <description>STOP interrupt enable clear</description>
60185 <description>RXPEND interrupt enable clear</description>
60193 <description>TXSEND interrupt enable clear</description>
60201 <description>DACHG interrupt enable clear</description>
60209 <description>CCC interrupt enable clear</description>
60217 <description>ERRWARN interrupt enable clear</description>
60225 <description>DDRMATCHED interrupt enable clear</description>
60233 <description>CHANDLED interrupt enable clear</description>
60241 <description>EVENT interrupt enable clear</description>
60251 <description>Slave Interrupt Mask</description>
60260 <description>START interrupt mask</description>
60267 <description>MATCHED interrupt mask</description>
60274 <description>STOP interrupt mask</description>
60281 <description>RXPEND interrupt mask</description>
60288 <description>TXSEND interrupt mask</description>
60295 <description>DACHG interrupt mask</description>
60302 <description>CCC interrupt mask</description>
60309 <description>ERRWARN interrupt mask</description>
60316 <description>DDRMATCHED interrupt mask</description>
60323 <description>CHANDLED interrupt mask</description>
60330 <description>EVENT interrupt mask</description>
60339 <description>Slave Errors and Warnings</description>
60348 <description>Overrun error</description>
60356 <description>Underrun error</description>
60364 <description>Underrun and Not Acknowledged (NACKed) error</description>
60372 <description>Terminated error</description>
60380 <description>Invalid start error</description>
60388 <description>SDR parity error</description>
60396 <description>HDR parity error</description>
60404 <description>HDR-DDR CRC error</description>
60412 <description>S0 or S1 error</description>
60420 <description>Over-read error</description>
60428 <description>Over-write error</description>
60438 <description>Slave DMA Control</description>
60447 <description>DMA Read (From-bus) trigger</description>
60454 <description>DMA not used</description>
60459 <description>DMA is enabled for 1 frame</description>
60464 <description>DMA enable</description>
60471 <description>DMA Write (To-bus) trigger</description>
60478 <description>NOT_USED</description>
60483 <description>ENABLE_ONE_FRAME</description>
60488 <description>ENABLE</description>
60495 <description>Width of DMA operations</description>
60502 <description>BYTE, Default = 1</description>
60507 <description>BYTE, Default = 1</description>
60512 <description>HALF_WORD</description>
60521 <description>Slave Data Control</description>
60530 <description>Flush the to-bus buffer/FIFO</description>
60537 <description>Flushes the from-bus buffer/FIFO</description>
60544 <description>Unlock</description>
60551 <description>Trigger level for TX FIFO emptiness</description>
60558 <description>Trigger on empty</description>
60563 <description>Trigger on full or less</description>
60568 <description>Trigger on .5 full or less</description>
60573 <description>Trigger on 1 less than full or less (Default)</description>
60580 <description>Trigger level for RX FIFO fullness</description>
60587 <description>Trigger on not empty</description>
60592 <description>Trigger on or more full</description>
60597 <description>Trigger on .5 or more full</description>
60602 <description>Trigger on 3/4 or more full</description>
60609 <description>Count of bytes in TX</description>
60616 <description>Count of bytes in RX</description>
60623 <description>TX is full</description>
60630 <description>TX is not full</description>
60635 <description>TX is full</description>
60642 <description>RX is empty</description>
60649 <description>RX is not empty</description>
60654 <description>RX is empty</description>
60663 <description>Slave Write Data Byte</description>
60672 <description>The data byte to send to the master</description>
60679 <description>End</description>
60686 <description>End also</description>
60695 <description>Slave Write Data Byte End</description>
60704 <description>The data byte to send to the master</description>
60713 <description>Slave Write Data Half-word</description>
60722 <description>The 1st byte to send to the master</description>
60729 <description>The 2nd byte to send to the master</description>
60736 <description>End of message</description>
60745 <description>Slave Write Data Half-word End</description>
60754 <description>The 1st byte to send to the master</description>
60761 <description>The 2nd byte to send to the master</description>
60770 <description>Slave Read Data Byte</description>
60779 <description>Byte read from the master</description>
60788 <description>Slave Read Data Half-word</description>
60797 <description>The 1st byte read from the slave</description>
60804 <description>The 2nd byte read from the slave</description>
60813 <description>Slave Capabilities 2</description>
60822 <description>Map Count</description>
60829 <description>I2C 10-bit Address</description>
60836 <description>Does not support I2C10B</description>
60841 <description>Supports I2C10B</description>
60848 <description>I2C SW Reset</description>
60855 <description>Does not support I2CRST</description>
60860 <description>Supports I2CRST</description>
60867 <description>I2C Device ID</description>
60874 <description>Does not support I2CDEVID</description>
60879 <description>Supports I2CDEVID</description>
60886 <description>In-Band Interrupt EXTDATA</description>
60893 <description>Does not support IBIEXT</description>
60898 <description>Supports IBIEXT</description>
60905 <description>In-Band Interrupt Extended Register</description>
60912 <description>Does not support IBIXREG</description>
60917 <description>Supports IBIXREG</description>
60924 <description>Slave Reset</description>
60931 <description>Does not support Slave Reset</description>
60936 <description>Supports Slave Reset</description>
60943 <description>GROUP</description>
60950 <description>Does not supports v1.1 Group addressing</description>
60955 <description>Supports one group</description>
60960 <description>Supports two groups</description>
60965 <description>Supports three groups</description>
60972 <description>Supports SETAASA</description>
60979 <description>Slave-Slave(s)-Tunnel subscriber capable</description>
60986 <description>Slave-Slave(s)-Tunnel write capable</description>
60995 <description>Slave Capabilities</description>
61004 <description>ID 48b handler</description>
61011 <description>APPLICATION</description>
61016 <description>HW</description>
61021 <description>HW_BUT</description>
61026 <description>PARTNO</description>
61033 <description>ID register</description>
61040 <description>HDR support</description>
61047 <description>Master</description>
61054 <description>MASTERNOTSUPPORTED</description>
61059 <description>MASTERSUPPORTED</description>
61066 <description>Static address</description>
61073 <description>NO_STATIC</description>
61078 <description>STATIC</description>
61083 <description>HW_CONTROL</description>
61088 <description>CONFIG</description>
61095 <description>Common Command Codes (CCC) handling</description>
61102 <description>In-Band Interrupts, Master Requests, Hot Join events</description>
61109 <description>Time control</description>
61116 <description>NO_TIME_CONTROL_TYPE</description>
61121 <description>ATLEAST1_TIME_CONTROL</description>
61128 <description>External FIFO</description>
61135 <description>NO_EXT_FIFO</description>
61140 <description>STD_EXT_FIFO</description>
61145 <description>REQUEST_EXT_FIFO</description>
61152 <description>FIFO transmit</description>
61159 <description>FIFO_2BYTE</description>
61164 <description>FIFO_4BYTE: 4-byte TX FIFO</description>
61169 <description>FIFO_8BYTE: 8-byte TX FIFO</description>
61174 <description>FIFO_16BYTE: 16-byte TX FIFO</description>
61181 <description>FIFO receive</description>
61188 <description>FIFO_2BYTE</description>
61193 <description>FIFO_4BYTE</description>
61198 <description>FIFO_8BYTE</description>
61203 <description>FIFO_16BYTE</description>
61210 <description>INT</description>
61217 <description>Interrupts are not supported</description>
61222 <description>Interrupts are supported</description>
61229 <description>DMA</description>
61236 <description>DMA is not supported</description>
61241 <description>DMA is supported</description>
61250 <description>Slave Maximum Limits</description>
61259 <description>Maximum read length</description>
61266 <description>Maximum write length</description>
61275 <description>Slave ID Part Number</description>
61284 <description>Part number</description>
61293 <description>Slave ID Extension</description>
61302 <description>Device Characteristic Register</description>
61309 <description>Bus Characteristics Register</description>
61318 <description>Slave Vendor ID</description>
61327 <description>Vendor ID</description>
61336 <description>Slave Time Control Clock</description>
61345 <description>Clock accuracy</description>
61352 <description>Clock frequency</description>
61361 <description>Slave Message Map Address</description>
61370 <description>Matched Address Index</description>
61377 <description>Last Static Address Matched</description>
61384 <description>Matched Previous Address Index 1</description>
61391 <description>Matched Previous Index 2</description>
61400 <description>Master Main Control</description>
61409 <description>Request</description>
61416 <description>NONE</description>
61421 <description>EMITSTARTADDR</description>
61426 <description>EMITSTOP</description>
61431 <description>IBIACKNACK</description>
61436 <description>PROCESSDAA</description>
61441 <description>FORCEEXIT and SLAVERESET</description>
61446 <description>AUTOIBI</description>
61453 <description>Bus type with EmitStartAddr</description>
61460 <description>I3C</description>
61465 <description>I2C</description>
61470 <description>DDR</description>
61477 <description>In-Band Interrupt (IBI) response</description>
61484 <description>ACK</description>
61489 <description>NACK</description>
61494 <description>ACK_WITH_MANDATORY</description>
61499 <description>MANUAL</description>
61506 <description>DIR</description>
61513 <description>DIRWRITE: Write</description>
61518 <description>DIRREAD: Read</description>
61525 <description>ADDR</description>
61532 <description>Read terminate</description>
61541 <description>Master Status</description>
61550 <description>State of the master</description>
61557 <description>IDLE: the bus has STOPped.</description>
61562 <description>SLVREQ</description>
61567 <description>MSGSDR</description>
61572 <description>NORMACT</description>
61577 <description>MSGDDR</description>
61582 <description>DAA</description>
61587 <description>IBIACK</description>
61592 <description>IBIRCV</description>
61599 <description>Between messages or Dynamic Address Assignments (DAA)</description>
61606 <description>Not acknowledged</description>
61613 <description>In-Band Interrupt (IBI) type</description>
61620 <description>NONE</description>
61625 <description>IBI</description>
61630 <description>MR</description>
61635 <description>HJ</description>
61642 <description>Slave start</description>
61650 <description>Master control done</description>
61658 <description>COMPLETE</description>
61666 <description>RXPEND</description>
61673 <description>TX buffer/FIFO not yet full</description>
61680 <description>In-Band Interrupt (IBI) won</description>
61688 <description>Error or warning</description>
61695 <description>Now master (now this module is a master)</description>
61703 <description>IBI address</description>
61712 <description>Master In-band Interrupt Registry and Rules</description>
61721 <description>ADDR0</description>
61728 <description>ADDR1</description>
61735 <description>ADDR2</description>
61742 <description>ADDR3</description>
61749 <description>ADDR4</description>
61756 <description>Set Most Significant address Bit to 0</description>
61763 <description>No IBI byte</description>
61772 <description>Master Interrupt Set</description>
61781 <description>Slave start interrupt enable</description>
61789 <description>Master control done interrupt enable</description>
61797 <description>Completed message interrupt enable</description>
61805 <description>RX pending interrupt enable</description>
61813 <description>TX buffer/FIFO is not full interrupt enable</description>
61821 <description>In-Band Interrupt (IBI) won interrupt enable</description>
61829 <description>Error or warning (ERRWARN) interrupt enable</description>
61837 … <description>Now master (now this I3C module is a master) interrupt enable</description>
61847 <description>Master Interrupt Clear</description>
61856 <description>SLVSTART interrupt enable clear</description>
61864 <description>MCTRLDONE interrupt enable clear</description>
61872 <description>COMPLETE interrupt enable clear</description>
61880 <description>RXPEND interrupt enable clear</description>
61888 <description>TXNOTFULL interrupt enable clear</description>
61896 <description>IBIWON interrupt enable clear</description>
61904 <description>ERRWARN interrupt enable clear</description>
61912 <description>NOWMASTER interrupt enable clear</description>
61922 <description>Master Interrupt Mask</description>
61931 <description>SLVSTART interrupt mask</description>
61938 <description>MCTRLDONE interrupt mask</description>
61945 <description>COMPLETE interrupt mask</description>
61952 <description>RXPEND interrupt mask</description>
61959 <description>TXNOTFULL interrupt mask</description>
61966 <description>IBIWON interrupt mask</description>
61973 <description>ERRWARN interrupt mask</description>
61980 <description>NOWMASTER interrupt mask</description>
61989 <description>Master Errors and Warnings</description>
61998 <description>Not acknowledge (NACK) error</description>
62006 <description>WRABT (Write abort) error</description>
62014 <description>Terminate error</description>
62022 <description>High data rate parity</description>
62030 <description>High data rate CRC error</description>
62038 <description>Over-read error</description>
62046 <description>Over-write error</description>
62054 <description>Message error</description>
62062 <description>Invalid request error</description>
62070 <description>TIMEOUT error</description>
62080 <description>Master DMA Control</description>
62089 <description>DMA from bus</description>
62096 <description>NOT_USED</description>
62101 <description>ENABLE_ONE_FRAME</description>
62106 <description>ENABLE</description>
62113 <description>DMA to bus</description>
62120 <description>NOT_USED</description>
62125 <description>ENABLE_ONE_FRAME</description>
62130 <description>ENABLE</description>
62137 <description>DMA width</description>
62144 <description>BYTE</description>
62149 <description>BYTE</description>
62154 <description>HALF_WORD</description>
62163 <description>Master Data Control</description>
62172 <description>Flush to-bus buffer/FIFO</description>
62179 <description>Flush from-bus buffer/FIFO</description>
62186 <description>Unlock</description>
62193 <description>TX trigger level</description>
62200 <description>Trigger on note empty</description>
62205 <description>Trigger on 1/4 or more full</description>
62210 <description>Trigger on 1/2 or more full</description>
62215 <description>Default, Trigger on 3/4 or more full</description>
62222 <description>RX trigger level</description>
62229 <description>Trigger on empty</description>
62234 <description>Trigger on 1/4 full or less</description>
62239 <description>Trigger on 1/2 full or less</description>
62244 <description>Default, Trigger on 1 less than full or less</description>
62251 <description>TX byte count</description>
62258 <description>RX byte count</description>
62265 <description>TX is full</description>
62272 <description>RX is empty</description>
62281 <description>Master Write Data Byte</description>
62290 <description>Data byte</description>
62297 <description>End of message</description>
62304 <description>End of message also</description>
62313 <description>Master Write Data Byte End</description>
62322 <description>Data</description>
62331 <description>Master Write Data Half-word</description>
62340 <description>Data byte 0</description>
62347 <description>Data byte 1</description>
62354 <description>End of message</description>
62363 <description>Master Write Data Byte End</description>
62372 <description>DATA 0</description>
62379 <description>DATA 1</description>
62388 <description>Master Read Data Byte</description>
62397 <description>VALUE</description>
62406 <description>Master Read Data Half-word</description>
62415 <description>LSB</description>
62422 <description>MSB</description>
62431 <description>Byte-only Write Byte Data (to bus)</description>
62440 <description>Value</description>
62449 <description>Master Write Message in SDR mode</description>
62459 <description>Direction</description>
62466 <description>Write</description>
62471 <description>Read</description>
62478 <description>Address to be written to</description>
62485 <description>End of SDR message</description>
62492 <description>I2C</description>
62499 <description>I3C message</description>
62504 <description>I2C message</description>
62511 <description>Length</description>
62520 <description>Master Write Message Data in SDR mode</description>
62530 <description>Data</description>
62539 <description>Master Read Message in SDR mode</description>
62548 <description>Data</description>
62557 <description>Master Write Message in DDR mode</description>
62567 <description>Length of message</description>
62574 <description>End of message</description>
62583 <description>Master Write Message Data in DDR mode</description>
62593 <description>Data</description>
62602 <description>Master Read Message in DDR mode</description>
62611 <description>Data</description>
62620 <description>Master Dynamic Address</description>
62629 <description>Dynamic address valid</description>
62636 <description>Dynamic address</description>
62645 <description>Map Feature Control 0</description>
62654 <description>Enable</description>
62661 <description>Dynamic Address</description>
62668 <description>Cause</description>
62677 <description>Extended IBI Data 1</description>
62686 <description>Count</description>
62693 <description>Maximum</description>
62700 <description>Extra byte 1</description>
62707 <description>Extra byte 2</description>
62714 <description>Extra byte 3</description>
62723 <description>Extended IBI Data 2</description>
62732 <description>Extra byte 4</description>
62739 <description>Extra byte 5</description>
62746 <description>Extra byte 6</description>
62753 <description>Extra byte 7</description>
62762 <description>Slave Module ID</description>
62771 <description>ID</description>
62782 <description>PMC</description>
62793 …<description>Power Management Control [Reset by: PoR, Pin Reset, Software Reset and BoDs reset]</d…
62802 <description>Power Mode Control.</description>
62809 <description>ACTIVE power mode.</description>
62814 <description>DEEP-SLEEP low power mode.</description>
62819 <description>POWER-DOWN low power mode.</description>
62824 <description>DEEP-POWER-DOWN low power mode.</description>
62831 … <description>Select the Power Management Controller (PMC) functional clock :</description>
62838 <description>1 MHz Free Running Oscillator.</description>
62843 <description>12 MHz Free Running Oscillator.</description>
62850 …description>Select Memories supply source in DEEP-SLEEP low power mode: Note: in POWER-DOWN and DE…
62857 … <description>Memories are supplied by LDO_MEM in 'DEEP-SLEEP' low power mode.</description>
62862 …<description>Memories are supplied by DCDC/LDO_DEEPSLEEP in 'DEEP-SLEEP' low power mode.</descript…
62869 …<description>Select Core Logic supply source when waking up from DEEP-SLEEP and POWER-DOWN low pow…
62876 <description>Core Logic is supplied by DCDC Converter.</description>
62881 … <description>Core Logic is supplied by LDO CORE (configured in High Power mode).</description>
62888 … <description>Select Core Logic supply source during DEEP-SLEEP low power mode :</description>
62895 <description>LDO CORE in Low Power Mode.</description>
62900 <description>LDO CORE in High Power Mode.</description>
62905 <description>DCDC Converter.</description>
62912 <description>Select DCDC power shut off management:</description>
62919 …<description>DCDC shut off is by managed the Hardware State Machines (see CMD register).</descript…
62924 …<description>DCDC shut off is by managed via PDRUNCFG0, PDRUNCFGSET0 and PDRUNCFGCLR0 registers.</…
62931 <description>Select LDO CORE power shut off management:</description>
62938 …<description>LDO CORE shut off is by managed the Hardware State Machines (see CMD register).</desc…
62943 … <description>LDO CORE shut off is by managed via LDOCORE0 (HPREGEN and LPREGEN).</description>
62950 <description>Select LDO FLASH NV power shut off management:</description>
62957 …<description>LDO FLASH NV shut off is by managed the Hardware State Machines (see CMD register).</…
62962 …<description>LDO FLASH NV shut off is by managed via PDRUNCFG0, PDRUNCFGSET0 and PDRUNCFGCLR0 regi…
62971 <description>Power Management Controller FSM (Finite State Machines) status</description>
62980 … <description>Power Management Controller Main Finite State Machine (FSM) status.</description>
62987 <description>POWER UP : The IC is powering up.</description>
62992 …<description>ACTIVE : Power up is completed. The IC is in normal functional operation mode.</descr…
62997 <description>POWER-DOWN : the IC has entered POWER-DOWN mode.</description>
63002 <description>DEEP-SLEEP: The IC has entered DEEP-SLEEP mode.</description>
63007 <description>DEEP-POWER-DOWN : The IC entred DEEP-POWER-DOWN mode.</description>
63012 … <description>IC Structural Test Mode : The IC has entered in IC Test mode.</description>
63019 <description>POWER UP Finite State Machine (FSM) status.</description>
63026 <description>DEEP-SLEEP Finite State Machine (FSM) status.</description>
63033 <description>POWER-DOWN Finite State Machine (FSM) status.</description>
63040 <description>DEEP-POWER-DOWN Finite State Machine (FSM) status.</description>
63047 <description>Latest IC Boot cause:.</description>
63054 …<description>Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detect…
63059 <description>Latest IC boot was from DEEP-SLEEP low power mode.</description>
63064 <description>Latest IC boot was from POWER-DOWN low power mode.</description>
63069 <description>Latest IC boot was from DEEP-POWER-DOWN low power mode.</description>
63076 …<description>Indicates the power status of the DCDC (enabled or disabled) as driven by the Hardwar…
63083 … <description>DCDC is currently disabled by the Hardware Finite State Machine (FSM).</description>
63088 … <description>DCDC is currently enabled by the Hardware Finite State Machine (FSM).</description>
63095 …description>Indicates the power status of the LDO CORE High Power Mode (enabled or disabled) as dr…
63102 …<description>LDO CORE High Power Mode is currently disabled by the Hardware Finite State Machine (…
63107 …<description>LDO CORE High Power Mode is currently enabled by the Hardware Finite State Machine (F…
63114 …description>Indicates the power status of the LDO CORE Low Power Mode (enabled or disabled) as dri…
63121 …<description>LDO CORE Low Power Mode is currently disabled by the Hardware Finite State Machine (F…
63126 …<description>LDO CORE Low Power Mode is currently enabled by the Hardware Finite State Machine (FS…
63133 …description>Indicates the status of the LDO CORE Exponential Timer (enabled or disabled) as driven…
63140 …description>It is set by ITRC (Intrusion and Tamper Response Controller) when RAM_02 and RAM_03 ha…
63147 <description>Indicates current status of wafer test level.</description>
63156 <description>Reset Control</description>
63165 …<description>Wake-up from DEEP-POWER-DOWN reset event (either from wake up I/O or RTC or OS Event …
63172 <description>Reset event from DEEP-POWER-DOWN mode is disbaled.</description>
63177 <description>Reset event from DEEP-POWER-DOWN mode is enabled.</description>
63184 <description>Software reset enable.</description>
63191 <description>Software reset is disabled.</description>
63196 <description>Software reset is enabled.</description>
63203 <description>BOD_VDDMAIN reset enabled.</description>
63210 … <description>And any other value than b10: BOD_VDDMAIN reset is enabled.</description>
63215 <description>BOD_VDDMAIN reset is disabled.</description>
63222 <description>BOD_CORE reset enabled.</description>
63229 … <description>And any other value than b10: BOD_CORE reset is enabled.</description>
63234 <description>BODCORE reset is disabled.</description>
63241 <description>BOD_VDDMAIN reset enabled.</description>
63248 … <description>And any other value than b10: BOD_VDDMAIN reset is enabled.</description>
63253 <description>BOD_VDDMAIN reset is disabled.</description>
63260 <description>BOD_CORE reset enable.</description>
63267 … <description>And any other value than b10: BOD_CORE reset is enabled.</description>
63272 <description>BOD_CORE reset is disabled.</description>
63281 <description>Reset Cause</description>
63290 …<description>1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit.<…
63298 …<description>1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit.</desc…
63305 …<description>1 : The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN …
63312 …<description>1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write …
63319 …<description>1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit…
63326 …<description>1 : The last chip reset was caused by a Software. Write '1' to clear this bit.</descr…
63333 …<description>1 : A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode. Write '1' to clear…
63340 …<description>1 : A RTC (either RTC Alarm or RTC wake up) reset event occured during DEEP-POWER-DOW…
63347 …<description>1 : A OS Event Timer reset event occured during DEEP-POWER-DOWN mode. Write '1' to cl…
63354 …<description>1 : The last chip reset was caused by the code Watchdog. Write '1' to clear this bit.…
63361 …description>In DEEP-POWER-DOWN mode, indicates which reset event occured first between DPDRESET_WA…
63368 <description>No event</description>
63373 <description>WAKEUPIO</description>
63378 <description>RTC</description>
63383 …<description>Both WAKEUPIO and RTC events occured at the same time (less than 1 nano-second from e…
63388 <description>OSTIMER</description>
63393 …<description>Both WAKEUPIO and OSTIMER events occured at the same time (less than 1 nano-second fr…
63398 …<description>Both RTC and OSTIMER events occured at the same time (less than 1 nano-second from ea…
63403 …<description>WAKEUPIO, RTC and OSTIMER events occured at the same time (less than 1 nano-second fr…
63412 <description>DCDC (first) control</description>
63421 <description>Constant On-Time calibration.</description>
63428 <description>Select the type of ZCD comparator.</description>
63435 <description>Alter Internal biasing currents.</description>
63442 … <description>Selection of auto scaling of COT period with variations in VDD.</description>
63449 <description>One-shot generator reference current trimming signal.</description>
63456 <description>Disable Current sensing.</description>
63463 <description>Set output regulation voltage.</description>
63470 <description>0.95 V.</description>
63475 <description>0.975 V.</description>
63480 <description>1 V.</description>
63485 <description>1.025 V.</description>
63490 <description>1.05 V.</description>
63495 <description>1.075 V.</description>
63500 <description>1.1 V.</description>
63505 <description>1.125 V.</description>
63510 <description>1.15 V.</description>
63515 <description>1.175 V.</description>
63520 <description>1.2 V.</description>
63527 <description>Enable staggered switching of power switches.</description>
63534 <description>Enable shorting of Inductor during PFM idle time.</description>
63541 <description>Set output regulation voltage during Deep Sleep.</description>
63550 …<description>DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, …
63559 <description>Adjust the offset voltage of BJT based comparator.</description>
63566 <description>Adjust Max inductor peak current limiting.</description>
63573 <description>Enable Digital test signals.</description>
63580 <description>Bandgap calibration parameter.</description>
63587 <description>Bandgap calibration parameter.</description>
63594 <description>Select the output signal for test.</description>
63601 <description>Modify COT behavior.</description>
63608 <description>Force bypass mode.</description>
63615 <description>Change the scaling ratio of the feedforward compensation.</description>
63622 <description>Force full PFM PMOS and NMOS cycle.</description>
63629 … <description>Change the range of the peak detector of current inside the inductor.</description>
63636 <description>Constant Off-Time calibration input.</description>
63643 <description>Enable Constant Off-Time feature.</description>
63652 …<description>Bias current source control register [Reset by: PoR, Pin Reset, Software Reset]</desc…
63661 <description>Trimming bits to adjust absolute voltage value.</description>
63668 <description>Trimming bits to adjust deviations in curvature on silicon.</description>
63675 <description>Trimming bits for flash reference current (250nA).</description>
63682 <description>Enable analog test bus inside PMU bias.</description>
63689 <description>Select an internal node inside PMU bias.</description>
63698 …description>Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Rese…
63707 <description>Sets the Always-On domain LDO output level.</description>
63714 <description>1.22 V.</description>
63719 <description>0.7 V.</description>
63724 <description>0.725 V.</description>
63729 <description>0.75 V.</description>
63734 <description>0.775 V.</description>
63739 <description>0.8 V.</description>
63744 <description>0.825 V.</description>
63749 <description>0.85 V.</description>
63754 <description>0.875 V.</description>
63759 <description>0.9 V.</description>
63764 <description>0.96 V.</description>
63769 <description>0.97 V.</description>
63774 <description>0.98 V.</description>
63779 <description>0.99 V.</description>
63784 <description>1 V.</description>
63789 <description>1.01 V.</description>
63794 <description>1.02 V.</description>
63799 <description>1.03 V.</description>
63804 <description>1.04 V.</description>
63809 <description>1.05 V.</description>
63814 <description>1.06 V.</description>
63819 <description>1.07 V.</description>
63824 <description>1.08 V.</description>
63829 <description>1.09 V.</description>
63834 <description>1.1 V.</description>
63839 <description>1.11 V.</description>
63844 <description>1.12 V.</description>
63849 <description>1.13 V.</description>
63854 <description>1.14 V.</description>
63859 <description>1.15 V.</description>
63864 <description>1.16 V.</description>
63869 <description>1.22 V.</description>
63876 … <description>Sets the Always-On domain LDO output level in all power down modes.</description>
63883 <description>Sets the Always-On domain LDO Boost output level.</description>
63890 …<description>Sets the Always-On domain LDO Boost output level in all power down modes.</descriptio…
63897 <description>Controls LDOMEM bleed current.</description>
63904 <description>Bleed current is disabled.</description>
63909 <description>Bleed current is enabled.</description>
63916 <description>Control the LDO AO boost mode in ACTIVE mode.</description>
63923 <description>LDO AO Boost Mode is disabled.</description>
63928 <description>LDO AO Boost Mode is enabled.</description>
63935 …<description>Control the LDO AO boost mode in the different low power modes (DEEP-SLEEP, POWER-DOW…
63942 <description>LDO AO Boost Mode is disabled.</description>
63947 <description>LDO AO Boost Mode is enabled.</description>
63956 …<description>Memories LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, D…
63965 <description>Sets the Memories LDO output level.</description>
63972 <description>1.22 V.</description>
63977 <description>0.7 V.</description>
63982 <description>0.725 V.</description>
63987 <description>0.75 V.</description>
63992 <description>0.775 V.</description>
63997 <description>0.8 V.</description>
64002 <description>0.825 V.</description>
64007 <description>0.85 V.</description>
64012 <description>0.875 V.</description>
64017 <description>0.9 V.</description>
64022 <description>0.96 V.</description>
64027 <description>0.97 V.</description>
64032 <description>0.98 V.</description>
64037 <description>0.99 V.</description>
64042 <description>1 V.</description>
64047 <description>1.01 V.</description>
64052 <description>1.02 V.</description>
64057 <description>1.03 V.</description>
64062 <description>1.04 V.</description>
64067 <description>1.05 V.</description>
64072 <description>1.06 V.</description>
64077 <description>1.07 V.</description>
64082 <description>1.08 V.</description>
64087 <description>1.09 V.</description>
64092 <description>1.1 V.</description>
64097 <description>1.11 V.</description>
64102 <description>1.12 V.</description>
64107 <description>1.13 V.</description>
64112 <description>1.14 V.</description>
64117 <description>1.15 V.</description>
64122 <description>1.16 V.</description>
64127 <description>1.22 V.</description>
64134 <description>Sets the Memories LDO output level in all power down modes.</description>
64141 <description>Sets the Memories LDO Boost output level.</description>
64148 … <description>Sets the Memories LDO Boost output level in all power down modes.</description>
64155 <description>Controls LDOMEM bleed current.</description>
64162 <description>Bleed current is disbaled.</description>
64167 <description>Bleed current is enabled.</description>
64176 …<description>LDO CORE (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Rese…
64185 <description>Enables bandgap.</description>
64192 <description>Disable bandgap.</description>
64197 <description>Enable bandgap.</description>
64204 <description>High power regulator enable.</description>
64211 <description>Disable High power regulator.</description>
64216 <description>Enable High power regulator.</description>
64223 <description>Low power regulator enable.</description>
64230 <description>Disable Low power regulator.</description>
64235 <description>Enable Low power regulator.</description>
64242 <description>Core Low Voltage Detector (LVD) enable.</description>
64249 <description>Disable Core Low Voltage Detector.</description>
64254 <description>Enable Core Low Voltage Detector.</description>
64261 <description>Exponential Timer enable.</description>
64268 <description>Disable the Exponential Timer.</description>
64273 <description>Enable the Exponential Timer.</description>
64280 <description>Low power mode refresh rate trim.</description>
64287 <description>Bandgap buffer enable to ADC. For test buffer.</description>
64294 <description>LDO CORE Low Voltage Detector (LVD) Trimmings.</description>
64301 … <description>High power regulator current adjustment. Max regulator current setting.</description>
64308 <description>Low Power regulation point select.</description>
64315 <description>750 mV.</description>
64320 <description>800 mV.</description>
64325 <description>850 mV.</description>
64330 <description>900 mV.</description>
64337 <description>Sense bus output select.</description>
64344 <description>High Power regulation point select.</description>
64353 …description>Flash High Voltage LDO control register [Reset by: PoR, Pin Reset, Brown Out Detectors…
64362 <description>Sets the LDO output level.</description>
64369 <description>1.650 V.</description>
64374 <description>1.700 V.</description>
64379 <description>1.750 V.</description>
64384 <description>1.800 V.</description>
64389 <description>1.850 V.</description>
64394 <description>1.900 V.</description>
64399 <description>1.950 V.</description>
64404 <description>2.0 V.</description>
64411 <description>Activate LDO bypass.</description>
64418 <description>Disable bypass mode (for normal operations).</description>
64423 <description>Activate LDO bypass.</description>
64430 <description>Put the output in high impedance state.</description>
64437 <description>Output in normal state.</description>
64442 <description>Output in High Impedance state.</description>
64449 <description>LDO Shutdown.</description>
64456 <description>Output in High normal state.</description>
64461 <description>Output in High Impedance state.</description>
64470 …description>eFUSE (One Time Programmable Memory) Programming LDO control register [Reset by: PoR, …
64479 <description>Sets the LDO output level.</description>
64486 <description>1.650 V.</description>
64491 <description>1.700 V.</description>
64496 <description>1.750 V.</description>
64501 <description>1.800 V.</description>
64506 <description>1.850 V.</description>
64511 <description>1.900 V.</description>
64516 <description>1.950 V.</description>
64521 <description>2.0 V.</description>
64528 <description>Activate LDO bypass.</description>
64535 <description>Disable bypass mode (for normal operations).</description>
64540 <description>Activate LDO bypass.</description>
64547 <description>Put the output in high impedance state.</description>
64554 <description>Output in High normal state.</description>
64559 <description>Output in High Impedance state.</description>
64566 <description>LDO Shutdown.</description>
64573 <description>Output in High normal state.</description>
64578 <description>Output in High Impedance state.</description>
64587 <description>VDDMAIN Brown Out Dectector control</description>
64596 <description>BoD trigger level.</description>
64603 <description>1.00 V.</description>
64608 <description>1.10 V.</description>
64613 <description>1.20 V.</description>
64618 <description>1.30 V.</description>
64623 <description>1.40 V.</description>
64628 <description>1.50 V.</description>
64633 <description>1.60 V.</description>
64638 <description>1.65 V.</description>
64643 <description>1.70 V.</description>
64648 <description>1.75 V.</description>
64653 <description>1.80 V.</description>
64658 <description>1.90 V.</description>
64663 <description>2.00 V.</description>
64668 <description>2.10 V.</description>
64673 <description>2.20 V.</description>
64678 <description>2.30 V.</description>
64683 <description>2.40 V.</description>
64688 <description>2.50 V.</description>
64693 <description>2.60 V.</description>
64698 <description>2.70 V.</description>
64703 <description>2.80 V.</description>
64708 <description>2.90 V.</description>
64713 <description>3.00 V.</description>
64718 <description>3.10 V.</description>
64723 <description>3.20 V.</description>
64728 <description>3.30 V.</description>
64733 <description>3.30 V.</description>
64738 <description>3.30 V.</description>
64743 <description>3.30 V.</description>
64748 <description>3.30 V.</description>
64753 <description>3.30 V.</description>
64758 <description>3.30 V.</description>
64765 <description>BoD Hysteresis control.</description>
64772 <description>25 mV.</description>
64777 <description>50 mV.</description>
64782 <description>75 mV.</description>
64787 <description>100 mV.</description>
64796 …description>Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Bro…
64805 <description>BoD trigger level.</description>
64812 <description>0.60 V.</description>
64817 <description>0.65 V.</description>
64822 <description>0.70 V.</description>
64827 <description>0.75 V.</description>
64832 <description>0.80 V.</description>
64837 <description>0.85 V.</description>
64842 <description>0.90 V.</description>
64847 <description>0.95 V.</description>
64854 <description>BOD_CORE Hysteresis control.</description>
64861 <description>25 mV.</description>
64866 <description>50 mV.</description>
64871 <description>75 mV.</description>
64876 <description>100 mV.</description>
64885 …description>LDO CORE (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Rese…
64894 <description>High Power regulation point select during Deep-Sleep.</description>
64901 …<description>LDO CORE module spare inputs control bits. Loaded at boot time with the values coming…
64908 <description>Exponential timer test enable.</description>
64915 <description>Internal Delay cell output.</description>
64922 <description>Exponential timer refresh output.</description>
64931 <description>Analog References fast wake-up Control register [Reset by: PoR]</description>
64940 …<description>Analog References fast wake-up in case of wake-up from a low power mode (DEEP-SLEEP, …
64947 …<description>Analog References fast wake-up feature is disbaledd in case of wake-up from any Low p…
64952 …<description>Analog References fast wake-up feature is enabledd in case of wake-up from any Low po…
64959 … <description>Analog References fast wake-up in case of Hardware Pin reset:</description>
64966 …<description>Analog References fast wake-up feature is disbaledd in case of Hardware Pin reset.</d…
64971 …<description>Analog References fast wake-up feature is enabledd in case of Hardware Pin reset.</de…
64980 …description>1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out De…
64989 <description>Frequency trimming bits.</description>
64996 <description>Debug control bits to set the analog/digital test modes.</description>
65003 <description>Divider selection bits.</description>
65010 <description>2.0.</description>
65015 <description>4.0.</description>
65020 <description>6.0.</description>
65025 <description>8.0.</description>
65030 <description>10.0.</description>
65035 <description>12.0.</description>
65040 <description>14.0.</description>
65045 <description>16.0.</description>
65050 <description>18.0.</description>
65055 <description>20.0.</description>
65060 <description>22.0.</description>
65065 <description>24.0.</description>
65070 <description>26.0.</description>
65075 <description>28.0.</description>
65080 <description>30.0.</description>
65085 <description>32.0.</description>
65090 <description>34.0.</description>
65095 <description>36.0.</description>
65100 <description>38.0.</description>
65105 <description>40.0.</description>
65110 <description>42.0.</description>
65115 <description>44.0.</description>
65120 <description>46.0.</description>
65125 <description>48.0.</description>
65130 <description>50.0.</description>
65135 <description>52.0.</description>
65140 <description>54.0.</description>
65145 <description>56.0.</description>
65150 <description>58.0.</description>
65155 <description>60.0.</description>
65160 <description>62.0.</description>
65165 <description>1.0.</description>
65174 …<description>32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detec…
65183 <description>Temperature coefficient trimming bits.</description>
65190 <description>Bias trimming bits (course frequency trimming).</description>
65197 <description>Capacitive dac calibration bits (fine frequency trimming).</description>
65204 <description>Debug control bits to set the analog/digital test modes.</description>
65213 …<description>32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors…
65222 <description>reference output current selection inputs.</description>
65229 <description>Oscillator Bypass Test Mode control.</description>
65236 <description>Oscillation mode.</description>
65241 <description>Bypass test mode is enabled.</description>
65248 <description>bias current selection inputs.</description>
65255 <description>oscillator amplitude selection inputs.</description>
65262 <description>Capa bank setting input.</description>
65269 <description>Capa bank setting output.</description>
65276 <description>Source selection for xo32k_captest_start_ao_set.</description>
65283 <description>Sourced from CAPTESTSTART.</description>
65288 <description>Sourced from calibration.</description>
65295 <description>Start test.</description>
65302 <description>Enable signal for cap test.</description>
65309 <description>Select the input for test.</description>
65316 <description>Oscillator output pin (osc_out).</description>
65321 <description>Oscillator input pin (osc_in).</description>
65330 <description>Analog Comparator control</description>
65339 <description>Hysteris when hyst = '1'.</description>
65346 <description>Hysteresis is disbaled.</description>
65351 <description>Hysteresis is enabled.</description>
65358 …<description>Dedicated control bit to select between internal VREF and VDDA (for the resistive lad…
65365 <description>Select internal VREF.</description>
65370 <description>Select VDDA.</description>
65377 <description>Low power mode.</description>
65384 <description>High speed mode.</description>
65389 <description>Low power mode (Low speed).</description>
65396 <description>Control word for P multiplexer:.</description>
65403 <description>VREF (See fiedl VREFINPUT).</description>
65408 <description>Pin P0_0.</description>
65413 <description>Pin P0_9.</description>
65418 <description>Pin P0_18.</description>
65423 <description>Pin P1_14.</description>
65428 <description>Pin P2_23.</description>
65435 <description>Control word for N multiplexer:.</description>
65442 <description>VREF (See field VREFINPUT).</description>
65447 <description>Pin P0_0.</description>
65452 <description>Pin P0_9.</description>
65457 <description>Pin P0_18.</description>
65462 <description>Pin P1_14.</description>
65467 <description>Pin P2_23.</description>
65474 … <description>Control reference voltage step, per steps of (VREFINPUT/31).</description>
65481 <description>Control the filtering of the Analog Comparator output.</description>
65488 <description>Bypass mode.</description>
65493 <description>Filter 1 clock period.</description>
65498 <description>Filter 2 clock period.</description>
65503 <description>Filter 3 clock period.</description>
65510 <description>Filter Clock divider.</description>
65517 … <description>Filter clock period duration equals 1 Analog Comparator clock period.</description>
65522 … <description>Filter clock period duration equals 2 Analog Comparator clock period.</description>
65527 … <description>Filter clock period duration equals 4 Analog Comparator clock period.</description>
65532 … <description>Filter clock period duration equals 8 Analog Comparator clock period.</description>
65537 … <description>Filter clock period duration equals 16 Analog Comparator clock period.</description>
65542 … <description>Filter clock period duration equals 32 Analog Comparator clock period.</description>
65547 … <description>Filter clock period duration equals 64 Analog Comparator clock period.</description>
65552 … <description>Filter clock period duration equals 128 Analog Comparator clock period.</description>
65561 <description>no description available</description>
65570 <description>Enable DCDC (self clearing bit).</description>
65577 <description>No effect.</description>
65582 … <description>Enable DCDC. Automatically reset to '0' by the Hardware.</description>
65589 <description>Disable DCDC (self clearing bit).</description>
65596 <description>No effect.</description>
65601 … <description>Disbale DCDC. Automatically reset to '0' by the Hardware.</description>
65608 <description>Enable LDO CORE High Power Mode (self clearing bit).</description>
65615 <description>No effect.</description>
65620 …<description>Enable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware.</descrip…
65627 <description>Disbale LDO CORE High Power Mode (self clearing bit).</description>
65634 <description>No effect.</description>
65639 …<description>Disable LDO CORE High Power Mode. Automatically reset to '0' by the Hardware.</descri…
65646 <description>Enable LDO CORE Low Power Mode (self clearing bit).</description>
65653 <description>No effect.</description>
65658 …<description>Enable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware.</descript…
65665 <description>Disable LDO CORE Low Power Mode (self clearing bit).</description>
65672 <description>No effect.</description>
65677 …<description>Disable LDO CORE Low Power Mode. Automatically reset to '0' by the Hardware.</descrip…
65686 …<description>Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset]</descriptio…
65695 …<description>Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down …
65702 <description>Rising edge detection is disbaled.</description>
65707 <description>Rising edge detection is enabled.</description>
65714 …<description>Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down…
65721 <description>Falling edge detection is disbaled.</description>
65726 <description>Falling edge detection is enabled.</description>
65733 …<description>Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down …
65740 <description>Rising edge detection is disbaled.</description>
65745 <description>Rising edge detection is enabled.</description>
65752 …<description>Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down…
65759 <description>Falling edge detection is disbaled.</description>
65764 <description>Falling edge detection is enabled.</description>
65771 …<description>Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down …
65778 <description>Rising edge detection is disbaled.</description>
65783 <description>Rising edge detection is enabled.</description>
65790 …<description>Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down…
65797 <description>Falling edge detection is disbaled.</description>
65802 <description>Falling edge detection is enabled.</description>
65809 …<description>Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down …
65816 <description>Rising edge detection is disbaled.</description>
65821 <description>Rising edge detection is enabled.</description>
65828 …<description>Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down…
65835 <description>Falling edge detection is disbaled.</description>
65840 <description>Falling edge detection is enabled.</description>
65847 …<description>Enable / disable detection of rising edge events on Wake Up 4 pin in Deep Power Down …
65854 <description>Rising edge detection is disbaled.</description>
65859 <description>Rising edge detection is enabled.</description>
65866 …<description>Enable / disable detection of falling edge events on Wake Up 4 pin in Deep Power Down…
65873 <description>Falling edge detection is disbaled.</description>
65878 <description>Falling edge detection is enabled.</description>
65885 … <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
65892 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
65897 <description>Pull-down. Pull-down resistor enabled.</description>
65902 <description>Pull-up. Pull-up resistor enabled.</description>
65907 <description>Repeater. Repeater mode.</description>
65914 … <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
65921 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
65926 <description>Pull-down. Pull-down resistor enabled.</description>
65931 <description>Pull-up. Pull-up resistor enabled.</description>
65936 <description>Repeater. Repeater mode.</description>
65943 … <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
65950 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
65955 <description>Pull-down. Pull-down resistor enabled.</description>
65960 <description>Pull-up. Pull-up resistor enabled.</description>
65965 <description>Repeater. Repeater mode.</description>
65972 … <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
65979 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
65984 <description>Pull-down. Pull-down resistor enabled.</description>
65989 <description>Pull-up. Pull-up resistor enabled.</description>
65994 <description>Repeater. Repeater mode.</description>
66001 … <description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
66008 … <description>Inactive. Inactive (no pull-down/pull-up resistor enabled).</description>
66013 <description>Pull-down. Pull-down resistor enabled.</description>
66018 <description>Pull-up. Pull-up resistor enabled.</description>
66023 <description>Repeater. Repeater mode.</description>
66030 … <description>Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 10 to 19).</description>
66037 <description>WAKEUP IO PAD mode control comes from IOCON.</description>
66042 … <description>WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 10 to 19).</description>
66049 <description>WAKEUP IO event detector reset control.</description>
66056 <description>Bloc is reset.</description>
66061 <description>Bloc is not reset.</description>
66070 <description>Wake-up I/O source</description>
66079 …<description>Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.</de…
66086 …<description>Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.</descriptio…
66091 … <description>Last wake up from Deep Power down mode was triggred by wake up I/O 0.</description>
66098 …<description>Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.</de…
66105 …<description>Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.</descriptio…
66110 … <description>Last wake up from Deep Power down mode was triggred by wake up I/O 1.</description>
66117 …<description>Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.</de…
66124 …<description>Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.</descriptio…
66129 … <description>Last wake up from Deep Power down mode was triggred by wake up I/O 2.</description>
66136 …<description>Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.</de…
66143 …<description>Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.</descriptio…
66148 … <description>Last wake up from Deep Power down mode was triggred by wake up I/O 3.</description>
66155 …<description>Allows to identify Wake up I/O 4 as the wake-up source from Deep Power Down mode.</de…
66162 …<description>Last wake up from Deep Power down mode was NOT triggred by wake up I/O 4.</descriptio…
66167 … <description>Last wake up from Deep Power down mode was triggred by wake up I/O 4.</description>
66174 …<description>In DEEP-POWER-DOWN mode, indicates which wake up I/O event occured first when several…
66181 <description>None</description>
66186 <description>Wake up I/O 0</description>
66191 <description>Wake up I/O 1</description>
66196 <description>Wake up I/O 2</description>
66201 <description>Wake up I/O 3</description>
66206 <description>Wake up I/O 4</description>
66215 <description>Life Cycle State as configured in the OTP</description>
66224 <description>Life Cycle state</description>
66231 <description>NXP Blank</description>
66236 <description>NXP Fab</description>
66241 <description>NXP provisioned</description>
66246 <description>NXP failure analysis (field return)</description>
66251 <description>NXP Development sample</description>
66256 <description>Bricked sample</description>
66265 <description>Power status from various analog modules (DCDC, LDO, etc)</description>
66274 <description>DCDC converter power OK.</description>
66281 <description>Flash High Voltage LDO power OK.</description>
66288 <description>eFUSE Programming LDO power OK.</description>
66295 <description>CORE LDO power OK.</description>
66304 <description>Clock status</description>
66313 <description>XTAL oscillator 32 K OK signal.</description>
66320 <description>FRO 1 MHz CCO voltage detector output.</description>
66327 … <description>XTAL32 KHZ oscillator oscillation failure detection indicator.</description>
66334 …<description>No oscillation failure has been detetced since the last time this bit has been cleare…
66339 …<description>At least one oscillation failure has been detetced since the last time this bit has b…
66348 <description>Always-on 0</description>
66357 <description>General purpose always on domain data storage.</description>
66366 <description>Always-on 1</description>
66375 <description>The last chip reset was caused by a Power On Reset.</description>
66382 <description>The last chip reset was caused by a Pin Reset.</description>
66389 …<description>The last chip reset was caused by a Brown Out Detector (BoD), either BOD_VDDMAIN or B…
66396 …<description>The last chip reset was caused by a System Reset requested by the ARM CPU.</descripti…
66403 <description>The last chip reset was caused by the Watchdog Timer.</description>
66410 <description>The last chip reset was caused by a Software event.</description>
66417 … <description>A Wake-up I/O reset event occured during DEEP-POWER-DOWN mode.</description>
66424 <description>A RTC event occured during DEEP-POWER-DOWN mode.</description>
66431 <description>An OS Timer event occured during a DEEP-POWER-DOWN mode.</description>
66438 <description>The last chip reset was caused by the code Watchdog.</description>
66445 …description>In DEEP-POWER-DOWN mode, indicates which reset event occured first, between a wake up …
66452 <description>No event</description>
66457 <description>WAKEUPIO</description>
66462 <description>RTC</description>
66467 …<description>Both WAKEUPIO and RTC events occured at the same time (the 2 events occured within 1 …
66472 <description>OSTIMER</description>
66477 …<description>Both WAKEUPIO and OSTIMER events occured at the same time (the 2 events occured withi…
66482 …<description>Both RTC and OSTIMER events occured at the same time (the 2 events occured within 1 n…
66487 …<description>WAKEUPIO, RTC and OSTIMER events occured at the same time (the 3 events occured withi…
66494 <description>ROM Boot Fatal Error Counter.</description>
66503 …<description>General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Res…
66512 <description>General purpose always on domain data storage.</description>
66521 …<description>Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep P…
66530 <description>Reserved.</description>
66537 <description>Control the activation of LDO MEM High Z mode.</description>
66544 <description>LDO MEM High Z mode is disbaledd.</description>
66549 <description>LDO MEM High Z mode is enabledd.</description>
66556 <description>Reserved.</description>
66563 …description>Controls LDO MEM bleed current. This field is expected to be controlled by the Low Pow…
66570 <description>LDO_MEM bleed current is enabledd.</description>
66575 …description>LDO_MEM bleed current is disbaledd. Should be set before entering in Deep Sleep low po…
66582 <description>Reserved.</description>
66589 <description>VREF isolation control.</description>
66596 <description>VREF module isolation is disbaledd.</description>
66601 <description>VREF module isolation is enabledd.</description>
66610 <description>Dummy Status bus from PMU</description>
66619 <description>Dummy Status bus from PMU.</description>
66628 <description>32 KHz clocks source control</description>
66637 …description>Select the 32K oscillator to be used in for the RTC, the OS Event Timer and the rest o…
66644 <description>FRO 32 KHz.</description>
66649 <description>XTAL 32KHz.</description>
66658 <description>OS Event Timer control</description>
66667 <description>Active high reset.</description>
66674 <description>Enable OSTIMER 32 KHz clock.</description>
66681 …<description>Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode).</…
66688 <description>Select OS Event Timer Clock source</description>
66695 <description>32-KHz Free Running Oscillator (FRO)</description>
66700 <description>32-KHz Crystal Oscillator (XTAL)</description>
66705 <description>1-MHz FRO</description>
66710 <description>System Bus clock</description>
66719 …description>Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN …
66728 …<description>Controls Comparators 1/2/3 Bias power during DEEP-SLEEP (always shut down during POWE…
66735 <description>Analog Bias is powered on during low power mode.</description>
66740 <description>Analog Bias is powered off during low power mode.</description>
66747 …<description>Controls High Speed Comparator0 DAC power during DEEP-SLEEP (always shut down during …
66754 … <description>High Speed Comparator0 DAC is powered on during low power mode.</description>
66759 … <description>High Speed Comparator0 DAC is powered off during low power mode.</description>
66766 …<description>Controls High Speed Comparator1 DAC power during DEEP-SLEEP (always shut down during …
66773 … <description>High Speed Comparator1 DAC is powered on during low power mode.</description>
66778 … <description>High Speed Comparator1 DAC is powered off during low power mode.</description>
66785 …<description>Controls High Speed Comparator2 DAC power during DEEP-SLEEP (always shut down during …
66792 … <description>High Speed Comparator2 DAC is powered on during low power mode.</description>
66797 … <description>High Speed Comparator2 DAC is powered off during low power mode.</description>
66804 …<description>Controls DAC0 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-…
66811 <description>DAC0 is powered on during low power mode.</description>
66816 <description>DAC0 is powered off during low power mode.</description>
66823 …<description>Controls DAC1 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-…
66830 <description>DAC1 is powered on during low power mode.</description>
66835 <description>DAC1 is powered off during low power mode.</description>
66842 …<description>Controls DAC2 power during DEEP-SLEEP & POWER-DOWN (always shut down during DEEP-…
66849 <description>DAC2 is powered on during low power mode.</description>
66854 <description>DAC2 is powered off during low power mode.</description>
66861 …<description>Controls DAC0 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always d…
66868 <description>DAC Stop Mode is disbaledd.</description>
66873 <description>DAC Stop Mode is enabledd.</description>
66880 …<description>Controls DAC1 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always d…
66887 <description>DAC Stop Mode is disbaledd.</description>
66892 <description>DAC Stop Mode is enabledd.</description>
66899 …<description>Controls DAC2 Stop mode during DEEP-SLEEP & POWER-DOWN (DAC stop mode is always d…
66906 <description>DAC Stop Mode is disbaledd.</description>
66911 <description>DAC Stop Mode is enabledd.</description>
66920 …<description>Record time-out errors that might occur at different stages during IC power up</descr…
66929 …<description>1: a time out event occured during power up when waiting for DCDC to become functiona…
66936 …<description>1: a time out event occured during power up when waiting for LDO Flash NV to become f…
66943 …<description>1: a time out event occured during power up when waiting for SRAM to become functiona…
66950 …<description>1: a time out event occured during power up when waiting for Flash initialization.</d…
66957 …<description>1: a time out event occured during deep sleep when waiting for LDO Flash NV or SRAM s…
66964 …<description>1: a time out event occured during deep sleep when waiting for DCDC to become functio…
66971 …<description>1: a time out event occured during deep sleep when waiting for LDO Flash NV to become…
66978 …<description>1: a time out event occured during deep sleep when waiting for SRAM to become functio…
66985 …<description>1: a time out event occured during power down when waiting for for LDO Flash NV or SR…
66992 …<description>1: a time out event occured during power down when waiting for DCDC or BOD_VDDMAIN to…
66999 …<description>1: a time out event occured during power down when waiting for LDO Flash NV to become…
67006 …<description>1: a time out event occured during power down when waiting for SRAM to become functio…
67013 …<description>1: a time out event occured during power down when waiting for Flash initialization.<…
67022 <description>Various time out values used by PMC state machines</description>
67031 …description>(400 us @ 1 MHz as default) Maximum value the PMC state machine will wait for an ackno…
67038 …<description>(25 us @ 1 MHz as default) Time out value used when shutting down Flash LDOs.</descri…
67045 …<description>(35 us @ 1 MHz as default) Time out value used when powerup the BOD_CORE and BOD_VDDM…
67052 …<description>(13 us @ 1 MHz as default) Time out value used when powerup the FRO 192 MHz to initia…
67061 …description>Controls the power to various modules during Low Power modes - DEEP-SLEEP, POWER-DOWN …
67070 …<description>Controls Analog Bias power during DEEP-SLEEP and POWER-DOWN (always shut down during …
67077 <description>Analog Bias is powered on during low power mode.</description>
67082 <description>Analog Bias is powered off during low power mode.</description>
67089 …<description>Controls Core Logic BoD power during DEEP-SLEEP and POWER-DOWN (always shut down duri…
67096 <description>BOD_CORE is powered on during low power mode.</description>
67101 <description>BOD_CORE is powered off during low power mode.</description>
67108 …<description>Controls BOD_VDDMAIN power during DEEP-SLEEP and POWER-DOWN (always shut down during …
67115 <description>BOD_VDDMAIN is powered on during low power mode.</description>
67120 <description>BOD_VDDMAIN is powered off during low power mode.</description>
67127 …<description>Controls 1 MHz Free Running Oscillator power during DEEP-SLEEP, POWER-DOWN and DEEP-P…
67134 <description>FRO 1MHz is powered on during low power mode.</description>
67139 <description>FRO 1MHz is powered off during low power mode.</description>
67146 …<description>Controls 192MHz Free Running Oscillator power during DEEP-SLEEP (always shut down dur…
67153 <description>FRO 192 MHz is powered on during low power mode.</description>
67158 <description>FRO 192 MHz is powered off during low power mode.</description>
67165 … <description>Controls power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.</description>
67172 <description>FRO 32 KHz is powered on during low power mode.</description>
67177 <description>FRO 32 KHz is powered off during low power mode.</description>
67184 …<description>Controls crystal 32 KHz power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.</des…
67191 <description>crystal 32 KHz is powered on during low power mode.</description>
67196 <description>crystal 32 KHz is powered off during low power mode.</description>
67203 …<description>Controls high speed crystal power during DEEP-SLEEP (always shut down during POWER-DO…
67210 <description>High speed crystal is powered on during low power mode.</description>
67215 … <description>High speed crystal is powered off during low power mode.</description>
67222 …<description>Controls System PLL (also refered as PLL0) power during DEEP-SLEEP (always shut down …
67229 … <description>System PLL (also refered as PLL0) is powered on during low power mode.</description>
67234 … <description>System PLL (also refered as PLL0) is powered off during low power mode.</description>
67241 …<description>Controls USB PLL (also refered as PLL1) power during DEEP-SLEEP (always shut down dur…
67248 … <description>USB PLL (also refered as PLL1) is powered on during low power mode.</description>
67253 … <description>USB PLL (also refered as PLL1) is powered off during low power mode.</description>
67260 …<description>Controls USB Full Speed phy power during DEEP-SLEEP (always shut down during POWER-DO…
67267 <description>USB Full Speed phy is powered on during low power mode.</description>
67272 … <description>USB Full Speed phy is powered off during low power mode.</description>
67279 …<description>Controls Analog Comparator power during DEEP-SLEEP and POWER-DOWN (always shut down d…
67286 <description>Analog Comparator is powered on during low power mode.</description>
67291 <description>Analog Comparator is powered off during low power mode.</description>
67298 …<description>Controls Memories LDO power during DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN.</descr…
67305 <description>Memories LDO is powered on during low power mode.</description>
67310 <description>Memories LDO is powered off during low power mode.</description>
67317 …<description>Controls USB high speed LDO power during DEEP-SLEEP (always shut down during POWER-DO…
67324 <description>USB high speed LDO is powered on during low power mode.</description>
67329 … <description>USB high speed LDO is powered off during low power mode.</description>
67336 …<description>Controls High speed crystal LDO power during DEEP-SLEEP (always shut down during POWE…
67343 … <description>High speed crystal LDO is powered on during low power mode.</description>
67348 … <description>High speed crystal LDO is powered off during low power mode.</description>
67355 …<description>Controls Flash NV (high voltage) LDO power during DEEP-SLEEP (always shut down during…
67362 … <description>Flash NV (high voltage) is powered on during low power mode.</description>
67367 … <description>Flash NV (high voltage) is powered off during low power mode.</description>
67374 …description>Controls PLL0 Spread Sprectrum module power during DEEP-SLEEP (PLL0 Spread Spectrum is…
67381 … <description>PLL0 Spread Sprectrum module is powered on during low power mode.</description>
67386 … <description>PLL0 Spread Sprectrum module is powered off during low power mode.</description>
67393 …<description>Controls ROM power during DEEP-SLEEP (ROM is always shut down during POWER-DOWN and D…
67400 <description>ROM is powered on during low power mode.</description>
67405 <description>ROM is powered off during low power mode.</description>
67412 …<description>Controls High Speed Comparator0 power during DEEP-SLEEP (always shut down during POWE…
67419 … <description>High Speed Comparator is powered on during low power mode.</description>
67424 … <description>High Speed Comparator is powered off during low power mode.</description>
67431 …<description>Controls High Speed Comparator1 power during DEEP-SLEEP (always shut down during POWE…
67438 … <description>High Speed Comparator is powered on during low power mode.</description>
67443 … <description>High Speed Comparator is powered off during low power mode.</description>
67450 …<description>Controls High Speed Comparator2 power during DEEP-SLEEP (always shut down during POWE…
67457 … <description>High Speed Comparator is powered on during low power mode.</description>
67462 … <description>High Speed Comparator is powered off during low power mode.</description>
67469 …<description>Controls Operational Amplifier0 power during DEEP-SLEEP (always shut down during POWE…
67476 … <description>Operational Amplifier is powered on during low power mode.</description>
67481 … <description>Operational Amplifier is powered off during low power mode.</description>
67488 …<description>Controls Operational Amplifier1 power during DEEP-SLEEP (always shut down during POWE…
67495 … <description>Operational Amplifier is powered on during low power mode.</description>
67500 … <description>Operational Amplifier is powered off during low power mode.</description>
67507 …<description>Controls Operational Amplifier2 power during DEEP-SLEEP (always shut down during POWE…
67514 … <description>Operational Amplifier is powered on during low power mode.</description>
67519 … <description>Operational Amplifier is powered off during low power mode.</description>
67526 …<description>Controls VREF power during DEEP-SLEEP (always shut down during POWER-DOWN and DEEP-PO…
67533 <description>VREF is powered on during low power mode.</description>
67538 <description>VREF is powered off during low power mode.</description>
67547 …description>Controls all SRAM instances power down modes during Low Power modes [Reset by: PoR, Pi…
67556 <description>Controls RAM_X0 power down modes during low power modes.</description>
67563 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67568 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67575 <description>Controls RAM_00 power down modes during low power modes.</description>
67582 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67587 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67594 <description>Controls RAM_01 power down modes during low power modes.</description>
67601 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67606 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67613 <description>Controls RAM_02 power down modes during low power modes.</description>
67620 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67625 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67632 <description>Controls RAM_03 power down modes during low power modes.</description>
67639 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67644 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67651 <description>Controls RAM_10 power down modes during low power modes.</description>
67658 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67663 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67670 <description>Controls RAM_20 power down modes during low power modes.</description>
67677 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67682 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67689 <description>Controls RAM_30 power down modes during low power modes.</description>
67696 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67701 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67708 <description>Controls RAM_40 power down modes during low power modes.</description>
67715 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67720 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67727 <description>Controls RAM_41 power down modes during low power modes.</description>
67734 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67739 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67746 <description>Controls RAM_42 power down modes during low power modes.</description>
67753 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67758 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67765 <description>Controls RAM_43 power down modes during low power modes.</description>
67772 …description>DEEP-SLEEP: the SRAM instance keeps the configuration it has before entering DEEP-SLEE…
67777 …<description>The SRAM is in 'Deep Sleep' mode (In this mode there is data retention).</description>
67784 …<description>Controls Embedded Flash Cache SRAM power down modes during low power modes.</descript…
67791 … <description>Controls FlexSPI Cache SRAM power down modes during low power modes.</description>
67798 …description>Controls FlexSPI Dual Port Register Files power down modes during deep sleep. In power…
67805 …description>DEEP-SLEEP: all FlexSPI dual port register files keep the configuration they had befor…
67810 …description>DEEP-SLEEP: all FlexSPI Dual Port egister files are in 'Power Down' mode (In this mode…
67819 <description>Power configuration 0</description>
67828 <description>Controls power to Bulk DCDC Converter.</description>
67835 <description>DCDC is powered.</description>
67840 <description>DCDC is powered down.</description>
67847 <description>Controls power to .</description>
67854 <description>Analog Bias is powered.</description>
67859 <description>Analog Bias is powered down.</description>
67866 <description>Controls power to Core Brown Out Detector (BOD_CORE).</description>
67873 <description>BOD_CORE is powered.</description>
67878 <description>BOD_CORE is powered down.</description>
67885 <description>Controls power to VDDMAIN Brown Out Detector (BOD_VDDMAIN).</description>
67892 <description>BOD_VDDMAIN is powered.</description>
67897 <description>BOD_VDDMAIN is powered down.</description>
67904 …<description>Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96…
67911 <description>FRO 192MHz is powered.</description>
67916 <description>FRO 192MHz is powered down.</description>
67923 <description>Controls power to the Free Running Oscillator (FRO) 32 KHz.</description>
67930 <description>FRO32KHz is powered.</description>
67935 <description>FRO32KHz is powered down.</description>
67942 <description>Controls power to crystal 32 KHz.</description>
67949 <description>Crystal 32KHz is powered.</description>
67954 <description>Crystal 32KHz is powered down.</description>
67961 <description>Controls power to high speed crystal.</description>
67968 <description>High speed crystal is powered.</description>
67973 <description>High speed crystal is powered down.</description>
67980 <description>Controls power to System PLL (also refered as PLL0).</description>
67987 <description>PLL0 is powered.</description>
67992 <description>PLL0 is powered down.</description>
67999 <description>Controls power to USB PLL (also refered as PLL1).</description>
68006 <description>PLL1 is powered.</description>
68011 <description>PLL1 is powered down.</description>
68018 <description>Controls power to USB Full Speed phy.</description>
68025 <description>USB Full Speed phy is powered.</description>
68030 <description>USB Full Speed phy is powered down.</description>
68037 <description>Controls power to Analog Comparator.</description>
68044 <description>Analog Comparator is powered.</description>
68049 <description>Analog Comparator is powered down.</description>
68056 <description>Controls power to Memories LDO.</description>
68063 <description>Memories LDO is powered.</description>
68068 <description>Memories LDO is powered down.</description>
68075 <description>Controls power to eFUSE Programming LDO.</description>
68082 <description>USB high speed LDO is powered.</description>
68087 <description>USB high speed LDO is powered down.</description>
68094 <description>Controls power to high speed crystal LDO.</description>
68101 <description>High speed crystal LDO is powered.</description>
68106 <description>High speed crystal LDO is powered down.</description>
68113 <description>Controls power to Flasn NV (high voltage) LDO.</description>
68120 <description>Flash NV LDO is powered.</description>
68125 <description>Flash NV LDO is powered down.</description>
68132 <description>Controls power to System PLL (PLL0) Spread Spectrum module.</description>
68139 <description>PLL0 Sread spectrum module is powered.</description>
68144 <description>PLL0 Sread spectrum module is powered down.</description>
68151 <description>Controls power to High Speed Comparator0</description>
68158 <description>High Speed Comparator0 is powered on.</description>
68163 <description>High Speed Comparator0 is powered down.</description>
68170 <description>Controls power to High Speed Comparator1</description>
68177 <description>High Speed Comparator1 is powered on</description>
68182 <description>High Speed Comparator1 is powered down</description>
68189 <description>Controls power to High Speed Comparator2</description>
68196 <description>High Speed Comparator2 is powered on</description>
68201 <description>High Speed Comparator2 is powered down</description>
68208 <description>Controls power to Operational Amplifier0</description>
68215 <description>Operational Amplifier0 is powered on.</description>
68220 <description>Operational Amplifier0 is powered down.</description>
68227 <description>Controls power to Operational Amplifier1</description>
68234 <description>Operational Amplifier1 is powered on</description>
68239 <description>Operational Amplifier1 is powered down</description>
68246 <description>Controls power to Operational Amplifier2</description>
68253 <description>Operational Amplifier2 is powered on</description>
68258 <description>Operational Amplifier2 is powered down</description>
68265 <description>Controls power to VREF module</description>
68272 <description>VREF is powered on.</description>
68277 <description>VREF is powered down.</description>
68286 <description>Power configuration 1</description>
68295 <description>Controls power of Comparators 1/2/3 bias.</description>
68302 <description>Comparators 1/2/3 bias is powered.</description>
68307 <description>Comparators 1/2/3 bias is powered down.</description>
68314 <description>Controls power to High Speed Comparator0 DAC.</description>
68321 <description>High Speed Comparator0 DAC is powered.</description>
68326 <description>High Speed Comparator0 DAC is powered down.</description>
68333 <description>Controls power to High Speed Comparator1 DAC.</description>
68340 <description>High Speed Comparator1 DAC is powered.</description>
68345 <description>High Speed Comparator1 DAC is powered down.</description>
68352 <description>Controls power to High Speed Comparator2 DAC.</description>
68359 <description>High Speed Comparator2 DAC is powered.</description>
68364 <description>High Speed Comparator2 DAC is powered down.</description>
68371 <description>Controls power to DAC0.</description>
68378 <description>DAC0 is powered.</description>
68383 <description>DAC0 is powered down.</description>
68390 <description>Controls power to DAC1.</description>
68397 <description>DAC1 is powered.</description>
68402 <description>DAC1 is powered down.</description>
68409 <description>Controls power to DAC2.</description>
68416 <description>DAC2 is powered.</description>
68421 <description>DAC2 is powered down.</description>
68428 <description>Controls DAC0 Stop mode.</description>
68435 <description>DAC0 Stop mode is disbaledd.</description>
68440 <description>DAC0 Stop mode is enabledd.</description>
68447 <description>Controls DAC1 Stop mode.</description>
68454 <description>DAC1 Stop mode is disbaledd.</description>
68459 <description>DAC1 Stop mode is enabledd.</description>
68466 <description>Controls DAC2 Stop mode.</description>
68473 <description>DAC2 Stop mode is disbaledd.</description>
68478 <description>DAC2 Stop mode is enabledd.</description>
68487 <description>Power configuration set 0</description>
68496 …<description>Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 reg…
68505 <description>Power configuration set 1</description>
68514 …<description>Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 reg…
68523 <description>Power configuration clear 0</description>
68532 …<description>Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 r…
68541 <description>Power configuration clear 1</description>
68550 …<description>Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 r…
68559 …<description>ROM control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Res…
68568 <description>Shutdown pin (active low).</description>
68575 <description>Shutdown delayed pin (active low).</description>
68582 <description>Read Margin Enable.</description>
68589 <description>read margin control setting.</description>
68596 <description>precharge margin control setting.</description>
68603 <description>VDDMIN enable setting.</description>
68612 …<description>All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset…
68621 <description>Source Biasing voltage.</description>
68628 <description>Low leakage.</description>
68633 <description>Medium leakage.</description>
68638 <description>Highest leakage.</description>
68643 <description>Disable.</description>
68650 <description>Read Margin control settings.</description>
68657 <description>Write Margin control settings.</description>
68664 <description>Write read margin enable.</description>
68673 …description>RAM_X0, and RAM_00 to RAM_30 power modes controls [Reset by: PoR, Pin Reset, Brown Out…
68682 <description>RAM_X0 Light Sleep mode.</description>
68689 <description>RAM_X0 Deep sleep mode.</description>
68696 <description>RAM_X0 Deep sleep delayed.</description>
68703 <description>RAM_X0 Sleep mode disable.</description>
68710 <description>RAM_00 Light Sleep mode.</description>
68717 <description>RAM_00 Deep sleep mode.</description>
68724 <description>RAM_00 Deep sleep delayed.</description>
68731 <description>RAM_00 Sleep mode disable.</description>
68738 <description>RAM_01 Light Sleep mode.</description>
68745 <description>RAM_01 Deep sleep mode.</description>
68752 <description>RAM_01 Deep sleep delayed.</description>
68759 <description>RAM_01 Sleep mode disable.</description>
68766 <description>RAM_02 Light Sleep mode.</description>
68773 <description>RAM_02 Deep sleep mode.</description>
68780 <description>RAM_02 Deep sleep delayed.</description>
68787 <description>RAM_02 Sleep mode disable.</description>
68794 <description>RAM_03 Light Sleep mode.</description>
68801 <description>RAM_03 Deep sleep mode.</description>
68808 <description>RAM_03 Deep sleep delayed.</description>
68815 <description>RAM_03 Sleep mode disable.</description>
68822 <description>RAM_10 Light Sleep mode.</description>
68829 <description>RAM_10 Deep sleep mode.</description>
68836 <description>RAM_10 Deep sleep delayed.</description>
68843 <description>RAM_10 Sleep mode disable.</description>
68850 <description>RAM_20 Light Sleep mode.</description>
68857 <description>RAM_20 Deep sleep mode.</description>
68864 <description>RAM_20 Deep sleep delayed.</description>
68871 <description>RAM_20 Sleep mode disable.</description>
68878 <description>RAM_30 Light Sleep mode.</description>
68885 <description>RAM_30 Deep sleep mode.</description>
68892 <description>RAM_30 Deep sleep delayed.</description>
68899 <description>RAM_30 Light Sleep mode delayed.</description>
68908 …description>RAM_40 to RAM_43 power modes controls [Reset by: PoR, Pin Reset, Brown Out Detectors R…
68917 <description>RAM_40 Light Sleep mode.</description>
68924 <description>RAM_40 Deep sleep mode.</description>
68931 <description>RAM_40 Deep sleep delayed.</description>
68938 <description>RAM_40 Sleep mode disable.</description>
68945 <description>RAM_41 Light Sleep mode.</description>
68952 <description>RAM_41 Deep sleep mode.</description>
68959 <description>RAM_41 Deep sleep delayed.</description>
68966 <description>RAM_41 Sleep mode disable.</description>
68973 <description>RAM_42 Light Sleep mode.</description>
68980 <description>RAM_42 Deep sleep mode.</description>
68987 <description>RAM_42 Deep sleep delayed.</description>
68994 <description>RAM_42 Sleep mode disable.</description>
69001 <description>RAM_43 Light Sleep mode.</description>
69008 <description>RAM_43 Deep sleep mode.</description>
69015 <description>RAM_43 Deep sleep delayed.</description>
69022 <description>RAM_43 Sleep mode disable.</description>
69029 <description>Flash Cache RAM Light Sleep mode.</description>
69036 <description>Flash Cache RAM Deep sleep mode.</description>
69043 <description>Flash Cache RAM Deep sleep delayed.</description>
69050 <description>Flash Cache RAM Sleep mode disable.</description>
69057 <description>Flex SPI Cache RAM Light Sleep mode.</description>
69064 <description>Flex SPI Cache RAM Deep sleep mode.</description>
69071 <description>Flex SPI Cache RAM Deep sleep delayed.</description>
69078 <description>Flex SPI Cache RAM Sleep mode disable.</description>
69087 …description>All SRAMs Read/Write assist control signals [Reset by: PoR, Pin Reset, Brown Out Detec…
69096 <description>Read Assist control for all 4 Kbytes size SRAM instances.</description>
69103 <description>Read assist is enabled for all 4 Kbytes SRAM instances.</description>
69108 … <description>Read assist is disbaled for all 4 Kbytes SRAM instances.</description>
69115 …<description>Read assist bias settings always Margin control for assist for all 4 Kbytes size SRAM…
69122 <description>Write Assist enable for all 4 Kbytes size SRAM instances.</description>
69129 … <description>Write assist is enabled for all 4 Kbytes SRAM instances.</description>
69134 … <description>Write assist is disbaled for all 4 Kbytes SRAM instances.</description>
69141 …<description>Write assist bias settings always Margin control for assist for all 4 Kbytes size SRA…
69148 <description>Read Assist control for all 16 Kbytes size SRAM instances.</description>
69155 … <description>Read assist is enabled for all 16 Kbytes SRAM instances.</description>
69160 … <description>Read assist is disbaled for all 16 Kbytes SRAM instances.</description>
69167 …<description>Read assist bias settings always Margin control for assist for all 16Kbytes size SRAM…
69174 <description>Write Assist enable for all 16 Kbytes size SRAM instances.</description>
69181 … <description>Write assist is enabled for all 16 Kbytes SRAM instances.</description>
69186 … <description>Write assist is disbaled for all 16 Kbytes SRAM instances.</description>
69193 …<description>Write assist bias settings always Margin control for assist for all 16Kbytes size SRA…
69200 <description>Read Assist control for all 32 Kbytes size SRAM instances.</description>
69207 … <description>Read assist is enabled for all 32 Kbytes SRAM instances.</description>
69212 … <description>Read assist is disbaled for all 32 Kbytes SRAM instances.</description>
69219 …<description>Read assist bias settings always Margin control for assist for all 32Kbytes size SRAM…
69226 <description>Write Assist enable for all 32 Kbytes size SRAM instances.</description>
69233 … <description>Write assist is enabled for all 32 Kbytes SRAM instances.</description>
69238 … <description>Write assist is disbaled for all 32 Kbytes SRAM instances.</description>
69245 …<description>Write assist bias settings always Margin control for assist for all 32Kbytes size SRA…
69252 … <description>Read Assist control for all Flash Cache (8 Kbytes size) SRAM instances.</description>
69259 <description>Read assist is enabled.</description>
69264 <description>Write assist is disbaled.</description>
69271 …<description>Read assist bias settings always Margin control for assist for all Flash Cache SRAM i…
69278 … <description>Write Assist enable for all Flash Cache (8 Kbytes size) SRAM instances.</description>
69285 <description>Write assist is enabled.</description>
69290 <description>Write assist is disbaled.</description>
69297 …<description>Write assist bias settings always Margin control for assist for all Flash Cache SRAM …
69304 …<description>Read Assist control for all FlexSPI Cache (8 Kbytes size) SRAM instances.</descriptio…
69311 <description>Read assist is enabled.</description>
69316 <description>Write assist is disbaled.</description>
69323 …<description>Read assist bias settings always Margin control for assist for all FlexSPI Cache SRAM…
69330 …<description>Write Assist enable for all FlexSPI Cache (8 Kbytes size) SRAM instances.</descriptio…
69337 <description>Write assist is enabled.</description>
69342 <description>Write assist is disbaled.</description>
69349 …<description>Write assist bias settings always Margin control for assist for all FlexSPI Cache SRA…
69358 …description>All FlexSPI Dual Port Register Files power modes controls [Reset by: PoR, Pin Reset, B…
69367 <description>All FlexSPI Dual Port register files power down mode.</description>
69374 … <description>Enable power down mode for all FlexSPI Dual Port register files.</description>
69379 … <description>Disable power down mode for all FlexSPI Dual Port register files.</description>
69386 …<description>All FlexSPI Dual Port register files read wordline drivers power control.</descriptio…
69393 …<description>All FlexSPI Dual Port register files read wordline drivers are NOT power gated.</desc…
69398 …<description>All FlexSPI Dual Port register files read wordline drivers are power gated.</descript…
69405 …<description>All FlexSPI Dual Port register files write wordline drivers power control.</descripti…
69412 …<description>All FlexSPI Dual Port register files write wordline drivers are NOT power gated.</des…
69417 …<description>All FlexSPI Dual Port register files write wordline drivers are power gated.</descrip…
69424 …<description>All FlexSPI Dual Port register files Read/Write trim enable. Not to be used in produc…
69431 <description>Disable VALRD/VALWR.</description>
69436 <description>Enable VALRD/VALWR.</description>
69443 …<description>All FlexSPI Dual Port register files Read cycle characterisation. Not to be used in p…
69450 …<description>All FlexSPI Dual Port register files Write cycle characterisation. Not to be used in …
69459 …<description>Sense control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down R…
69468 <description>enables the wd_sense 0.</description>
69475 <description>Sense0 is disbaled.</description>
69480 <description>Sense0 is enabled.</description>
69487 <description>enables the wd_sense 1.</description>
69494 <description>Sense1 is disbaled.</description>
69499 <description>Sense1 is enabled.</description>
69506 <description>wd_sense scale set.</description>
69513 <description>Selects the test point to be tested by the wd_sense 0.</description>
69520 <description>Selects the test point to be tested by the wd_sense 1.</description>
69527 <description>Digital output of the wd_sense 0 block.</description>
69534 <description>Digital output of the wd_sense 1 block.</description>
69543 …<description>ACBUS and DCBUS control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Po…
69552 <description>AC Bus control.</description>
69559 <description>DC Bus control.</description>
69568 …<description>Analog I/O Debug control. [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep …
69577 <description>Controls PMU DC BUS Voltage Output, pin P. P0_26</description>
69584 <description>Analog switch is closed. (enable)</description>
69589 <description>Analog switch is open. (disable)</description>
69596 <description>Controls PMU DC BUS Voltage Output, pin N. P1_2</description>
69603 <description>Analog switch is closed. (enable)</description>
69608 <description>Analog switch is open. (disable)</description>
69615 <description>Controls PMU AC BUS Voltage Output, pin P. P1_17</description>
69622 <description>Analog switch is closed. (enable)</description>
69627 <description>Analog switch is open. (disable)</description>
69634 <description>Controls PMU AC BUS Voltage Output, pin N. P1_23</description>
69641 <description>Analog switch is closed. (enable)</description>
69646 <description>Analog switch is open. (disable)</description>
69653 … <description>Controls Oscillators Macro DC BUS Voltage Output, pin P. P0_15</description>
69660 <description>Analog switch is closed. (enable)</description>
69665 <description>Analog switch is open. (disable)</description>
69672 … <description>Controls Oscillators Macro DC BUS Voltage Output, pin N. P0_31</description>
69679 <description>Analog switch is closed. (enable)</description>
69684 <description>Analog switch is open. (disable)</description>
69691 … <description>Controls Oscillators Macro AC BUS Voltage Output, pin P. P1_0</description>
69698 <description>Analog switch is closed. (enable)</description>
69703 <description>Analog switch is open. (disable)</description>
69710 … <description>Controls Oscillators Macro AC BUS Voltage Output, pin N. P1_9</description>
69717 <description>Analog switch is closed. (enable)</description>
69722 <description>Analog switch is open. (disable)</description>
69729 <description>Controls Aux Bias DC BUS Voltage Output, pin P. P0_11</description>
69736 <description>Analog switch is closed. (enable)</description>
69741 <description>Analog switch is open. (disable)</description>
69748 <description>Controls Aux Bias DC BUS Voltage Output, pin N. P0_12</description>
69755 <description>Analog switch is closed. (enable)</description>
69760 <description>Analog switch is open. (disable)</description>
69767 <description>Controls Aux Bias AC BUS Voltage Output, pin P. P0_9</description>
69774 <description>Analog switch is closed. (enable)</description>
69779 <description>Analog switch is open. (disable)</description>
69786 <description>Controls Aux Bias AC BUS Voltage Output, pin N. P0_18</description>
69793 <description>Analog switch is closed. (enable)</description>
69798 <description>Analog switch is open. (disable)</description>
69807 …<description>FlexSPI Bootrom scratch register 0 [Reset by: PoR, Brown Out Detectors Reset]</descri…
69816 <description>FlexSPI Bootrom scratch data storage.</description>
69825 …<description>FlexSPI Bootrom scratch register 1 [Reset by: PoR, Brown Out Detectors Reset]</descri…
69834 <description>FlexSPI Bootrom scratch data storage,</description>
69845 <description>system controller</description>
69856 <description>Write Lock Out</description>
69865 <description>Lock Out</description>
69872 <description>Normal Mode: Allow writes to all registers.</description>
69877 … <description>Protected Mode: Do not allow writes to all registers except LOCKOUT.</description>
69886 <description>Shared Signal Select for Flexcomm 0</description>
69895 <description>SCK Input Select</description>
69902 <description>Selects the dedicated FCn_SCK signal</description>
69907 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
69912 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
69919 <description>WS Input Select</description>
69926 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
69931 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
69936 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
69943 <description>DATA Input Select</description>
69950 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
69955 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
69960 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
69967 <description>DATA Output Select</description>
69974 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
69979 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
69984 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
69993 <description>Shared Signal Select for Flexcomm 1</description>
70002 <description>SCK Input Select</description>
70009 <description>Selects the dedicated FCn_SCK signal</description>
70014 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70019 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70026 <description>WS Input Select</description>
70033 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70038 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70043 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70050 <description>DATA Input Select</description>
70057 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70062 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70067 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70074 <description>DATA Output Select</description>
70081 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70086 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70091 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70100 <description>Shared Signal Select for Flexcomm 2</description>
70109 <description>SCK Input Select</description>
70116 <description>Selects the dedicated FCn_SCK signal</description>
70121 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70126 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70133 <description>WS Input Select</description>
70140 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70145 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70150 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70157 <description>DATA Input Select</description>
70164 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70169 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70174 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70181 <description>DATA Output Select</description>
70188 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70193 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70198 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70207 <description>Shared Signal Select for Flexcomm 4</description>
70216 <description>SCK Input Select</description>
70223 <description>Selects the dedicated FCn_SCK signal</description>
70228 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70233 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70240 <description>WS Input Select</description>
70247 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70252 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70257 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70264 <description>DATA Input Select</description>
70271 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70276 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70281 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70288 <description>DATA Output Select</description>
70295 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70300 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70305 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70314 <description>Shared Signal Select for Flexcomm 5</description>
70323 <description>SCK Input Select</description>
70330 <description>Selects the dedicated FCn_SCK signal</description>
70335 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70340 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70347 <description>WS Input Select</description>
70354 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70359 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70364 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70371 <description>DATA Input Select</description>
70378 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70383 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70388 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70395 <description>DATA Output Select</description>
70402 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70407 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70412 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70421 <description>Shared Signal Select for Flexcomm 6</description>
70430 <description>SCK Input Select</description>
70437 <description>Selects the dedicated FCn_SCK signal</description>
70442 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70447 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70454 <description>WS Input Select</description>
70461 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70466 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70471 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70478 <description>DATA Input Select</description>
70485 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70490 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70495 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70502 <description>DATA Output Select</description>
70509 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70514 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70519 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70528 <description>Shared Signal Select for Flexcomm 7</description>
70537 <description>SCK Input Select</description>
70544 <description>Selects the dedicated FCn_SCK signal</description>
70549 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70554 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70561 <description>WS Input Select</description>
70568 <description>Selects the dedicated FCn_TXD_SCL_MISO_WS signal</description>
70573 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70578 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70585 <description>DATA Input Select</description>
70592 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA input</description>
70597 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70602 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70609 <description>DATA Output Select</description>
70616 <description>Selects the dedicated FCn_RXD_SDA_MOSI_DATA output</description>
70621 <description>Selects from shared signal set 0 (SHAREDSET0)</description>
70626 <description>Selects from shared signal set 1 (SHAREDSET1)</description>
70637 <description>Shared Signal Set n</description>
70646 <description>SCK Source Select</description>
70653 <description>Flexcomm 0</description>
70658 <description>Flexcomm 1</description>
70663 <description>Flexcomm 2</description>
70668 <description>Flexcomm 4</description>
70673 <description>Flexcomm 5</description>
70678 <description>Flexcomm 6</description>
70683 <description>Flexcomm 7</description>
70690 <description>WS Source Select</description>
70697 <description>Flexcomm 0</description>
70702 <description>Flexcomm 1</description>
70707 <description>Flexcomm 2</description>
70712 <description>Flexcomm 4</description>
70717 <description>Flexcomm 5</description>
70722 <description>Flexcomm 6</description>
70727 <description>Flexcomm 7</description>
70734 <description>DATA Input Source Select</description>
70741 <description>Flexcomm 0</description>
70746 <description>Flexcomm 1</description>
70751 <description>Flexcomm 2</description>
70756 <description>Flexcomm 4</description>
70761 <description>Flexcomm 5</description>
70766 <description>Flexcomm 6</description>
70771 <description>Flexcomm 7</description>
70778 <description>DOUT Enable for Flexcomm 0</description>
70785 <description>Does not contribute</description>
70790 <description>Contributes</description>
70797 <description>DOUT Enable for Flexcomm 1</description>
70804 <description>Does not contribute</description>
70809 <description>Contributes</description>
70816 <description>DOUT Enable for Flexcomm 2</description>
70823 <description>Does not contribute</description>
70828 <description>Contributes</description>
70835 <description>DOUT Enable for Flexcomm 3</description>
70842 <description>Does not contribute</description>
70847 <description>Contributes</description>
70854 <description>DOUT Enable for Flexcomm 4</description>
70861 <description>Does not contribute</description>
70866 <description>Contributes</description>
70873 <description>DOUT Enable for Flexcomm 5</description>
70880 <description>Does not contribute</description>
70885 <description>Contributes</description>
70892 <description>DOUT Enable for Flexcomm 6</description>
70899 <description>Does not contribute</description>
70904 <description>Contributes</description>
70911 <description>DOUT Enable for Flexcomm 7</description>
70918 <description>Does not contribute</description>
70923 <description>Contributes</description>
70932 <description>Status register for USB HS</description>
70941 <description>USB_HS: Low voltage detection on 3.3V supply.</description>
70948 <description>3v3 supply is good.</description>
70953 <description>3v3 supply is too low.</description>
70962 <description>Gray Code LSB Input</description>
70971 <description>Gray code (least-significant)</description>
70980 <description>Gray Code MSB Input</description>
70989 <description>Gray code (most-significant)</description>
70998 <description>Binary Code LSB Input</description>
71007 <description>Binary converted code (least-significant)</description>
71016 <description>Binary Code MSB Input</description>
71025 <description>Binary converted code (most-significant)</description>
71036 <description>SPI FILTER</description>
71051 <description>Control Register</description>
71060 <description>Active Chip Select for P1 filter</description>
71067 …<description>Sets CS1 as the read location for the firmware image and sets CS0 as the write locati…
71074 <description>Address Byte Select Mode for P1</description>
71081 <description>Sets the filter to 4-byte address mode</description>
71088 <description>Address Byte Select Mode for P1</description>
71095 …<description>Normal Operation. The Address byte mode is determined by the Op Code Command</descrip…
71102 <description>Clear dirty state for P1</description>
71109 <description>Filter Enable bit for P1 filter</description>
71116 …description>Filter Enabled. CS# inputs to the filter are enabled and the filter state machine cont…
71123 <description>Flash Mode Select for P1</description>
71130 …description>Single Flash Mode. Supports a single physical flash device as described in Section 3.2…
71137 <description>Active Chip Select for P0 filter</description>
71144 …<description>Sets CS1 as the read location for the firmware image and sets CS0 as the write locati…
71151 <description>Address Byte Select for P0 filter</description>
71158 <description>Sets the filter to 4-byte address mode</description>
71165 <description>Address Byte Select Mode for P0 filter</description>
71172 …description>Sets the Byte Mode to 3-byte and gives control of the function to the P0_BYTE_SEL in t…
71179 <description>Clear dirty state for P0</description>
71186 <description>Filter Enable bit for P0</description>
71193 …description>Filter Enabled. CS# inputs to the filter are enabled and the filter state machine cont…
71200 <description>Flash Mode Select for P0</description>
71207 …<description>Dual Flash Mode. Supports two separate physical flash devices as described in Section…
71212 …description>Single Flash Mode. Supports a single physical flash device as described in Section 3.2…
71221 <description>Interrupt Register</description>
71230 <description>Indicates dirty state of the inactive Flash for P0 filter</description>
71237 …<description>Indicates that a write has occurred to the FW Code region of the inactive Flash and t…
71244 <description>Indicates dirty state of the inactive Flash for P1 filter</description>
71251 <description>Indicates normal operation</description>
71258 <description>Indicates Port 0 Blocked Op Code</description>
71265 <description>Indicates normal operation</description>
71272 <description>Indicates Port 1 Blocked Op Code</description>
71279 <description>Indicates normal operation</description>
71286 <description>Indicates Port 0 Bytemode interrupt</description>
71293 <description>Indicates normal operation</description>
71300 <description>Indicates Port 1 Bytemode interrupt</description>
71307 <description>Indicates normal operation</description>
71314 <description>Indicates Port 0 F8 Op Code Command Interrupt</description>
71321 <description>Indicates normal operation</description>
71328 <description>Indicates Port 1 F8 Op Code Command Interrupt</description>
71335 <description>Indicates normal operation</description>
71344 <description>Interrupt Mask Register</description>
71353 <description>Mask bit for P0_DIRTY_INT</description>
71360 <description>Indicates P0_DIRTY_INT interrupt is disabled.</description>
71367 <description>Mask bit for P1_DIRTY_INT</description>
71374 … <description>Indicates normal operation. P1_DIRTY_INT interrupt is enabled.</description>
71381 <description>Mask bit for P0_BLK_MASK</description>
71388 <description>Indicates P0_BLK_MASK is enabled.</description>
71395 <description>Mask bit for P1_BLK_MASK</description>
71402 <description>Indicates P1_BLK_MASK is enabled.</description>
71409 <description>Mask bit for P0_BYTEMODE_MASK</description>
71416 <description>Indicates P0_BYTEMODE_MASK is enabled.</description>
71423 <description>Mask bit for P1_BYTEMODE_MASK</description>
71430 <description>Indicates P1_BYTEMODE_MASK is enabled.</description>
71437 <description>Mask bit for P0_F8_MASK</description>
71444 <description>Indicates P0_F8_MASK is enabled.</description>
71451 <description>Mask bit for P1_F8_MASK</description>
71458 <description>Indicates P1_F8_MASK is enabled.</description>
71467 <description>Status Register</description>
71476 <description>Indicates the Dirty State of the P1 inactive Flash</description>
71483 …description>Indicates that a write to the inactive Flash has been detected and the state of the fl…
71490 <description>Indicates the P1 Address Byte Mode</description>
71497 <description>4-Byte Address Mode</description>
71504 <description>Indicates the Dirty State of the P0 inactive Flash</description>
71511 …description>Indicates that a write to the inactive Flash has been detected and the state of the fl…
71518 <description>Indicates the P0 Address Byte Mode</description>
71525 <description>4-Byte Address Mode</description>
71534 <description>Test Control Register</description>
71543 <description>Selects the active CS when PO_BYP_EN is set</description>
71550 <description>CS1</description>
71557 <description>Enables bypassing of the filter logic</description>
71564 <description>Filter Bypass Disabled</description>
71571 <description>Selects the active CS when P1_BYP_EN is set</description>
71578 <description>CS1</description>
71585 <description>Enables bypassing of the filter logic</description>
71592 <description>Filter Bypass Disabled</description>
71599 <description>Sets the Flash memory manufacturer</description>
71606 <description>Macronix</description>
71611 <description>Windbond</description>
71616 <description>Micron</description>
71623 <description>Sets the Flash memory manufacturer</description>
71630 <description>Macronix</description>
71635 <description>Windbond</description>
71640 <description>Micron</description>
71649 <description>Port 0 filter address region 1</description>
71658 <description>Address Lower LSBs</description>
71665 <description>Address Lower MSBs</description>
71672 <description>Address Upper LSBs</description>
71679 <description>Address Upper MSBs</description>
71688 <description>Port 0 filter address region 2</description>
71697 <description>Address Lower LSBs</description>
71704 <description>Address Lower MSBs</description>
71711 <description>Address Upper LSBs</description>
71718 <description>Address Upper MSBs</description>
71727 <description>Port 0 filter address region 3</description>
71736 <description>Address Lower LSBs</description>
71743 <description>Address Lower MSBs</description>
71750 <description>Address Upper LSBs</description>
71757 <description>Address Upper MSBs</description>
71766 <description>Port 1 filter address region 1</description>
71775 <description>Address Lower LSBs</description>
71782 <description>Address Lower MSBs</description>
71789 <description>Address Upper LSBs</description>
71796 <description>Address Upper MSBs</description>
71805 <description>Port 1 filter address region 2</description>
71814 <description>Address Lower LSBs</description>
71821 <description>Address Lower MSBs</description>
71828 <description>Address Upper LSBs</description>
71835 <description>Address Upper MSBs</description>
71844 <description>Port 1 filter address region 3</description>
71853 <description>Address Lower LSBs</description>
71860 <description>Address Lower MSBs</description>
71867 <description>Address Upper LSBs</description>
71874 <description>Address Upper MSBs</description>
71883 <description>Version</description>
71892 <description>Minor revision</description>
71899 <description>Major Revision</description>
71908 <description>Programmable OP-Code0</description>
71917 <description>Programmable Filter state 0</description>
71924 …<description>This bit determines whether the Programmable Op Code filter is executed after receipt…
71931 …<description>Filter after 7th bit for all Commands Op Codes that need to be filtered.</description>
71938 <description>Programmable OP Code 0</description>
71947 <description>Programmable OP-Code1</description>
71956 <description>Programmable Filter state 1</description>
71963 …<description>This bit determines whether the Programmable Op Code filter is executed after receipt…
71970 …<description>Filter after 7th bit for all Commands Op Codes that need to be filtered.</description>
71977 <description>Programmable OP Code 1</description>
71986 <description>Programmable OP-Code2</description>
71995 <description>Programmable Filter state 2</description>
72002 …<description>This bit determines whether the Programmable Op Code filter is executed after receipt…
72009 …<description>Filter after 7th bit for all Commands Op Codes that need to be filtered.</description>
72016 <description>Programmable OP Code 0</description>
72025 <description>Programmable OP-Code3</description>
72034 <description>Programmable Filter state 3</description>
72041 …<description>This bit determines whether the Programmable Op Code filter is executed after receipt…
72048 …<description>Filter after 7th bit for all Commands Op Codes that need to be filtered.</description>
72055 <description>Programmable OP Code 3</description>
72064 <description>Programmable OP-Code4</description>
72073 <description>Programmable Filter state 4</description>
72080 …<description>This bit determines whether the Programmable Op Code filter is executed after receipt…
72087 …<description>Filter after 7th bit for all Commands Op Codes that need to be filtered.</description>
72094 <description>Programmable OP Code 4</description>
72103 <description>P0 Blocked Op Code</description>
72112 <description>Port 0 Blocked Op Code</description>
72121 <description>P1 Blocked Op Code</description>
72130 <description>Port 1 Blocked Op Code</description>
72139 <description>Port 0 Max Address Mask</description>
72148 <description>Port 0 Max Address Mask LSB</description>
72155 <description>Port 0 Max Address Mask MSB</description>
72164 <description>Port 1 Max Address Mask</description>
72173 <description>Port 1 Max Address Mask LSB</description>
72180 <description>Port 1 Max Address Mask MSB</description>
72191 <description>RTC</description>
72206 <description>RTC Year and Month Counters Register</description>
72215 <description>MON_CNT</description>
72222 <description>Illegal Value</description>
72227 <description>January</description>
72232 <description>February</description>
72237 <description>March</description>
72242 <description>April</description>
72247 <description>May</description>
72252 <description>June</description>
72257 <description>July</description>
72262 <description>August</description>
72267 <description>September</description>
72272 <description>October</description>
72277 <description>November</description>
72282 <description>December</description>
72287 <description>Illegal Value</description>
72292 <description>Illegal Value</description>
72297 <description>Illegal Value</description>
72304 <description>Year Offset Count Value</description>
72313 <description>RTC Days and Day-of-Week Counters Register</description>
72322 <description>Days Counter Value.</description>
72329 <description>Day of Week Counter Value.</description>
72336 <description>Sunday</description>
72341 <description>Monday</description>
72346 <description>Tuesday</description>
72351 <description>Wednesday</description>
72356 <description>Thursday</description>
72361 <description>Friday</description>
72366 <description>Saturday</description>
72375 <description>RTC Hours and Minutes Counters Register</description>
72384 <description>Minutes Counter Value.</description>
72391 <description>Hours Counter Value.</description>
72400 <description>RTC Seconds Counters Register</description>
72409 <description>Seconds Counter Value.</description>
72418 <description>RTC Year and Months Alarm Register</description>
72427 <description>Months Value for Alarm.</description>
72434 <description>Year Value for Alarm.</description>
72443 <description>RTC Days Alarm Register</description>
72452 <description>Days Value for Alarm.</description>
72461 <description>RTC Hours and Minutes Alarm Register</description>
72470 <description>Minutes Value for Alarm.</description>
72477 <description>Hours Value for Alarm.</description>
72486 <description>RTC Seconds Alarm Register</description>
72495 <description>ALM_SEC</description>
72502 <description>Decrement Seconds Counter by 1.</description>
72509 <description>Increment Seconds Counter by 1.</description>
72518 <description>RTC Control Register</description>
72527 <description>Fine compensation enable bit</description>
72534 <description>Fine compensation is disabled</description>
72539 <description>Fine compensation is enabled.</description>
72546 <description>Compensation enable bit</description>
72553 <description>Coarse Compensation is disabled.</description>
72558 <description>Coarse Compensation is enabled.</description>
72565 <description>Alarm Match bits.</description>
72572 <description>Only Seconds, Minutes, and Hours matched.</description>
72577 <description>Only Seconds, Minutes, Hours, and Days matched.</description>
72582 <description>Only Seconds, Minutes, Hours, Days, and Months matched.</description>
72587 … <description>Only Seconds, Minutes, Hours, Days, Months, and Year (offset) matched.</description>
72594 <description>Sampling timer clocks mask</description>
72601 <description>Sampling clocks are not gated when in standby mode</description>
72606 <description>Sampling clocks are gated in standby mode</description>
72613 <description>Daylight Saving Enable.</description>
72620 …<description>Disabled. Daylight saving changes are not applied. Daylight saving registers can be m…
72625 <description>Enabled. Daylight saving changes are applied.</description>
72632 <description>Software Reset bit.</description>
72639 <description>Software Reset cleared.</description>
72644 <description>Software Reset asserted.</description>
72651 <description>RTC Clock Output Selection.</description>
72658 <description>No Output Clock</description>
72663 <description>Fine 1 Hz Clock with both precise edges</description>
72668 <description>32.768 kHz Clock</description>
72673 <description>Coarse 1 Hz Clock with both precise edges</description>
72682 <description>RTC Status Register</description>
72691 <description>Invalidate CPU read/write access bit.</description>
72698 … <description>Time /Date Counters can be read/written. Time /Date is valid.</description>
72703 …<description>Time /Date Counter values are changing or Time /Date is invalid and cannot be read or…
72710 <description>Write Protect Enable status bit.</description>
72717 <description>Registers are unlocked and can be accessed.</description>
72722 <description>Registers are locked and in read-only mode.</description>
72729 <description>CPU Low Voltage Warning status bit.</description>
72736 <description>CPU in Normal Operating Voltage.</description>
72741 …<description>CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode.</desc…
72748 <description>Reset Source bit.</description>
72755 …<description>Part was reset due to Standby Mode Exit (that is when VDD is powered up and VBAT was …
72760 …<description>Part was reset due to Power-On Reset (that is Power On Reset when both VBAT and VDD a…
72767 <description>Compensation Interval bit.</description>
72774 <description>Write Enable bits.</description>
72781 <description>Disable Write Protection - Registers are unlocked.</description>
72786 <description>Disable Write Protection - Registers are unlocked.</description>
72791 <description>Enable Write Protection - Registers are locked.</description>
72796 <description>Disable Write Protection - Registers are unlocked.</description>
72803 <description>Bus Error bit.</description>
72811 <description>Read and Write accesses are normal.</description>
72816 … <description>Read or Write accesses occurred when INVAL_BIT was asserted.</description>
72823 <description>Compensation Done bit.</description>
72831 <description>Compensation busy or not enabled.</description>
72836 <description>Compensation completed.</description>
72845 <description>RTC Interrupt Status Register</description>
72854 <description>Tamper Interrupt Status bit.</description>
72861 <description>Interrupt is de-asserted.</description>
72866 <description>Interrupt is asserted (Default on reset) .</description>
72873 <description>Alarm Interrupt Status bit.</description>
72881 <description>Interrupt is de-asserted.</description>
72886 <description>Interrupt is asserted.</description>
72893 <description>Days Interrupt Status bit.</description>
72901 <description>Interrupt is de-asserted.</description>
72906 <description>Interrupt is asserted.</description>
72913 <description>Hours Interrupt Status bit.</description>
72921 <description>Interrupt is de-asserted.</description>
72926 <description>Interrupt is asserted.</description>
72933 <description>Minutes Interrupt Status bit.</description>
72941 <description>Interrupt is de-asserted.</description>
72946 <description>Interrupt is asserted.</description>
72953 <description>1 Hz Interval Interrupt Status bit.</description>
72961 <description>Interrupt is de-asserted.</description>
72966 <description>Interrupt is asserted.</description>
72973 <description>2 Hz Interval Interrupt Status bit.</description>
72981 <description>Interrupt is de-asserted.</description>
72986 <description>Interrupt is asserted.</description>
72993 <description>4 Hz Interval Interrupt Status bit.</description>
73001 <description>Interrupt is de-asserted.</description>
73006 <description>Interrupt is asserted.</description>
73013 <description>8 Hz Interval Interrupt Status bit.</description>
73021 <description>Interrupt is de-asserted.</description>
73026 <description>Interrupt is asserted.</description>
73033 <description>16 Hz Interval Interrupt Status bit.</description>
73041 <description>Interrupt is de-asserted.</description>
73046 <description>Interrupt is asserted.</description>
73053 <description>32 Hz Interval Interrupt Status bit.</description>
73061 <description>Interrupt is de-asserted.</description>
73066 <description>Interrupt is asserted.</description>
73073 <description>64 Hz Interval Interrupt Status bit.</description>
73081 <description>Interrupt is de-asserted.</description>
73086 <description>Interrupt is asserted.</description>
73093 <description>128 Hz Interval Interrupt Status bit.</description>
73101 <description>Interrupt is de-asserted.</description>
73106 <description>Interrupt is asserted.</description>
73113 <description>256 Hz Interval Interrupt Status bit.</description>
73121 <description>Interrupt is de-asserted.</description>
73126 <description>Interrupt is asserted.</description>
73133 <description>512 Hz Interval Interrupt Status bit.</description>
73141 <description>Interrupt is de-asserted.</description>
73146 <description>Interrupt is asserted.</description>
73155 <description>RTC Interrupt Enable Register</description>
73164 <description>Tamper Interrupt Enable bit.</description>
73171 <description>Interrupt is disabled.</description>
73176 <description>Interrupt is enabled (Default on reset).</description>
73183 <description>Alarm Interrupt Enable bit.</description>
73190 <description>Interrupt is disabled.</description>
73195 <description>Interrupt is enabled.</description>
73202 <description>Days Interrupt Enable bit.</description>
73209 <description>Interrupt is disabled.</description>
73214 <description>Interrupt is enabled.</description>
73221 <description>Hours Interrupt Enable bit.</description>
73228 <description>Interrupt is disabled.</description>
73233 <description>Interrupt is enabled.</description>
73240 <description>Minutes Interrupt Enable bit.</description>
73247 <description>Interrupt is disabled.</description>
73252 <description>Interrupt is enabled.</description>
73259 <description>1 Hz Interval Interrupt Enable bit.</description>
73266 <description>Interrupt is disabled.</description>
73271 <description>Interrupt is enabled.</description>
73278 <description>2 Hz Interval Interrupt Enable bit.</description>
73285 <description>Interrupt is disabled.</description>
73290 <description>Interrupt is enabled.</description>
73297 <description>4 Hz Interval Interrupt Enable bit.</description>
73304 <description>Interrupt is disabled.</description>
73309 <description>Interrupt is enabled.</description>
73316 <description>8 Hz Interval Interrupt Enable bit.</description>
73323 <description>Interrupt is disabled.</description>
73328 <description>Interrupt is enabled.</description>
73335 <description>16 Hz Interval Interrupt Enable bit.</description>
73342 <description>Interrupt is disabled.</description>
73347 <description>Interrupt is enabled.</description>
73354 <description>32 Hz Interval Interrupt Enable bit.</description>
73361 <description>Interrupt is disabled.</description>
73366 <description>Interrupt is enabled.</description>
73373 <description>64 Hz Interval Interrupt Enable bit.</description>
73380 <description>Interrupt is disabled.</description>
73385 <description>Interrupt is enabled.</description>
73392 <description>128 Hz Interval Interrupt Enable bit.</description>
73399 <description>Interrupt is disabled.</description>
73404 <description>Interrupt is enabled.</description>
73411 <description>256 Hz Interval Interrupt Enable bit.</description>
73418 <description>Interrupt is disabled.</description>
73423 <description>Interrupt is enabled.</description>
73430 <description>512 Hz Interval Interrupt Enable bit.</description>
73437 <description>Interrupt is disabled.</description>
73442 <description>Interrupt is enabled.</description>
73451 <description>RTC General Purpose Data Register</description>
73460 <description>32 kHz RTC OSC Control</description>
73467 <description>Enables the oscillator</description>
73472 <description>Disables the oscillator</description>
73479 <description>Switched capacitor 2 pF enable</description>
73486 <description>Disables capacitor</description>
73491 <description>Enables capacitor</description>
73498 <description>Switched capacitor 4 pF enable</description>
73505 <description>Disables capacitor</description>
73510 <description>Enables capacitor</description>
73517 <description>Switched capacitor 8 pF enable</description>
73524 <description>Disables capacitor</description>
73529 <description>Enables capacitor</description>
73536 <description>Switched capacitor 16 pF enable</description>
73543 <description>Disables capacitor</description>
73548 <description>Enables capacitor</description>
73555 <description>Reserved</description>
73562 <description>Reserved</description>
73569 <description>Boot mode override bit</description>
73576 <description>Boot in RUN</description>
73581 <description>Boot in VLPR</description>
73588 <description>Reserved</description>
73595 <description>Reserved</description>
73602 <description>Reserved</description>
73609 <description>Reserved</description>
73616 <description>Reserved</description>
73623 <description>Reserved</description>
73630 <description>Reserved</description>
73637 <description>Reserved</description>
73646 <description>RTC Daylight Saving Hour Register</description>
73655 <description>Daylight Saving Time (DST) Hours End Value.</description>
73662 <description>Daylight Saving Time (DST) Hours Start Value.</description>
73671 <description>RTC Daylight Saving Month Register</description>
73680 <description>Daylight Saving Time (DST) Month End Value.</description>
73687 <description>Daylight Saving Time (DST) Month Start Value.</description>
73696 <description>RTC Daylight Saving Day Register</description>
73705 <description>Daylight Saving Time (DST) Day End Value.</description>
73712 <description>Daylight Saving Time (DST) Day Start Value.</description>
73721 <description>RTC Compensation Register</description>
73730 <description>Compensation Value</description>
73739 <description>RTC Tamper Status and Control Register</description>
73748 <description>Tamper Control.</description>
73755 …<description>Tamper Status reporting disabled. However, corresponding tamper status bit will still…
73760 …<description>Tamper Status reporting enabled. Corresponding tamper status bit will cause tamper in…
73767 <description>Tamper Status Bit</description>
73775 <description>No Tamper Detected.</description>
73780 <description>Tamper Event Detected.</description>
73789 <description>RTC Tamper 01 Filter Configuration Register</description>
73798 <description>Tamper Detect Bit 1 Filter Duration</description>
73805 <description>Filtering operation disabled.</description>
73810 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73815 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73820 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73825 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73830 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73835 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73840 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73845 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73850 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73857 <description>Tamper Filter 1 Clock Select</description>
73864 <description>32 kHz clock</description>
73869 <description>512 Hz clock</description>
73874 <description>128 Hz clock</description>
73879 <description>64 Hz clock</description>
73884 <description>16 Hz clock</description>
73889 <description>8 Hz clock</description>
73894 <description>4 Hz clock</description>
73899 <description>2 Hz clock</description>
73906 <description>Tamper Detect Input Bit 1 Polarity Control</description>
73913 <description>Tamper detect input bit 1 is active high.</description>
73918 <description>Tamper detect input bit 1 is active low.</description>
73925 <description>Tamper Detect Bit 0 Filter Duration</description>
73932 <description>Filtering operation disabled.</description>
73937 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73942 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73947 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73952 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73957 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73962 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73967 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73972 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73977 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
73984 <description>Tamper Filter 0 Clock Select</description>
73991 <description>32 kHz clock</description>
73996 <description>512 Hz clock</description>
74001 <description>128 Hz clock</description>
74006 <description>64 Hz clock</description>
74011 <description>16 Hz clock</description>
74016 <description>8 Hz clock</description>
74021 <description>4 Hz clock</description>
74026 <description>2 Hz clock</description>
74033 <description>Tamper Detect Input Bit 0 Polarity Control</description>
74040 <description>Tamper detect input bit 0 is active high.</description>
74045 <description>Tamper detect input bit 0 is active low.</description>
74054 <description>RTC Tamper 23 Filter Configuration Register</description>
74063 <description>Tamper Detect Bit 3 Filter Duration</description>
74070 <description>Filtering operation disabled.</description>
74075 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74080 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74085 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74090 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74095 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74100 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74105 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74110 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74115 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74122 <description>Tamper Filter 3 Clock Select</description>
74129 <description>32 kHz clock</description>
74134 <description>512 Hz clock</description>
74139 <description>128 Hz clock</description>
74144 <description>64 Hz clock</description>
74149 <description>16 Hz clock</description>
74154 <description>8 Hz clock</description>
74159 <description>4 Hz clock</description>
74164 <description>2 Hz clock</description>
74171 <description>Tamper Detect Input Bit 3 Polarity Control</description>
74178 <description>Tamper detect input bit 3 is active high.</description>
74183 <description>Tamper detect input bit 3 is active low.</description>
74190 <description>Tamper Detect Bit 2 Filter Duration</description>
74197 <description>Filtering operation disabled.</description>
74202 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74207 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74212 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74217 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74222 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74227 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74232 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74237 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74242 …<description>Number of tamper filter clock cycles to be counted when tamper is asserted.</descript…
74249 <description>Tamper Filter 2 Clock Select</description>
74256 <description>32 kHz clock</description>
74261 <description>512 Hz clock</description>
74266 <description>128 Hz clock</description>
74271 <description>64 Hz clock</description>
74276 <description>16 Hz clock</description>
74281 <description>8 Hz clock</description>
74286 <description>4 Hz clock</description>
74291 <description>2 Hz clock</description>
74298 <description>Tamper Detect Input Bit 2 Polarity Control</description>
74305 <description>Tamper detect input bit 2 is active high.</description>
74310 <description>Tamper detect input bit 2 is active low.</description>
74319 <description>RTC Control 2 Register</description>
74328 <description>Tamper Configuration Over</description>
74335 <description>Tamper filter processing disabled.</description>
74340 <description>Tamper filter processing enabled.</description>
74351 <description>CACHE64</description>
74362 <description>Cache control register</description>
74371 <description>Cache enable</description>
74378 <description>Cache disabled</description>
74383 <description>Cache enabled</description>
74390 <description>Enable Write Buffer</description>
74397 <description>Write buffer disabled</description>
74402 <description>Write buffer enabled</description>
74409 <description>Invalidate Way 0</description>
74416 <description>No operation</description>
74421 <description>When setting the GO bit, invalidate all lines in way 0.</description>
74428 <description>Push Way 0</description>
74435 <description>No operation</description>
74440 … <description>When setting the GO bit, push all modified lines in way 0</description>
74447 <description>Invalidate Way 1</description>
74454 <description>No operation</description>
74459 <description>When setting the GO bit, invalidate all lines in way 1</description>
74466 <description>Push Way 1</description>
74473 <description>No operation</description>
74478 … <description>When setting the GO bit, push all modified lines in way 1</description>
74485 <description>Initiate Cache Command</description>
74492 <description>Write: no effect. Read: no cache command active.</description>
74497 …<description>Write: initiate command indicated by bits 27-24. Read: cache command active.</descrip…
74506 <description>Cache line control register</description>
74515 <description>Initiate Cache Line Command</description>
74522 <description>Write: no effect. Read: no line command active.</description>
74527 …<description>Write: initiate line command indicated by bits 27-24. Read: line command active.</des…
74534 <description>Cache address</description>
74541 <description>Way select</description>
74548 <description>Way 0</description>
74553 <description>Way 1</description>
74560 <description>Tag/Data Select</description>
74567 <description>Data</description>
74572 <description>Tag</description>
74579 <description>Line Command Initial Valid Bit</description>
74586 <description>Line Command Initial Modified Bit</description>
74593 <description>Line Command Way</description>
74600 <description>Line Command</description>
74607 <description>Search and read or write</description>
74612 <description>Invalidate</description>
74617 <description>Push</description>
74622 <description>Clear</description>
74629 <description>Line Address Select</description>
74636 <description>Cache address</description>
74641 <description>Physical address</description>
74648 <description>Line access type</description>
74655 <description>Read</description>
74660 <description>Write</description>
74669 <description>Cache search address register</description>
74678 <description>Initiate Cache Line Command</description>
74685 <description>Write: no effect. Read: no line command active.</description>
74690 …<description>Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active…
74697 <description>Physical Address</description>
74706 <description>Cache read/write value register</description>
74715 <description>Cache read/write Data</description>
74726 <description>CACHE64_POLSEL</description>
74738 <description>Region 0 Top Boundary</description>
74747 <description>Upper limit of Region 0</description>
74756 <description>Region 1 Top Boundary</description>
74765 <description>Upper limit of Region 1</description>
74774 <description>Policy Select</description>
74783 <description>Policy Select for Region 0</description>
74790 <description>Non-cache</description>
74795 <description>Write-thru</description>
74800 <description>Write-back</description>
74805 <description>Invalid</description>
74812 <description>Policy Select for Region 0</description>
74819 <description>Non-cache</description>
74824 <description>Write-thru</description>
74829 <description>Write-back</description>
74834 <description>Invalid</description>
74841 <description>Policy Select for Region 0</description>
74848 <description>Non-cache</description>
74853 <description>Write-thru</description>
74858 <description>Write-back</description>
74863 <description>Invalid</description>
74874 <description>OSTIMER</description>
74891 <description>EVTIMER Low Register</description>
74900 <description>EVTimer Count value</description>
74909 <description>EVTIMER High Register</description>
74918 <description>EVTimer Count value</description>
74927 <description>Local Capture Low Register for CPU</description>
74936 <description>EVTimer Capture value</description>
74945 <description>Local Capture High Register for CPU</description>
74954 <description>EVTimer Capture value</description>
74963 <description>Local Match Low Register for CPU</description>
74972 <description>EVTimer Match value</description>
74981 <description>Local Match High Register for CPU</description>
74990 <description>EVTimer Match value</description>
74999 <description>OS Event Timer Control Register for CPU</description>
75008 <description>Interrupt Flag</description>
75015 <description>Interrupt/Wake-up Request</description>
75022 … <description>Interrupt/wake-up requests due to the OSTIMER_INTR flag are blocked.</description>
75027 …<description>An interrupt/wake-up request to the domain processor will be asserted when the OSTIME…
75034 <description>EVTimer Match Write Ready</description>
75045 <description>OSTIMER</description>
75060 <description>no description available</description>
75071 <description>Status register</description>
75080 <description>High to indicate the CSS is executing a Crypto Sequence</description>
75087 <description>High to indicate the CSS has an active interrupt</description>
75094 <description>High to indicate the CSS has detected an internal error</description>
75101 <description>High to indicate the internal PRNG is ready</description>
75108 …description>Signature Verify Result Status; 0 == No Verify Run; 1 == Signature Verify Failed; 2 ==…
75115 <description>Current command privilege level</description>
75122 <description>Entropy quality of the current DRBG instance</description>
75129 <description>When set, it indicates the DTRNG is gathering entropy</description>
75136 … <description>IRQ for GDET has detected a negative glitch: active high irq</description>
75143 … <description>IRQ for GDET has detected a positive glitch: active high irq</description>
75150 <description>no description available</description>
75159 <description>CSS Control register</description>
75168 <description>CSS enable 0=CSS disabled, 1= CSS is enabled</description>
75175 <description>Write to 1 to start a CSS Operation</description>
75182 <description>Write to 1 to perform a CSS synchronous Reset</description>
75189 …description>CSS Command Field: List of Valid commands:; CIPHER; AUTH_CIPHER; ECSIGN; ECVFY; ECKXCH…
75196 <description>Defines Endianness - 1: BigEndian, 0: Little Endian</description>
75203 <description>reserved</description>
75212 <description>CSS command configuration register</description>
75221 <description>refer to reference manual for assignment of this field</description>
75230 <description>CSS configuration register</description>
75239 <description>reserved</description>
75246 <description>maximum aes start delay</description>
75253 <description>reserved</description>
75260 …<description>1=enable sha2 direct mode: direct access from external; bus to css internal sha</desc…
75269 <description>Keystore index 0 - for commands that access a single key</description>
75278 <description>keystore is indexed as an array of 128 bit key slots</description>
75285 <description>reserved</description>
75294 <description>Keystore index 1 - for commands that access 2 keys</description>
75303 <description>keystore is indexed as an array of 128 bit key slots</description>
75310 <description>reserved</description>
75319 <description>key properties request</description>
75328 …<description>for commands that create a key - requested properties; of the key that is being creat…
75337 <description>CSS DMA Source 0</description>
75346 …<description>defines the System address of the start of the; data to be transferred to the CSS via…
75355 <description>CSS DMA Source 0 length</description>
75364 …<description>Size in bytes of the data to be transferred from; the target defined in SFR CSS_DMA_S…
75373 <description>CSS DMA Source 1</description>
75382 …<description>defines the System address of the start of the; data to be transferred to the CSS via…
75391 <description>CSS DMA Source 2</description>
75400 …<description>defines the System address of the start of the; data to be transferred to the CSS via…
75409 <description>CSS DMA Source 2 length</description>
75418 …<description>Size in bytes of the data to be transferred from; the target defined in SFR CSS_DMA_S…
75427 <description>CSS DMA Result 0</description>
75436 …<description>defines the System Start address of where the result; of the CSS operation will be tr…
75445 <description>CSS DMA Result 0 Size</description>
75454 <description>Size in bytes of the data to be transferred to</description>
75463 <description>Interrupt enable</description>
75472 <description>Interrupt enable bit</description>
75479 <description>GDET Interrupt enable bit</description>
75486 <description>reserved</description>
75495 <description>Interrupt status clear</description>
75504 <description>Interrupt status clear</description>
75511 <description>GDET Interrupt status clear</description>
75518 <description>reserved</description>
75527 <description>Interrupt status set</description>
75536 <description>Set interrupt by software</description>
75543 <description>Set GDET interrupt by software</description>
75550 <description>Set GDET interrupt by software</description>
75557 <description>reserved</description>
75566 <description>Status register</description>
75575 <description>Bus access error: public or private bus</description>
75582 <description>Operational error:; CSS has been incorrectly operated</description>
75589 …<description>Algorithm error: An internal algorithm has; produced an unexpected result.</descripti…
75596 <description>Data integrity error:; Internal data integrity check failed</description>
75603 …<description>Hardware fault error: Attempt to change the value; of an internal register</descripti…
75610 <description>User Read of CSS_PRNG_DATOUT when CSS_STATUS.PRNG_RDY; is 0</description>
75617 <description>Indicates Error Level which has been triggerer. 0, 1 ,2</description>
75624 … <description>DTRNG unable to gather entropy with the current; configuration</description>
75631 <description>no description available</description>
75640 <description>Interrupt status clear</description>
75649 <description>1=clear CSS error status bits and exit CSS error state</description>
75656 <description>reserved</description>
75665 <description>CSS Version</description>
75674 <description>extended revision version: possible values 0-9</description>
75681 <description>minor release versino digit0: possible values 0-9</description>
75688 <description>minor release version digit1: possible values 0-9</description>
75695 <description>major release version: possible values 1-9</description>
75702 <description>reserved</description>
75711 <description>CSS Config</description>
75720 <description>cipher command is supported</description>
75727 <description>auth_cipher command is supported</description>
75734 <description>ecsign command is supported</description>
75741 <description>ecvfy command is supported</description>
75748 <description>dhkey_xch command is supported</description>
75755 <description>keygen command is supported</description>
75762 <description>keyin command is supported</description>
75769 <description>keyout command is supported</description>
75776 <description>kdelete command is supported</description>
75783 <description>keyprov command is supported</description>
75790 <description>ckdf command is supported</description>
75797 <description>hkdf command is supported</description>
75804 <description>tls_init command is supported</description>
75811 <description>hash command is supported</description>
75818 <description>hmac command is supported</description>
75825 <description>cmac command is supported</description>
75832 <description>drbg_req command is supported</description>
75839 <description>drbg_test command is supported</description>
75846 <description>dtrng_cfg_load command is supported</description>
75853 <description>dtrng_eval command is supported</description>
75860 <description>gdet_cfg_load command is supported</description>
75867 <description>gdet_trim command is supported</description>
75874 <description>reserved</description>
75883 <description>PRNG SW read out register</description>
75892 <description>32-bit wide pseudo-random number</description>
75901 <description>CSS GDET Event Counter</description>
75910 <description>Number of glitch event recorded</description>
75917 <description>The GDET event counter has been cleared</description>
75924 <description>reserved</description>
75933 <description>CSS GDET Event Counter Clear</description>
75942 <description>1=clear GDET event counter clear</description>
75949 <description>reserved</description>
75958 <description>CSS SHA2 Status Register</description>
75967 <description>no description available</description>
75974 <description>reserved</description>
75983 <description>SHA2 Control register</description>
75992 <description>Write to 1 to Init the SHA2 Module</description>
75999 <description>Write to 1 to Reset a SHA2 operation</description>
76006 <description>Write to 1 to Init the SHA2 Kernel</description>
76013 <description>Write to 1 to Load the SHA2 Kernel</description>
76020 …<description>SHA2 MODE:; 2'b11 - SHA512; 2'b10 - SHA384; 2'b01 - SHA224; 2'b00 - SHA256</descripti…
76027 <description>r-eserved</description>
76034 <description>Write to 1 to Reverse byte endianess</description>
76041 <description>r-eserved</description>
76050 <description>CSS SHA_DATA IN Register 0</description>
76059 <description>Output CSS_SHA_DATIN from CSS Application being executed</description>
76068 <description>CSS CSS_SHA_DATA Out Register 0</description>
76077 <description>Output SHA_DATA from CSS Application being executed</description>
76086 <description>CSS SHA_DATA Out Register 1</description>
76095 <description>Output SHA_DATA from CSS Application being executed</description>
76104 <description>CSS SHA_DATA Out Register 2</description>
76113 <description>Output SHA_DATA from CSS Application being executed</description>
76122 <description>CSS SHA_DATA Out Register 3</description>
76131 <description>Output SHA_DATA from CSS Application being executed</description>
76140 <description>CSS SHA_DATA Out Register 4</description>
76149 <description>Output SHA_DATA from CSS Application being executed</description>
76158 <description>CSS SHA_DATA Out Register 5</description>
76167 <description>Output SHA_DATA from CSS Application being executed</description>
76176 <description>CSS SHA_DATA Out Register 6</description>
76185 <description>Output SHA_DATA from CSS Application being executed</description>
76194 <description>CSS SHA_DATA Out Register 7</description>
76203 <description>Output SHA_DATA from CSS Application being executed</description>
76212 <description>CSS CSS_SHA_DATA Out Register 8</description>
76221 <description>Output SHA_DATA from CSS Application being executed</description>
76230 <description>CSS SHA_DATA Out Register 9</description>
76239 <description>Output SHA_DATA from CSS Application being executed</description>
76248 <description>CSS SHA_DATA Out Register 10</description>
76257 <description>Output SHA_DATA from CSS Application being executed</description>
76266 <description>CSS SHA_DATA Out Register 11</description>
76275 <description>Output SHA_DATA from CSS Application being executed</description>
76284 <description>CSS SHA_DATA Out Register 12</description>
76293 <description>Output SHA_DATA from CSS Application being executed</description>
76302 <description>CSS SHA_DATA Out Register 13</description>
76311 <description>Output SHA_DATA from CSS Application being executed</description>
76320 <description>CSS SHA_DATA Out Register 14</description>
76329 <description>Output SHA_DATA from CSS Application being executed</description>
76338 <description>CSS SHA_DATA Out Register 15</description>
76347 <description>Output SHA_DATA from CSS Application being executed</description>
76356 <description>Status register</description>
76365 <description>Key size: 0-128, 1-256</description>
76372 <description>Reserved 0</description>
76379 <description>Key is active</description>
76386 <description>First slot in a multislot key</description>
76393 <description>Hardware Feature General Purpose</description>
76400 <description>Hardware Feature Retention</description>
76407 <description>Hardware Feature Output</description>
76414 <description>Reserved 1</description>
76421 <description>CMAC key</description>
76428 <description>KSK key</description>
76435 <description>Real Time Fingerprint key</description>
76442 <description>Derivation key for CKDF command</description>
76449 <description>Derivation key for HKDF command</description>
76456 <description>Ecc signing key</description>
76463 <description>Ecc diffie hellman key</description>
76470 <description>Aes key</description>
76477 <description>Hmac key</description>
76484 <description>Key wrapping key</description>
76491 <description>Key unwrapping key</description>
76498 <description>TLS Pre Master Secret</description>
76505 <description>TLS Master Secret</description>
76512 <description>Supply KEYGEN source</description>
76519 <description>Hardware out key</description>
76526 <description>Ok to wrap key</description>
76533 <description>Device Unique Key</description>
76540 <description>Priviledge level</description>
76549 <description>Status register</description>
76558 <description>Key size: 0-128, 1-256</description>
76565 <description>Reserved 0</description>
76572 <description>Key is active</description>
76579 <description>First slot in a multislot key</description>
76586 <description>Hardware Feature General Purpose</description>
76593 <description>Hardware Feature Retention</description>
76600 <description>Hardware Feature Output</description>
76607 <description>Reserved 1</description>
76614 <description>CMAC key</description>
76621 <description>KSK key</description>
76628 <description>Real Time Fingerprint key</description>
76635 <description>Derivation key for CKDF command</description>
76642 <description>Derivation key for HKDF command</description>
76649 <description>Ecc signing key</description>
76656 <description>Ecc diffie hellman key</description>
76663 <description>Aes key</description>
76670 <description>Hmac key</description>
76677 <description>Key wrapping key</description>
76684 <description>Key unwrapping key</description>
76691 <description>TLS Pre Master Secret</description>
76698 <description>TLS Master Secret</description>
76705 <description>Supply KEYGEN source</description>
76712 <description>Hardware out key</description>
76719 <description>Ok to wrap key</description>
76726 <description>Device Unique Key</description>
76733 <description>Priviledge level</description>
76742 <description>Status register</description>
76751 <description>Key size: 0-128, 1-256</description>
76758 <description>Reserved 0</description>
76765 <description>Key is active</description>
76772 <description>First slot in a multislot key</description>
76779 <description>Hardware Feature General Purpose</description>
76786 <description>Hardware Feature Retention</description>
76793 <description>Hardware Feature Output</description>
76800 <description>Reserved 1</description>
76807 <description>CMAC key</description>
76814 <description>KSK key</description>
76821 <description>Real Time Fingerprint key</description>
76828 <description>Derivation key for CKDF command</description>
76835 <description>Derivation key for HKDF command</description>
76842 <description>Ecc signing key</description>
76849 <description>Ecc diffie hellman key</description>
76856 <description>Aes key</description>
76863 <description>Hmac key</description>
76870 <description>Key wrapping key</description>
76877 <description>Key unwrapping key</description>
76884 <description>TLS Pre Master Secret</description>
76891 <description>TLS Master Secret</description>
76898 <description>Supply KEYGEN source</description>
76905 <description>Hardware out key</description>
76912 <description>Ok to wrap key</description>
76919 <description>Device Unique Key</description>
76926 <description>Priviledge level</description>
76935 <description>Status register</description>
76944 <description>Key size: 0-128, 1-256</description>
76951 <description>Reserved 0</description>
76958 <description>Key is active</description>
76965 <description>First slot in a multislot key</description>
76972 <description>Hardware Feature General Purpose</description>
76979 <description>Hardware Feature Retention</description>
76986 <description>Hardware Feature Output</description>
76993 <description>Reserved 1</description>
77000 <description>CMAC key</description>
77007 <description>KSK key</description>
77014 <description>Real Time Fingerprint key</description>
77021 <description>Derivation key for CKDF command</description>
77028 <description>Derivation key for HKDF command</description>
77035 <description>Ecc signing key</description>
77042 <description>Ecc diffie hellman key</description>
77049 <description>Aes key</description>
77056 <description>Hmac key</description>
77063 <description>Key wrapping key</description>
77070 <description>Key unwrapping key</description>
77077 <description>TLS Pre Master Secret</description>
77084 <description>TLS Master Secret</description>
77091 <description>Supply KEYGEN source</description>
77098 <description>Hardware out key</description>
77105 <description>Ok to wrap key</description>
77112 <description>Device Unique Key</description>
77119 <description>Priviledge level</description>
77128 <description>Status register</description>
77137 <description>Key size: 0-128, 1-256</description>
77144 <description>Reserved 0</description>
77151 <description>Key is active</description>
77158 <description>First slot in a multislot key</description>
77165 <description>Hardware Feature General Purpose</description>
77172 <description>Hardware Feature Retention</description>
77179 <description>Hardware Feature Output</description>
77186 <description>Reserved 1</description>
77193 <description>CMAC key</description>
77200 <description>KSK key</description>
77207 <description>Real Time Fingerprint key</description>
77214 <description>Derivation key for CKDF command</description>
77221 <description>Derivation key for HKDF command</description>
77228 <description>Ecc signing key</description>
77235 <description>Ecc diffie hellman key</description>
77242 <description>Aes key</description>
77249 <description>Hmac key</description>
77256 <description>Key wrapping key</description>
77263 <description>Key unwrapping key</description>
77270 <description>TLS Pre Master Secret</description>
77277 <description>TLS Master Secret</description>
77284 <description>Supply KEYGEN source</description>
77291 <description>Hardware out key</description>
77298 <description>Ok to wrap key</description>
77305 <description>Device Unique Key</description>
77312 <description>Priviledge level</description>
77321 <description>Status register</description>
77330 <description>Key size: 0-128, 1-256</description>
77337 <description>Reserved 0</description>
77344 <description>Key is active</description>
77351 <description>First slot in a multislot key</description>
77358 <description>Hardware Feature General Purpose</description>
77365 <description>Hardware Feature Retention</description>
77372 <description>Hardware Feature Output</description>
77379 <description>Reserved 1</description>
77386 <description>CMAC key</description>
77393 <description>KSK key</description>
77400 <description>Real Time Fingerprint key</description>
77407 <description>Derivation key for CKDF command</description>
77414 <description>Derivation key for HKDF command</description>
77421 <description>Ecc signing key</description>
77428 <description>Ecc diffie hellman key</description>
77435 <description>Aes key</description>
77442 <description>Hmac key</description>
77449 <description>Key wrapping key</description>
77456 <description>Key unwrapping key</description>
77463 <description>TLS Pre Master Secret</description>
77470 <description>TLS Master Secret</description>
77477 <description>Supply KEYGEN source</description>
77484 <description>Hardware out key</description>
77491 <description>Ok to wrap key</description>
77498 <description>Device Unique Key</description>
77505 <description>Priviledge level</description>
77514 <description>Status register</description>
77523 <description>Key size: 0-128, 1-256</description>
77530 <description>Reserved 0</description>
77537 <description>Key is active</description>
77544 <description>First slot in a multislot key</description>
77551 <description>Hardware Feature General Purpose</description>
77558 <description>Hardware Feature Retention</description>
77565 <description>Hardware Feature Output</description>
77572 <description>Reserved 1</description>
77579 <description>CMAC key</description>
77586 <description>KSK key</description>
77593 <description>Real Time Fingerprint key</description>
77600 <description>Derivation key for CKDF command</description>
77607 <description>Derivation key for HKDF command</description>
77614 <description>Ecc signing key</description>
77621 <description>Ecc diffie hellman key</description>
77628 <description>Aes key</description>
77635 <description>Hmac key</description>
77642 <description>Key wrapping key</description>
77649 <description>Key unwrapping key</description>
77656 <description>TLS Pre Master Secret</description>
77663 <description>TLS Master Secret</description>
77670 <description>Supply KEYGEN source</description>
77677 <description>Hardware out key</description>
77684 <description>Ok to wrap key</description>
77691 <description>Device Unique Key</description>
77698 <description>Priviledge level</description>
77707 <description>Status register</description>
77716 <description>Key size: 0-128, 1-256</description>
77723 <description>Reserved 0</description>
77730 <description>Key is active</description>
77737 <description>First slot in a multislot key</description>
77744 <description>Hardware Feature General Purpose</description>
77751 <description>Hardware Feature Retention</description>
77758 <description>Hardware Feature Output</description>
77765 <description>Reserved 1</description>
77772 <description>CMAC key</description>
77779 <description>KSK key</description>
77786 <description>Real Time Fingerprint key</description>
77793 <description>Derivation key for CKDF command</description>
77800 <description>Derivation key for HKDF command</description>
77807 <description>Ecc signing key</description>
77814 <description>Ecc diffie hellman key</description>
77821 <description>Aes key</description>
77828 <description>Hmac key</description>
77835 <description>Key wrapping key</description>
77842 <description>Key unwrapping key</description>
77849 <description>TLS Pre Master Secret</description>
77856 <description>TLS Master Secret</description>
77863 <description>Supply KEYGEN source</description>
77870 <description>Hardware out key</description>
77877 <description>Ok to wrap key</description>
77884 <description>Device Unique Key</description>
77891 <description>Priviledge level</description>
77900 <description>Status register</description>
77909 <description>Key size: 0-128, 1-256</description>
77916 <description>Reserved 0</description>
77923 <description>Key is active</description>
77930 <description>First slot in a multislot key</description>
77937 <description>Hardware Feature General Purpose</description>
77944 <description>Hardware Feature Retention</description>
77951 <description>Hardware Feature Output</description>
77958 <description>Reserved 1</description>
77965 <description>CMAC key</description>
77972 <description>KSK key</description>
77979 <description>Real Time Fingerprint key</description>
77986 <description>Derivation key for CKDF command</description>
77993 <description>Derivation key for HKDF command</description>
78000 <description>Ecc signing key</description>
78007 <description>Ecc diffie hellman key</description>
78014 <description>Aes key</description>
78021 <description>Hmac key</description>
78028 <description>Key wrapping key</description>
78035 <description>Key unwrapping key</description>
78042 <description>TLS Pre Master Secret</description>
78049 <description>TLS Master Secret</description>
78056 <description>Supply KEYGEN source</description>
78063 <description>Hardware out key</description>
78070 <description>Ok to wrap key</description>
78077 <description>Device Unique Key</description>
78084 <description>Priviledge level</description>
78093 <description>Status register</description>
78102 <description>Key size: 0-128, 1-256</description>
78109 <description>Reserved 0</description>
78116 <description>Key is active</description>
78123 <description>First slot in a multislot key</description>
78130 <description>Hardware Feature General Purpose</description>
78137 <description>Hardware Feature Retention</description>
78144 <description>Hardware Feature Output</description>
78151 <description>Reserved 1</description>
78158 <description>CMAC key</description>
78165 <description>KSK key</description>
78172 <description>Real Time Fingerprint key</description>
78179 <description>Derivation key for CKDF command</description>
78186 <description>Derivation key for HKDF command</description>
78193 <description>Ecc signing key</description>
78200 <description>Ecc diffie hellman key</description>
78207 <description>Aes key</description>
78214 <description>Hmac key</description>
78221 <description>Key wrapping key</description>
78228 <description>Key unwrapping key</description>
78235 <description>TLS Pre Master Secret</description>
78242 <description>TLS Master Secret</description>
78249 <description>Supply KEYGEN source</description>
78256 <description>Hardware out key</description>
78263 <description>Ok to wrap key</description>
78270 <description>Device Unique Key</description>
78277 <description>Priviledge level</description>
78286 <description>Status register</description>
78295 <description>Key size: 0-128, 1-256</description>
78302 <description>Reserved 0</description>
78309 <description>Key is active</description>
78316 <description>First slot in a multislot key</description>
78323 <description>Hardware Feature General Purpose</description>
78330 <description>Hardware Feature Retention</description>
78337 <description>Hardware Feature Output</description>
78344 <description>Reserved 1</description>
78351 <description>CMAC key</description>
78358 <description>KSK key</description>
78365 <description>Real Time Fingerprint key</description>
78372 <description>Derivation key for CKDF command</description>
78379 <description>Derivation key for HKDF command</description>
78386 <description>Ecc signing key</description>
78393 <description>Ecc diffie hellman key</description>
78400 <description>Aes key</description>
78407 <description>Hmac key</description>
78414 <description>Key wrapping key</description>
78421 <description>Key unwrapping key</description>
78428 <description>TLS Pre Master Secret</description>
78435 <description>TLS Master Secret</description>
78442 <description>Supply KEYGEN source</description>
78449 <description>Hardware out key</description>
78456 <description>Ok to wrap key</description>
78463 <description>Device Unique Key</description>
78470 <description>Priviledge level</description>
78479 <description>Status register</description>
78488 <description>Key size: 0-128, 1-256</description>
78495 <description>Reserved 0</description>
78502 <description>Key is active</description>
78509 <description>First slot in a multislot key</description>
78516 <description>Hardware Feature General Purpose</description>
78523 <description>Hardware Feature Retention</description>
78530 <description>Hardware Feature Output</description>
78537 <description>Reserved 1</description>
78544 <description>CMAC key</description>
78551 <description>KSK key</description>
78558 <description>Real Time Fingerprint key</description>
78565 <description>Derivation key for CKDF command</description>
78572 <description>Derivation key for HKDF command</description>
78579 <description>Ecc signing key</description>
78586 <description>Ecc diffie hellman key</description>
78593 <description>Aes key</description>
78600 <description>Hmac key</description>
78607 <description>Key wrapping key</description>
78614 <description>Key unwrapping key</description>
78621 <description>TLS Pre Master Secret</description>
78628 <description>TLS Master Secret</description>
78635 <description>Supply KEYGEN source</description>
78642 <description>Hardware out key</description>
78649 <description>Ok to wrap key</description>
78656 <description>Device Unique Key</description>
78663 <description>Priviledge level</description>
78672 <description>Status register</description>
78681 <description>Key size: 0-128, 1-256</description>
78688 <description>Reserved 0</description>
78695 <description>Key is active</description>
78702 <description>First slot in a multislot key</description>
78709 <description>Hardware Feature General Purpose</description>
78716 <description>Hardware Feature Retention</description>
78723 <description>Hardware Feature Output</description>
78730 <description>Reserved 1</description>
78737 <description>CMAC key</description>
78744 <description>KSK key</description>
78751 <description>Real Time Fingerprint key</description>
78758 <description>Derivation key for CKDF command</description>
78765 <description>Derivation key for HKDF command</description>
78772 <description>Ecc signing key</description>
78779 <description>Ecc diffie hellman key</description>
78786 <description>Aes key</description>
78793 <description>Hmac key</description>
78800 <description>Key wrapping key</description>
78807 <description>Key unwrapping key</description>
78814 <description>TLS Pre Master Secret</description>
78821 <description>TLS Master Secret</description>
78828 <description>Supply KEYGEN source</description>
78835 <description>Hardware out key</description>
78842 <description>Ok to wrap key</description>
78849 <description>Device Unique Key</description>
78856 <description>Priviledge level</description>
78865 <description>Status register</description>
78874 <description>Key size: 0-128, 1-256</description>
78881 <description>Reserved 0</description>
78888 <description>Key is active</description>
78895 <description>First slot in a multislot key</description>
78902 <description>Hardware Feature General Purpose</description>
78909 <description>Hardware Feature Retention</description>
78916 <description>Hardware Feature Output</description>
78923 <description>Reserved 1</description>
78930 <description>CMAC key</description>
78937 <description>KSK key</description>
78944 <description>Real Time Fingerprint key</description>
78951 <description>Derivation key for CKDF command</description>
78958 <description>Derivation key for HKDF command</description>
78965 <description>Ecc signing key</description>
78972 <description>Ecc diffie hellman key</description>
78979 <description>Aes key</description>
78986 <description>Hmac key</description>
78993 <description>Key wrapping key</description>
79000 <description>Key unwrapping key</description>
79007 <description>TLS Pre Master Secret</description>
79014 <description>TLS Master Secret</description>
79021 <description>Supply KEYGEN source</description>
79028 <description>Hardware out key</description>
79035 <description>Ok to wrap key</description>
79042 <description>Device Unique Key</description>
79049 <description>Priviledge level</description>
79058 <description>Status register</description>
79067 <description>Key size: 0-128, 1-256</description>
79074 <description>Reserved 0</description>
79081 <description>Key is active</description>
79088 <description>First slot in a multislot key</description>
79095 <description>Hardware Feature General Purpose</description>
79102 <description>Hardware Feature Retention</description>
79109 <description>Hardware Feature Output</description>
79116 <description>Reserved 1</description>
79123 <description>CMAC key</description>
79130 <description>KSK key</description>
79137 <description>Real Time Fingerprint key</description>
79144 <description>Derivation key for CKDF command</description>
79151 <description>Derivation key for HKDF command</description>
79158 <description>Ecc signing key</description>
79165 <description>Ecc diffie hellman key</description>
79172 <description>Aes key</description>
79179 <description>Hmac key</description>
79186 <description>Key wrapping key</description>
79193 <description>Key unwrapping key</description>
79200 <description>TLS Pre Master Secret</description>
79207 <description>TLS Master Secret</description>
79214 <description>Supply KEYGEN source</description>
79221 <description>Hardware out key</description>
79228 <description>Ok to wrap key</description>
79235 <description>Device Unique Key</description>
79242 <description>Priviledge level</description>
79251 <description>Status register</description>
79260 <description>Key size: 0-128, 1-256</description>
79267 <description>Reserved 0</description>
79274 <description>Key is active</description>
79281 <description>First slot in a multislot key</description>
79288 <description>Hardware Feature General Purpose</description>
79295 <description>Hardware Feature Retention</description>
79302 <description>Hardware Feature Output</description>
79309 <description>Reserved 1</description>
79316 <description>CMAC key</description>
79323 <description>KSK key</description>
79330 <description>Real Time Fingerprint key</description>
79337 <description>Derivation key for CKDF command</description>
79344 <description>Derivation key for HKDF command</description>
79351 <description>Ecc signing key</description>
79358 <description>Ecc diffie hellman key</description>
79365 <description>Aes key</description>
79372 <description>Hmac key</description>
79379 <description>Key wrapping key</description>
79386 <description>Key unwrapping key</description>
79393 <description>TLS Pre Master Secret</description>
79400 <description>TLS Master Secret</description>
79407 <description>Supply KEYGEN source</description>
79414 <description>Hardware out key</description>
79421 <description>Ok to wrap key</description>
79428 <description>Device Unique Key</description>
79435 <description>Priviledge level</description>
79444 <description>Status register</description>
79453 <description>Key size: 0-128, 1-256</description>
79460 <description>Reserved 0</description>
79467 <description>Key is active</description>
79474 <description>First slot in a multislot key</description>
79481 <description>Hardware Feature General Purpose</description>
79488 <description>Hardware Feature Retention</description>
79495 <description>Hardware Feature Output</description>
79502 <description>Reserved 1</description>
79509 <description>CMAC key</description>
79516 <description>KSK key</description>
79523 <description>Real Time Fingerprint key</description>
79530 <description>Derivation key for CKDF command</description>
79537 <description>Derivation key for HKDF command</description>
79544 <description>Ecc signing key</description>
79551 <description>Ecc diffie hellman key</description>
79558 <description>Aes key</description>
79565 <description>Hmac key</description>
79572 <description>Key wrapping key</description>
79579 <description>Key unwrapping key</description>
79586 <description>TLS Pre Master Secret</description>
79593 <description>TLS Master Secret</description>
79600 <description>Supply KEYGEN source</description>
79607 <description>Hardware out key</description>
79614 <description>Ok to wrap key</description>
79621 <description>Device Unique Key</description>
79628 <description>Priviledge level</description>
79637 <description>Status register</description>
79646 <description>Key size: 0-128, 1-256</description>
79653 <description>Reserved 0</description>
79660 <description>Key is active</description>
79667 <description>First slot in a multislot key</description>
79674 <description>Hardware Feature General Purpose</description>
79681 <description>Hardware Feature Retention</description>
79688 <description>Hardware Feature Output</description>
79695 <description>Reserved 1</description>
79702 <description>CMAC key</description>
79709 <description>KSK key</description>
79716 <description>Real Time Fingerprint key</description>
79723 <description>Derivation key for CKDF command</description>
79730 <description>Derivation key for HKDF command</description>
79737 <description>Ecc signing key</description>
79744 <description>Ecc diffie hellman key</description>
79751 <description>Aes key</description>
79758 <description>Hmac key</description>
79765 <description>Key wrapping key</description>
79772 <description>Key unwrapping key</description>
79779 <description>TLS Pre Master Secret</description>
79786 <description>TLS Master Secret</description>
79793 <description>Supply KEYGEN source</description>
79800 <description>Hardware out key</description>
79807 <description>Ok to wrap key</description>
79814 <description>Device Unique Key</description>
79821 <description>Priviledge level</description>
79830 <description>Status register</description>
79839 <description>Key size: 0-128, 1-256</description>
79846 <description>Reserved 0</description>
79853 <description>Key is active</description>
79860 <description>First slot in a multislot key</description>
79867 <description>Hardware Feature General Purpose</description>
79874 <description>Hardware Feature Retention</description>
79881 <description>Hardware Feature Output</description>
79888 <description>Reserved 1</description>
79895 <description>CMAC key</description>
79902 <description>KSK key</description>
79909 <description>Real Time Fingerprint key</description>
79916 <description>Derivation key for CKDF command</description>
79923 <description>Derivation key for HKDF command</description>
79930 <description>Ecc signing key</description>
79937 <description>Ecc diffie hellman key</description>
79944 <description>Aes key</description>
79951 <description>Hmac key</description>
79958 <description>Key wrapping key</description>
79965 <description>Key unwrapping key</description>
79972 <description>TLS Pre Master Secret</description>
79979 <description>TLS Master Secret</description>
79986 <description>Supply KEYGEN source</description>
79993 <description>Hardware out key</description>
80000 <description>Ok to wrap key</description>
80007 <description>Device Unique Key</description>
80014 <description>Priviledge level</description>
80023 <description>Status register</description>
80032 <description>Key size: 0-128, 1-256</description>
80039 <description>Reserved 0</description>
80046 <description>Key is active</description>
80053 <description>First slot in a multislot key</description>
80060 <description>Hardware Feature General Purpose</description>
80067 <description>Hardware Feature Retention</description>
80074 <description>Hardware Feature Output</description>
80081 <description>Reserved 1</description>
80088 <description>CMAC key</description>
80095 <description>KSK key</description>
80102 <description>Real Time Fingerprint key</description>
80109 <description>Derivation key for CKDF command</description>
80116 <description>Derivation key for HKDF command</description>
80123 <description>Ecc signing key</description>
80130 <description>Ecc diffie hellman key</description>
80137 <description>Aes key</description>
80144 <description>Hmac key</description>
80151 <description>Key wrapping key</description>
80158 <description>Key unwrapping key</description>
80165 <description>TLS Pre Master Secret</description>
80172 <description>TLS Master Secret</description>
80179 <description>Supply KEYGEN source</description>
80186 <description>Hardware out key</description>
80193 <description>Ok to wrap key</description>
80200 <description>Device Unique Key</description>
80207 <description>Priviledge level</description>
80216 <description>SW control for the CSS boot addr</description>
80225 <description>32-bit wide boot offset</description>
80234 <description>CSS Debug Config SFR</description>
80243 <description>Debug Config 0</description>
80250 <description>Debug Config 1</description>
80257 <description>reserved</description>
80268 <description>FLASH</description>
80283 <description>Command</description>
80292 <description>command register.</description>
80301 <description>Event</description>
80310 <description>When bit is set, the controller and flash are reset.</description>
80317 …<description>When bit is set, the controller wakes up from whatever low power or powerdown mode wa…
80324 … <description>When bit is set, a running program/erase command is aborted.</description>
80333 <description>Read burst</description>
80342 <description>burst 2 XOR mask.</description>
80349 <description>Burst 1 descriptor.</description>
80356 <description>Burst 2 descriptor.</description>
80363 <description>Burst 3 descriptor.</description>
80372 <description>Start address for next flash command</description>
80381 …<description>Address / Start address for commands that take an address (range) as a parameter.</de…
80390 <description>End address for next flash command</description>
80399 …description>Stop address for commands that take an address range as a parameter (the word specifie…
80408 <description>Test configuration</description>
80417 …<description>These bit fields select which internal signal is brought onto the DCM1/2 pads.</descr…
80424 …<description>These bit fields select which internal signal is brought onto the DCM1/2 pads.</descr…
80431 <description>This bit controls the extclk48mhz controller output.</description>
80440 <description>Parity register; Memory parity data</description>
80449 <description>parity register; Memory parity data.</description>
80460 <description>Flexible SeQuence register 0-3</description>
80469 <description>Start state of sub-sequence 1.</description>
80476 <description>End state of sub-sequence 1.</description>
80483 <description>Start state of sub-sequence 2.</description>
80490 <description>End state of sub-sequence 2.</description>
80501 <description>Data register</description>
80510 <description>Memory data, or command parameter, or command result.</description>
80519 <description>Clear interrupt enables</description>
80528 <description>Clears the fail interrupt.</description>
80535 <description>Clears the error interrupt.</description>
80542 <description>Clears the done interrupt.</description>
80549 <description>Clears the ECC error interrupt.</description>
80558 <description>Set interrupt enables</description>
80567 <description>Sets Fail interrupt.</description>
80574 <description>Sets error interrupt</description>
80581 <description>Sets done interrupt.</description>
80588 <description>Sets ECC error interrupt.</description>
80597 <description>Interrupt status</description>
80606 … <description>This status bit is set if execution of a (legal) command failed.</description>
80613 … <description>This status bit is set if execution of an illegal command is detected.</description>
80620 <description>This status bit is set at the end of command execution.</description>
80627 …description>This status bit is set if, during a memory read operation (either a user-requested rea…
80636 <description>Interrupt enable</description>
80645 <description>Enables fail interrupt.</description>
80652 <description>Enables error interrupt.</description>
80659 <description>Enables done interrupt.</description>
80666 <description>Enables ECC error interrupt.</description>
80675 <description>Clear interrupt status</description>
80684 <description>Clears fail interrupt status.</description>
80691 <description>Clears error interrupt status.</description>
80698 <description>Clears done interrupt status.</description>
80705 <description>Clears ECC error interrupt status.</description>
80714 <description>Set interrupt status</description>
80723 <description>Sets fail interrupt status.</description>
80730 <description>Sets error interrupt status.</description>
80737 <description>Sets done interrupt status.</description>
80744 <description>Sets ECC error interrupt status.</description>
80753 <description>Module identification</description>
80762 <description>Aperture i.</description>
80769 <description>Minor revision i.</description>
80776 <description>Major revision i.</description>
80783 <description>Identifier.</description>
80794 <description>PRINCE</description>
80805 <description>Encryption Enable register</description>
80814 <description>Enables PRINCE encryption for flash programming.</description>
80821 …<description>Encryption of writes to the flash controller DATAW* registers is disabled.</descripti…
80826 …description>Encryption of writes to the flash controller DATAW* registers is enabled. Reading of P…
80835 <description>Data Mask register, 32 Least Significant Bits</description>
80844 … <description>Value of the 32 Least Significant Bits of the 64-bit data mask.</description>
80853 <description>Data Mask register, 32 Most Significant Bits</description>
80862 … <description>Value of the 32 Most Significant Bits of the 64-bit data mask.</description>
80871 <description>Lock register</description>
80880 <description>Lock Region 0 registers.</description>
80887 … <description>Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..</description>
80892 …<description>Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..</description>
80899 <description>Lock Region 1 registers.</description>
80906 … <description>Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..</description>
80911 …<description>Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..</description>
80918 <description>Lock Region 2 registers.</description>
80925 … <description>Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..</description>
80930 …<description>Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..</description>
80937 <description>Lock the Mask registers.</description>
80944 <description>Disabled. MASK_LSB, and MASK_MSB are writable..</description>
80949 <description>Enabled. MASK_LSB, and MASK_MSB are not writable..</description>
80958 <description>Initial Vector register for region 0, Least Significant Bits</description>
80967 …<description>Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.<…
80976 <description>Initial Vector register for region 0, Most Significant Bits</description>
80985 …<description>Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.</…
80994 <description>Base Address for region 0 register</description>
81003 <description>Fixed portion of the base address of region 0.</description>
81010 <description>Programmable portion of the base address of region 0.</description>
81019 <description>Sub-Region Enable register for region 0</description>
81028 …<description>Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum o…
81037 <description>Initial Vector register for region 1, Least Significant Bits</description>
81046 …<description>Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.<…
81055 <description>Initial Vector register for region 1, Most Significant Bits</description>
81064 …<description>Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.</…
81073 <description>Base Address for region 1 register</description>
81082 <description>Fixed portion of the base address of region 1.</description>
81089 <description>Programmable portion of the base address of region 1.</description>
81098 <description>Sub-Region Enable register for region 1</description>
81107 …<description>Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum o…
81116 <description>Initial Vector register for region 2, Least Significant Bits</description>
81125 …<description>Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector.<…
81134 <description>Initial Vector register for region 2, Most Significant Bits</description>
81143 …<description>Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector.</…
81152 <description>Base Address for region 2 register</description>
81161 <description>Fixed portion of the base address of region 2.</description>
81168 <description>Programmable portion of the base address of region 2.</description>
81177 <description>Sub-Region Enable register for region 2</description>
81186 …<description>Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum o…
81195 <description>Error status register</description>
81204 <description>PRINCE Error Status. This bit is write-1 to clear.</description>
81211 <description>No PRINCE error.</description>
81216 …<description>Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1.</desc…
81227 <description>XOM enable for sub region i</description>
81236 <description>XOM enable</description>
81243 …<description>A 0 in bit n means that decryption of data associated with sub-region n is done for b…
81248 …<description>A 1 in bit n means that decryption of data associated with sub-region n is done for c…
81259 <description>PUF</description>
81270 <description>Control</description>
81279 <description>Begin Zeroize operation</description>
81286 <description>Begin Enroll operation</description>
81293 <description>Begin Start operation</description>
81300 <description>Begin Stop operation</description>
81307 <description>Begin Get Key operation</description>
81314 <description>Begin Unwrap operation</description>
81321 <description>Begin Wrap Generated Random operation</description>
81328 <description>Begin Wrap operation</description>
81335 <description>Begin Generate Random operation</description>
81342 <description>Begin Test PUF operation</description>
81351 <description>Operation Result</description>
81360 <description>Result code of last operation</description>
81367 … <description>Last operation was successful or operation is in progress.</description>
81372 <description>Provided AC is not for the current product/version.</description>
81377 … <description>AC in the second phase is not for the current product/version.</description>
81382 <description>Provided AC is corrupted.</description>
81387 <description>AC in the second phase is corrupted.</description>
81392 <description>Authentication of the provided AC failed.</description>
81397 … <description>Authentication of the provided AC failed in the second phase.</description>
81402 <description>SRAM PUF quality verification fails.</description>
81407 <description>Incorrect or unsupported context is provided.</description>
81412 …<description>A data destination was set that is not allowed according to other settings and the cu…
81417 <description>PUF SRAM access has failed.</description>
81424 <description>Number of last operation</description>
81431 <description>Operation is in progress.</description>
81436 <description>Last operation was Enroll.</description>
81441 <description>Last operation was Start.</description>
81446 <description>Last operation was Stop.</description>
81451 <description>Last operation was Get Key.</description>
81456 <description>Last operation was Unwrap.</description>
81461 <description>Last operation was Wrap Generated Random.</description>
81466 <description>Last operation was Wrap.</description>
81471 <description>Last operation was Generate Random.</description>
81476 <description>Last operation was Test PUF.</description>
81481 <description>Last operation was Initialization.</description>
81486 <description>Last operation was Zeroize.</description>
81495 <description>Status</description>
81504 <description>Operation is in progress</description>
81511 <description>Last operation was successful</description>
81518 <description>Last operation failed</description>
81525 <description>Zeroized or Locked state</description>
81532 <description>Operation rejected</description>
81540 <description>Request for data in transfer via the DIR register</description>
81547 <description>Request for data out transfer via the DOR register</description>
81556 <description>Allow</description>
81565 <description>Enroll operation</description>
81572 <description>Enroll operation is not allowed</description>
81577 <description>Enroll operation is allowed</description>
81584 <description>Start operation</description>
81591 <description>Start operation is not allowed</description>
81596 <description>Start operation is allowed</description>
81603 <description>Stop operation</description>
81610 <description>Stop operation is not allowed</description>
81615 <description>Stop operation is allowed</description>
81622 <description>Get Key operation</description>
81629 <description>Get Key operation is not allowed</description>
81634 <description>Get Key operation is allowed</description>
81641 <description>Unwrap operation</description>
81648 <description>Unwrap operation is not allowed</description>
81653 <description>Unwrap operation is allowed</description>
81660 <description>Wrap Generated Random operation</description>
81667 <description>Wrap Generated Random operation is not allowed</description>
81672 <description>Wrap Generated Random operation is allowed</description>
81679 <description>Wrap operation</description>
81686 <description>Wrap operation is not allowed</description>
81691 <description>Wrap operation is allowed</description>
81698 <description>Generate Random operation</description>
81705 <description>Generate Random operation is not allowed</description>
81710 <description>Generate Random operation is allowed</description>
81717 <description>Test PUF operation</description>
81724 <description>Test PUF operation is not allowed</description>
81729 <description>Test PUF operation is allowed</description>
81738 <description>Interrupt Enable</description>
81747 <description>Interrupt enable</description>
81754 <description>Disables all QuiddiKey interrupts</description>
81759 …<description>Enables all QuiddiKey interrupts that are enabled in the Interrupt Mask register</des…
81768 <description>Interrupt Mask</description>
81777 <description>Enable busy interrupt</description>
81784 <description>Enable ok interrupt</description>
81791 <description>Enable error interrupt</description>
81798 <description>Enable zeroized interrupt</description>
81805 <description>Enable rejected interrupt</description>
81812 <description>Enable data in request interrupt</description>
81819 <description>Enable data out request interrupt</description>
81828 <description>Interrupt Status</description>
81837 …<description>Negative edge occurred on busy, which means that an operation has completed</descript…
81845 …<description>Positive edge occurred on ok, which means that an operation successfully completed</d…
81853 …<description>Positive edge occurred on error, which means that an operation has failed</descriptio…
81861 …<description>Positive edge occurred on zeroized, which means that QuiddiKey has moved to the Zeroi…
81869 …<description>Positive edge occurred on rejected, which means that a command was rejected</descript…
81877 …<description>Positive edge occurred on di_request, which means that a data in transfer is requeste…
81885 …<description>Positive edge occurred on do_request, which means that a data out transfer is request…
81895 <description>Key Destination</description>
81904 <description>Key will be made available via the DOR register</description>
81911 <description>Key will be made available via the KO interface</description>
81920 <description>Data Input</description>
81929 <description>Input data to QuiddiKey</description>
81938 <description>Data Output</description>
81947 <description>Output data from QuiddiKey</description>
81956 <description>Miscellaneous</description>
81965 <description>Defines the endianness of data in DIR and DOR:</description>
81972 <description>Little endian</description>
81977 <description>Big endian (default)</description>
81986 <description>Interface Status</description>
81995 <description>An APB error occurred</description>
82005 <description>Test</description>
82014 <description>Isolates QuiddiKey and runs BIST</description>
82021 <description>BIST is in progress or finishing up (after bist_enable = 0)</description>
82028 <description>BIST is in progress</description>
82035 <description>BIST has passed</description>
82042 <description>BIST has failed</description>
82049 <description>BIST is not allowed</description>
82058 <description>PUF Score</description>
82067 … <description>PUF score obtained during the last Test PUF, Enroll or Start operation</description>
82076 <description>Hardware Restrict User Context 0</description>
82085 <description>Restrict user context 0</description>
82092 <description>Bit can be used</description>
82097 <description>Bit cannot be used</description>
82104 <description>Restrict user context 0</description>
82111 <description>Bit can be used</description>
82116 <description>Bit cannot be used</description>
82123 <description>Restrict user context 0</description>
82130 <description>Bit can be used</description>
82135 <description>Bit cannot be used</description>
82142 <description>Restrict user context 0</description>
82149 <description>Bit can be used</description>
82154 <description>Bit cannot be used</description>
82161 <description>Restrict user context 0</description>
82168 <description>Bit can be used</description>
82173 <description>Bit cannot be used</description>
82180 <description>Restrict user context 0</description>
82187 <description>Bit can be used</description>
82192 <description>Bit cannot be used</description>
82199 <description>Restrict user context 0</description>
82206 <description>Bit can be used</description>
82211 <description>Bit cannot be used</description>
82218 <description>Restrict user context 0</description>
82225 <description>Bit can be used</description>
82230 <description>Bit cannot be used</description>
82237 <description>Restrict user context 0</description>
82244 <description>Bit can be used</description>
82249 <description>Bit cannot be used</description>
82256 <description>Restrict user context 0</description>
82263 <description>Bit can be used</description>
82268 <description>Bit cannot be used</description>
82275 <description>Restrict user context 0</description>
82282 <description>Bit can be used</description>
82287 <description>Bit cannot be used</description>
82294 <description>Restrict user context 0</description>
82301 <description>Bit can be used</description>
82306 <description>Bit cannot be used</description>
82313 <description>Restrict user context 0</description>
82320 <description>Bit can be used</description>
82325 <description>Bit cannot be used</description>
82332 <description>Restrict user context 0</description>
82339 <description>Bit can be used</description>
82344 <description>Bit cannot be used</description>
82351 <description>Restrict user context 0</description>
82358 <description>Bit can be used</description>
82363 <description>Bit cannot be used</description>
82370 <description>Restrict user context 0</description>
82377 <description>Bit can be used</description>
82382 <description>Bit cannot be used</description>
82389 <description>Restrict user context 0</description>
82396 <description>Bit can be used</description>
82401 <description>Bit cannot be used</description>
82408 <description>Restrict user context 0</description>
82415 <description>Bit can be used</description>
82420 <description>Bit cannot be used</description>
82427 <description>Restrict user context 0</description>
82434 <description>Bit can be used</description>
82439 <description>Bit cannot be used</description>
82446 <description>Restrict user context 0</description>
82453 <description>Bit can be used</description>
82458 <description>Bit cannot be used</description>
82465 <description>Restrict user context 0</description>
82472 <description>Bit can be used</description>
82477 <description>Bit cannot be used</description>
82484 <description>Restrict user context 0</description>
82491 <description>Bit can be used</description>
82496 <description>Bit cannot be used</description>
82503 <description>Restrict user context 0</description>
82510 <description>Bit can be used</description>
82515 <description>Bit cannot be used</description>
82522 <description>Restrict user context 0</description>
82529 <description>Bit can be used</description>
82534 <description>Bit cannot be used</description>
82541 <description>Restrict user context 0</description>
82548 <description>Bit can be used</description>
82553 <description>Bit cannot be used</description>
82560 <description>Restrict user context 0</description>
82567 <description>Bit can be used</description>
82572 <description>Bit cannot be used</description>
82579 <description>Restrict user context 0</description>
82586 <description>Bit can be used</description>
82591 <description>Bit cannot be used</description>
82598 <description>Restrict user context 0</description>
82605 <description>Bit can be used</description>
82610 <description>Bit cannot be used</description>
82617 <description>Restrict user context 0</description>
82624 <description>Bit can be used</description>
82629 <description>Bit cannot be used</description>
82636 <description>Restrict user context 0</description>
82643 <description>Bit can be used</description>
82648 <description>Bit cannot be used</description>
82655 <description>Restrict user context 0</description>
82662 <description>Bit can be used</description>
82667 <description>Bit cannot be used</description>
82674 <description>Restrict user context 0</description>
82681 <description>Bit can be used</description>
82686 <description>Bit cannot be used</description>
82695 <description>Hardware Restrict User Context 1</description>
82704 <description>Restrict user context 1</description>
82711 <description>Bit can be used</description>
82716 <description>Bit cannot be used</description>
82723 <description>Restrict user context 1</description>
82730 <description>Bit can be used</description>
82735 <description>Bit cannot be used</description>
82742 <description>Restrict user context 1</description>
82749 <description>Bit can be used</description>
82754 <description>Bit cannot be used</description>
82761 <description>Restrict user context 1</description>
82768 <description>Bit can be used</description>
82773 <description>Bit cannot be used</description>
82780 <description>Restrict user context 1</description>
82787 <description>Bit can be used</description>
82792 <description>Bit cannot be used</description>
82799 <description>Restrict user context 1</description>
82806 <description>Bit can be used</description>
82811 <description>Bit cannot be used</description>
82818 <description>Restrict user context 1</description>
82825 <description>Bit can be used</description>
82830 <description>Bit cannot be used</description>
82837 <description>Restrict user context 1</description>
82844 <description>Bit can be used</description>
82849 <description>Bit cannot be used</description>
82856 <description>Restrict user context 1</description>
82863 <description>Bit can be used</description>
82868 <description>Bit cannot be used</description>
82875 <description>Restrict user context 1</description>
82882 <description>Bit can be used</description>
82887 <description>Bit cannot be used</description>
82894 <description>Restrict user context 1</description>
82901 <description>Bit can be used</description>
82906 <description>Bit cannot be used</description>
82913 <description>Restrict user context 1</description>
82920 <description>Bit can be used</description>
82925 <description>Bit cannot be used</description>
82932 <description>Restrict user context 1</description>
82939 <description>Bit can be used</description>
82944 <description>Bit cannot be used</description>
82951 <description>Restrict user context 1</description>
82958 <description>Bit can be used</description>
82963 <description>Bit cannot be used</description>
82970 <description>Restrict user context 1</description>
82977 <description>Bit can be used</description>
82982 <description>Bit cannot be used</description>
82989 <description>Restrict user context 1</description>
82996 <description>Bit can be used</description>
83001 <description>Bit cannot be used</description>
83008 <description>Restrict user context 1</description>
83015 <description>Bit can be used</description>
83020 <description>Bit cannot be used</description>
83027 <description>Restrict user context 1</description>
83034 <description>Bit can be used</description>
83039 <description>Bit cannot be used</description>
83046 <description>Restrict user context 1</description>
83053 <description>Bit can be used</description>
83058 <description>Bit cannot be used</description>
83065 <description>Restrict user context 1</description>
83072 <description>Bit can be used</description>
83077 <description>Bit cannot be used</description>
83084 <description>Restrict user context 1</description>
83091 <description>Bit can be used</description>
83096 <description>Bit cannot be used</description>
83103 <description>Restrict user context 1</description>
83110 <description>Bit can be used</description>
83115 <description>Bit cannot be used</description>
83122 <description>Restrict user context 1</description>
83129 <description>Bit can be used</description>
83134 <description>Bit cannot be used</description>
83141 <description>Restrict user context 1</description>
83148 <description>Bit can be used</description>
83153 <description>Bit cannot be used</description>
83160 <description>Restrict user context 1</description>
83167 <description>Bit can be used</description>
83172 <description>Bit cannot be used</description>
83179 <description>Restrict user context 1</description>
83186 <description>Bit can be used</description>
83191 <description>Bit cannot be used</description>
83198 <description>Restrict user context 1</description>
83205 <description>Bit can be used</description>
83210 <description>Bit cannot be used</description>
83217 <description>Restrict user context 1</description>
83224 <description>Bit can be used</description>
83229 <description>Bit cannot be used</description>
83236 <description>Restrict user context 1</description>
83243 <description>Bit can be used</description>
83248 <description>Bit cannot be used</description>
83255 <description>Restrict user context 1</description>
83262 <description>Bit can be used</description>
83267 <description>Bit cannot be used</description>
83274 <description>Restrict user context 1</description>
83281 <description>Bit can be used</description>
83286 <description>Bit cannot be used</description>
83293 <description>Restrict user context 1</description>
83300 <description>Bit can be used</description>
83305 <description>Bit cannot be used</description>
83314 <description>Hardware Settings</description>
83323 <description>Enroll operations disable</description>
83330 <description>Enroll operations are enabled</description>
83335 <description>Enroll operations are disabled</description>
83342 <description>Start operations disable</description>
83349 <description>Start operations are enabled</description>
83354 <description>Start operations are disabled</description>
83361 <description>Stop operations disable</description>
83368 <description>Stop operations are enabled</description>
83373 <description>Stop operations are disabled</description>
83380 <description>Get Key operations</description>
83387 <description>Get Key operations are enabled</description>
83392 <description>Get Key operations are disabled</description>
83399 <description>Unwrap operations</description>
83406 <description>Unwrap operations are enabled</description>
83411 <description>Unwrap operations are disabled</description>
83418 <description>Wrap Generated Random operations</description>
83425 <description>Wrap Generated Random operations are enabled</description>
83430 <description>Wrap Generated Random operations are disabled</description>
83437 <description>Wrap operations</description>
83444 <description>Wrap operations are enabled</description>
83449 <description>Wrap operations are disabled</description>
83456 <description>Generate Random operations</description>
83463 <description>Generate Random operations are enabled</description>
83468 <description>Generate Random operations are disabled</description>
83475 <description>Test PUF operations</description>
83482 <description>Test PUF operations are enabled</description>
83487 <description>Test PUF operations are disabled</description>
83496 <description>Hardware Information</description>
83505 <description>BIST configuration</description>
83512 <description>BIST is not included</description>
83517 <description>BIST is included</description>
83524 <description>Wrap configuration</description>
83531 <description>Wrap is not included</description>
83536 <description>Wrap is included</description>
83543 <description>QuiddiKey configuration</description>
83550 <description>QuiddiKey configuration is Safe.</description>
83555 <description>QuiddiKey configuration is Plus.</description>
83564 <description>Hardware Identifier</description>
83573 <description>Hardware identifier</description>
83582 <description>Hardware Version</description>
83591 <description>Hardware version, patch part</description>
83598 <description>Hardware version, minor part</description>
83605 <description>Hardware version, major part</description>
83614 <description>Status</description>
83623 <description>PUF SRAM Controller State</description>
83632 <description>SRAM Configuration</description>
83641 <description>SRAM Source Biasing voltage control</description>
83648 <description>SRAM Read Margin control settings</description>
83655 <description>SRAM Write Margin control settings</description>
83662 <description>SRAM Write Read Margin Enable</description>
83669 <description>Enabled</description>
83676 <description>SRAM Read Assist Enable</description>
83683 <description>Enabled</description>
83690 <description>SRAM Read Assist settings</description>
83697 <description>SRAM Write Assist Enable</description>
83704 <description>Enabled</description>
83711 <description>SRAM Write Assist settings</description>
83718 <description>STBP</description>
83725 <description>Enabled</description>
83734 <description>Interrupt Enable Clear</description>
83743 <description>READY Interrupt Enable clear</description>
83750 <description>APB_ERR Interrupt Enable clear</description>
83759 <description>Interrupt Enable Set</description>
83768 <description>READY Interrupt Enable set</description>
83775 <description>APB_ERR Interrupt Enable set</description>
83784 <description>Interrupt Status</description>
83793 <description>READY Interrupt Status</description>
83800 <description>APB_ERR Interrupt Status</description>
83809 <description>Interrupt Enable</description>
83818 <description>READY Interrupt Enable</description>
83825 <description>Enabled</description>
83832 <description>APB_ERR Interrupt Enable</description>
83839 <description>Enabled</description>
83848 <description>Interrupt Status Clear</description>
83857 <description>READY Interrupt Status clear</description>
83864 <description>APB_ERR Interrupt Status Clear</description>
83873 <description>Interrupt Status set</description>
83882 <description>READY Interrupt Status set</description>
83889 <description>APB_ERR Interrupt Status Set</description>
83898 <description>Module Identification</description>
83907 <description>Aperture size of the register interface</description>
83914 <description>Minor revision of module implementation</description>
83921 <description>Major revision of module implementation</description>
83928 <description>Identification number</description>
83939 <description>PUF Key Context Management</description>
83950 <description>PUF command blocking configuration</description>
83959 <description>Disable PUF enroll command</description>
83966 <description>Disable PUF start command</description>
83973 <description>Disable PUF stop command</description>
83980 <description>Disable PUF get key command</description>
83987 <description>Disable PUF unwrap key command</description>
83994 <description>Disable PUF generate and wrap key command</description>
84001 <description>Disable PUF wrap key command</description>
84008 <description>Disable PUF generate and wrap key command</description>
84015 <description>Disable PUF test command</description>
84024 …<description>Lock the security level of PUF block until key generate, wrap or unwrap operation is …
84033 <description>Disable PUF enroll command</description>
84040 <description>Nonsecure user</description>
84047 <description>Anti-pole of security level</description>
84054 <description>Pattern</description>
84063 <description>Application defined context mask</description>
84072 <description>Application defined context</description>
84083 <description>ROMC</description>
84097 <description>ROMC Data Registers</description>
84106 <description>Data Fix Registers</description>
84115 <description>ROMC Control Register</description>
84124 <description>Data Fix Enable</description>
84131 <description>Trigger an opcode patch for ROMPATCHnA</description>
84136 <description>Trigger a data fix for ROMPATCHnA</description>
84143 <description>Data Fix Enable</description>
84150 <description>Trigger an opcode patch for ROMPATCHnA</description>
84155 <description>Trigger a data fix for ROMPATCHnA</description>
84162 <description>Data Fix Enable</description>
84169 <description>Trigger an opcode patch for ROMPATCHnA</description>
84174 <description>Trigger a data fix for ROMPATCHnA</description>
84181 <description>Data Fix Enable</description>
84188 <description>Trigger an opcode patch for ROMPATCHnA</description>
84193 <description>Trigger a data fix for ROMPATCHnA</description>
84200 <description>Data Fix Enable</description>
84207 <description>Trigger an opcode patch for ROMPATCHnA</description>
84212 <description>Trigger a data fix for ROMPATCHnA</description>
84219 <description>Data Fix Enable</description>
84226 <description>Trigger an opcode patch for ROMPATCHnA</description>
84231 <description>Trigger a data fix for ROMPATCHnA</description>
84238 <description>Data Fix Enable</description>
84245 <description>Trigger an opcode patch for ROMPATCHnA</description>
84250 <description>Trigger a data fix for ROMPATCHnA</description>
84257 <description>Data Fix Enable</description>
84264 <description>Trigger an opcode patch for ROMPATCHnA</description>
84269 <description>Trigger a data fix for ROMPATCHnA</description>
84276 <description>Data Fix Enable</description>
84283 <description>Trigger an opcode patch for ROMPATCHnA</description>
84288 <description>Trigger a data fix for ROMPATCHnA</description>
84295 <description>Data Fix Enable</description>
84302 <description>Trigger an opcode patch for ROMPATCHnA</description>
84307 <description>Trigger a data fix for ROMPATCHnA</description>
84314 <description>Data Fix Enable</description>
84321 <description>Trigger an opcode patch for ROMPATCHnA</description>
84326 <description>Trigger a data fix for ROMPATCHnA</description>
84333 <description>Data Fix Enable</description>
84340 <description>Trigger an opcode patch for ROMPATCHnA</description>
84345 <description>Trigger a data fix for ROMPATCHnA</description>
84352 <description>Data Fix Enable</description>
84359 <description>Trigger an opcode patch for ROMPATCHnA</description>
84364 <description>Trigger a data fix for ROMPATCHnA</description>
84371 <description>Data Fix Enable</description>
84378 <description>Trigger an opcode patch for ROMPATCHnA</description>
84383 <description>Trigger a data fix for ROMPATCHnA</description>
84390 <description>Data Fix Enable</description>
84397 <description>Trigger an opcode patch for ROMPATCHnA</description>
84402 <description>Trigger a data fix for ROMPATCHnA</description>
84409 <description>Data Fix Enable</description>
84416 <description>Trigger an opcode patch for ROMPATCHnA</description>
84421 <description>Trigger a data fix for ROMPATCHnA</description>
84428 <description>ROMC Disable</description>
84435 <description>Does not affect any ROMC functions (default)</description>
84440 … <description>Disables all ROMC functions: data fixing and opcode patching</description>
84449 <description>ROMC Enable Register High</description>
84458 <description>ROMC Enable Register Low</description>
84467 <description>Enable Address Comparator</description>
84474 <description>Address comparator is disabled</description>
84479 …description>Address comparator is enabled; after the associated address is matched, the ROMC will …
84490 <description>ROMC Address Registers</description>
84499 <description>THUMB Comparator Select</description>
84506 <description>ARM patch</description>
84511 <description>THUMB patch (ignore if a data fix)</description>
84518 <description>Address Comparator Registers</description>
84527 <description>ROMC Status Register</description>
84536 <description>ROMC Source Number</description>
84543 <description>Address Comparator 0 matched</description>
84548 <description>Address Comparator 1 matched</description>
84553 <description>Address Comparator 15 matched</description>
84560 <description>ROMC AHB Multiple Address Comparator Match Indicator</description>
84568 <description>No event or comparator collisions have occurred</description>
84573 <description>A collision has occurred</description>
84584 <description>DMA0 controller</description>
84599 <description>DMA control</description>
84608 <description>DMA controller master enable.</description>
84615 <description>DMA controller is disabled.</description>
84620 <description>Enabled.</description>
84629 <description>Interrupt status</description>
84638 …<description>Summarizes whether any enabled interrupts (other than error interrupts) are pending.<…
84645 <description>No enabled interrupts are pending.</description>
84650 <description>At least one enabled interrupt is pending.</description>
84657 <description>Summarizes whether any error interrupts are pending.</description>
84664 <description>No error interrupts are pending.</description>
84669 <description>At least one error interrupt is pending.</description>
84678 <description>SRAM address of the channel configuration table</description>
84687 <description>Offset</description>
84696 <description>Channel Enable read and set for all DMA channels</description>
84705 <description>Enable for DMA channel</description>
84712 <description>DMA channel is disabled.</description>
84717 <description>DMA channel is enabled.</description>
84724 <description>Enable for DMA channel</description>
84731 <description>DMA channel is disabled.</description>
84736 <description>DMA channel is enabled.</description>
84743 <description>Enable for DMA channel</description>
84750 <description>DMA channel is disabled.</description>
84755 <description>DMA channel is enabled.</description>
84762 <description>Enable for DMA channel</description>
84769 <description>DMA channel is disabled.</description>
84774 <description>DMA channel is enabled.</description>
84781 <description>Enable for DMA channel</description>
84788 <description>DMA channel is disabled.</description>
84793 <description>DMA channel is enabled.</description>
84800 <description>Enable for DMA channel</description>
84807 <description>DMA channel is disabled.</description>
84812 <description>DMA channel is enabled.</description>
84819 <description>Enable for DMA channel</description>
84826 <description>DMA channel is disabled.</description>
84831 <description>DMA channel is enabled.</description>
84838 <description>Enable for DMA channel</description>
84845 <description>DMA channel is disabled.</description>
84850 <description>DMA channel is enabled.</description>
84857 <description>Enable for DMA channel</description>
84864 <description>DMA channel is disabled.</description>
84869 <description>DMA channel is enabled.</description>
84876 <description>Enable for DMA channel</description>
84883 <description>DMA channel is disabled.</description>
84888 <description>DMA channel is enabled.</description>
84895 <description>Enable for DMA channel</description>
84902 <description>DMA channel is disabled.</description>
84907 <description>DMA channel is enabled.</description>
84914 <description>Enable for DMA channel</description>
84921 <description>DMA channel is disabled.</description>
84926 <description>DMA channel is enabled.</description>
84933 <description>Enable for DMA channel</description>
84940 <description>DMA channel is disabled.</description>
84945 <description>DMA channel is enabled.</description>
84952 <description>Enable for DMA channel</description>
84959 <description>DMA channel is disabled.</description>
84964 <description>DMA channel is enabled.</description>
84971 <description>Enable for DMA channel</description>
84978 <description>DMA channel is disabled.</description>
84983 <description>DMA channel is enabled.</description>
84990 <description>Enable for DMA channel</description>
84997 <description>DMA channel is disabled.</description>
85002 <description>DMA channel is enabled.</description>
85009 <description>Enable for DMA channel</description>
85016 <description>DMA channel is disabled.</description>
85021 <description>DMA channel is enabled.</description>
85028 <description>Enable for DMA channel</description>
85035 <description>DMA channel is disabled.</description>
85040 <description>DMA channel is enabled.</description>
85047 <description>Enable for DMA channel</description>
85054 <description>DMA channel is disabled.</description>
85059 <description>DMA channel is enabled.</description>
85066 <description>Enable for DMA channel</description>
85073 <description>DMA channel is disabled.</description>
85078 <description>DMA channel is enabled.</description>
85085 <description>Enable for DMA channel</description>
85092 <description>DMA channel is disabled.</description>
85097 <description>DMA channel is enabled.</description>
85104 <description>Enable for DMA channel</description>
85111 <description>DMA channel is disabled.</description>
85116 <description>DMA channel is enabled.</description>
85123 <description>Enable for DMA channel</description>
85130 <description>DMA channel is disabled.</description>
85135 <description>DMA channel is enabled.</description>
85142 <description>Enable for DMA channel</description>
85149 <description>DMA channel is disabled.</description>
85154 <description>DMA channel is enabled.</description>
85161 <description>Enable for DMA channel</description>
85168 <description>DMA channel is disabled.</description>
85173 <description>DMA channel is enabled.</description>
85180 <description>Enable for DMA channel</description>
85187 <description>DMA channel is disabled.</description>
85192 <description>DMA channel is enabled.</description>
85199 <description>Enable for DMA channel</description>
85206 <description>DMA channel is disabled.</description>
85211 <description>DMA channel is enabled.</description>
85218 <description>Enable for DMA channel</description>
85225 <description>DMA channel is disabled.</description>
85230 <description>DMA channel is enabled.</description>
85237 <description>Enable for DMA channel</description>
85244 <description>DMA channel is disabled.</description>
85249 <description>DMA channel is enabled.</description>
85256 <description>Enable for DMA channel</description>
85263 <description>DMA channel is disabled.</description>
85268 <description>DMA channel is enabled.</description>
85275 <description>Enable for DMA channel</description>
85282 <description>DMA channel is disabled.</description>
85287 <description>DMA channel is enabled.</description>
85294 <description>Enable for DMA channel</description>
85301 <description>DMA channel is disabled.</description>
85306 <description>DMA channel is enabled.</description>
85315 <description>Channel Enable read and set for all DMA channels</description>
85324 <description>Enable for DMA channel</description>
85331 <description>DMA channel is disabled.</description>
85336 <description>DMA channel is enabled.</description>
85343 <description>Enable for DMA channel</description>
85350 <description>DMA channel is disabled.</description>
85355 <description>DMA channel is enabled.</description>
85362 <description>Enable for DMA channel</description>
85369 <description>DMA channel is disabled.</description>
85374 <description>DMA channel is enabled.</description>
85381 <description>Enable for DMA channel</description>
85388 <description>DMA channel is disabled.</description>
85393 <description>DMA channel is enabled.</description>
85400 <description>Enable for DMA channel</description>
85407 <description>DMA channel is disabled.</description>
85412 <description>DMA channel is enabled.</description>
85419 <description>Enable for DMA channel</description>
85426 <description>DMA channel is disabled.</description>
85431 <description>DMA channel is enabled.</description>
85438 <description>Enable for DMA channel</description>
85445 <description>DMA channel is disabled.</description>
85450 <description>DMA channel is enabled.</description>
85457 <description>Enable for DMA channel</description>
85464 <description>DMA channel is disabled.</description>
85469 <description>DMA channel is enabled.</description>
85476 <description>Enable for DMA channel</description>
85483 <description>DMA channel is disabled.</description>
85488 <description>DMA channel is enabled.</description>
85495 <description>Enable for DMA channel</description>
85502 <description>DMA channel is disabled.</description>
85507 <description>DMA channel is enabled.</description>
85514 <description>Enable for DMA channel</description>
85521 <description>DMA channel is disabled.</description>
85526 <description>DMA channel is enabled.</description>
85533 <description>Enable for DMA channel</description>
85540 <description>DMA channel is disabled.</description>
85545 <description>DMA channel is enabled.</description>
85552 <description>Enable for DMA channel</description>
85559 <description>DMA channel is disabled.</description>
85564 <description>DMA channel is enabled.</description>
85571 <description>Enable for DMA channel</description>
85578 <description>DMA channel is disabled.</description>
85583 <description>DMA channel is enabled.</description>
85590 <description>Enable for DMA channel</description>
85597 <description>DMA channel is disabled.</description>
85602 <description>DMA channel is enabled.</description>
85609 <description>Enable for DMA channel</description>
85616 <description>DMA channel is disabled.</description>
85621 <description>DMA channel is enabled.</description>
85628 <description>Enable for DMA channel</description>
85635 <description>DMA channel is disabled.</description>
85640 <description>DMA channel is enabled.</description>
85647 <description>Enable for DMA channel</description>
85654 <description>DMA channel is disabled.</description>
85659 <description>DMA channel is enabled.</description>
85666 <description>Enable for DMA channel</description>
85673 <description>DMA channel is disabled.</description>
85678 <description>DMA channel is enabled.</description>
85685 <description>Enable for DMA channel</description>
85692 <description>DMA channel is disabled.</description>
85697 <description>DMA channel is enabled.</description>
85706 <description>Channel Enable Clear for all DMA channels</description>
85715 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85723 <description>No effect.</description>
85728 <description>DMA channel is cleared.</description>
85735 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85743 <description>No effect.</description>
85748 <description>DMA channel is cleared.</description>
85755 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85763 <description>No effect.</description>
85768 <description>DMA channel is cleared.</description>
85775 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85783 <description>No effect.</description>
85788 <description>DMA channel is cleared.</description>
85795 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85803 <description>No effect.</description>
85808 <description>DMA channel is cleared.</description>
85815 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85823 <description>No effect.</description>
85828 <description>DMA channel is cleared.</description>
85835 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85843 <description>No effect.</description>
85848 <description>DMA channel is cleared.</description>
85855 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85863 <description>No effect.</description>
85868 <description>DMA channel is cleared.</description>
85875 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85883 <description>No effect.</description>
85888 <description>DMA channel is cleared.</description>
85895 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85903 <description>No effect.</description>
85908 <description>DMA channel is cleared.</description>
85915 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85923 <description>No effect.</description>
85928 <description>DMA channel is cleared.</description>
85935 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85943 <description>No effect.</description>
85948 <description>DMA channel is cleared.</description>
85955 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85963 <description>No effect.</description>
85968 <description>DMA channel is cleared.</description>
85975 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
85983 <description>No effect.</description>
85988 <description>DMA channel is cleared.</description>
85995 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86003 <description>No effect.</description>
86008 <description>DMA channel is cleared.</description>
86015 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86023 <description>No effect.</description>
86028 <description>DMA channel is cleared.</description>
86035 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86043 <description>No effect.</description>
86048 <description>DMA channel is cleared.</description>
86055 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86063 <description>No effect.</description>
86068 <description>DMA channel is cleared.</description>
86075 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86083 <description>No effect.</description>
86088 <description>DMA channel is cleared.</description>
86095 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86103 <description>No effect.</description>
86108 <description>DMA channel is cleared.</description>
86115 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86123 <description>No effect.</description>
86128 <description>DMA channel is cleared.</description>
86135 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86143 <description>No effect.</description>
86148 <description>DMA channel is cleared.</description>
86155 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86163 <description>No effect.</description>
86168 <description>DMA channel is cleared.</description>
86175 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86183 <description>No effect.</description>
86188 <description>DMA channel is cleared.</description>
86195 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86203 <description>No effect.</description>
86208 <description>DMA channel is cleared.</description>
86215 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86223 <description>No effect.</description>
86228 <description>DMA channel is cleared.</description>
86235 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86243 <description>No effect.</description>
86248 <description>DMA channel is cleared.</description>
86255 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86263 <description>No effect.</description>
86268 <description>DMA channel is cleared.</description>
86275 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86283 <description>No effect.</description>
86288 <description>DMA channel is cleared.</description>
86295 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86303 <description>No effect.</description>
86308 <description>DMA channel is cleared.</description>
86315 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86323 <description>No effect.</description>
86328 <description>DMA channel is cleared.</description>
86335 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
86343 <description>No effect.</description>
86348 <description>DMA channel is cleared.</description>
86357 <description>Channel Enable Clear for all DMA channels</description>
86366 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86374 <description>No effect.</description>
86379 <description>DMA channel is cleared.</description>
86386 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86394 <description>No effect.</description>
86399 <description>DMA channel is cleared.</description>
86406 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86414 <description>No effect.</description>
86419 <description>DMA channel is cleared.</description>
86426 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86434 <description>No effect.</description>
86439 <description>DMA channel is cleared.</description>
86446 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86454 <description>No effect.</description>
86459 <description>DMA channel is cleared.</description>
86466 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86474 <description>No effect.</description>
86479 <description>DMA channel is cleared.</description>
86486 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86494 <description>No effect.</description>
86499 <description>DMA channel is cleared.</description>
86506 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86514 <description>No effect.</description>
86519 <description>DMA channel is cleared.</description>
86526 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86534 <description>No effect.</description>
86539 <description>DMA channel is cleared.</description>
86546 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86554 <description>No effect.</description>
86559 <description>DMA channel is cleared.</description>
86566 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86574 <description>No effect.</description>
86579 <description>DMA channel is cleared.</description>
86586 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86594 <description>No effect.</description>
86599 <description>DMA channel is cleared.</description>
86606 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86614 <description>No effect.</description>
86619 <description>DMA channel is cleared.</description>
86626 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86634 <description>No effect.</description>
86639 <description>DMA channel is cleared.</description>
86646 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86654 <description>No effect.</description>
86659 <description>DMA channel is cleared.</description>
86666 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86674 <description>No effect.</description>
86679 <description>DMA channel is cleared.</description>
86686 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86694 <description>No effect.</description>
86699 <description>DMA channel is cleared.</description>
86706 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86714 <description>No effect.</description>
86719 <description>DMA channel is cleared.</description>
86726 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86734 <description>No effect.</description>
86739 <description>DMA channel is cleared.</description>
86746 …<description>Writing ones to this register clears the corresponding bits in ENABLESET1.</descripti…
86754 <description>No effect.</description>
86759 <description>DMA channel is cleared.</description>
86768 <description>Channel Active status for all DMA channels</description>
86777 <description>Active flag for DMA channel.</description>
86784 <description>DMA channel is not active.</description>
86789 <description>DMA channel is active.</description>
86796 <description>Active flag for DMA channel.</description>
86803 <description>DMA channel is not active.</description>
86808 <description>DMA channel is active.</description>
86815 <description>Active flag for DMA channel.</description>
86822 <description>DMA channel is not active.</description>
86827 <description>DMA channel is active.</description>
86834 <description>Active flag for DMA channel.</description>
86841 <description>DMA channel is not active.</description>
86846 <description>DMA channel is active.</description>
86853 <description>Active flag for DMA channel.</description>
86860 <description>DMA channel is not active.</description>
86865 <description>DMA channel is active.</description>
86872 <description>Active flag for DMA channel.</description>
86879 <description>DMA channel is not active.</description>
86884 <description>DMA channel is active.</description>
86891 <description>Active flag for DMA channel.</description>
86898 <description>DMA channel is not active.</description>
86903 <description>DMA channel is active.</description>
86910 <description>Active flag for DMA channel.</description>
86917 <description>DMA channel is not active.</description>
86922 <description>DMA channel is active.</description>
86929 <description>Active flag for DMA channel.</description>
86936 <description>DMA channel is not active.</description>
86941 <description>DMA channel is active.</description>
86948 <description>Active flag for DMA channel.</description>
86955 <description>DMA channel is not active.</description>
86960 <description>DMA channel is active.</description>
86967 <description>Active flag for DMA channel.</description>
86974 <description>DMA channel is not active.</description>
86979 <description>DMA channel is active.</description>
86986 <description>Active flag for DMA channel.</description>
86993 <description>DMA channel is not active.</description>
86998 <description>DMA channel is active.</description>
87005 <description>Active flag for DMA channel.</description>
87012 <description>DMA channel is not active.</description>
87017 <description>DMA channel is active.</description>
87024 <description>Active flag for DMA channel.</description>
87031 <description>DMA channel is not active.</description>
87036 <description>DMA channel is active.</description>
87043 <description>Active flag for DMA channel.</description>
87050 <description>DMA channel is not active.</description>
87055 <description>DMA channel is active.</description>
87062 <description>Active flag for DMA channel.</description>
87069 <description>DMA channel is not active.</description>
87074 <description>DMA channel is active.</description>
87081 <description>Active flag for DMA channel.</description>
87088 <description>DMA channel is not active.</description>
87093 <description>DMA channel is active.</description>
87100 <description>Active flag for DMA channel.</description>
87107 <description>DMA channel is not active.</description>
87112 <description>DMA channel is active.</description>
87119 <description>Active flag for DMA channel.</description>
87126 <description>DMA channel is not active.</description>
87131 <description>DMA channel is active.</description>
87138 <description>Active flag for DMA channel.</description>
87145 <description>DMA channel is not active.</description>
87150 <description>DMA channel is active.</description>
87157 <description>Active flag for DMA channel.</description>
87164 <description>DMA channel is not active.</description>
87169 <description>DMA channel is active.</description>
87176 <description>Active flag for DMA channel.</description>
87183 <description>DMA channel is not active.</description>
87188 <description>DMA channel is active.</description>
87195 <description>Active flag for DMA channel.</description>
87202 <description>DMA channel is not active.</description>
87207 <description>DMA channel is active.</description>
87214 <description>Active flag for DMA channel.</description>
87221 <description>DMA channel is not active.</description>
87226 <description>DMA channel is active.</description>
87233 <description>Active flag for DMA channel.</description>
87240 <description>DMA channel is not active.</description>
87245 <description>DMA channel is active.</description>
87252 <description>Active flag for DMA channel.</description>
87259 <description>DMA channel is not active.</description>
87264 <description>DMA channel is active.</description>
87271 <description>Active flag for DMA channel.</description>
87278 <description>DMA channel is not active.</description>
87283 <description>DMA channel is active.</description>
87290 <description>Active flag for DMA channel.</description>
87297 <description>DMA channel is not active.</description>
87302 <description>DMA channel is active.</description>
87309 <description>Active flag for DMA channel.</description>
87316 <description>DMA channel is not active.</description>
87321 <description>DMA channel is active.</description>
87328 <description>Active flag for DMA channel.</description>
87335 <description>DMA channel is not active.</description>
87340 <description>DMA channel is active.</description>
87347 <description>Active flag for DMA channel.</description>
87354 <description>DMA channel is not active.</description>
87359 <description>DMA channel is active.</description>
87366 <description>Active flag for DMA channel.</description>
87373 <description>DMA channel is not active.</description>
87378 <description>DMA channel is active.</description>
87387 <description>Channel Active status for all DMA channels</description>
87396 <description>Active flag for DMA channel.</description>
87403 <description>DMA channel is not active.</description>
87408 <description>DMA channel is active.</description>
87415 <description>Active flag for DMA channel.</description>
87422 <description>DMA channel is not active.</description>
87427 <description>DMA channel is active.</description>
87434 <description>Active flag for DMA channel.</description>
87441 <description>DMA channel is not active.</description>
87446 <description>DMA channel is active.</description>
87453 <description>Active flag for DMA channel.</description>
87460 <description>DMA channel is not active.</description>
87465 <description>DMA channel is active.</description>
87472 <description>Active flag for DMA channel.</description>
87479 <description>DMA channel is not active.</description>
87484 <description>DMA channel is active.</description>
87491 <description>Active flag for DMA channel.</description>
87498 <description>DMA channel is not active.</description>
87503 <description>DMA channel is active.</description>
87510 <description>Active flag for DMA channel.</description>
87517 <description>DMA channel is not active.</description>
87522 <description>DMA channel is active.</description>
87529 <description>Active flag for DMA channel.</description>
87536 <description>DMA channel is not active.</description>
87541 <description>DMA channel is active.</description>
87548 <description>Active flag for DMA channel.</description>
87555 <description>DMA channel is not active.</description>
87560 <description>DMA channel is active.</description>
87567 <description>Active flag for DMA channel.</description>
87574 <description>DMA channel is not active.</description>
87579 <description>DMA channel is active.</description>
87586 <description>Active flag for DMA channel.</description>
87593 <description>DMA channel is not active.</description>
87598 <description>DMA channel is active.</description>
87605 <description>Active flag for DMA channel.</description>
87612 <description>DMA channel is not active.</description>
87617 <description>DMA channel is active.</description>
87624 <description>Active flag for DMA channel.</description>
87631 <description>DMA channel is not active.</description>
87636 <description>DMA channel is active.</description>
87643 <description>Active flag for DMA channel.</description>
87650 <description>DMA channel is not active.</description>
87655 <description>DMA channel is active.</description>
87662 <description>Active flag for DMA channel.</description>
87669 <description>DMA channel is not active.</description>
87674 <description>DMA channel is active.</description>
87681 <description>Active flag for DMA channel.</description>
87688 <description>DMA channel is not active.</description>
87693 <description>DMA channel is active.</description>
87700 <description>Active flag for DMA channel.</description>
87707 <description>DMA channel is not active.</description>
87712 <description>DMA channel is active.</description>
87719 <description>Active flag for DMA channel.</description>
87726 <description>DMA channel is not active.</description>
87731 <description>DMA channel is active.</description>
87738 <description>Active flag for DMA channel.</description>
87745 <description>DMA channel is not active.</description>
87750 <description>DMA channel is active.</description>
87757 <description>Active flag for DMA channel.</description>
87764 <description>DMA channel is not active.</description>
87769 <description>DMA channel is active.</description>
87778 <description>Channel Busy status for all DMA channels</description>
87787 <description>Busy flag for DMA channel.</description>
87794 <description>DMA channel is not busy.</description>
87799 <description>DMA channel is busy.</description>
87806 <description>Busy flag for DMA channel.</description>
87813 <description>DMA channel is not busy.</description>
87818 <description>DMA channel is busy.</description>
87825 <description>Busy flag for DMA channel.</description>
87832 <description>DMA channel is not busy.</description>
87837 <description>DMA channel is busy.</description>
87844 <description>Busy flag for DMA channel.</description>
87851 <description>DMA channel is not busy.</description>
87856 <description>DMA channel is busy.</description>
87863 <description>Busy flag for DMA channel.</description>
87870 <description>DMA channel is not busy.</description>
87875 <description>DMA channel is busy.</description>
87882 <description>Busy flag for DMA channel.</description>
87889 <description>DMA channel is not busy.</description>
87894 <description>DMA channel is busy.</description>
87901 <description>Busy flag for DMA channel.</description>
87908 <description>DMA channel is not busy.</description>
87913 <description>DMA channel is busy.</description>
87920 <description>Busy flag for DMA channel.</description>
87927 <description>DMA channel is not busy.</description>
87932 <description>DMA channel is busy.</description>
87939 <description>Busy flag for DMA channel.</description>
87946 <description>DMA channel is not busy.</description>
87951 <description>DMA channel is busy.</description>
87958 <description>Busy flag for DMA channel.</description>
87965 <description>DMA channel is not busy.</description>
87970 <description>DMA channel is busy.</description>
87977 <description>Busy flag for DMA channel.</description>
87984 <description>DMA channel is not busy.</description>
87989 <description>DMA channel is busy.</description>
87996 <description>Busy flag for DMA channel.</description>
88003 <description>DMA channel is not busy.</description>
88008 <description>DMA channel is busy.</description>
88015 <description>Busy flag for DMA channel.</description>
88022 <description>DMA channel is not busy.</description>
88027 <description>DMA channel is busy.</description>
88034 <description>Busy flag for DMA channel.</description>
88041 <description>DMA channel is not busy.</description>
88046 <description>DMA channel is busy.</description>
88053 <description>Busy flag for DMA channel.</description>
88060 <description>DMA channel is not busy.</description>
88065 <description>DMA channel is busy.</description>
88072 <description>Busy flag for DMA channel.</description>
88079 <description>DMA channel is not busy.</description>
88084 <description>DMA channel is busy.</description>
88091 <description>Busy flag for DMA channel.</description>
88098 <description>DMA channel is not busy.</description>
88103 <description>DMA channel is busy.</description>
88110 <description>Busy flag for DMA channel.</description>
88117 <description>DMA channel is not busy.</description>
88122 <description>DMA channel is busy.</description>
88129 <description>Busy flag for DMA channel.</description>
88136 <description>DMA channel is not busy.</description>
88141 <description>DMA channel is busy.</description>
88148 <description>Busy flag for DMA channel.</description>
88155 <description>DMA channel is not busy.</description>
88160 <description>DMA channel is busy.</description>
88167 <description>Busy flag for DMA channel.</description>
88174 <description>DMA channel is not busy.</description>
88179 <description>DMA channel is busy.</description>
88186 <description>Busy flag for DMA channel.</description>
88193 <description>DMA channel is not busy.</description>
88198 <description>DMA channel is busy.</description>
88205 <description>Busy flag for DMA channel.</description>
88212 <description>DMA channel is not busy.</description>
88217 <description>DMA channel is busy.</description>
88224 <description>Busy flag for DMA channel.</description>
88231 <description>DMA channel is not busy.</description>
88236 <description>DMA channel is busy.</description>
88243 <description>Busy flag for DMA channel.</description>
88250 <description>DMA channel is not busy.</description>
88255 <description>DMA channel is busy.</description>
88262 <description>Busy flag for DMA channel.</description>
88269 <description>DMA channel is not busy.</description>
88274 <description>DMA channel is busy.</description>
88281 <description>Busy flag for DMA channel.</description>
88288 <description>DMA channel is not busy.</description>
88293 <description>DMA channel is busy.</description>
88300 <description>Busy flag for DMA channel.</description>
88307 <description>DMA channel is not busy.</description>
88312 <description>DMA channel is busy.</description>
88319 <description>Busy flag for DMA channel.</description>
88326 <description>DMA channel is not busy.</description>
88331 <description>DMA channel is busy.</description>
88338 <description>Busy flag for DMA channel.</description>
88345 <description>DMA channel is not busy.</description>
88350 <description>DMA channel is busy.</description>
88357 <description>Busy flag for DMA channel.</description>
88364 <description>DMA channel is not busy.</description>
88369 <description>DMA channel is busy.</description>
88376 <description>Busy flag for DMA channel.</description>
88383 <description>DMA channel is not busy.</description>
88388 <description>DMA channel is busy.</description>
88397 <description>Channel Busy status for all DMA channels</description>
88406 <description>Busy flag for DMA channel.</description>
88413 <description>DMA channel is not busy.</description>
88418 <description>DMA channel is busy.</description>
88425 <description>Busy flag for DMA channel.</description>
88432 <description>DMA channel is not busy.</description>
88437 <description>DMA channel is busy.</description>
88444 <description>Busy flag for DMA channel.</description>
88451 <description>DMA channel is not busy.</description>
88456 <description>DMA channel is busy.</description>
88463 <description>Busy flag for DMA channel.</description>
88470 <description>DMA channel is not busy.</description>
88475 <description>DMA channel is busy.</description>
88482 <description>Busy flag for DMA channel.</description>
88489 <description>DMA channel is not busy.</description>
88494 <description>DMA channel is busy.</description>
88501 <description>Busy flag for DMA channel.</description>
88508 <description>DMA channel is not busy.</description>
88513 <description>DMA channel is busy.</description>
88520 <description>Busy flag for DMA channel.</description>
88527 <description>DMA channel is not busy.</description>
88532 <description>DMA channel is busy.</description>
88539 <description>Busy flag for DMA channel.</description>
88546 <description>DMA channel is not busy.</description>
88551 <description>DMA channel is busy.</description>
88558 <description>Busy flag for DMA channel.</description>
88565 <description>DMA channel is not busy.</description>
88570 <description>DMA channel is busy.</description>
88577 <description>Busy flag for DMA channel.</description>
88584 <description>DMA channel is not busy.</description>
88589 <description>DMA channel is busy.</description>
88596 <description>Busy flag for DMA channel.</description>
88603 <description>DMA channel is not busy.</description>
88608 <description>DMA channel is busy.</description>
88615 <description>Busy flag for DMA channel.</description>
88622 <description>DMA channel is not busy.</description>
88627 <description>DMA channel is busy.</description>
88634 <description>Busy flag for DMA channel.</description>
88641 <description>DMA channel is not busy.</description>
88646 <description>DMA channel is busy.</description>
88653 <description>Busy flag for DMA channel.</description>
88660 <description>DMA channel is not busy.</description>
88665 <description>DMA channel is busy.</description>
88672 <description>Busy flag for DMA channel.</description>
88679 <description>DMA channel is not busy.</description>
88684 <description>DMA channel is busy.</description>
88691 <description>Busy flag for DMA channel.</description>
88698 <description>DMA channel is not busy.</description>
88703 <description>DMA channel is busy.</description>
88710 <description>Busy flag for DMA channel.</description>
88717 <description>DMA channel is not busy.</description>
88722 <description>DMA channel is busy.</description>
88729 <description>Busy flag for DMA channel.</description>
88736 <description>DMA channel is not busy.</description>
88741 <description>DMA channel is busy.</description>
88748 <description>Busy flag for DMA channel.</description>
88755 <description>DMA channel is not busy.</description>
88760 <description>DMA channel is busy.</description>
88767 <description>Busy flag for DMA channel.</description>
88774 <description>DMA channel is not busy.</description>
88779 <description>DMA channel is busy.</description>
88788 <description>Error Interrupt status for all DMA channels</description>
88797 <description>Error Interrupt flag for DMA channel.</description>
88804 <description>The Error Interrupt is not active for DMA channel.</description>
88809 <description>The Error Interrupt is pending for DMA channel.</description>
88816 <description>Error Interrupt flag for DMA channel.</description>
88823 <description>The Error Interrupt is not active for DMA channel.</description>
88828 <description>The Error Interrupt is pending for DMA channel.</description>
88835 <description>Error Interrupt flag for DMA channel.</description>
88842 <description>The Error Interrupt is not active for DMA channel.</description>
88847 <description>The Error Interrupt is pending for DMA channel.</description>
88854 <description>Error Interrupt flag for DMA channel.</description>
88861 <description>The Error Interrupt is not active for DMA channel.</description>
88866 <description>The Error Interrupt is pending for DMA channel.</description>
88873 <description>Error Interrupt flag for DMA channel.</description>
88880 <description>The Error Interrupt is not active for DMA channel.</description>
88885 <description>The Error Interrupt is pending for DMA channel.</description>
88892 <description>Error Interrupt flag for DMA channel.</description>
88899 <description>The Error Interrupt is not active for DMA channel.</description>
88904 <description>The Error Interrupt is pending for DMA channel.</description>
88911 <description>Error Interrupt flag for DMA channel.</description>
88918 <description>The Error Interrupt is not active for DMA channel.</description>
88923 <description>The Error Interrupt is pending for DMA channel.</description>
88930 <description>Error Interrupt flag for DMA channel.</description>
88937 <description>The Error Interrupt is not active for DMA channel.</description>
88942 <description>The Error Interrupt is pending for DMA channel.</description>
88949 <description>Error Interrupt flag for DMA channel.</description>
88956 <description>The Error Interrupt is not active for DMA channel.</description>
88961 <description>The Error Interrupt is pending for DMA channel.</description>
88968 <description>Error Interrupt flag for DMA channel.</description>
88975 <description>The Error Interrupt is not active for DMA channel.</description>
88980 <description>The Error Interrupt is pending for DMA channel.</description>
88987 <description>Error Interrupt flag for DMA channel.</description>
88994 <description>The Error Interrupt is not active for DMA channel.</description>
88999 <description>The Error Interrupt is pending for DMA channel.</description>
89006 <description>Error Interrupt flag for DMA channel.</description>
89013 <description>The Error Interrupt is not active for DMA channel.</description>
89018 <description>The Error Interrupt is pending for DMA channel.</description>
89025 <description>Error Interrupt flag for DMA channel.</description>
89032 <description>The Error Interrupt is not active for DMA channel.</description>
89037 <description>The Error Interrupt is pending for DMA channel.</description>
89044 <description>Error Interrupt flag for DMA channel.</description>
89051 <description>The Error Interrupt is not active for DMA channel.</description>
89056 <description>The Error Interrupt is pending for DMA channel.</description>
89063 <description>Error Interrupt flag for DMA channel.</description>
89070 <description>The Error Interrupt is not active for DMA channel.</description>
89075 <description>The Error Interrupt is pending for DMA channel.</description>
89082 <description>Error Interrupt flag for DMA channel.</description>
89089 <description>The Error Interrupt is not active for DMA channel.</description>
89094 <description>The Error Interrupt is pending for DMA channel.</description>
89101 <description>Error Interrupt flag for DMA channel.</description>
89108 <description>The Error Interrupt is not active for DMA channel.</description>
89113 <description>The Error Interrupt is pending for DMA channel.</description>
89120 <description>Error Interrupt flag for DMA channel.</description>
89127 <description>The Error Interrupt is not active for DMA channel.</description>
89132 <description>The Error Interrupt is pending for DMA channel.</description>
89139 <description>Error Interrupt flag for DMA channel.</description>
89146 <description>The Error Interrupt is not active for DMA channel.</description>
89151 <description>The Error Interrupt is pending for DMA channel.</description>
89158 <description>Error Interrupt flag for DMA channel.</description>
89165 <description>The Error Interrupt is not active for DMA channel.</description>
89170 <description>The Error Interrupt is pending for DMA channel.</description>
89177 <description>Error Interrupt flag for DMA channel.</description>
89184 <description>The Error Interrupt is not active for DMA channel.</description>
89189 <description>The Error Interrupt is pending for DMA channel.</description>
89196 <description>Error Interrupt flag for DMA channel.</description>
89203 <description>The Error Interrupt is not active for DMA channel.</description>
89208 <description>The Error Interrupt is pending for DMA channel.</description>
89215 <description>Error Interrupt flag for DMA channel.</description>
89222 <description>The Error Interrupt is not active for DMA channel.</description>
89227 <description>The Error Interrupt is pending for DMA channel.</description>
89234 <description>Error Interrupt flag for DMA channel.</description>
89241 <description>The Error Interrupt is not active for DMA channel.</description>
89246 <description>The Error Interrupt is pending for DMA channel.</description>
89253 <description>Error Interrupt flag for DMA channel.</description>
89260 <description>The Error Interrupt is not active for DMA channel.</description>
89265 <description>The Error Interrupt is pending for DMA channel.</description>
89272 <description>Error Interrupt flag for DMA channel.</description>
89279 <description>The Error Interrupt is not active for DMA channel.</description>
89284 <description>The Error Interrupt is pending for DMA channel.</description>
89291 <description>Error Interrupt flag for DMA channel.</description>
89298 <description>The Error Interrupt is not active for DMA channel.</description>
89303 <description>The Error Interrupt is pending for DMA channel.</description>
89310 <description>Error Interrupt flag for DMA channel.</description>
89317 <description>The Error Interrupt is not active for DMA channel.</description>
89322 <description>The Error Interrupt is pending for DMA channel.</description>
89329 <description>Error Interrupt flag for DMA channel.</description>
89336 <description>The Error Interrupt is not active for DMA channel.</description>
89341 <description>The Error Interrupt is pending for DMA channel.</description>
89348 <description>Error Interrupt flag for DMA channel.</description>
89355 <description>The Error Interrupt is not active for DMA channel.</description>
89360 <description>The Error Interrupt is pending for DMA channel.</description>
89367 <description>Error Interrupt flag for DMA channel.</description>
89374 <description>The Error Interrupt is not active for DMA channel.</description>
89379 <description>The Error Interrupt is pending for DMA channel.</description>
89386 <description>Error Interrupt flag for DMA channel.</description>
89393 <description>The Error Interrupt is not active for DMA channel.</description>
89398 <description>The Error Interrupt is pending for DMA channel.</description>
89407 <description>Error Interrupt status for all DMA channels</description>
89416 <description>Error Interrupt flag for DMA channel.</description>
89423 <description>The Error Interrupt is not active for DMA channel.</description>
89428 <description>The Error Interrupt is pending for DMA channel.</description>
89435 <description>Error Interrupt flag for DMA channel.</description>
89442 <description>The Error Interrupt is not active for DMA channel.</description>
89447 <description>The Error Interrupt is pending for DMA channel.</description>
89454 <description>Error Interrupt flag for DMA channel.</description>
89461 <description>The Error Interrupt is not active for DMA channel.</description>
89466 <description>The Error Interrupt is pending for DMA channel.</description>
89473 <description>Error Interrupt flag for DMA channel.</description>
89480 <description>The Error Interrupt is not active for DMA channel.</description>
89485 <description>The Error Interrupt is pending for DMA channel.</description>
89492 <description>Error Interrupt flag for DMA channel.</description>
89499 <description>The Error Interrupt is not active for DMA channel.</description>
89504 <description>The Error Interrupt is pending for DMA channel.</description>
89511 <description>Error Interrupt flag for DMA channel.</description>
89518 <description>The Error Interrupt is not active for DMA channel.</description>
89523 <description>The Error Interrupt is pending for DMA channel.</description>
89530 <description>Error Interrupt flag for DMA channel.</description>
89537 <description>The Error Interrupt is not active for DMA channel.</description>
89542 <description>The Error Interrupt is pending for DMA channel.</description>
89549 <description>Error Interrupt flag for DMA channel.</description>
89556 <description>The Error Interrupt is not active for DMA channel.</description>
89561 <description>The Error Interrupt is pending for DMA channel.</description>
89568 <description>Error Interrupt flag for DMA channel.</description>
89575 <description>The Error Interrupt is not active for DMA channel.</description>
89580 <description>The Error Interrupt is pending for DMA channel.</description>
89587 <description>Error Interrupt flag for DMA channel.</description>
89594 <description>The Error Interrupt is not active for DMA channel.</description>
89599 <description>The Error Interrupt is pending for DMA channel.</description>
89606 <description>Error Interrupt flag for DMA channel.</description>
89613 <description>The Error Interrupt is not active for DMA channel.</description>
89618 <description>The Error Interrupt is pending for DMA channel.</description>
89625 <description>Error Interrupt flag for DMA channel.</description>
89632 <description>The Error Interrupt is not active for DMA channel.</description>
89637 <description>The Error Interrupt is pending for DMA channel.</description>
89644 <description>Error Interrupt flag for DMA channel.</description>
89651 <description>The Error Interrupt is not active for DMA channel.</description>
89656 <description>The Error Interrupt is pending for DMA channel.</description>
89663 <description>Error Interrupt flag for DMA channel.</description>
89670 <description>The Error Interrupt is not active for DMA channel.</description>
89675 <description>The Error Interrupt is pending for DMA channel.</description>
89682 <description>Error Interrupt flag for DMA channel.</description>
89689 <description>The Error Interrupt is not active for DMA channel.</description>
89694 <description>The Error Interrupt is pending for DMA channel.</description>
89701 <description>Error Interrupt flag for DMA channel.</description>
89708 <description>The Error Interrupt is not active for DMA channel.</description>
89713 <description>The Error Interrupt is pending for DMA channel.</description>
89720 <description>Error Interrupt flag for DMA channel.</description>
89727 <description>The Error Interrupt is not active for DMA channel.</description>
89732 <description>The Error Interrupt is pending for DMA channel.</description>
89739 <description>Error Interrupt flag for DMA channel.</description>
89746 <description>The Error Interrupt is not active for DMA channel.</description>
89751 <description>The Error Interrupt is pending for DMA channel.</description>
89758 <description>Error Interrupt flag for DMA channel.</description>
89765 <description>The Error Interrupt is not active for DMA channel.</description>
89770 <description>The Error Interrupt is pending for DMA channel.</description>
89777 <description>Error Interrupt flag for DMA channel.</description>
89784 <description>The Error Interrupt is not active for DMA channel.</description>
89789 <description>The Error Interrupt is pending for DMA channel.</description>
89798 <description>Interrupt Enable read and Set for all DMA channels</description>
89807 <description>Interrupt Enable read and set for DMA channel.</description>
89814 <description>The Interrupt for DMA channel is disabled.</description>
89819 <description>The Interrupt for DMA channel is enabled.</description>
89826 <description>Interrupt Enable read and set for DMA channel.</description>
89833 <description>The Interrupt for DMA channel is disabled.</description>
89838 <description>The Interrupt for DMA channel is enabled.</description>
89845 <description>Interrupt Enable read and set for DMA channel.</description>
89852 <description>The Interrupt for DMA channel is disabled.</description>
89857 <description>The Interrupt for DMA channel is enabled.</description>
89864 <description>Interrupt Enable read and set for DMA channel.</description>
89871 <description>The Interrupt for DMA channel is disabled.</description>
89876 <description>The Interrupt for DMA channel is enabled.</description>
89883 <description>Interrupt Enable read and set for DMA channel.</description>
89890 <description>The Interrupt for DMA channel is disabled.</description>
89895 <description>The Interrupt for DMA channel is enabled.</description>
89902 <description>Interrupt Enable read and set for DMA channel.</description>
89909 <description>The Interrupt for DMA channel is disabled.</description>
89914 <description>The Interrupt for DMA channel is enabled.</description>
89921 <description>Interrupt Enable read and set for DMA channel.</description>
89928 <description>The Interrupt for DMA channel is disabled.</description>
89933 <description>The Interrupt for DMA channel is enabled.</description>
89940 <description>Interrupt Enable read and set for DMA channel.</description>
89947 <description>The Interrupt for DMA channel is disabled.</description>
89952 <description>The Interrupt for DMA channel is enabled.</description>
89959 <description>Interrupt Enable read and set for DMA channel.</description>
89966 <description>The Interrupt for DMA channel is disabled.</description>
89971 <description>The Interrupt for DMA channel is enabled.</description>
89978 <description>Interrupt Enable read and set for DMA channel.</description>
89985 <description>The Interrupt for DMA channel is disabled.</description>
89990 <description>The Interrupt for DMA channel is enabled.</description>
89997 <description>Interrupt Enable read and set for DMA channel.</description>
90004 <description>The Interrupt for DMA channel is disabled.</description>
90009 <description>The Interrupt for DMA channel is enabled.</description>
90016 <description>Interrupt Enable read and set for DMA channel.</description>
90023 <description>The Interrupt for DMA channel is disabled.</description>
90028 <description>The Interrupt for DMA channel is enabled.</description>
90035 <description>Interrupt Enable read and set for DMA channel.</description>
90042 <description>The Interrupt for DMA channel is disabled.</description>
90047 <description>The Interrupt for DMA channel is enabled.</description>
90054 <description>Interrupt Enable read and set for DMA channel.</description>
90061 <description>The Interrupt for DMA channel is disabled.</description>
90066 <description>The Interrupt for DMA channel is enabled.</description>
90073 <description>Interrupt Enable read and set for DMA channel.</description>
90080 <description>The Interrupt for DMA channel is disabled.</description>
90085 <description>The Interrupt for DMA channel is enabled.</description>
90092 <description>Interrupt Enable read and set for DMA channel.</description>
90099 <description>The Interrupt for DMA channel is disabled.</description>
90104 <description>The Interrupt for DMA channel is enabled.</description>
90111 <description>Interrupt Enable read and set for DMA channel.</description>
90118 <description>The Interrupt for DMA channel is disabled.</description>
90123 <description>The Interrupt for DMA channel is enabled.</description>
90130 <description>Interrupt Enable read and set for DMA channel.</description>
90137 <description>The Interrupt for DMA channel is disabled.</description>
90142 <description>The Interrupt for DMA channel is enabled.</description>
90149 <description>Interrupt Enable read and set for DMA channel.</description>
90156 <description>The Interrupt for DMA channel is disabled.</description>
90161 <description>The Interrupt for DMA channel is enabled.</description>
90168 <description>Interrupt Enable read and set for DMA channel.</description>
90175 <description>The Interrupt for DMA channel is disabled.</description>
90180 <description>The Interrupt for DMA channel is enabled.</description>
90187 <description>Interrupt Enable read and set for DMA channel.</description>
90194 <description>The Interrupt for DMA channel is disabled.</description>
90199 <description>The Interrupt for DMA channel is enabled.</description>
90206 <description>Interrupt Enable read and set for DMA channel.</description>
90213 <description>The Interrupt for DMA channel is disabled.</description>
90218 <description>The Interrupt for DMA channel is enabled.</description>
90225 <description>Interrupt Enable read and set for DMA channel.</description>
90232 <description>The Interrupt for DMA channel is disabled.</description>
90237 <description>The Interrupt for DMA channel is enabled.</description>
90244 <description>Interrupt Enable read and set for DMA channel.</description>
90251 <description>The Interrupt for DMA channel is disabled.</description>
90256 <description>The Interrupt for DMA channel is enabled.</description>
90263 <description>Interrupt Enable read and set for DMA channel.</description>
90270 <description>The Interrupt for DMA channel is disabled.</description>
90275 <description>The Interrupt for DMA channel is enabled.</description>
90282 <description>Interrupt Enable read and set for DMA channel.</description>
90289 <description>The Interrupt for DMA channel is disabled.</description>
90294 <description>The Interrupt for DMA channel is enabled.</description>
90301 <description>Interrupt Enable read and set for DMA channel.</description>
90308 <description>The Interrupt for DMA channel is disabled.</description>
90313 <description>The Interrupt for DMA channel is enabled.</description>
90320 <description>Interrupt Enable read and set for DMA channel.</description>
90327 <description>The Interrupt for DMA channel is disabled.</description>
90332 <description>The Interrupt for DMA channel is enabled.</description>
90339 <description>Interrupt Enable read and set for DMA channel.</description>
90346 <description>The Interrupt for DMA channel is disabled.</description>
90351 <description>The Interrupt for DMA channel is enabled.</description>
90358 <description>Interrupt Enable read and set for DMA channel.</description>
90365 <description>The Interrupt for DMA channel is disabled.</description>
90370 <description>The Interrupt for DMA channel is enabled.</description>
90377 <description>Interrupt Enable read and set for DMA channel.</description>
90384 <description>The Interrupt for DMA channel is disabled.</description>
90389 <description>The Interrupt for DMA channel is enabled.</description>
90396 <description>Interrupt Enable read and set for DMA channel.</description>
90403 <description>The Interrupt for DMA channel is disabled.</description>
90408 <description>The Interrupt for DMA channel is enabled.</description>
90417 <description>Interrupt Enable read and Set for all DMA channels</description>
90426 <description>Interrupt Enable read and set for DMA channel.</description>
90433 <description>The Interrupt for DMA channel is disabled.</description>
90438 <description>The Interrupt for DMA channel is enabled.</description>
90445 <description>Interrupt Enable read and set for DMA channel.</description>
90452 <description>The Interrupt for DMA channel is disabled.</description>
90457 <description>The Interrupt for DMA channel is enabled.</description>
90464 <description>Interrupt Enable read and set for DMA channel.</description>
90471 <description>The Interrupt for DMA channel is disabled.</description>
90476 <description>The Interrupt for DMA channel is enabled.</description>
90483 <description>Interrupt Enable read and set for DMA channel.</description>
90490 <description>The Interrupt for DMA channel is disabled.</description>
90495 <description>The Interrupt for DMA channel is enabled.</description>
90502 <description>Interrupt Enable read and set for DMA channel.</description>
90509 <description>The Interrupt for DMA channel is disabled.</description>
90514 <description>The Interrupt for DMA channel is enabled.</description>
90521 <description>Interrupt Enable read and set for DMA channel.</description>
90528 <description>The Interrupt for DMA channel is disabled.</description>
90533 <description>The Interrupt for DMA channel is enabled.</description>
90540 <description>Interrupt Enable read and set for DMA channel.</description>
90547 <description>The Interrupt for DMA channel is disabled.</description>
90552 <description>The Interrupt for DMA channel is enabled.</description>
90559 <description>Interrupt Enable read and set for DMA channel.</description>
90566 <description>The Interrupt for DMA channel is disabled.</description>
90571 <description>The Interrupt for DMA channel is enabled.</description>
90578 <description>Interrupt Enable read and set for DMA channel.</description>
90585 <description>The Interrupt for DMA channel is disabled.</description>
90590 <description>The Interrupt for DMA channel is enabled.</description>
90597 <description>Interrupt Enable read and set for DMA channel.</description>
90604 <description>The Interrupt for DMA channel is disabled.</description>
90609 <description>The Interrupt for DMA channel is enabled.</description>
90616 <description>Interrupt Enable read and set for DMA channel.</description>
90623 <description>The Interrupt for DMA channel is disabled.</description>
90628 <description>The Interrupt for DMA channel is enabled.</description>
90635 <description>Interrupt Enable read and set for DMA channel.</description>
90642 <description>The Interrupt for DMA channel is disabled.</description>
90647 <description>The Interrupt for DMA channel is enabled.</description>
90654 <description>Interrupt Enable read and set for DMA channel.</description>
90661 <description>The Interrupt for DMA channel is disabled.</description>
90666 <description>The Interrupt for DMA channel is enabled.</description>
90673 <description>Interrupt Enable read and set for DMA channel.</description>
90680 <description>The Interrupt for DMA channel is disabled.</description>
90685 <description>The Interrupt for DMA channel is enabled.</description>
90692 <description>Interrupt Enable read and set for DMA channel.</description>
90699 <description>The Interrupt for DMA channel is disabled.</description>
90704 <description>The Interrupt for DMA channel is enabled.</description>
90711 <description>Interrupt Enable read and set for DMA channel.</description>
90718 <description>The Interrupt for DMA channel is disabled.</description>
90723 <description>The Interrupt for DMA channel is enabled.</description>
90730 <description>Interrupt Enable read and set for DMA channel.</description>
90737 <description>The Interrupt for DMA channel is disabled.</description>
90742 <description>The Interrupt for DMA channel is enabled.</description>
90749 <description>Interrupt Enable read and set for DMA channel.</description>
90756 <description>The Interrupt for DMA channel is disabled.</description>
90761 <description>The Interrupt for DMA channel is enabled.</description>
90768 <description>Interrupt Enable read and set for DMA channel.</description>
90775 <description>The Interrupt for DMA channel is disabled.</description>
90780 <description>The Interrupt for DMA channel is enabled.</description>
90787 <description>Interrupt Enable read and set for DMA channel.</description>
90794 <description>The Interrupt for DMA channel is disabled.</description>
90799 <description>The Interrupt for DMA channel is enabled.</description>
90808 <description>Interrupt Enable Clear for all DMA channels</description>
90817 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90824 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90831 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90838 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90845 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90852 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90859 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90866 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90873 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90880 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90887 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90894 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90901 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90908 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90915 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90922 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90929 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90936 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90943 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90950 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90957 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90964 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90971 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90978 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90985 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90992 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
90999 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91006 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91013 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91020 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91027 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91034 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
91043 <description>Interrupt Enable Clear for all DMA channels</description>
91052 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91059 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91066 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91073 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91080 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91087 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91094 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91101 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91108 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91115 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91122 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91129 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91136 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91143 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91150 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91157 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91164 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91171 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91178 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91185 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet1.</descrip…
91194 <description>Interrupt A status for all DMA channels</description>
91203 <description>Interrupt A status for DMA channel.</description>
91210 <description>The DMA channel interrupt A is not active.</description>
91215 <description>The DMA channel interrupt A is active.</description>
91222 <description>Interrupt A status for DMA channel.</description>
91229 <description>The DMA channel interrupt A is not active.</description>
91234 <description>The DMA channel interrupt A is active.</description>
91241 <description>Interrupt A status for DMA channel.</description>
91248 <description>The DMA channel interrupt A is not active.</description>
91253 <description>The DMA channel interrupt A is active.</description>
91260 <description>Interrupt A status for DMA channel.</description>
91267 <description>The DMA channel interrupt A is not active.</description>
91272 <description>The DMA channel interrupt A is active.</description>
91279 <description>Interrupt A status for DMA channel.</description>
91286 <description>The DMA channel interrupt A is not active.</description>
91291 <description>The DMA channel interrupt A is active.</description>
91298 <description>Interrupt A status for DMA channel.</description>
91305 <description>The DMA channel interrupt A is not active.</description>
91310 <description>The DMA channel interrupt A is active.</description>
91317 <description>Interrupt A status for DMA channel.</description>
91324 <description>The DMA channel interrupt A is not active.</description>
91329 <description>The DMA channel interrupt A is active.</description>
91336 <description>Interrupt A status for DMA channel.</description>
91343 <description>The DMA channel interrupt A is not active.</description>
91348 <description>The DMA channel interrupt A is active.</description>
91355 <description>Interrupt A status for DMA channel.</description>
91362 <description>The DMA channel interrupt A is not active.</description>
91367 <description>The DMA channel interrupt A is active.</description>
91374 <description>Interrupt A status for DMA channel.</description>
91381 <description>The DMA channel interrupt A is not active.</description>
91386 <description>The DMA channel interrupt A is active.</description>
91393 <description>Interrupt A status for DMA channel.</description>
91400 <description>The DMA channel interrupt A is not active.</description>
91405 <description>The DMA channel interrupt A is active.</description>
91412 <description>Interrupt A status for DMA channel.</description>
91419 <description>The DMA channel interrupt A is not active.</description>
91424 <description>The DMA channel interrupt A is active.</description>
91431 <description>Interrupt A status for DMA channel.</description>
91438 <description>The DMA channel interrupt A is not active.</description>
91443 <description>The DMA channel interrupt A is active.</description>
91450 <description>Interrupt A status for DMA channel.</description>
91457 <description>The DMA channel interrupt A is not active.</description>
91462 <description>The DMA channel interrupt A is active.</description>
91469 <description>Interrupt A status for DMA channel.</description>
91476 <description>The DMA channel interrupt A is not active.</description>
91481 <description>The DMA channel interrupt A is active.</description>
91488 <description>Interrupt A status for DMA channel.</description>
91495 <description>The DMA channel interrupt A is not active.</description>
91500 <description>The DMA channel interrupt A is active.</description>
91507 <description>Interrupt A status for DMA channel.</description>
91514 <description>The DMA channel interrupt A is not active.</description>
91519 <description>The DMA channel interrupt A is active.</description>
91526 <description>Interrupt A status for DMA channel.</description>
91533 <description>The DMA channel interrupt A is not active.</description>
91538 <description>The DMA channel interrupt A is active.</description>
91545 <description>Interrupt A status for DMA channel.</description>
91552 <description>The DMA channel interrupt A is not active.</description>
91557 <description>The DMA channel interrupt A is active.</description>
91564 <description>Interrupt A status for DMA channel.</description>
91571 <description>The DMA channel interrupt A is not active.</description>
91576 <description>The DMA channel interrupt A is active.</description>
91583 <description>Interrupt A status for DMA channel.</description>
91590 <description>The DMA channel interrupt A is not active.</description>
91595 <description>The DMA channel interrupt A is active.</description>
91602 <description>Interrupt A status for DMA channel.</description>
91609 <description>The DMA channel interrupt A is not active.</description>
91614 <description>The DMA channel interrupt A is active.</description>
91621 <description>Interrupt A status for DMA channel.</description>
91628 <description>The DMA channel interrupt A is not active.</description>
91633 <description>The DMA channel interrupt A is active.</description>
91640 <description>Interrupt A status for DMA channel.</description>
91647 <description>The DMA channel interrupt A is not active.</description>
91652 <description>The DMA channel interrupt A is active.</description>
91659 <description>Interrupt A status for DMA channel.</description>
91666 <description>The DMA channel interrupt A is not active.</description>
91671 <description>The DMA channel interrupt A is active.</description>
91678 <description>Interrupt A status for DMA channel.</description>
91685 <description>The DMA channel interrupt A is not active.</description>
91690 <description>The DMA channel interrupt A is active.</description>
91697 <description>Interrupt A status for DMA channel.</description>
91704 <description>The DMA channel interrupt A is not active.</description>
91709 <description>The DMA channel interrupt A is active.</description>
91716 <description>Interrupt A status for DMA channel.</description>
91723 <description>The DMA channel interrupt A is not active.</description>
91728 <description>The DMA channel interrupt A is active.</description>
91735 <description>Interrupt A status for DMA channel.</description>
91742 <description>The DMA channel interrupt A is not active.</description>
91747 <description>The DMA channel interrupt A is active.</description>
91754 <description>Interrupt A status for DMA channel.</description>
91761 <description>The DMA channel interrupt A is not active.</description>
91766 <description>The DMA channel interrupt A is active.</description>
91773 <description>Interrupt A status for DMA channel.</description>
91780 <description>The DMA channel interrupt A is not active.</description>
91785 <description>The DMA channel interrupt A is active.</description>
91792 <description>Interrupt A status for DMA channel.</description>
91799 <description>The DMA channel interrupt A is not active.</description>
91804 <description>The DMA channel interrupt A is active.</description>
91813 <description>Interrupt A status for all DMA channels</description>
91822 <description>Interrupt A status for DMA channel.</description>
91829 <description>The DMA channel interrupt A is not active.</description>
91834 <description>The DMA channel interrupt A is active.</description>
91841 <description>Interrupt A status for DMA channel.</description>
91848 <description>The DMA channel interrupt A is not active.</description>
91853 <description>The DMA channel interrupt A is active.</description>
91860 <description>Interrupt A status for DMA channel.</description>
91867 <description>The DMA channel interrupt A is not active.</description>
91872 <description>The DMA channel interrupt A is active.</description>
91879 <description>Interrupt A status for DMA channel.</description>
91886 <description>The DMA channel interrupt A is not active.</description>
91891 <description>The DMA channel interrupt A is active.</description>
91898 <description>Interrupt A status for DMA channel.</description>
91905 <description>The DMA channel interrupt A is not active.</description>
91910 <description>The DMA channel interrupt A is active.</description>
91917 <description>Interrupt A status for DMA channel.</description>
91924 <description>The DMA channel interrupt A is not active.</description>
91929 <description>The DMA channel interrupt A is active.</description>
91936 <description>Interrupt A status for DMA channel.</description>
91943 <description>The DMA channel interrupt A is not active.</description>
91948 <description>The DMA channel interrupt A is active.</description>
91955 <description>Interrupt A status for DMA channel.</description>
91962 <description>The DMA channel interrupt A is not active.</description>
91967 <description>The DMA channel interrupt A is active.</description>
91974 <description>Interrupt A status for DMA channel.</description>
91981 <description>The DMA channel interrupt A is not active.</description>
91986 <description>The DMA channel interrupt A is active.</description>
91993 <description>Interrupt A status for DMA channel.</description>
92000 <description>The DMA channel interrupt A is not active.</description>
92005 <description>The DMA channel interrupt A is active.</description>
92012 <description>Interrupt A status for DMA channel.</description>
92019 <description>The DMA channel interrupt A is not active.</description>
92024 <description>The DMA channel interrupt A is active.</description>
92031 <description>Interrupt A status for DMA channel.</description>
92038 <description>The DMA channel interrupt A is not active.</description>
92043 <description>The DMA channel interrupt A is active.</description>
92050 <description>Interrupt A status for DMA channel.</description>
92057 <description>The DMA channel interrupt A is not active.</description>
92062 <description>The DMA channel interrupt A is active.</description>
92069 <description>Interrupt A status for DMA channel.</description>
92076 <description>The DMA channel interrupt A is not active.</description>
92081 <description>The DMA channel interrupt A is active.</description>
92088 <description>Interrupt A status for DMA channel.</description>
92095 <description>The DMA channel interrupt A is not active.</description>
92100 <description>The DMA channel interrupt A is active.</description>
92107 <description>Interrupt A status for DMA channel.</description>
92114 <description>The DMA channel interrupt A is not active.</description>
92119 <description>The DMA channel interrupt A is active.</description>
92126 <description>Interrupt A status for DMA channel.</description>
92133 <description>The DMA channel interrupt A is not active.</description>
92138 <description>The DMA channel interrupt A is active.</description>
92145 <description>Interrupt A status for DMA channel.</description>
92152 <description>The DMA channel interrupt A is not active.</description>
92157 <description>The DMA channel interrupt A is active.</description>
92164 <description>Interrupt A status for DMA channel.</description>
92171 <description>The DMA channel interrupt A is not active.</description>
92176 <description>The DMA channel interrupt A is active.</description>
92183 <description>Interrupt A status for DMA channel.</description>
92190 <description>The DMA channel interrupt A is not active.</description>
92195 <description>The DMA channel interrupt A is active.</description>
92204 <description>Interrupt B status for all DMA channels</description>
92213 <description>Interrupt B status for DMA channel.</description>
92220 <description>The DMA channel interrupt B is not active.</description>
92225 <description>The DMA channel interrupt B is active.</description>
92232 <description>Interrupt B status for DMA channel.</description>
92239 <description>The DMA channel interrupt B is not active.</description>
92244 <description>The DMA channel interrupt B is active.</description>
92251 <description>Interrupt B status for DMA channel.</description>
92258 <description>The DMA channel interrupt B is not active.</description>
92263 <description>The DMA channel interrupt B is active.</description>
92270 <description>Interrupt B status for DMA channel.</description>
92277 <description>The DMA channel interrupt B is not active.</description>
92282 <description>The DMA channel interrupt B is active.</description>
92289 <description>Interrupt B status for DMA channel.</description>
92296 <description>The DMA channel interrupt B is not active.</description>
92301 <description>The DMA channel interrupt B is active.</description>
92308 <description>Interrupt B status for DMA channel.</description>
92315 <description>The DMA channel interrupt B is not active.</description>
92320 <description>The DMA channel interrupt B is active.</description>
92327 <description>Interrupt B status for DMA channel.</description>
92334 <description>The DMA channel interrupt B is not active.</description>
92339 <description>The DMA channel interrupt B is active.</description>
92346 <description>Interrupt B status for DMA channel.</description>
92353 <description>The DMA channel interrupt B is not active.</description>
92358 <description>The DMA channel interrupt B is active.</description>
92365 <description>Interrupt B status for DMA channel.</description>
92372 <description>The DMA channel interrupt B is not active.</description>
92377 <description>The DMA channel interrupt B is active.</description>
92384 <description>Interrupt B status for DMA channel.</description>
92391 <description>The DMA channel interrupt B is not active.</description>
92396 <description>The DMA channel interrupt B is active.</description>
92403 <description>Interrupt B status for DMA channel.</description>
92410 <description>The DMA channel interrupt B is not active.</description>
92415 <description>The DMA channel interrupt B is active.</description>
92422 <description>Interrupt B status for DMA channel.</description>
92429 <description>The DMA channel interrupt B is not active.</description>
92434 <description>The DMA channel interrupt B is active.</description>
92441 <description>Interrupt B status for DMA channel.</description>
92448 <description>The DMA channel interrupt B is not active.</description>
92453 <description>The DMA channel interrupt B is active.</description>
92460 <description>Interrupt B status for DMA channel.</description>
92467 <description>The DMA channel interrupt B is not active.</description>
92472 <description>The DMA channel interrupt B is active.</description>
92479 <description>Interrupt B status for DMA channel.</description>
92486 <description>The DMA channel interrupt B is not active.</description>
92491 <description>The DMA channel interrupt B is active.</description>
92498 <description>Interrupt B status for DMA channel.</description>
92505 <description>The DMA channel interrupt B is not active.</description>
92510 <description>The DMA channel interrupt B is active.</description>
92517 <description>Interrupt B status for DMA channel.</description>
92524 <description>The DMA channel interrupt B is not active.</description>
92529 <description>The DMA channel interrupt B is active.</description>
92536 <description>Interrupt B status for DMA channel.</description>
92543 <description>The DMA channel interrupt B is not active.</description>
92548 <description>The DMA channel interrupt B is active.</description>
92555 <description>Interrupt B status for DMA channel.</description>
92562 <description>The DMA channel interrupt B is not active.</description>
92567 <description>The DMA channel interrupt B is active.</description>
92574 <description>Interrupt B status for DMA channel.</description>
92581 <description>The DMA channel interrupt B is not active.</description>
92586 <description>The DMA channel interrupt B is active.</description>
92593 <description>Interrupt B status for DMA channel.</description>
92600 <description>The DMA channel interrupt B is not active.</description>
92605 <description>The DMA channel interrupt B is active.</description>
92612 <description>Interrupt B status for DMA channel.</description>
92619 <description>The DMA channel interrupt B is not active.</description>
92624 <description>The DMA channel interrupt B is active.</description>
92631 <description>Interrupt B status for DMA channel.</description>
92638 <description>The DMA channel interrupt B is not active.</description>
92643 <description>The DMA channel interrupt B is active.</description>
92650 <description>Interrupt B status for DMA channel.</description>
92657 <description>The DMA channel interrupt B is not active.</description>
92662 <description>The DMA channel interrupt B is active.</description>
92669 <description>Interrupt B status for DMA channel.</description>
92676 <description>The DMA channel interrupt B is not active.</description>
92681 <description>The DMA channel interrupt B is active.</description>
92688 <description>Interrupt B status for DMA channel.</description>
92695 <description>The DMA channel interrupt B is not active.</description>
92700 <description>The DMA channel interrupt B is active.</description>
92707 <description>Interrupt B status for DMA channel.</description>
92714 <description>The DMA channel interrupt B is not active.</description>
92719 <description>The DMA channel interrupt B is active.</description>
92726 <description>Interrupt B status for DMA channel.</description>
92733 <description>The DMA channel interrupt B is not active.</description>
92738 <description>The DMA channel interrupt B is active.</description>
92745 <description>Interrupt B status for DMA channel.</description>
92752 <description>The DMA channel interrupt B is not active.</description>
92757 <description>The DMA channel interrupt B is active.</description>
92764 <description>Interrupt B status for DMA channel.</description>
92771 <description>The DMA channel interrupt B is not active.</description>
92776 <description>The DMA channel interrupt B is active.</description>
92783 <description>Interrupt B status for DMA channel.</description>
92790 <description>The DMA channel interrupt B is not active.</description>
92795 <description>The DMA channel interrupt B is active.</description>
92802 <description>Interrupt B status for DMA channel.</description>
92809 <description>The DMA channel interrupt B is not active.</description>
92814 <description>The DMA channel interrupt B is active.</description>
92823 <description>Interrupt B status for all DMA channels</description>
92832 <description>Interrupt B status for DMA channel.</description>
92839 <description>The DMA channel interrupt B is not active.</description>
92844 <description>The DMA channel interrupt B is active.</description>
92851 <description>Interrupt B status for DMA channel.</description>
92858 <description>The DMA channel interrupt B is not active.</description>
92863 <description>The DMA channel interrupt B is active.</description>
92870 <description>Interrupt B status for DMA channel.</description>
92877 <description>The DMA channel interrupt B is not active.</description>
92882 <description>The DMA channel interrupt B is active.</description>
92889 <description>Interrupt B status for DMA channel.</description>
92896 <description>The DMA channel interrupt B is not active.</description>
92901 <description>The DMA channel interrupt B is active.</description>
92908 <description>Interrupt B status for DMA channel.</description>
92915 <description>The DMA channel interrupt B is not active.</description>
92920 <description>The DMA channel interrupt B is active.</description>
92927 <description>Interrupt B status for DMA channel.</description>
92934 <description>The DMA channel interrupt B is not active.</description>
92939 <description>The DMA channel interrupt B is active.</description>
92946 <description>Interrupt B status for DMA channel.</description>
92953 <description>The DMA channel interrupt B is not active.</description>
92958 <description>The DMA channel interrupt B is active.</description>
92965 <description>Interrupt B status for DMA channel.</description>
92972 <description>The DMA channel interrupt B is not active.</description>
92977 <description>The DMA channel interrupt B is active.</description>
92984 <description>Interrupt B status for DMA channel.</description>
92991 <description>The DMA channel interrupt B is not active.</description>
92996 <description>The DMA channel interrupt B is active.</description>
93003 <description>Interrupt B status for DMA channel.</description>
93010 <description>The DMA channel interrupt B is not active.</description>
93015 <description>The DMA channel interrupt B is active.</description>
93022 <description>Interrupt B status for DMA channel.</description>
93029 <description>The DMA channel interrupt B is not active.</description>
93034 <description>The DMA channel interrupt B is active.</description>
93041 <description>Interrupt B status for DMA channel.</description>
93048 <description>The DMA channel interrupt B is not active.</description>
93053 <description>The DMA channel interrupt B is active.</description>
93060 <description>Interrupt B status for DMA channel.</description>
93067 <description>The DMA channel interrupt B is not active.</description>
93072 <description>The DMA channel interrupt B is active.</description>
93079 <description>Interrupt B status for DMA channel.</description>
93086 <description>The DMA channel interrupt B is not active.</description>
93091 <description>The DMA channel interrupt B is active.</description>
93098 <description>Interrupt B status for DMA channel.</description>
93105 <description>The DMA channel interrupt B is not active.</description>
93110 <description>The DMA channel interrupt B is active.</description>
93117 <description>Interrupt B status for DMA channel.</description>
93124 <description>The DMA channel interrupt B is not active.</description>
93129 <description>The DMA channel interrupt B is active.</description>
93136 <description>Interrupt B status for DMA channel.</description>
93143 <description>The DMA channel interrupt B is not active.</description>
93148 <description>The DMA channel interrupt B is active.</description>
93155 <description>Interrupt B status for DMA channel.</description>
93162 <description>The DMA channel interrupt B is not active.</description>
93167 <description>The DMA channel interrupt B is active.</description>
93174 <description>Interrupt B status for DMA channel.</description>
93181 <description>The DMA channel interrupt B is not active.</description>
93186 <description>The DMA channel interrupt B is active.</description>
93193 <description>Interrupt B status for DMA channel.</description>
93200 <description>The DMA channel interrupt B is not active.</description>
93205 <description>The DMA channel interrupt B is active.</description>
93214 <description>Set ValidPending control bits for all DMA channels</description>
93223 <description>SetValid control for DMA channel.</description>
93230 <description>No effect.</description>
93235 <description>Sets the ValidPending control bit for DMA channel.</description>
93242 <description>SetValid control for DMA channel.</description>
93249 <description>No effect.</description>
93254 <description>Sets the ValidPending control bit for DMA channel.</description>
93261 <description>SetValid control for DMA channel.</description>
93268 <description>No effect.</description>
93273 <description>Sets the ValidPending control bit for DMA channel.</description>
93280 <description>SetValid control for DMA channel.</description>
93287 <description>No effect.</description>
93292 <description>Sets the ValidPending control bit for DMA channel.</description>
93299 <description>SetValid control for DMA channel.</description>
93306 <description>No effect.</description>
93311 <description>Sets the ValidPending control bit for DMA channel.</description>
93318 <description>SetValid control for DMA channel.</description>
93325 <description>No effect.</description>
93330 <description>Sets the ValidPending control bit for DMA channel.</description>
93337 <description>SetValid control for DMA channel.</description>
93344 <description>No effect.</description>
93349 <description>Sets the ValidPending control bit for DMA channel.</description>
93356 <description>SetValid control for DMA channel.</description>
93363 <description>No effect.</description>
93368 <description>Sets the ValidPending control bit for DMA channel.</description>
93375 <description>SetValid control for DMA channel.</description>
93382 <description>No effect.</description>
93387 <description>Sets the ValidPending control bit for DMA channel.</description>
93394 <description>SetValid control for DMA channel.</description>
93401 <description>No effect.</description>
93406 <description>Sets the ValidPending control bit for DMA channel.</description>
93413 <description>SetValid control for DMA channel.</description>
93420 <description>No effect.</description>
93425 <description>Sets the ValidPending control bit for DMA channel.</description>
93432 <description>SetValid control for DMA channel.</description>
93439 <description>No effect.</description>
93444 <description>Sets the ValidPending control bit for DMA channel.</description>
93451 <description>SetValid control for DMA channel.</description>
93458 <description>No effect.</description>
93463 <description>Sets the ValidPending control bit for DMA channel.</description>
93470 <description>SetValid control for DMA channel.</description>
93477 <description>No effect.</description>
93482 <description>Sets the ValidPending control bit for DMA channel.</description>
93489 <description>SetValid control for DMA channel.</description>
93496 <description>No effect.</description>
93501 <description>Sets the ValidPending control bit for DMA channel.</description>
93508 <description>SetValid control for DMA channel.</description>
93515 <description>No effect.</description>
93520 <description>Sets the ValidPending control bit for DMA channel.</description>
93527 <description>SetValid control for DMA channel.</description>
93534 <description>No effect.</description>
93539 <description>Sets the ValidPending control bit for DMA channel.</description>
93546 <description>SetValid control for DMA channel.</description>
93553 <description>No effect.</description>
93558 <description>Sets the ValidPending control bit for DMA channel.</description>
93565 <description>SetValid control for DMA channel.</description>
93572 <description>No effect.</description>
93577 <description>Sets the ValidPending control bit for DMA channel.</description>
93584 <description>SetValid control for DMA channel.</description>
93591 <description>No effect.</description>
93596 <description>Sets the ValidPending control bit for DMA channel.</description>
93603 <description>SetValid control for DMA channel.</description>
93610 <description>No effect.</description>
93615 <description>Sets the ValidPending control bit for DMA channel.</description>
93622 <description>SetValid control for DMA channel.</description>
93629 <description>No effect.</description>
93634 <description>Sets the ValidPending control bit for DMA channel.</description>
93641 <description>SetValid control for DMA channel.</description>
93648 <description>No effect.</description>
93653 <description>Sets the ValidPending control bit for DMA channel.</description>
93660 <description>SetValid control for DMA channel.</description>
93667 <description>No effect.</description>
93672 <description>Sets the ValidPending control bit for DMA channel.</description>
93679 <description>SetValid control for DMA channel.</description>
93686 <description>No effect.</description>
93691 <description>Sets the ValidPending control bit for DMA channel.</description>
93698 <description>SetValid control for DMA channel.</description>
93705 <description>No effect.</description>
93710 <description>Sets the ValidPending control bit for DMA channel.</description>
93717 <description>SetValid control for DMA channel.</description>
93724 <description>No effect.</description>
93729 <description>Sets the ValidPending control bit for DMA channel.</description>
93736 <description>SetValid control for DMA channel.</description>
93743 <description>No effect.</description>
93748 <description>Sets the ValidPending control bit for DMA channel.</description>
93755 <description>SetValid control for DMA channel.</description>
93762 <description>No effect.</description>
93767 <description>Sets the ValidPending control bit for DMA channel.</description>
93774 <description>SetValid control for DMA channel.</description>
93781 <description>No effect.</description>
93786 <description>Sets the ValidPending control bit for DMA channel.</description>
93793 <description>SetValid control for DMA channel.</description>
93800 <description>No effect.</description>
93805 <description>Sets the ValidPending control bit for DMA channel.</description>
93812 <description>SetValid control for DMA channel.</description>
93819 <description>No effect.</description>
93824 <description>Sets the ValidPending control bit for DMA channel.</description>
93833 <description>Set ValidPending control bits for all DMA channels</description>
93842 <description>SetValid control for DMA channel.</description>
93849 <description>No effect.</description>
93854 <description>Sets the ValidPending control bit for DMA channel.</description>
93861 <description>SetValid control for DMA channel.</description>
93868 <description>No effect.</description>
93873 <description>Sets the ValidPending control bit for DMA channel.</description>
93880 <description>SetValid control for DMA channel.</description>
93887 <description>No effect.</description>
93892 <description>Sets the ValidPending control bit for DMA channel.</description>
93899 <description>SetValid control for DMA channel.</description>
93906 <description>No effect.</description>
93911 <description>Sets the ValidPending control bit for DMA channel.</description>
93918 <description>SetValid control for DMA channel.</description>
93925 <description>No effect.</description>
93930 <description>Sets the ValidPending control bit for DMA channel.</description>
93937 <description>SetValid control for DMA channel.</description>
93944 <description>No effect.</description>
93949 <description>Sets the ValidPending control bit for DMA channel.</description>
93956 <description>SetValid control for DMA channel.</description>
93963 <description>No effect.</description>
93968 <description>Sets the ValidPending control bit for DMA channel.</description>
93975 <description>SetValid control for DMA channel.</description>
93982 <description>No effect.</description>
93987 <description>Sets the ValidPending control bit for DMA channel.</description>
93994 <description>SetValid control for DMA channel.</description>
94001 <description>No effect.</description>
94006 <description>Sets the ValidPending control bit for DMA channel.</description>
94013 <description>SetValid control for DMA channel.</description>
94020 <description>No effect.</description>
94025 <description>Sets the ValidPending control bit for DMA channel.</description>
94032 <description>SetValid control for DMA channel.</description>
94039 <description>No effect.</description>
94044 <description>Sets the ValidPending control bit for DMA channel.</description>
94051 <description>SetValid control for DMA channel.</description>
94058 <description>No effect.</description>
94063 <description>Sets the ValidPending control bit for DMA channel.</description>
94070 <description>SetValid control for DMA channel.</description>
94077 <description>No effect.</description>
94082 <description>Sets the ValidPending control bit for DMA channel.</description>
94089 <description>SetValid control for DMA channel.</description>
94096 <description>No effect.</description>
94101 <description>Sets the ValidPending control bit for DMA channel.</description>
94108 <description>SetValid control for DMA channel.</description>
94115 <description>No effect.</description>
94120 <description>Sets the ValidPending control bit for DMA channel.</description>
94127 <description>SetValid control for DMA channel.</description>
94134 <description>No effect.</description>
94139 <description>Sets the ValidPending control bit for DMA channel.</description>
94146 <description>SetValid control for DMA channel.</description>
94153 <description>No effect.</description>
94158 <description>Sets the ValidPending control bit for DMA channel.</description>
94165 <description>SetValid control for DMA channel.</description>
94172 <description>No effect.</description>
94177 <description>Sets the ValidPending control bit for DMA channel.</description>
94184 <description>SetValid control for DMA channel.</description>
94191 <description>No effect.</description>
94196 <description>Sets the ValidPending control bit for DMA channel.</description>
94203 <description>SetValid control for DMA channel.</description>
94210 <description>No effect.</description>
94215 <description>Sets the ValidPending control bit for DMA channel.</description>
94224 <description>Set Trigger control bits for all DMA channels</description>
94233 <description>Set Trigger control bit for DMA channel.</description>
94240 <description>No effect.</description>
94245 <description>Sets the Trig bit for DMA channel.</description>
94252 <description>Set Trigger control bit for DMA channel.</description>
94259 <description>No effect.</description>
94264 <description>Sets the Trig bit for DMA channel.</description>
94271 <description>Set Trigger control bit for DMA channel.</description>
94278 <description>No effect.</description>
94283 <description>Sets the Trig bit for DMA channel.</description>
94290 <description>Set Trigger control bit for DMA channel.</description>
94297 <description>No effect.</description>
94302 <description>Sets the Trig bit for DMA channel.</description>
94309 <description>Set Trigger control bit for DMA channel.</description>
94316 <description>No effect.</description>
94321 <description>Sets the Trig bit for DMA channel.</description>
94328 <description>Set Trigger control bit for DMA channel.</description>
94335 <description>No effect.</description>
94340 <description>Sets the Trig bit for DMA channel.</description>
94347 <description>Set Trigger control bit for DMA channel.</description>
94354 <description>No effect.</description>
94359 <description>Sets the Trig bit for DMA channel.</description>
94366 <description>Set Trigger control bit for DMA channel.</description>
94373 <description>No effect.</description>
94378 <description>Sets the Trig bit for DMA channel.</description>
94385 <description>Set Trigger control bit for DMA channel.</description>
94392 <description>No effect.</description>
94397 <description>Sets the Trig bit for DMA channel.</description>
94404 <description>Set Trigger control bit for DMA channel.</description>
94411 <description>No effect.</description>
94416 <description>Sets the Trig bit for DMA channel.</description>
94423 <description>Set Trigger control bit for DMA channel.</description>
94430 <description>No effect.</description>
94435 <description>Sets the Trig bit for DMA channel.</description>
94442 <description>Set Trigger control bit for DMA channel.</description>
94449 <description>No effect.</description>
94454 <description>Sets the Trig bit for DMA channel.</description>
94461 <description>Set Trigger control bit for DMA channel.</description>
94468 <description>No effect.</description>
94473 <description>Sets the Trig bit for DMA channel.</description>
94480 <description>Set Trigger control bit for DMA channel.</description>
94487 <description>No effect.</description>
94492 <description>Sets the Trig bit for DMA channel.</description>
94499 <description>Set Trigger control bit for DMA channel.</description>
94506 <description>No effect.</description>
94511 <description>Sets the Trig bit for DMA channel.</description>
94518 <description>Set Trigger control bit for DMA channel.</description>
94525 <description>No effect.</description>
94530 <description>Sets the Trig bit for DMA channel.</description>
94537 <description>Set Trigger control bit for DMA channel.</description>
94544 <description>No effect.</description>
94549 <description>Sets the Trig bit for DMA channel.</description>
94556 <description>Set Trigger control bit for DMA channel.</description>
94563 <description>No effect.</description>
94568 <description>Sets the Trig bit for DMA channel.</description>
94575 <description>Set Trigger control bit for DMA channel.</description>
94582 <description>No effect.</description>
94587 <description>Sets the Trig bit for DMA channel.</description>
94594 <description>Set Trigger control bit for DMA channel.</description>
94601 <description>No effect.</description>
94606 <description>Sets the Trig bit for DMA channel.</description>
94613 <description>Set Trigger control bit for DMA channel.</description>
94620 <description>No effect.</description>
94625 <description>Sets the Trig bit for DMA channel.</description>
94632 <description>Set Trigger control bit for DMA channel.</description>
94639 <description>No effect.</description>
94644 <description>Sets the Trig bit for DMA channel.</description>
94651 <description>Set Trigger control bit for DMA channel.</description>
94658 <description>No effect.</description>
94663 <description>Sets the Trig bit for DMA channel.</description>
94670 <description>Set Trigger control bit for DMA channel.</description>
94677 <description>No effect.</description>
94682 <description>Sets the Trig bit for DMA channel.</description>
94689 <description>Set Trigger control bit for DMA channel.</description>
94696 <description>No effect.</description>
94701 <description>Sets the Trig bit for DMA channel.</description>
94708 <description>Set Trigger control bit for DMA channel.</description>
94715 <description>No effect.</description>
94720 <description>Sets the Trig bit for DMA channel.</description>
94727 <description>Set Trigger control bit for DMA channel.</description>
94734 <description>No effect.</description>
94739 <description>Sets the Trig bit for DMA channel.</description>
94746 <description>Set Trigger control bit for DMA channel.</description>
94753 <description>No effect.</description>
94758 <description>Sets the Trig bit for DMA channel.</description>
94765 <description>Set Trigger control bit for DMA channel.</description>
94772 <description>No effect.</description>
94777 <description>Sets the Trig bit for DMA channel.</description>
94784 <description>Set Trigger control bit for DMA channel.</description>
94791 <description>No effect.</description>
94796 <description>Sets the Trig bit for DMA channel.</description>
94803 <description>Set Trigger control bit for DMA channel.</description>
94810 <description>No effect.</description>
94815 <description>Sets the Trig bit for DMA channel.</description>
94822 <description>Set Trigger control bit for DMA channel.</description>
94829 <description>No effect.</description>
94834 <description>Sets the Trig bit for DMA channel.</description>
94843 <description>Set Trigger control bits for all DMA channels</description>
94852 <description>Set Trigger control bit for DMA channel.</description>
94859 <description>No effect.</description>
94864 <description>Sets the Trig bit for DMA channel.</description>
94871 <description>Set Trigger control bit for DMA channel.</description>
94878 <description>No effect.</description>
94883 <description>Sets the Trig bit for DMA channel.</description>
94890 <description>Set Trigger control bit for DMA channel.</description>
94897 <description>No effect.</description>
94902 <description>Sets the Trig bit for DMA channel.</description>
94909 <description>Set Trigger control bit for DMA channel.</description>
94916 <description>No effect.</description>
94921 <description>Sets the Trig bit for DMA channel.</description>
94928 <description>Set Trigger control bit for DMA channel.</description>
94935 <description>No effect.</description>
94940 <description>Sets the Trig bit for DMA channel.</description>
94947 <description>Set Trigger control bit for DMA channel.</description>
94954 <description>No effect.</description>
94959 <description>Sets the Trig bit for DMA channel.</description>
94966 <description>Set Trigger control bit for DMA channel.</description>
94973 <description>No effect.</description>
94978 <description>Sets the Trig bit for DMA channel.</description>
94985 <description>Set Trigger control bit for DMA channel.</description>
94992 <description>No effect.</description>
94997 <description>Sets the Trig bit for DMA channel.</description>
95004 <description>Set Trigger control bit for DMA channel.</description>
95011 <description>No effect.</description>
95016 <description>Sets the Trig bit for DMA channel.</description>
95023 <description>Set Trigger control bit for DMA channel.</description>
95030 <description>No effect.</description>
95035 <description>Sets the Trig bit for DMA channel.</description>
95042 <description>Set Trigger control bit for DMA channel.</description>
95049 <description>No effect.</description>
95054 <description>Sets the Trig bit for DMA channel.</description>
95061 <description>Set Trigger control bit for DMA channel.</description>
95068 <description>No effect.</description>
95073 <description>Sets the Trig bit for DMA channel.</description>
95080 <description>Set Trigger control bit for DMA channel.</description>
95087 <description>No effect.</description>
95092 <description>Sets the Trig bit for DMA channel.</description>
95099 <description>Set Trigger control bit for DMA channel.</description>
95106 <description>No effect.</description>
95111 <description>Sets the Trig bit for DMA channel.</description>
95118 <description>Set Trigger control bit for DMA channel.</description>
95125 <description>No effect.</description>
95130 <description>Sets the Trig bit for DMA channel.</description>
95137 <description>Set Trigger control bit for DMA channel.</description>
95144 <description>No effect.</description>
95149 <description>Sets the Trig bit for DMA channel.</description>
95156 <description>Set Trigger control bit for DMA channel.</description>
95163 <description>No effect.</description>
95168 <description>Sets the Trig bit for DMA channel.</description>
95175 <description>Set Trigger control bit for DMA channel.</description>
95182 <description>No effect.</description>
95187 <description>Sets the Trig bit for DMA channel.</description>
95194 <description>Set Trigger control bit for DMA channel.</description>
95201 <description>No effect.</description>
95206 <description>Sets the Trig bit for DMA channel.</description>
95213 <description>Set Trigger control bit for DMA channel.</description>
95220 <description>No effect.</description>
95225 <description>Sets the Trig bit for DMA channel.</description>
95234 <description>Channel Abort control for all DMA channels</description>
95243 <description>Abort control for DMA channel.</description>
95250 <description>No effect.</description>
95255 <description>Aborts DMA operations on channel.</description>
95262 <description>Abort control for DMA channel.</description>
95269 <description>No effect.</description>
95274 <description>Aborts DMA operations on channel.</description>
95281 <description>Abort control for DMA channel.</description>
95288 <description>No effect.</description>
95293 <description>Aborts DMA operations on channel.</description>
95300 <description>Abort control for DMA channel.</description>
95307 <description>No effect.</description>
95312 <description>Aborts DMA operations on channel.</description>
95319 <description>Abort control for DMA channel.</description>
95326 <description>No effect.</description>
95331 <description>Aborts DMA operations on channel.</description>
95338 <description>Abort control for DMA channel.</description>
95345 <description>No effect.</description>
95350 <description>Aborts DMA operations on channel.</description>
95357 <description>Abort control for DMA channel.</description>
95364 <description>No effect.</description>
95369 <description>Aborts DMA operations on channel.</description>
95376 <description>Abort control for DMA channel.</description>
95383 <description>No effect.</description>
95388 <description>Aborts DMA operations on channel.</description>
95395 <description>Abort control for DMA channel.</description>
95402 <description>No effect.</description>
95407 <description>Aborts DMA operations on channel.</description>
95414 <description>Abort control for DMA channel.</description>
95421 <description>No effect.</description>
95426 <description>Aborts DMA operations on channel.</description>
95433 <description>Abort control for DMA channel.</description>
95440 <description>No effect.</description>
95445 <description>Aborts DMA operations on channel.</description>
95452 <description>Abort control for DMA channel.</description>
95459 <description>No effect.</description>
95464 <description>Aborts DMA operations on channel.</description>
95471 <description>Abort control for DMA channel.</description>
95478 <description>No effect.</description>
95483 <description>Aborts DMA operations on channel.</description>
95490 <description>Abort control for DMA channel.</description>
95497 <description>No effect.</description>
95502 <description>Aborts DMA operations on channel.</description>
95509 <description>Abort control for DMA channel.</description>
95516 <description>No effect.</description>
95521 <description>Aborts DMA operations on channel.</description>
95528 <description>Abort control for DMA channel.</description>
95535 <description>No effect.</description>
95540 <description>Aborts DMA operations on channel.</description>
95547 <description>Abort control for DMA channel.</description>
95554 <description>No effect.</description>
95559 <description>Aborts DMA operations on channel.</description>
95566 <description>Abort control for DMA channel.</description>
95573 <description>No effect.</description>
95578 <description>Aborts DMA operations on channel.</description>
95585 <description>Abort control for DMA channel.</description>
95592 <description>No effect.</description>
95597 <description>Aborts DMA operations on channel.</description>
95604 <description>Abort control for DMA channel.</description>
95611 <description>No effect.</description>
95616 <description>Aborts DMA operations on channel.</description>
95623 <description>Abort control for DMA channel.</description>
95630 <description>No effect.</description>
95635 <description>Aborts DMA operations on channel.</description>
95642 <description>Abort control for DMA channel.</description>
95649 <description>No effect.</description>
95654 <description>Aborts DMA operations on channel.</description>
95661 <description>Abort control for DMA channel.</description>
95668 <description>No effect.</description>
95673 <description>Aborts DMA operations on channel.</description>
95680 <description>Abort control for DMA channel.</description>
95687 <description>No effect.</description>
95692 <description>Aborts DMA operations on channel.</description>
95699 <description>Abort control for DMA channel.</description>
95706 <description>No effect.</description>
95711 <description>Aborts DMA operations on channel.</description>
95718 <description>Abort control for DMA channel.</description>
95725 <description>No effect.</description>
95730 <description>Aborts DMA operations on channel.</description>
95737 <description>Abort control for DMA channel.</description>
95744 <description>No effect.</description>
95749 <description>Aborts DMA operations on channel.</description>
95756 <description>Abort control for DMA channel.</description>
95763 <description>No effect.</description>
95768 <description>Aborts DMA operations on channel.</description>
95775 <description>Abort control for DMA channel.</description>
95782 <description>No effect.</description>
95787 <description>Aborts DMA operations on channel.</description>
95794 <description>Abort control for DMA channel.</description>
95801 <description>No effect.</description>
95806 <description>Aborts DMA operations on channel.</description>
95813 <description>Abort control for DMA channel.</description>
95820 <description>No effect.</description>
95825 <description>Aborts DMA operations on channel.</description>
95832 <description>Abort control for DMA channel.</description>
95839 <description>No effect.</description>
95844 <description>Aborts DMA operations on channel.</description>
95853 <description>Channel Abort control for all DMA channels</description>
95862 <description>Abort control for DMA channel.</description>
95869 <description>No effect.</description>
95874 <description>Aborts DMA operations on channel.</description>
95881 <description>Abort control for DMA channel.</description>
95888 <description>No effect.</description>
95893 <description>Aborts DMA operations on channel.</description>
95900 <description>Abort control for DMA channel.</description>
95907 <description>No effect.</description>
95912 <description>Aborts DMA operations on channel.</description>
95919 <description>Abort control for DMA channel.</description>
95926 <description>No effect.</description>
95931 <description>Aborts DMA operations on channel.</description>
95938 <description>Abort control for DMA channel.</description>
95945 <description>No effect.</description>
95950 <description>Aborts DMA operations on channel.</description>
95957 <description>Abort control for DMA channel.</description>
95964 <description>No effect.</description>
95969 <description>Aborts DMA operations on channel.</description>
95976 <description>Abort control for DMA channel.</description>
95983 <description>No effect.</description>
95988 <description>Aborts DMA operations on channel.</description>
95995 <description>Abort control for DMA channel.</description>
96002 <description>No effect.</description>
96007 <description>Aborts DMA operations on channel.</description>
96014 <description>Abort control for DMA channel.</description>
96021 <description>No effect.</description>
96026 <description>Aborts DMA operations on channel.</description>
96033 <description>Abort control for DMA channel.</description>
96040 <description>No effect.</description>
96045 <description>Aborts DMA operations on channel.</description>
96052 <description>Abort control for DMA channel.</description>
96059 <description>No effect.</description>
96064 <description>Aborts DMA operations on channel.</description>
96071 <description>Abort control for DMA channel.</description>
96078 <description>No effect.</description>
96083 <description>Aborts DMA operations on channel.</description>
96090 <description>Abort control for DMA channel.</description>
96097 <description>No effect.</description>
96102 <description>Aborts DMA operations on channel.</description>
96109 <description>Abort control for DMA channel.</description>
96116 <description>No effect.</description>
96121 <description>Aborts DMA operations on channel.</description>
96128 <description>Abort control for DMA channel.</description>
96135 <description>No effect.</description>
96140 <description>Aborts DMA operations on channel.</description>
96147 <description>Abort control for DMA channel.</description>
96154 <description>No effect.</description>
96159 <description>Aborts DMA operations on channel.</description>
96166 <description>Abort control for DMA channel.</description>
96173 <description>No effect.</description>
96178 <description>Aborts DMA operations on channel.</description>
96185 <description>Abort control for DMA channel.</description>
96192 <description>No effect.</description>
96197 <description>Aborts DMA operations on channel.</description>
96204 <description>Abort control for DMA channel.</description>
96211 <description>No effect.</description>
96216 <description>Aborts DMA operations on channel.</description>
96223 <description>Abort control for DMA channel.</description>
96230 <description>No effect.</description>
96235 <description>Aborts DMA operations on channel.</description>
96246 <description>no description available</description>
96250 <description>Configuration register for DMA channel</description>
96259 <description>Peripheral request Enable.</description>
96266 <description>Peripheral DMA requests disabled.</description>
96271 <description>Peripheral DMA requests enabled.</description>
96278 <description>Hardware Triggering Enable for channel.</description>
96285 <description>Hardware triggering not used for channel.</description>
96290 <description>Hardware triggering used for channel.</description>
96297 <description>Trigger Polarity.</description>
96304 …<description>Active low - falling edge. Hardware trigger is active low or falling edge triggered, …
96309 …<description>Active high - rising edge. Hardware trigger is active high or rising edge triggered, …
96316 <description>Trigger Type.</description>
96323 …<description>Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, …
96328 <description>Level.</description>
96335 <description>Trigger Burst.</description>
96342 <description>Single transfer.</description>
96347 <description>Burst transfer.</description>
96354 <description>Burst Power.</description>
96361 <description>Source Burst Wrap.</description>
96368 <description>Disabled.</description>
96373 <description>Enabled.</description>
96380 <description>Destination Burst Wrap.</description>
96387 …<description>Disabled. Destination burst wrapping is not enabled for this DMA channel.</descriptio…
96392 … <description>Enabled. Destination burst wrapping is enabled for this DMA channel.</description>
96399 … <description>Priority of channel when multiple DMA requests are pending.</description>
96408 <description>Control and status register for DMA channel</description>
96417 <description>Valid pending flag for this channel.</description>
96424 <description>No effect on DMA operation.</description>
96429 <description>Valid pending.</description>
96436 <description>Trigger flag.</description>
96443 …<description>Not triggered. The trigger for this DMA channel is not set. DMA operations will not b…
96448 …<description>Triggered. The trigger for this DMA channel is set. DMA operations will be carried ou…
96457 <description>Transfer configuration register for DMA channel</description>
96466 <description>Configuration Valid flag.</description>
96473 <description>Not valid.</description>
96478 <description>Valid.</description>
96485 <description>Reload.</description>
96492 …<description>Disabled. The channels' control structure should not be reloaded when the current des…
96497 …<description>Enabled. The channels' control structure should be reloaded when the current descript…
96504 <description>Software Trigger.</description>
96511 <description>Not set.</description>
96516 <description>Set.</description>
96523 <description>Clear Trigger.</description>
96530 <description>Not cleared.</description>
96535 <description>Cleared.</description>
96542 <description>Set Interrupt flag A for channel.</description>
96549 <description>No effect.</description>
96554 …<description>Set. The INTA flag for this channel will be set when the current descriptor is exhaus…
96561 <description>Set Interrupt flag B for channel.</description>
96568 <description>No effect.</description>
96573 …<description>Set. The INTB flag for this channel will be set when the current descriptor is exhaus…
96580 <description>Transfer width used for this DMA channel.</description>
96587 <description>8-bit.</description>
96592 <description>16-bit.</description>
96597 <description>32-bit.</description>
96604 <description>Source address increment</description>
96611 <description>No increment.</description>
96616 <description>1 x width.</description>
96621 <description>2 x width.</description>
96626 <description>4 x width.</description>
96633 <description>Destination address increment</description>
96640 <description>No increment.</description>
96645 <description>1 x width.</description>
96650 <description>2 x width.</description>
96655 <description>4 x width.</description>
96662 … <description>Total number of transfers to be performed, minus 1 encoded.</description>
96674 <description>SCTimer</description>
96689 <description>SCTimer Configuration</description>
96698 <description>SCT Operation</description>
96705 …<description>Dual counter. The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.<…
96710 … <description>Unified counter. The SCT operates as a unified 32-bit counter.</description>
96717 <description>SCT Clock Mode</description>
96724 …<description>System Clock Mode. The system clock clocks the entire SCT module including all counte…
96729 …description>Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and…
96734 …description>SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module…
96739 …description>Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selecte…
96746 …description>SCT Clock Select. The specific functionality of the designated input/edge is dependent…
96753 <description>Rising edges on input 0</description>
96758 <description>Falling edges on input 0</description>
96763 <description>Rising edges on input 1</description>
96768 <description>Falling edges on input 1</description>
96773 <description>Rising edges on input 2</description>
96778 <description>Falling edges on input 2</description>
96783 <description>Rising edges on input 3</description>
96788 <description>Falling edges on input 3</description>
96793 <description>Rising edges on input 4</description>
96798 <description>Falling edges on input 4</description>
96803 <description>Rising edges on input 5</description>
96808 <description>Falling edges on input 5</description>
96813 <description>Rising edges on input 6</description>
96818 <description>Falling edges on input 6</description>
96823 <description>Rising edges on input 7</description>
96828 <description>Falling edges on input 7</description>
96835 <description>No Reload Lower Match</description>
96842 <description>Reload. The default setting.</description>
96847 …<description>No Reload. Prevents the lower match registers from being reloaded from their respecti…
96854 <description>No Reload Higher Match</description>
96861 <description>Reload. The default setting.</description>
96866 …<description>No Reload. Prevents the higher match registers from being reloaded from their respect…
96873 <description>Input Synchronization</description>
96880 <description>Auto Limit Lower</description>
96887 <description>Disable.</description>
96892 …<description>Enable. A match on match register 0 is the LIMIT condition. No need to define an asso…
96899 <description>Auto Limit Higher</description>
96906 <description>Disable.</description>
96911 …<description>Enable. A match on match register 0 is the LIMIT condition. No need to define an asso…
96920 <description>SCT Control</description>
96929 <description>Down Counter Low</description>
96936 <description>Up. The L or unified counter is counting up.</description>
96941 <description>Down. The L or unified counter is counting down.</description>
96948 <description>Stop Counter Low</description>
96955 <description>Disable</description>
96960 <description>Enable</description>
96967 <description>Halt Counter Low</description>
96974 <description>Disable</description>
96979 <description>Enable</description>
96986 <description>Clear Counter Low</description>
96993 <description>Bidirectional Select Low</description>
97000 …<description>Up. The counter counts up to a limit condition, then is cleared to zero.</description>
97005 …<description>Up-down. The counter counts up to a limit, then counts down to a limit condition or t…
97012 <description>Prescaler for Low Counter</description>
97019 <description>Down Counter High</description>
97026 <description>Up. The H counter is counting up.</description>
97031 <description>Down. The H counter is counting down.</description>
97038 <description>Stop Counter High</description>
97045 <description>Disable</description>
97050 <description>Enable</description>
97057 <description>Halt Counter High</description>
97064 <description>Disable</description>
97069 <description>Enable</description>
97076 <description>Clear Counter High</description>
97083 <description>Bidirectional Select High</description>
97090 …<description>Up. The H counter counts up to its limit condition, then is cleared to zero.</descrip…
97095 …<description>Up-down. The H counter counts up to its limit, then counts down to a limit condition …
97102 <description>Prescaler for High Counter</description>
97111 <description>SCT Limit Event Select</description>
97120 <description>Limit Event Counter Low</description>
97127 <description>Limit Event Counter High</description>
97136 <description>Halt Event Select</description>
97145 <description>Halt Event Low</description>
97152 <description>Halt Event High</description>
97161 <description>Stop Event Select</description>
97170 <description>Stop Event Low</description>
97177 <description>Stop Event High</description>
97186 <description>Start Event Select</description>
97195 …description>If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = bit 1…
97202 …description>If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = bit …
97211 <description>Dither Condition</description>
97220 …description>If bit n is one, event n clears the CTRL[STOP_L] = 0 (event 0 = bit 0, event 1 = bit 1…
97227 …description>If bit n is one, event n clears the CTRL[STOP_H] = 0 (event 0 = bit 16, event 1 = bit …
97236 <description>Counter</description>
97245 <description>Counter Low</description>
97252 <description>Counter High</description>
97261 <description>State</description>
97270 <description>State variable</description>
97277 <description>State variable</description>
97286 <description>Input</description>
97295 <description>Input 0 state. Input 0 state on the last SCT clock edge.</description>
97302 <description>Input 1 state. Input 1 state on the last SCT clock edge.</description>
97309 <description>Input 2 state. Input 2 state on the last SCT clock edge.</description>
97316 <description>Input 3 state. Input 3 state on the last SCT clock edge.</description>
97323 <description>Input 4 state. Input 4 state on the last SCT clock edge.</description>
97330 <description>Input 5 state. Input 5 state on the last SCT clock edge.</description>
97337 <description>Input 6 state. Input 6 state on the last SCT clock edge.</description>
97344 <description>Input 7 state. Input 7 state on the last SCT clock edge.</description>
97351 <description>Input 8 state. Input 8 state on the last SCT clock edge.</description>
97358 <description>Input 9 state. Input 9 state on the last SCT clock edge.</description>
97365 <description>Input 10 state. Input 10 state on the last SCT clock edge.</description>
97372 <description>Input 11 state. Input 11 state on the last SCT clock edge.</description>
97379 <description>Input 12 state. Input 12 state on the last SCT clock edge.</description>
97386 <description>Input 13 state. Input 13 state on the last SCT clock edge.</description>
97393 <description>Input 14 state. Input 14 state on the last SCT clock edge.</description>
97400 <description>Input 15 state. Input 15 state on the last SCT clock edge.</description>
97407 …<description>Input 0 state. Input 0 state following the synchronization specified by INSYNC.</desc…
97414 …<description>Input 1 state. Input 1 state following the synchronization specified by INSYNC.</desc…
97421 …<description>Input 2 state. Input 2 state following the synchronization specified by INSYNC.</desc…
97428 …<description>Input 3 state. Input 3 state following the synchronization specified by INSYNC.</desc…
97435 …<description>Input 4 state. Input 4 state following the synchronization specified by INSYNC.</desc…
97442 …<description>Input 5 state. Input 5 state following the synchronization specified by INSYNC.</desc…
97449 …<description>Input 6 state. Input 6 state following the synchronization specified by INSYNC.</desc…
97456 …<description>Input 7 state. Input 7 state following the synchronization specified by INSYNC.</desc…
97463 …<description>Input 8 state. Input 8 state following the synchronization specified by INSYNC.</desc…
97470 …<description>Input 9 state. Input 9 state following the synchronization specified by INSYNC.</desc…
97477 …<description>Input 10 state. Input 10 state following the synchronization specified by INSYNC.</de…
97484 …<description>Input 11 state. Input 11 state following the synchronization specified by INSYNC.</de…
97491 …<description>Input 12 state. Input 12 state following the synchronization specified by INSYNC.</de…
97498 …<description>Input 13 state. Input 13 state following the synchronization specified by INSYNC.</de…
97505 …<description>Input 14 state. Input 14 state following the synchronization specified by INSYNC.</de…
97512 …<description>Input 15 state. Input 15 state following the synchronization specified by INSYNC.</de…
97521 <description>Match/Capture Mode</description>
97530 <description>Register Mode Low n</description>
97537 <description>Match. Register n operates as a match register</description>
97542 <description>Capture. Register n operates as a capture register</description>
97549 <description>Register Mode Low n</description>
97556 <description>Match. Register n operates as a match register</description>
97561 <description>Capture. Register n operates as a capture register</description>
97568 <description>Register Mode Low n</description>
97575 <description>Match. Register n operates as a match register</description>
97580 <description>Capture. Register n operates as a capture register</description>
97587 <description>Register Mode Low n</description>
97594 <description>Match. Register n operates as a match register</description>
97599 <description>Capture. Register n operates as a capture register</description>
97606 <description>Register Mode Low n</description>
97613 <description>Match. Register n operates as a match register</description>
97618 <description>Capture. Register n operates as a capture register</description>
97625 <description>Register Mode Low n</description>
97632 <description>Match. Register n operates as a match register</description>
97637 <description>Capture. Register n operates as a capture register</description>
97644 <description>Register Mode Low n</description>
97651 <description>Match. Register n operates as a match register</description>
97656 <description>Capture. Register n operates as a capture register</description>
97663 <description>Register Mode Low n</description>
97670 <description>Match. Register n operates as a match register</description>
97675 <description>Capture. Register n operates as a capture register</description>
97682 <description>Register Mode Low n</description>
97689 <description>Match. Register n operates as a match register</description>
97694 <description>Capture. Register n operates as a capture register</description>
97701 <description>Register Mode Low n</description>
97708 <description>Match. Register n operates as a match register</description>
97713 <description>Capture. Register n operates as a capture register</description>
97720 <description>Register Mode Low n</description>
97727 <description>Match. Register n operates as a match register</description>
97732 <description>Capture. Register n operates as a capture register</description>
97739 <description>Register Mode Low n</description>
97746 <description>Match. Register n operates as a match register</description>
97751 <description>Capture. Register n operates as a capture register</description>
97758 <description>Register Mode Low n</description>
97765 <description>Match. Register n operates as a match register</description>
97770 <description>Capture. Register n operates as a capture register</description>
97777 <description>Register Mode Low n</description>
97784 <description>Match. Register n operates as a match register</description>
97789 <description>Capture. Register n operates as a capture register</description>
97796 <description>Register Mode Low n</description>
97803 <description>Match. Register n operates as a match register</description>
97808 <description>Capture. Register n operates as a capture register</description>
97815 <description>Register Mode Low n</description>
97822 <description>Match. Register n operates as a match register</description>
97827 <description>Capture. Register n operates as a capture register</description>
97834 <description>Register Mode High n</description>
97841 <description>Match. Register n operates as a match register</description>
97846 <description>Capture. Register n operates as a capture register</description>
97853 <description>Register Mode High n</description>
97860 <description>Match. Register n operates as a match register</description>
97865 <description>Capture. Register n operates as a capture register</description>
97872 <description>Register Mode High n</description>
97879 <description>Match. Register n operates as a match register</description>
97884 <description>Capture. Register n operates as a capture register</description>
97891 <description>Register Mode High n</description>
97898 <description>Match. Register n operates as a match register</description>
97903 <description>Capture. Register n operates as a capture register</description>
97910 <description>Register Mode High n</description>
97917 <description>Match. Register n operates as a match register</description>
97922 <description>Capture. Register n operates as a capture register</description>
97929 <description>Register Mode High n</description>
97936 <description>Match. Register n operates as a match register</description>
97941 <description>Capture. Register n operates as a capture register</description>
97948 <description>Register Mode High n</description>
97955 <description>Match. Register n operates as a match register</description>
97960 <description>Capture. Register n operates as a capture register</description>
97967 <description>Register Mode High n</description>
97974 <description>Match. Register n operates as a match register</description>
97979 <description>Capture. Register n operates as a capture register</description>
97986 <description>Register Mode High n</description>
97993 <description>Match. Register n operates as a match register</description>
97998 <description>Capture. Register n operates as a capture register</description>
98005 <description>Register Mode High n</description>
98012 <description>Match. Register n operates as a match register</description>
98017 <description>Capture. Register n operates as a capture register</description>
98024 <description>Register Mode High n</description>
98031 <description>Match. Register n operates as a match register</description>
98036 <description>Capture. Register n operates as a capture register</description>
98043 <description>Register Mode High n</description>
98050 <description>Match. Register n operates as a match register</description>
98055 <description>Capture. Register n operates as a capture register</description>
98062 <description>Register Mode High n</description>
98069 <description>Match. Register n operates as a match register</description>
98074 <description>Capture. Register n operates as a capture register</description>
98081 <description>Register Mode High n</description>
98088 <description>Match. Register n operates as a match register</description>
98093 <description>Capture. Register n operates as a capture register</description>
98100 <description>Register Mode High n</description>
98107 <description>Match. Register n operates as a match register</description>
98112 <description>Capture. Register n operates as a capture register</description>
98119 <description>Register Mode High n</description>
98126 <description>Match. Register n operates as a match register</description>
98131 <description>Capture. Register n operates as a capture register</description>
98140 <description>Output</description>
98149 <description>Output n</description>
98156 <description>Writing a 0 forces the corresponding output low</description>
98161 <description>Writing a 1 forces the corresponding output high</description>
98168 <description>Output n</description>
98175 <description>Writing a 0 forces the corresponding output low</description>
98180 <description>Writing a 1 forces the corresponding output high</description>
98187 <description>Output n</description>
98194 <description>Writing a 0 forces the corresponding output low</description>
98199 <description>Writing a 1 forces the corresponding output high</description>
98206 <description>Output n</description>
98213 <description>Writing a 0 forces the corresponding output low</description>
98218 <description>Writing a 1 forces the corresponding output high</description>
98225 <description>Output n</description>
98232 <description>Writing a 0 forces the corresponding output low</description>
98237 <description>Writing a 1 forces the corresponding output high</description>
98244 <description>Output n</description>
98251 <description>Writing a 0 forces the corresponding output low</description>
98256 <description>Writing a 1 forces the corresponding output high</description>
98263 <description>Output n</description>
98270 <description>Writing a 0 forces the corresponding output low</description>
98275 <description>Writing a 1 forces the corresponding output high</description>
98282 <description>Output n</description>
98289 <description>Writing a 0 forces the corresponding output low</description>
98294 <description>Writing a 1 forces the corresponding output high</description>
98301 <description>Output n</description>
98308 <description>Writing a 0 forces the corresponding output low</description>
98313 <description>Writing a 1 forces the corresponding output high</description>
98320 <description>Output n</description>
98327 <description>Writing a 0 forces the corresponding output low</description>
98332 <description>Writing a 1 forces the corresponding output high</description>
98341 <description>Output Counter Direction Control</description>
98350 <description>Set/Clear Operation on Output n</description>
98357 … <description>Set and clear do not depend on the direction of any counter.</description>
98362 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98367 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98374 <description>Set/Clear Operation on Output n</description>
98381 … <description>Set and clear do not depend on the direction of any counter.</description>
98386 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98391 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98398 <description>Set/Clear Operation on Output n</description>
98405 … <description>Set and clear do not depend on the direction of any counter.</description>
98410 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98415 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98422 <description>Set/Clear Operation on Output n</description>
98429 … <description>Set and clear do not depend on the direction of any counter.</description>
98434 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98439 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98446 <description>Set/Clear Operation on Output n</description>
98453 … <description>Set and clear do not depend on the direction of any counter.</description>
98458 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98463 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98470 <description>Set/Clear Operation on Output n</description>
98477 … <description>Set and clear do not depend on the direction of any counter.</description>
98482 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98487 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98494 <description>Set/Clear Operation on Output n</description>
98501 … <description>Set and clear do not depend on the direction of any counter.</description>
98506 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98511 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98518 <description>Set/Clear Operation on Output n</description>
98525 … <description>Set and clear do not depend on the direction of any counter.</description>
98530 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98535 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98542 <description>Set/Clear Operation on Output n</description>
98549 … <description>Set and clear do not depend on the direction of any counter.</description>
98554 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98559 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98566 <description>Set/Clear Operation on Output n</description>
98573 … <description>Set and clear do not depend on the direction of any counter.</description>
98578 …<description>Set and clear are reversed when counter L or the unified counter is counting down.</d…
98583 …<description>Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.<…
98592 <description>Output Conflict Resolution</description>
98601 <description>Effect of simultaneous set and clear on output n</description>
98608 <description>No change</description>
98613 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98618 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98623 <description>Toggle output</description>
98630 <description>Effect of simultaneous set and clear on output n</description>
98637 <description>No change</description>
98642 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98647 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98652 <description>Toggle output</description>
98659 <description>Effect of simultaneous set and clear on output n</description>
98666 <description>No change</description>
98671 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98676 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98681 <description>Toggle output</description>
98688 <description>Effect of simultaneous set and clear on output n</description>
98695 <description>No change</description>
98700 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98705 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98710 <description>Toggle output</description>
98717 <description>Effect of simultaneous set and clear on output n</description>
98724 <description>No change</description>
98729 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98734 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98739 <description>Toggle output</description>
98746 <description>Effect of simultaneous set and clear on output n</description>
98753 <description>No change</description>
98758 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98763 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98768 <description>Toggle output</description>
98775 <description>Effect of simultaneous set and clear on output n</description>
98782 <description>No change</description>
98787 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98792 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98797 <description>Toggle output</description>
98804 <description>Effect of simultaneous set and clear on output n</description>
98811 <description>No change</description>
98816 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98821 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98826 <description>Toggle output</description>
98833 <description>Effect of simultaneous set and clear on output n</description>
98840 <description>No change</description>
98845 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98850 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98855 <description>Toggle output</description>
98862 <description>Effect of simultaneous set and clear on output n</description>
98869 <description>No change</description>
98874 … <description>Set output (or clear based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98879 … <description>Clear output (or set based on the OUTPUTDIRCTRL[SETCLRn] field)</description>
98884 <description>Toggle output</description>
98893 <description>DMA Request 0</description>
98902 <description>DMA Request Event n</description>
98909 <description>DMA Request Event n</description>
98916 <description>DMA Request Event n</description>
98923 <description>DMA Request Event n</description>
98930 <description>DMA Request Event n</description>
98937 <description>DMA Request Event n</description>
98944 <description>DMA Request Event n</description>
98951 <description>DMA Request Event n</description>
98958 <description>DMA Request Event n</description>
98965 <description>DMA Request Event n</description>
98972 <description>DMA Request Event n</description>
98979 <description>DMA Request Event n</description>
98986 <description>DMA Request Event n</description>
98993 <description>DMA Request Event n</description>
99000 <description>DMA Request Event n</description>
99007 <description>DMA Request Event n</description>
99014 …<description>A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers fr…
99021 <description>DMA Request 0 State</description>
99030 <description>DMA Request 1</description>
99039 <description>DMA Request Event n</description>
99046 <description>DMA Request Event n</description>
99053 <description>DMA Request Event n</description>
99060 <description>DMA Request Event n</description>
99067 <description>DMA Request Event n</description>
99074 <description>DMA Request Event n</description>
99081 <description>DMA Request Event n</description>
99088 <description>DMA Request Event n</description>
99095 <description>DMA Request Event n</description>
99102 <description>DMA Request Event n</description>
99109 <description>DMA Request Event n</description>
99116 <description>DMA Request Event n</description>
99123 <description>DMA Request Event n</description>
99130 <description>DMA Request Event n</description>
99137 <description>DMA Request Event n</description>
99144 <description>DMA Request Event n</description>
99151 …<description>A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers fr…
99158 <description>DMA Request 1 State</description>
99167 <description>Event Interrupt Enable</description>
99176 <description>Event Interrupt Enable n</description>
99183 <description>Disable</description>
99188 <description>Enable</description>
99195 <description>Event Interrupt Enable n</description>
99202 <description>Disable</description>
99207 <description>Enable</description>
99214 <description>Event Interrupt Enable n</description>
99221 <description>Disable</description>
99226 <description>Enable</description>
99233 <description>Event Interrupt Enable n</description>
99240 <description>Disable</description>
99245 <description>Enable</description>
99252 <description>Event Interrupt Enable n</description>
99259 <description>Disable</description>
99264 <description>Enable</description>
99271 <description>Event Interrupt Enable n</description>
99278 <description>Disable</description>
99283 <description>Enable</description>
99290 <description>Event Interrupt Enable n</description>
99297 <description>Disable</description>
99302 <description>Enable</description>
99309 <description>Event Interrupt Enable n</description>
99316 <description>Disable</description>
99321 <description>Enable</description>
99328 <description>Event Interrupt Enable n</description>
99335 <description>Disable</description>
99340 <description>Enable</description>
99347 <description>Event Interrupt Enable n</description>
99354 <description>Disable</description>
99359 <description>Enable</description>
99366 <description>Event Interrupt Enable n</description>
99373 <description>Disable</description>
99378 <description>Enable</description>
99385 <description>Event Interrupt Enable n</description>
99392 <description>Disable</description>
99397 <description>Enable</description>
99404 <description>Event Interrupt Enable n</description>
99411 <description>Disable</description>
99416 <description>Enable</description>
99423 <description>Event Interrupt Enable n</description>
99430 <description>Disable</description>
99435 <description>Enable</description>
99442 <description>Event Interrupt Enable n</description>
99449 <description>Disable</description>
99454 <description>Enable</description>
99461 <description>Event Interrupt Enable n</description>
99468 <description>Disable</description>
99473 <description>Enable</description>
99482 <description>Event Flag</description>
99491 <description>Event Flag n</description>
99498 <description>No Flag</description>
99503 <description>Event n Flag</description>
99510 <description>Event Flag n</description>
99517 <description>No Flag</description>
99522 <description>Event n Flag</description>
99529 <description>Event Flag n</description>
99536 <description>No Flag</description>
99541 <description>Event n Flag</description>
99548 <description>Event Flag n</description>
99555 <description>No Flag</description>
99560 <description>Event n Flag</description>
99567 <description>Event Flag n</description>
99574 <description>No Flag</description>
99579 <description>Event n Flag</description>
99586 <description>Event Flag n</description>
99593 <description>No Flag</description>
99598 <description>Event n Flag</description>
99605 <description>Event Flag n</description>
99612 <description>No Flag</description>
99617 <description>Event n Flag</description>
99624 <description>Event Flag n</description>
99631 <description>No Flag</description>
99636 <description>Event n Flag</description>
99643 <description>Event Flag n</description>
99650 <description>No Flag</description>
99655 <description>Event n Flag</description>
99662 <description>Event Flag n</description>
99669 <description>No Flag</description>
99674 <description>Event n Flag</description>
99681 <description>Event Flag n</description>
99688 <description>No Flag</description>
99693 <description>Event n Flag</description>
99700 <description>Event Flag n</description>
99707 <description>No Flag</description>
99712 <description>Event n Flag</description>
99719 <description>Event Flag n</description>
99726 <description>No Flag</description>
99731 <description>Event n Flag</description>
99738 <description>Event Flag n</description>
99745 <description>No Flag</description>
99750 <description>Event n Flag</description>
99757 <description>Event Flag n</description>
99764 <description>No Flag</description>
99769 <description>Event n Flag</description>
99776 <description>Event Flag n</description>
99783 <description>No Flag</description>
99788 <description>Event n Flag</description>
99797 <description>Conflict Interrupt Enable</description>
99806 <description>No Change Conflict Event/Interrupt Enable</description>
99813 <description>No interrupt</description>
99818 <description>Interrupt</description>
99825 <description>No Change Conflict Event/Interrupt Enable</description>
99832 <description>No interrupt</description>
99837 <description>Interrupt</description>
99844 <description>No Change Conflict Event/Interrupt Enable</description>
99851 <description>No interrupt</description>
99856 <description>Interrupt</description>
99863 <description>No Change Conflict Event/Interrupt Enable</description>
99870 <description>No interrupt</description>
99875 <description>Interrupt</description>
99882 <description>No Change Conflict Event/Interrupt Enable</description>
99889 <description>No interrupt</description>
99894 <description>Interrupt</description>
99901 <description>No Change Conflict Event/Interrupt Enable</description>
99908 <description>No interrupt</description>
99913 <description>Interrupt</description>
99920 <description>No Change Conflict Event/Interrupt Enable</description>
99927 <description>No interrupt</description>
99932 <description>Interrupt</description>
99939 <description>No Change Conflict Event/Interrupt Enable</description>
99946 <description>No interrupt</description>
99951 <description>Interrupt</description>
99958 <description>No Change Conflict Event/Interrupt Enable</description>
99965 <description>No interrupt</description>
99970 <description>Interrupt</description>
99977 <description>No Change Conflict Event/Interrupt Enable</description>
99984 <description>No interrupt</description>
99989 <description>Interrupt</description>
99998 <description>Conflict Flag</description>
100007 <description>No Change Conflict Event Flag</description>
100014 <description>No Conflict Event</description>
100019 <description>A No Change Conflict Event occured</description>
100026 <description>No Change Conflict Event Flag</description>
100033 <description>No Conflict Event</description>
100038 <description>A No Change Conflict Event occured</description>
100045 <description>No Change Conflict Event Flag</description>
100052 <description>No Conflict Event</description>
100057 <description>A No Change Conflict Event occured</description>
100064 <description>No Change Conflict Event Flag</description>
100071 <description>No Conflict Event</description>
100076 <description>A No Change Conflict Event occured</description>
100083 <description>No Change Conflict Event Flag</description>
100090 <description>No Conflict Event</description>
100095 <description>A No Change Conflict Event occured</description>
100102 <description>No Change Conflict Event Flag</description>
100109 <description>No Conflict Event</description>
100114 <description>A No Change Conflict Event occured</description>
100121 <description>No Change Conflict Event Flag</description>
100128 <description>No Conflict Event</description>
100133 <description>A No Change Conflict Event occured</description>
100140 <description>No Change Conflict Event Flag</description>
100147 <description>No Conflict Event</description>
100152 <description>A No Change Conflict Event occured</description>
100159 <description>No Change Conflict Event Flag</description>
100166 <description>No Conflict Event</description>
100171 <description>A No Change Conflict Event occured</description>
100178 <description>No Change Conflict Event Flag</description>
100185 <description>No Conflict Event</description>
100190 <description>A No Change Conflict Event occured</description>
100197 <description>Bus Error Low/Unified</description>
100204 <description>Bus Error High</description>
100213 <description>Capture Value</description>
100223 <description>Capture n Low</description>
100230 <description>Capture n High</description>
100239 <description>Match Value</description>
100249 <description>Match n Low</description>
100256 <description>Match n High</description>
100265 <description>Capture Value</description>
100275 <description>Capture n Low</description>
100282 <description>Capture n High</description>
100291 <description>Match Value</description>
100301 <description>Match n Low</description>
100308 <description>Match n High</description>
100317 <description>Capture Value</description>
100327 <description>Capture n Low</description>
100334 <description>Capture n High</description>
100343 <description>Match Value</description>
100353 <description>Match n Low</description>
100360 <description>Match n High</description>
100369 <description>Capture Value</description>
100379 <description>Capture n Low</description>
100386 <description>Capture n High</description>
100395 <description>Match Value</description>
100405 <description>Match n Low</description>
100412 <description>Match n High</description>
100421 <description>Capture Value</description>
100431 <description>Capture n Low</description>
100438 <description>Capture n High</description>
100447 <description>Match Value</description>
100457 <description>Match n Low</description>
100464 <description>Match n High</description>
100473 <description>Capture Value</description>
100483 <description>Capture n Low</description>
100490 <description>Capture n High</description>
100499 <description>Match Value</description>
100509 <description>Match n Low</description>
100516 <description>Match n High</description>
100525 <description>Capture Value</description>
100535 <description>Capture n Low</description>
100542 <description>Capture n High</description>
100551 <description>Match Value</description>
100561 <description>Match n Low</description>
100568 <description>Match n High</description>
100577 <description>Capture Value</description>
100587 <description>Capture n Low</description>
100594 <description>Capture n High</description>
100603 <description>Match Value</description>
100613 <description>Match n Low</description>
100620 <description>Match n High</description>
100629 <description>Capture Value</description>
100639 <description>Capture n Low</description>
100646 <description>Capture n High</description>
100655 <description>Match Value</description>
100665 <description>Match n Low</description>
100672 <description>Match n High</description>
100681 <description>Capture Value</description>
100691 <description>Capture n Low</description>
100698 <description>Capture n High</description>
100707 <description>Match Value</description>
100717 <description>Match n Low</description>
100724 <description>Match n High</description>
100733 <description>Capture Value</description>
100743 <description>Capture n Low</description>
100750 <description>Capture n High</description>
100759 <description>Match Value</description>
100769 <description>Match n Low</description>
100776 <description>Match n High</description>
100785 <description>Capture Value</description>
100795 <description>Capture n Low</description>
100802 <description>Capture n High</description>
100811 <description>Match Value</description>
100821 <description>Match n Low</description>
100828 <description>Match n High</description>
100837 <description>Capture Value</description>
100847 <description>Capture n Low</description>
100854 <description>Capture n High</description>
100863 <description>Match Value</description>
100873 <description>Match n Low</description>
100880 <description>Match n High</description>
100889 <description>Capture Value</description>
100899 <description>Capture n Low</description>
100906 <description>Capture n High</description>
100915 <description>Match Value</description>
100925 <description>Match n Low</description>
100932 <description>Match n High</description>
100941 <description>Capture Value</description>
100951 <description>Capture n Low</description>
100958 <description>Capture n High</description>
100967 <description>Match Value</description>
100977 <description>Match n Low</description>
100984 <description>Match n High</description>
100993 <description>Capture Value</description>
101003 <description>Capture n Low</description>
101010 <description>Capture n High</description>
101019 <description>Match Value</description>
101029 <description>Match n Low</description>
101036 <description>Match n High</description>
101047 <description>Fractional Match</description>
101056 <description>Fractional Match Low</description>
101063 <description>Fractional Match High</description>
101072 <description>Capture Control</description>
101082 <description>Capture Control n Low</description>
101089 <description>Capture Control n High</description>
101098 <description>Match Reload Value</description>
101108 <description>Reload n Low</description>
101115 <description>Reload n High</description>
101124 <description>Capture Control</description>
101134 <description>Capture Control n Low</description>
101141 <description>Capture Control n High</description>
101150 <description>Match Reload Value</description>
101160 <description>Reload n Low</description>
101167 <description>Reload n High</description>
101176 <description>Capture Control</description>
101186 <description>Capture Control n Low</description>
101193 <description>Capture Control n High</description>
101202 <description>Match Reload Value</description>
101212 <description>Reload n Low</description>
101219 <description>Reload n High</description>
101228 <description>Capture Control</description>
101238 <description>Capture Control n Low</description>
101245 <description>Capture Control n High</description>
101254 <description>Match Reload Value</description>
101264 <description>Reload n Low</description>
101271 <description>Reload n High</description>
101280 <description>Capture Control</description>
101290 <description>Capture Control n Low</description>
101297 <description>Capture Control n High</description>
101306 <description>Match Reload Value</description>
101316 <description>Reload n Low</description>
101323 <description>Reload n High</description>
101332 <description>Capture Control</description>
101342 <description>Capture Control n Low</description>
101349 <description>Capture Control n High</description>
101358 <description>Match Reload Value</description>
101368 <description>Reload n Low</description>
101375 <description>Reload n High</description>
101384 <description>Capture Control</description>
101394 <description>Capture Control n Low</description>
101401 <description>Capture Control n High</description>
101410 <description>Match Reload Value</description>
101420 <description>Reload n Low</description>
101427 <description>Reload n High</description>
101436 <description>Capture Control</description>
101446 <description>Capture Control n Low</description>
101453 <description>Capture Control n High</description>
101462 <description>Match Reload Value</description>
101472 <description>Reload n Low</description>
101479 <description>Reload n High</description>
101488 <description>Capture Control</description>
101498 <description>Capture Control n Low</description>
101505 <description>Capture Control n High</description>
101514 <description>Match Reload Value</description>
101524 <description>Reload n Low</description>
101531 <description>Reload n High</description>
101540 <description>Capture Control</description>
101550 <description>Capture Control n Low</description>
101557 <description>Capture Control n High</description>
101566 <description>Match Reload Value</description>
101576 <description>Reload n Low</description>
101583 <description>Reload n High</description>
101592 <description>Capture Control</description>
101602 <description>Capture Control n Low</description>
101609 <description>Capture Control n High</description>
101618 <description>Match Reload Value</description>
101628 <description>Reload n Low</description>
101635 <description>Reload n High</description>
101644 <description>Capture Control</description>
101654 <description>Capture Control n Low</description>
101661 <description>Capture Control n High</description>
101670 <description>Match Reload Value</description>
101680 <description>Reload n Low</description>
101687 <description>Reload n High</description>
101696 <description>Capture Control</description>
101706 <description>Capture Control n Low</description>
101713 <description>Capture Control n High</description>
101722 <description>Match Reload Value</description>
101732 <description>Reload n Low</description>
101739 <description>Reload n High</description>
101748 <description>Capture Control</description>
101758 <description>Capture Control n Low</description>
101765 <description>Capture Control n High</description>
101774 <description>Match Reload Value</description>
101784 <description>Reload n Low</description>
101791 <description>Reload n High</description>
101800 <description>Capture Control</description>
101810 <description>Capture Control n Low</description>
101817 <description>Capture Control n High</description>
101826 <description>Match Reload Value</description>
101836 <description>Reload n Low</description>
101843 <description>Reload n High</description>
101852 <description>Capture Control</description>
101862 <description>Capture Control n Low</description>
101869 <description>Capture Control n High</description>
101878 <description>Match Reload Value</description>
101888 <description>Reload n Low</description>
101895 <description>Reload n High</description>
101906 <description>Fractional Match Reload</description>
101915 <description>Reload Fractional Match Low</description>
101922 <description>Reload Fractional Match High</description>
101933 <description>no description available</description>
101937 <description>Event n State</description>
101946 <description>Event State Mask n</description>
101955 <description>Event n Control</description>
101964 <description>Match Select</description>
101971 <description>High Event</description>
101978 <description>Low Counter</description>
101983 <description>High Counter</description>
101990 <description>Input/Output Select</description>
101997 <description>Selects the inputs selected by IOSEL.</description>
102002 <description>Selects the outputs selected by IOSEL.</description>
102009 <description>Input/Output Signal Select</description>
102016 <description>Input/Output Condition</description>
102023 <description>Low</description>
102028 <description>Rise</description>
102033 <description>Fall</description>
102038 <description>High</description>
102045 <description>Combination Mode</description>
102052 …<description>OR. The event occurs when either the specified match or I/O condition occurs.</descri…
102057 <description>MATCH. Uses the specified match only.</description>
102062 <description>IO. Uses the specified I/O condition only.</description>
102067 …<description>AND. The event occurs when the specified match and I/O condition occur simultaneously…
102074 <description>State Load</description>
102081 … <description>Add. STATEV value is added into STATE (the carry-out is ignored).</description>
102086 <description>Load. STATEV value is loaded into STATE.</description>
102093 <description>State Value</description>
102100 <description>Match Mem</description>
102107 <description>Direction</description>
102114 …<description>Direction independent. This event is triggered regardless of the count direction.</de…
102119 …<description>Counting up. This event is triggered only during up-counting when BIDIR = 1.</descrip…
102124 …<description>Counting down. This event is triggered only during down-counting when BIDIR = 1.</des…
102136 <description>no description available</description>
102140 <description>Output n Set</description>
102149 <description>Set</description>
102158 <description>Output n Clear</description>
102167 <description>Clear</description>
102179 <description>Flexcomm</description>
102195 <description>Peripheral Select and Flexcomm module ID</description>
102204 <description>Peripheral Select</description>
102211 <description>No peripheral selected.</description>
102216 <description>USART function selected</description>
102221 <description>SPI function selected</description>
102226 <description>I2C</description>
102231 <description>I2S Transmit</description>
102236 <description>I2S Receive</description>
102243 <description>Lock the peripheral select</description>
102250 <description>Peripheral select can be changed by software.</description>
102255 …<description>Peripheral select is locked and cannot be changed until this Flexcomm module or the e…
102262 <description>USART present indicator</description>
102269 … <description>This Flexcomm module does not include the USART function.</description>
102274 <description>This Flexcomm module includes the USART function.</description>
102281 <description>SPI present indicator</description>
102288 <description>This Flexcomm module does not include the SPI function.</description>
102293 <description>This Flexcomm module includes the SPI function.</description>
102300 <description>I2C present indicator</description>
102307 <description>I2C Not Present</description>
102312 <description>I2C Present</description>
102319 <description>I2S Present</description>
102326 <description>I2S Not Present</description>
102331 <description>I2S Present</description>
102338 <description>Flexcomm ID</description>
102347 <description>Peripheral Identification</description>
102356 <description>Minor revision of module implementation</description>
102363 <description>Major revision of module implementation</description>
102370 <description>Module identifier for the selected function</description>
102381 <description>Flexcomm</description>
102396 <description>Flexcomm</description>
102411 <description>Flexcomm</description>
102426 <description>Flexcomm</description>
102441 <description>Flexcomm</description>
102456 <description>Flexcomm</description>
102471 <description>Flexcomm</description>
102486 <description>Flexcomm</description>
102501 <description>I2C Bus Interface</description>
102518 <description>Configuration Register</description>
102527 <description>Master Enable</description>
102534 …description>Disabled. The I2C Master function is disabled. When disabled, the Master configuration…
102539 <description>Enabled. The I2C Master function is enabled.</description>
102546 <description>Slave Enable</description>
102553 …description>Disabled. The I2C slave function is disabled. When disabled, the Slave configuration s…
102558 <description>Enabled. The I2C slave function is enabled.</description>
102565 <description>Monitor Enable</description>
102572 …description>Disabled. The I2C Monitor function is disabled. When disabled, the Monitor function co…
102577 <description>Enabled. The I2C Monitor function is enabled.</description>
102584 <description>I2C bus Time-out Enable</description>
102591 …<description>Disabled. The time-out function is disabled. When disabled, the time-out function is …
102596 …description>Enabled. The time-out function is enabled. Both types of time-out flags will be genera…
102603 <description>Monitor function Clock Stretching</description>
102610 …description>Disabled. The Monitor function will not perform clock stretching. Software or DMA may …
102615 …description>Enabled. The Monitor function will perform clock stretching, to ensure that the softwa…
102622 <description>High Speed mode Capable enable</description>
102629 <description>Fast mode Plus enable</description>
102634 <description>High Speed mode enable</description>
102643 <description>Status Register</description>
102652 <description>Master Pending</description>
102659 …<description>In progress. Communication is in progress and the Master function is busy and cannot …
102664 …description>Pending. The Master function needs software service or is in the idle state. If the ma…
102671 <description>Master State code</description>
102678 …<description>Idle. The Master function is available to be used for a new transaction.</description>
102683 …description>Receive ready. Received data is available (in Master Receiver mode). Address plus Read…
102688 …description>Transmit ready. Data can be transmitted (in Master Transmitter mode). Address plus Wri…
102693 <description>NACK Address. Slave NACKed address.</description>
102698 <description>NACK Data. Slave NACKed transmitted data.</description>
102705 <description>Master Arbitration Loss flag</description>
102712 <description>No Arbitration Loss has occurred</description>
102717 …description>Arbitration loss. The Master function has experienced an Arbitration Loss. At this poi…
102724 <description>Master Start/Stop Error flag</description>
102731 <description>No Start/Stop Error has occurred.</description>
102736 …description>The Master function has experienced a Start/Stop Error. A Start or Stop was detected a…
102743 <description>Slave Pending</description>
102750 …<description>In progress. The Slave function does not currently need software service.</descriptio…
102755 …<description>Pending. The Slave function needs software service. Information about what is needed …
102762 <description>Slave State</description>
102769 …<description>Slave address. Address plus R/W received. At least one of the 4 slave addresses has b…
102774 … <description>Slave receive. Received data is available (in Slave Receiver mode).</description>
102779 … <description>Slave transmit. Data can be transmitted (in Slave Transmitter mode).</description>
102786 <description>Slave Not Stretching</description>
102793 …<description>Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleepm…
102798 …<description>Not stretching. The slave function is not currently stretching the I2C bus clock. Dee…
102805 <description>Slave address match Index T</description>
102812 <description>Address 0. Slave address 0 was matched.</description>
102817 <description>Address 1. Slave address 1 was matched.</description>
102822 <description>Address 2. Slave address 2 was matched.</description>
102827 <description>Address 3. Slave address 3 was matched.</description>
102834 <description>Slave selected flag</description>
102841 … <description>Not selected. The Slave function is not currently selected.</description>
102846 <description>Selected. The Slave function is currently selected.</description>
102853 <description>Slave Deselected flag</description>
102860 …description>Not deselected. The Slave function has not become deselected. This does not mean that …
102865 …description>Deselected. The Slave function has become deselected. This is specifically caused by t…
102872 <description>Monitor Ready</description>
102879 … <description>No data. The Monitor function does not currently have data available.</description>
102884 … <description>Data waiting. The Monitor function has data waiting to be read.</description>
102891 <description>Monitor Overflow flag</description>
102898 <description>No overrun. Monitor data has not overrun.</description>
102903 …description>Overrun. A Monitor data overrun has occurred. An overrun can only happen when Monitor …
102910 <description>Monitor Active flag</description>
102917 … <description>Inactive. The Monitor function considers the I2C bus to be inactive.</description>
102922 … <description>Active. The Monitor function considers the I2C bus to be active.</description>
102929 <description>Monitor Idle flag</description>
102936 …<description>Not idle. The I2C bus is not idle, or MONIDLE flag has been cleared by software.</des…
102941 …<description>Idle. The I2C bus has gone idle at least once, since the last time MONIDLE flag was c…
102948 <description>Event Time-out Interrupt flag</description>
102955 <description>No time-out. I2C bus events have not caused a time-out.</description>
102960 …<description>Event time-out. The time between I2C bus events has been longer than the time specifi…
102967 <description>SCL Time-out Interrupt flag</description>
102974 <description>No time-out. SCL low time has not caused a time-out.</description>
102979 <description>Time-out. SCL low time has caused a time-out.</description>
102988 <description>Interrupt Enable Set Register</description>
102997 <description>Master Pending interrupt Enable</description>
103004 <description>Disabled. The MstPending interrupt is disabled.</description>
103009 <description>Enabled. The MstPending interrupt is enabled.</description>
103016 <description>Master Arbitration Loss interrupt Enable</description>
103023 <description>Disabled. The MstArbLoss interrupt is disabled.</description>
103028 <description>Enabled. The MstArbLoss interrupt is enabled.</description>
103035 <description>Master Start/Stop Error interrupt Enable</description>
103042 <description>Disabled. The MstStStpErr interrupt is disabled.</description>
103047 <description>Enabled. The MstStStpErr interrupt is enabled.</description>
103054 <description>Slave Pending interrupt Enable</description>
103061 <description>Disabled. The SlvPending interrupt is disabled.</description>
103066 <description>Enabled. The SlvPending interrupt is enabled.</description>
103073 <description>Slave Not Stretching interrupt Enable</description>
103080 <description>Disabled. The SlvNotStr interrupt is disabled.</description>
103085 <description>Enabled. The SlvNotStr interrupt is enabled.</description>
103092 <description>Slave Deselect interrupt Enable</description>
103099 <description>Disabled. The SlvDeSel interrupt is disabled.</description>
103104 <description>Enabled. The SlvDeSel interrupt is enabled.</description>
103111 <description>Monitor data Ready interrupt Enable</description>
103118 <description>Disabled. The MonRdy interrupt is disabled.</description>
103123 <description>Enabled. The MonRdy interrupt is enabled.</description>
103130 <description>Monitor Overrun interrupt Enable</description>
103137 <description>Disabled. The MonOv interrupt is disabled.</description>
103142 <description>Enabled. The MonOv interrupt is enabled.</description>
103149 <description>Monitor Idle interrupt Enable</description>
103156 <description>Disabled. The MonIdle interrupt is disabled.</description>
103161 <description>Enabled. The MonIdle interrupt is enabled.</description>
103168 <description>Event Time-out interrupt Enable</description>
103175 <description>Disabled. The Event time-out interrupt is disabled.</description>
103180 <description>Enabled. The Event time-out interrupt is enabled.</description>
103187 <description>SCL Time-out interrupt Enable</description>
103194 <description>Disabled. The SCL time-out interrupt is disabled.</description>
103199 <description>Enabled. The SCL time-out interrupt is enabled.</description>
103208 <description>Interrupt Enable Clear Register</description>
103217 <description>Master Pending interrupt clear</description>
103224 <description>No effect on interrupt</description>
103229 <description>Clears the interrupt bit in INTENSET register</description>
103236 <description>Master Arbitration Loss interrupt clear</description>
103243 <description>No effect on interrupt</description>
103248 <description>Clears the interrupt bit in INTENSET register</description>
103255 <description>Master Start/Stop Error interrupt clear</description>
103262 <description>No effect on interrupt</description>
103267 <description>Clears the interrupt bit in INTENSET register</description>
103274 <description>Slave Pending interrupt clear</description>
103281 <description>No effect on interrupt</description>
103286 <description>Clears the interrupt bit in INTENSET register</description>
103293 <description>Slave Not Stretching interrupt clear</description>
103300 <description>No effect on interrupt</description>
103305 <description>Clears the interrupt bit in INTENSET register</description>
103312 <description>Slave Deselect interrupt clear</description>
103319 <description>No effect on interrupt</description>
103324 <description>Clears the interrupt bit in INTENSET register</description>
103331 <description>Monitor data Ready interrupt clear</description>
103338 <description>No effect on interrupt</description>
103343 <description>Clears the interrupt bit in INTENSET register</description>
103350 <description>Monitor Overrun interrupt clear</description>
103357 <description>No effect on interrupt</description>
103362 <description>Clears the interrupt bit in INTENSET register</description>
103369 <description>Monitor Idle interrupt clear</description>
103376 <description>No effect on interrupt</description>
103381 <description>Clears the interrupt bit in INTENSET register</description>
103388 <description>Event time-out interrupt clear</description>
103395 <description>No effect on interrupt</description>
103400 <description>Clears the interrupt bit in INTENSET register</description>
103407 <description>SCL time-out interrupt clear</description>
103414 <description>No effect on interrupt</description>
103419 <description>Clears the interrupt bit in INTENSET register</description>
103428 <description>Time-out Register</description>
103437 <description>Time-out time value, the bottom 4 bits</description>
103444 <description>Time-out time value</description>
103451 … <description>A time-out will occur after 16 counts of the I2C function clock.</description>
103456 … <description>A time-out will occur after 32 counts of the I2C function clock.</description>
103461 … <description>A time-out will occur after 65,536 counts of the I2C function clock.</description>
103470 <description>Clock Divider Register</description>
103479 <description>Divider Value</description>
103486 <description>FCLK is used directly by the I2C.</description>
103491 <description>FCLK is divided by 2 before being used by the I2C.</description>
103496 <description>FCLK is divided by 3 before being used by the I2C.</description>
103501 <description>FCLK is divided by 65,536 before being used by the I2C.</description>
103510 <description>Interrupt Status Register</description>
103519 <description>Master Pending</description>
103526 <description>Not active</description>
103531 <description>Active</description>
103538 <description>Master Arbitration Loss flag</description>
103545 <description>Not active</description>
103550 <description>Active</description>
103557 <description>Master Start/Stop Error flag</description>
103564 <description>Not active</description>
103569 <description>Active</description>
103576 <description>Slave Pending</description>
103583 <description>Not active</description>
103588 <description>Active</description>
103595 <description>Slave Not Stretching status</description>
103602 <description>Not active</description>
103607 <description>Active</description>
103614 <description>Slave Deselected flag</description>
103621 <description>Not active</description>
103626 <description>Active</description>
103633 <description>Monitor Ready</description>
103640 <description>Not active</description>
103645 <description>Active</description>
103652 <description>Monitor Overflow flag</description>
103659 <description>Not active</description>
103664 <description>Active</description>
103671 <description>Monitor Idle flag</description>
103678 <description>Not active</description>
103683 <description>Active</description>
103690 <description>Event Time-out Interrupt flag</description>
103697 <description>Not active</description>
103702 <description>Active</description>
103709 <description>SCL Time-out Interrupt flag</description>
103716 <description>Not active</description>
103721 <description>Active</description>
103730 <description>Master Control Register</description>
103739 <description>Master Continue(write-only)</description>
103746 <description>No effect</description>
103751 …description>Continue. Informs the Master function to continue to the next operation. This action m…
103758 <description>Master Start control(write-only)</description>
103765 <description>No effect</description>
103770 …<description>Start. A Start will be generated on the I2C bus at the next allowed time.</descriptio…
103777 <description>Master Stop control(write-only)</description>
103784 <description>No effect</description>
103789 …description>Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a …
103796 <description>Master DMA enable</description>
103803 … <description>Disable. No DMA requests are generated for master operation.</description>
103808 …description>Enable. A DMA request is generated for I2C master data operations. When this I2C maste…
103817 <description>Master Timing Register</description>
103826 <description>Master SCL Low time</description>
103833 …<description>2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.</description>
103838 …<description>3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.</description>
103843 …<description>4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.</description>
103848 …<description>5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.</description>
103853 …<description>6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.</description>
103858 …<description>7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.</description>
103863 …<description>8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.</description>
103868 …<description>9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.</description>
103875 <description>Master SCL High time</description>
103882 …<description>2 clocks. Minimum SCL high time is 2 clocks of the I2C clock pre-divider.</descriptio…
103887 …<description>3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .</descripti…
103892 …<description>4 clocks. Minimum SCL high time is 4 clocks of the I2C clock pre-divider.</descriptio…
103897 …<description>5 clocks. Minimum SCL high time is 5 clocks of the I2C clock pre-divider.</descriptio…
103902 …<description>6 clocks. Minimum SCL high time is 6 clocks of the I2C clock pre-divider.</descriptio…
103907 …<description>7 clocks. Minimum SCL high time is 7 clocks of the I2C clock pre-divider.</descriptio…
103912 …<description>8 clocks. Minimum SCL high time is 8 clocks of the I2C clock pre-divider.</descriptio…
103917 …<description>9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.</descriptio…
103926 <description>Master Data Register</description>
103935 <description>Master function data register</description>
103944 <description>Slave Control Register</description>
103953 <description>Slave Continue</description>
103960 <description>No effect</description>
103965 …description>Continue. Informs the Slave function to continue to the next operation, by clearing th…
103972 <description>Slave NACK</description>
103979 <description>No effect</description>
103984 …<description>NACK. Causes the Slave function to NACK the master when the slave is receiving data f…
103991 <description>Slave DMA enable</description>
103998 … <description>Disabled. No DMA requests are issued for Slave mode operation.</description>
104003 …<description>Enabled. DMA requests are issued for I2C slave data transmission and reception.</desc…
104010 <description>Automatic Acknowledge</description>
104017 …description>Normal, non-automatic operation. If AUTONACK = 0, then a SlvPending interrupt is gener…
104022 …description>A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be …
104029 <description>Automatic Match Read</description>
104036 … <description>In Automatic Mode, the expected next operation is an I2C write.</description>
104041 … <description>In Automatic Mode, the expected next operation is an I2C read.</description>
104050 <description>Slave Data Register</description>
104059 <description>Slave function data register</description>
104068 <description>Slave Address Register</description>
104077 <description>Slave Address n Disable</description>
104084 <description>Enabled. Slave Address n is enabled.</description>
104089 <description>Ignored. Slave Address n is ignored.</description>
104096 <description>Slave Address.</description>
104103 <description>Automatic NACK operation</description>
104110 … <description>Normal operation, matching I2C addresses are not ignored.</description>
104115 …description>Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is se…
104124 <description>Slave Address Register</description>
104133 <description>Slave Address n Disable</description>
104140 <description>Enabled. Slave Address n is enabled.</description>
104145 <description>Ignored. Slave Address n is ignored.</description>
104152 <description>Slave Address.</description>
104159 <description>Automatic NACK operation</description>
104166 … <description>Normal operation, matching I2C addresses are not ignored.</description>
104171 …description>Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is se…
104180 <description>Slave Address Register</description>
104189 <description>Slave Address n Disable</description>
104196 <description>Enabled. Slave Address n is enabled.</description>
104201 <description>Ignored. Slave Address n is ignored.</description>
104208 <description>Slave Address.</description>
104215 <description>Automatic NACK operation</description>
104222 … <description>Normal operation, matching I2C addresses are not ignored.</description>
104227 …description>Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is se…
104236 <description>Slave Address Register</description>
104245 <description>Slave Address n Disable</description>
104252 <description>Enabled. Slave Address n is enabled.</description>
104257 <description>Ignored. Slave Address n is ignored.</description>
104264 <description>Slave Address.</description>
104271 <description>Automatic NACK operation</description>
104278 … <description>Normal operation, matching I2C addresses are not ignored.</description>
104283 …description>Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is se…
104292 <description>Slave Qualification for Address 0 Register</description>
104301 <description>Qualify mode for slave address 0</description>
104308 …<description>Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.</descripti…
104313 …<description>Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of address…
104320 <description>Slave address Qualifier for address 0</description>
104329 <description>Monitor Receiver Data Register</description>
104338 <description>Monitor function Receiver Data</description>
104345 <description>Monitor Received Start</description>
104352 …<description>No start detected. The Monitor function has not detected a Start event on the I2C bus…
104357 …<description>Start detected. The Monitor function has detected a Start event on the I2C bus.</desc…
104364 <description>Monitor Received Repeated Start</description>
104371 …<description>No repeated start detected. The Monitor function has not detected a Repeated Start ev…
104376 …<description>Repeated start detected. The Monitor function has detected a Repeated Start event on …
104383 <description>Monitor Received NACK</description>
104390 …description>Acknowledged. The data currently being provided by the Monitor function was acknowledg…
104395 …<description>Not acknowledged. The data currently being provided by the Monitor function was not a…
104404 <description>Peripheral Identification Register</description>
104413 <description>Aperture</description>
104420 <description>Minor revision of module implementation</description>
104427 <description>Major revision of module implementation</description>
104434 <description>Module identifier for the selected function</description>
104445 <description>I2C Bus Interface</description>
104461 <description>I2C Bus Interface</description>
104477 <description>I2C Bus Interface</description>
104493 <description>I2C Bus Interface</description>
104509 <description>I2C Bus Interface</description>
104525 <description>I2C Bus Interface</description>
104541 <description>I2C Bus Interface</description>
104557 <description>I2S Interface</description>
104574 <description>Configuration Register 1 for the Primary Channel Pair</description>
104583 <description>Main Enable</description>
104590 <description>Disabled</description>
104595 <description>Enabled</description>
104602 <description>Data Flow Pause</description>
104609 <description>Normal operation</description>
104614 <description>Pause</description>
104621 <description>Pair Count</description>
104628 <description>One Pair</description>
104633 <description>Two Pairs</description>
104638 <description>Three Pairs</description>
104643 <description>Four Pairs</description>
104650 <description>Master/Slave Configuration Selection</description>
104657 <description>Normal Slave Mode</description>
104662 <description>WS Synchronized Master Mode</description>
104667 <description>Master Using an Existing SCK Mode</description>
104672 <description>Normal Master Mode</description>
104679 <description>Mode</description>
104686 <description>Classic Mode</description>
104691 <description>DSP mode WS 50% duty cycle</description>
104696 <description>DSP mode WS 1 clock</description>
104701 <description>DSP mode WS 1 data</description>
104708 <description>Right Channel Low</description>
104715 <description>Right high</description>
104720 <description>Right low</description>
104727 <description>Left-Justify Data</description>
104734 <description>Right-justified</description>
104739 <description>Left-justified</description>
104746 <description>Single Channel Mode</description>
104753 <description>Dual channel</description>
104758 <description>Single channel</description>
104765 <description>PDM Data Selection</description>
104772 <description>Normal Operation</description>
104777 <description>DMIC subsystem</description>
104784 <description>SCK Polarity</description>
104791 <description>Falling edge</description>
104796 <description>Rising edge</description>
104803 <description>WS Polarity</description>
104810 <description>Not inverted</description>
104815 <description>Inverted. The WS signal is inverted.</description>
104822 <description>Data Length</description>
104829 <description>Data is 4 bits in length.</description>
104834 <description>Data is 5 bits in length.</description>
104839 <description>Data is 8 bits in length.</description>
104844 <description>Data is 31 bits in length.</description>
104849 <description>Data is 32 bits in length.</description>
104858 <description>Configuration Register 2 for the Primary Channel Pair</description>
104867 <description>Frame Length</description>
104874 <description>Frame is 4 bits in total length</description>
104879 <description>Frame is 5 bits in total length</description>
104884 <description>Frame is 512 bits in total length</description>
104889 <description>Frame is 2048 bits in total length</description>
104896 <description>Data Position</description>
104903 …<description>Data begins at bit position 0 (the first bit position) within the frame or WS phase</…
104908 … <description>Data begins at bit position 1 within the frame or WS phase</description>
104913 … <description>Data begins at bit position 2 within the frame or WS phase</description>
104922 <description>Status Register for the Primary Channel Pair</description>
104931 <description>Busy Status</description>
104938 <description>Idle</description>
104943 <description>Busy</description>
104950 <description>Slave Frame Error</description>
104958 <description>No error</description>
104963 <description>Error</description>
104970 <description>Left/Right Indication</description>
104977 <description>Left channel</description>
104982 <description>Right channel</description>
104989 <description>Data Paused</description>
104996 <description>Not Paused</description>
105001 <description>Paused</description>
105010 <description>Clock Divider</description>
105019 <description>Divider</description>
105026 <description>FCLK is used directly.</description>
105031 <description>FCLK is divided by 2.</description>
105036 <description>FCLK is divided by 3.</description>
105041 <description>FCLK is divided by 4,096.</description>
105050 <description>Configuration Register 1 for Channel Pair 1</description>
105059 <description>Pair Enable</description>
105066 <description>Disabled</description>
105071 <description>Enabled</description>
105078 <description>Single Channel Mode</description>
105085 <description>Dual Channel</description>
105090 <description>Single Channel</description>
105099 <description>Configuration Register 2 for Channel Pair 1</description>
105108 <description>Data Position</description>
105117 <description>Status Register for Channel Pair 1</description>
105126 <description>Busy Status for Channel Pair</description>
105133 … <description>Idle. The transmitter/receiver for this channel pair is currently idle.</description>
105138 …<description>Busy. The transmitter/receiver for this channel pair is currently processing data.</d…
105145 <description>Save Frame Error Flag</description>
105152 <description>No Error</description>
105157 <description>Error</description>
105164 <description>Left/Right Indication</description>
105171 <description>Left channel</description>
105176 <description>Right channel</description>
105183 <description>Data Paused Status Flag</description>
105190 …description>Data Not Paused. Data is not currently paused. A data pause may have been requested bu…
105195 … <description>Data Paused. A data pause has been requested and is now in force.</description>
105204 <description>Configuration Register 1 for Channel Pair 2</description>
105213 <description>Pair Enable</description>
105220 <description>Disabled</description>
105225 <description>Enabled</description>
105232 <description>Single Channel Mode</description>
105239 <description>Dual Channel</description>
105244 <description>Single Channel</description>
105253 <description>Configuration Register 2 for Channel Pair 2</description>
105262 <description>Data Position</description>
105271 <description>Status Register for Channel Pair 2</description>
105280 <description>Busy Status for Channel Pair</description>
105287 … <description>Idle. The transmitter/receiver for this channel pair is currently idle.</description>
105292 …<description>Busy. The transmitter/receiver for this channel pair is currently processing data.</d…
105299 <description>Save Frame Error Flag</description>
105306 <description>No Error</description>
105311 <description>Error</description>
105318 <description>Left/Right Indication</description>
105325 <description>Left channel</description>
105330 <description>Right channel</description>
105337 <description>Data Paused Status Flag</description>
105344 …description>Data Not Paused. Data is not currently paused. A data pause may have been requested bu…
105349 … <description>Data Paused. A data pause has been requested and is now in force.</description>
105358 <description>Configuration Register 1 for Channel Pair 3</description>
105367 <description>Pair Enable</description>
105374 <description>Disabled</description>
105379 <description>Enabled</description>
105386 <description>Single Channel Mode</description>
105393 <description>Dual Channel</description>
105398 <description>Single Channel</description>
105407 <description>Configuration Register 2 for Channel Pair 3</description>
105416 <description>Data Position</description>
105425 <description>Status Register for Channel Pair 3</description>
105434 <description>Busy Status for Channel Pair</description>
105441 … <description>Idle. The transmitter/receiver for this channel pair is currently idle.</description>
105446 …<description>Busy. The transmitter/receiver for this channel pair is currently processing data.</d…
105453 <description>Save Frame Error Flag</description>
105460 <description>No Error</description>
105465 <description>Error</description>
105472 <description>Left/Right Indication</description>
105479 <description>Left channel</description>
105484 <description>Right channel</description>
105491 <description>Data Paused Status Flag</description>
105498 …description>Data Not Paused. Data is not currently paused. A data pause may have been requested bu…
105503 … <description>Data Paused. A data pause has been requested and is now in force.</description>
105512 <description>FIFO Configuration and Enable</description>
105521 <description>Enable Transmit FIFO</description>
105528 <description>Disabled Transmit. The transmit FIFO is not enabled.</description>
105533 <description>Enabled transmit. The transmit FIFO is enabled.</description>
105540 <description>Enable Receive FIFO</description>
105547 <description>Disabled. The receive FIFO is not enabled.</description>
105552 <description>Enabled. The receive FIFO is enabled.</description>
105559 <description>Transmit I2S Empty 0</description>
105566 <description>Last value</description>
105571 <description>Zero</description>
105578 <description>Packing Format 48-bit data</description>
105585 <description>Bits_24</description>
105590 <description>Bits_32_16</description>
105597 <description>FIFO Size Configuration</description>
105604 <description>Size 32 Bits</description>
105609 <description>Size 48 Bits</description>
105616 <description>DMA Transmit</description>
105623 <description>Disabled</description>
105628 <description>Enabled</description>
105635 <description>DMA Receive</description>
105642 <description>Disabled</description>
105647 <description>Enabled</description>
105654 <description>Wake-up for Transmit FIFO Level</description>
105661 <description>Disabled</description>
105666 <description>Enabled</description>
105673 <description>Wake-up for Receive FIFO Level</description>
105680 … <description>Only enabled interrupts wake up the device from reduced power modes.</description>
105685 …description>A device wake-up for DMA occurs if the receive FIFO level reaches the value specified …
105692 …<description>Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is …
105699 …<description>Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is e…
105706 <description>Pop FIFO for Debug Reads</description>
105713 <description>Debug reads of the FIFO do not pop the FIFO.</description>
105718 <description>A debug read causes the FIFO to pop.</description>
105727 <description>FIFO Status</description>
105736 <description>TX FIFO Error</description>
105744 <description>No transmit FIFO error occured</description>
105749 <description>Transmit FIFO error occured</description>
105756 <description>RX FIFO Error</description>
105764 <description>No receive FIFO error occured</description>
105769 <description>Receive FIFO error occured</description>
105776 <description>Peripheral Interrupt</description>
105783 <description>No interrupt</description>
105788 <description>Interrupt</description>
105795 <description>Transmit FIFO Empty</description>
105802 <description>Transmit FIFO is not empty</description>
105807 …<description>Transmit FIFO is empty; however, the peripheral may still be processing the last piec…
105814 <description>Transmit FIFO Not Full</description>
105821 … <description>Transmit FIFO is full, and another write would cause an overflow</description>
105826 <description>Transmit FIFO is not full, so more data can be written</description>
105833 <description>Receive FIFO Not Empty</description>
105840 <description>Receive FIFO is empty</description>
105845 <description>Receive FIFO is not empty, so data can be read.</description>
105852 <description>Receive FIFO Full</description>
105859 <description>Receive FIFO is not full</description>
105864 <description>Receive FIFO is full</description>
105871 <description>Transmit FIFO Current Level</description>
105878 <description>TX FIFO is empty</description>
105885 <description>Receive FIFO Current Level</description>
105892 <description>RX FIFO is empty</description>
105899 <description>Receive FIFO Timeout</description>
105907 <description>RX FIFO on</description>
105912 …<description>RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG reg…
105921 <description>FIFO Trigger Settings</description>
105930 <description>Transmit FIFO Level Trigger Enable</description>
105937 … <description>Transmit FIFO level does not generate a FIFO level trigger.</description>
105942 …<description>An trigger generates if the transmit FIFO level reaches the value specified by the TX…
105949 <description>Receive FIFO Level Trigger Enable</description>
105956 … <description>Receive FIFO level does not generate a FIFO level trigger.</description>
105961 …<description>An trigger generates if the receive FIFO level reaches the value specified by the RXL…
105968 <description>Transmit FIFO Level Trigger Point</description>
105975 <description>Trigger when the TX FIFO becomes empty.</description>
105980 <description>Trigger when the TX FIFO level decreases to one entry.</description>
105985 …<description>Trigger when the TX FIFO level decreases to 15 entries (is no longer full).</descript…
105992 <description>Receive FIFO Level Trigger Point</description>
105999 …<description>Trigger when the RX FIFO has received 1 entry (the FIFO is no longer empty).</descrip…
106004 <description>Trigger when the RX FIFO has received 2 entries.</description>
106009 …<description>Trigger when the RX FIFO has received 16 entries (the FIFO has become full).</descrip…
106018 <description>FIFO Interrupt Enable Set and Read</description>
106027 <description>Transmit Error Interrupt</description>
106034 <description>Disabled. No interrupt generates for a transmit error.</description>
106039 … <description>Enabled. An interrupt generates when a transmit error occurs.</description>
106046 <description>Receive Error Interrupt</description>
106053 <description>Disabled</description>
106058 <description>Enabled</description>
106065 <description>Transmit Level Interrupt</description>
106072 <description>Disabled</description>
106077 <description>Enabled</description>
106084 <description>Receive Level Interrupt</description>
106091 <description>Disabled</description>
106096 <description>Enabled</description>
106103 <description>Receive Timeout</description>
106110 <description>No RX interrupt will be generated.</description>
106115 <description>Asserts RX interrupt if RX FIFO Timeout event occurs.</description>
106124 <description>FIFO Interrupt Enable Clear and Read</description>
106133 <description>Transmit Error Interrupt Clear</description>
106140 <description>Interrupt is not cleared.</description>
106145 <description>Interrupt is cleared.</description>
106152 <description>Receive Error Interrupt Clear</description>
106159 <description>Interrupt is not cleared.</description>
106164 <description>Interrupt is cleared.</description>
106171 <description>Transmit Level Interrupt Clear</description>
106178 <description>Interrupt is not cleared.</description>
106183 <description>Interrupt is cleared.</description>
106190 <description>Receive Level Interrupt Clear</description>
106197 <description>Interrupt is not cleared.</description>
106202 <description>Interrupt is cleared.</description>
106209 <description>Receive Timeout</description>
106216 <description>No effect</description>
106221 <description>Clear the interrupt</description>
106230 <description>FIFO Interrupt Status</description>
106239 <description>TX FIFO Error Interrupt Status</description>
106246 <description>Not pending</description>
106251 <description>Pending</description>
106258 <description>RX FIFO Error Interrupt Status</description>
106265 <description>Not pending</description>
106270 <description>Pending</description>
106277 <description>Transmit FIFO Level Interrupt Status</description>
106284 <description>Not pending</description>
106289 <description>Pending</description>
106296 <description>Receive FIFO Level Interrupt Status</description>
106303 <description>Not pending</description>
106308 <description>Pending</description>
106315 <description>Peripheral Interrupt Status</description>
106322 <description>Not pending</description>
106327 <description>Pending</description>
106334 <description>Receive Timeout Status</description>
106341 <description>Not pending</description>
106346 <description>Pending</description>
106355 <description>FIFO Write Data</description>
106364 <description>Transmit Data to the FIFO</description>
106373 <description>FIFO Write Data for Upper Data Bits</description>
106382 <description>Transmit Data to the FIFO</description>
106391 <description>FIFO Read Data</description>
106400 <description>Received Data from the FIFO</description>
106409 <description>FIFO Read Data for Upper Data Bits</description>
106418 <description>Received Data from the FIFO</description>
106427 <description>FIFO Data Read with No FIFO Pop</description>
106436 <description>Received Data from the FIFO</description>
106445 <description>FIFO Data Read for Upper Data Bits with No FIFO Pop</description>
106454 <description>Received Data from the FIFO</description>
106463 <description>FIFO Size Register</description>
106472 <description>Provides the size of the FIFO for software</description>
106481 <description>FIFO Receive Timeout Configuration</description>
106490 <description>Receive Timeout Counter Clock Prescaler</description>
106497 <description>Receive Timeout Value</description>
106504 <description>Receive Timeout Enable</description>
106511 <description>Disable RX FIFO timeout</description>
106516 <description>Enable RX FIFO timeout</description>
106523 <description>Receive Timeout Continue On Write</description>
106530 …<description>RX FIFO timeout counter is reset every time data is transferred from the peripheral i…
106535 …<description>RX FIFO timeout counter is not reset every time data is transferred from the peripher…
106542 <description>Receive Timeout Continue On Empty</description>
106549 … <description>RX FIFO timeout counter is reset when the RX FIFO becomes empty.</description>
106554 … <description>RX FIFO timeout counter is not reset when the RX FIFO becomes empty.</description>
106563 <description>FIFO Receive Timeout Counter</description>
106572 <description>Current RX FIFO timeout counter value</description>
106581 <description>I2S Module Identification</description>
106590 <description>Aperture</description>
106597 <description>Minor Revision</description>
106604 <description>Major Revision</description>
106611 <description>Module Identifier</description>
106622 <description>I2S Interface</description>
106638 <description>I2S Interface</description>
106654 <description>I2S Interface</description>
106670 <description>I2S Interface</description>
106686 <description>I2S Interface</description>
106702 <description>I2S Interface</description>
106718 <description>I2S Interface</description>
106734 <description>Serial Peripheral Interfaces (SPI)</description>
106751 <description>Configuration Register</description>
106760 <description>SPI Enable</description>
106767 …<description>Disabled. The SPI is disabled and the internal state machine and counters are reset.<…
106772 <description>Enabled. The SPI is enabled for operation.</description>
106779 <description>Master Mode Select</description>
106786 …<description>Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are i…
106791 …<description>Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are…
106798 <description>LSB First Mode Enable</description>
106805 … <description>Standard. Data is transmitted and received in standard MSB-first order.</description>
106810 … <description>Reverse. Data is transmitted and received in reverse order (LSB first).</description>
106817 <description>Clock Phase Select</description>
106824 <description>Change</description>
106829 <description>Capture</description>
106836 <description>Clock Polarity Select</description>
106843 … <description>Low. The rest state of the clock (between transfers) is low.</description>
106848 … <description>High. The rest state of the clock (between transfers) is high.</description>
106855 <description>Loopback Mode Enable</description>
106862 <description>Disabled</description>
106867 <description>Enabled</description>
106874 <description>SSEL0 Polarity Select</description>
106881 <description>Low. The SSEL0 pin is active low.</description>
106886 <description>High. The SSEL0 pin is active high.</description>
106893 <description>SSEL1 Polarity Select</description>
106900 <description>Low. The SSEL1 pin is active low.</description>
106905 <description>High. The SSEL1 pin is active high.</description>
106912 <description>SSEL2 Polarity Select</description>
106919 <description>Low. The SSEL2 pin is active low.</description>
106924 <description>High. The SSEL2 pin is active high.</description>
106931 <description>SSEL3 Polarity Select</description>
106938 <description>Low. The SSEL3 pin is active low.</description>
106943 <description>High. The SSEL3 pin is active high.</description>
106952 <description>Delay Register</description>
106961 <description>Pre-Delay</description>
106968 <description>No additional time is inserted</description>
106973 <description>1 SPI clock time is inserted</description>
106978 <description>2 SPI clock times are inserted</description>
106983 <description>15 SPI clock times are inserted</description>
106990 <description>Post-Delay</description>
106997 <description>No additional time is inserted</description>
107002 <description>1 SPI clock time is inserted</description>
107007 <description>2 SPI clock times are inserted</description>
107012 <description>15 SPI clock times are inserted</description>
107019 <description>Frame Delay</description>
107026 <description>No additional time is inserted</description>
107031 <description>1 SPI clock time is inserted</description>
107036 <description>2 SPI clock times are inserted</description>
107041 <description>15 SPI clock times are inserted</description>
107048 <description>Transfer Delay</description>
107055 …<description>The minimum time that SSEL is deasserted is 1 SPI clock time (zero-added time)</descr…
107060 … <description>The minimum time that SSEL is deasserted is 2 SPI clock times</description>
107065 … <description>The minimum time that SSEL is deasserted is 3 SPI clock times</description>
107070 … <description>The minimum time that SSEL is deasserted is 16 SPI clock times</description>
107079 <description>Status Register</description>
107088 <description>Slave Select Assert</description>
107095 <description>Slave Select Deassert</description>
107102 <description>Stalled Status Flag</description>
107109 <description>End Transfer Control</description>
107116 <description>Master Idle Status Flag</description>
107125 <description>Interrupt Enable Register</description>
107134 <description>Slave Select Assert Interrupt Enable</description>
107141 …<description>Disabled. No interrupt will be generated when any Slave Select transitions from deass…
107146 …<description>Enabled. An interrupt will be generated when any Slave Select transitions from deasse…
107153 <description>Slave Select Deassert Interrupt Enable</description>
107160 …<description>Disabled. No interrupt will be generated when all asserted Slave Selects transition t…
107165 …<description>Enabled. An interrupt will be generated when all asserted Slave Selects transition to…
107172 <description>Master Idle Interrupt Enable</description>
107179 … <description>No interrupt will be generated when the SPI master function is idle.</description>
107184 …<description>An interrupt will be generated when the SPI master function is fully idle.</descripti…
107193 <description>Interrupt Enable Clear Register</description>
107202 <description>Slave Select Assert Interrupt Enable</description>
107209 <description>No effect</description>
107214 … <description>Clear the Slave Select Assert Interrupt Enable bit (INTENSET[SSAEN])</description>
107221 <description>Slave Select Deassert Interrupt Enable</description>
107228 <description>No effect</description>
107233 … <description>Clear the Slave Select Deassert Interrupt Enable bit (INTENSET[SSDEN])</description>
107240 <description>Master Idle Interrupt Enable</description>
107247 <description>No effect</description>
107252 … <description>Clear the Master Idle Interrupt Enable bit (INTENSET[MSTIDLE])</description>
107261 <description>Clock Divider Register</description>
107270 <description>Rate Divider Value</description>
107279 <description>Interrupt Status Register</description>
107288 <description>Slave Select Assert Interrupt</description>
107295 <description>Disabled</description>
107300 <description>Enabled</description>
107307 <description>Slave Select Deassert Interrupt</description>
107314 <description>Disabled</description>
107319 <description>Enabled</description>
107326 <description>Master Idle Status Flag Interrupt</description>
107333 <description>Disabled</description>
107338 <description>Enabled</description>
107347 <description>FIFO Configuration Register</description>
107356 <description>Enable the Transmit FIFO</description>
107363 <description>The transmit FIFO is not enabled</description>
107368 <description>The transmit FIFO is enabled</description>
107375 <description>Enable the Receive FIFO</description>
107382 <description>The receive FIFO is not enabled</description>
107387 <description>The receive FIFO is enabled</description>
107394 <description>FIFO Size Configuration</description>
107401 <description>FIFO is configured as 16 entries of 8 bits.</description>
107406 <description>FIFO is configured as 8 entries of 16 bits.</description>
107411 <description>Not used</description>
107416 <description>Not used</description>
107423 <description>DMA Configuration for Transmit</description>
107430 <description>DMA is not used for the transmit function</description>
107435 …description>Issues DMA request for the transmit function if the FIFO is not full. Generally, data …
107442 <description>DMA Configuration for Receive</description>
107449 <description>DMA is not used for the receive function.</description>
107454 …description>Issues a DMA request for the receive function if the FIFO is not empty. Generally, dat…
107461 <description>Wake-up for Transmit FIFO Level</description>
107468 …<description>Only enabled interrupts will wake up the device form reduced power modes</description>
107473 …description>A device wake-up for DMA will occur if the transmit FIFO level reaches the value speci…
107480 <description>Wake-up for Receive FIFO Level</description>
107487 …<description>Only enabled interrupts will wake up the device form reduced power modes.</descriptio…
107492 …description>A device wake-up for DMA will occur if the receive FIFO level reaches the value specif…
107499 <description>Empty Command for the Transmit FIFO</description>
107506 <description>No effect</description>
107511 <description>The TX FIFO is emptied</description>
107518 <description>Empty Command for the Receive FIFO</description>
107525 <description>No effect</description>
107530 <description>The RX FIFO is emptied</description>
107537 <description>Pop FIFO for Debug Reads</description>
107544 <description>Debug reads of the FIFO do not pop the FIFO</description>
107549 <description>A debug read will cause the FIFO to pop</description>
107558 <description>FIFO Status Register</description>
107567 <description>TX FIFO Error</description>
107574 <description>A transmit FIFO error has not occurred.</description>
107579 …description>A transmit FIFO error has occurred. This error could be an overflow caused by pushing …
107586 <description>RX FIFO Error</description>
107593 <description>A receive FIFO overflow has not occurred</description>
107598 …<description>A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO…
107605 <description>Peripheral Interrupt</description>
107612 <description>The peripheral function has not asserted an interrupt</description>
107617 …description>Indicates that the peripheral function has asserted an interrupt. More information can…
107624 <description>Transmit FIFO Empty</description>
107631 <description>The transmit FIFO is not empty</description>
107636 …<description>The transmit FIFO is empty, although the peripheral may still be processing the last …
107643 <description>Transmit FIFO is Not Full</description>
107650 … <description>The transmit FIFO is full and another write would cause it to overflow</description>
107655 … <description>The transmit FIFO is not full, so more data can be written</description>
107662 <description>Receive FIFO is Not Empty</description>
107669 <description>When 0, the receive FIFO is empty</description>
107674 … <description>When 1, the receive FIFO is not empty, so data can be read</description>
107681 <description>Receive FIFO is Full</description>
107688 <description>The receive FIFO is not full</description>
107693 …<description>The receive FIFO is full. To prevent the peripheral from causing an overflow, data sh…
107700 <description>Transmit FIFO Current Level</description>
107707 <description>Receive FIFO Current Level</description>
107714 <description>Receive FIFO Timeout</description>
107722 <description>RX FIFO on</description>
107727 …<description>RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG reg…
107736 <description>FIFO Trigger Register</description>
107745 <description>Transmit FIFO Level Trigger Enable</description>
107752 … <description>Transmit FIFO level does not generate a FIFO level trigger</description>
107757 …<description>An trigger will be generated if the transmit FIFO level reaches the value specified b…
107764 <description>Receive FIFO Level Trigger Enable</description>
107771 … <description>Receive FIFO level does not generate a FIFO level trigger</description>
107776 …<description>An trigger will be generated if the receive FIFO level reaches the value specified by…
107783 <description>Transmit FIFO Level Trigger Point</description>
107790 <description>Trigger when the TX FIFO becomes empty</description>
107795 <description>Trigger when the TX FIFO level decreases to 1 entry</description>
107800 …<description>Trigger when the TX FIFO level decreases to 15 entries (is no longer full)</descripti…
107807 <description>Receive FIFO Level Trigger Point</description>
107814 … <description>Trigger when the RX FIFO has received 1 entry (is no longer empty)</description>
107819 <description>Trigger when the RX FIFO has received 2 entries</description>
107824 … <description>Trigger when the RX FIFO has received 16 entries (has become full)</description>
107833 <description>FIFO Interrupt Enable Register</description>
107842 <description>TX Error Interrupt Enable</description>
107849 <description>No interrupt will be generated for a transmit error</description>
107854 … <description>An interrupt will be generated when a transmit error occurs</description>
107861 <description>Receive Error Interrupt Enable</description>
107868 <description>No interrupt will be generated for a receive error</description>
107873 … <description>An interrupt will be generated when a receive error occurs</description>
107880 <description>Transmit FIFO Level Interrupt Enable</description>
107887 … <description>No interrupt will be generated based on the TX FIFO level</description>
107892 …description>If FIFOTRIG[TXLVLENA]=1, then an interrupt will be generated when the TX FIFO level de…
107899 <description>Receive FIFO Level Interrupt Enable</description>
107906 … <description>No interrupt will be generated based on the RX FIFO level</description>
107911 …description>If FIFOTRIG[RXLVLENA]=1, then an interrupt will be generated when the RX FIFO level in…
107918 <description>Receive Timeout</description>
107925 <description>No RX interrupt will be generated.</description>
107930 <description>Asserts RX interrupt if RX FIFO Timeout event occurs.</description>
107939 <description>FIFO Interrupt Enable Clear Register</description>
107948 <description>TX Error Interrupt Enable</description>
107955 <description>No effect</description>
107960 … <description>Clear the TX Error Interrupt Enable bit FIFOINTENSET[TXERR]</description>
107967 <description>Receive Error Interrupt Enable</description>
107974 <description>No effect</description>
107979 … <description>Clear the Receive Error Interrupt Enable bit FIFOINTENSET[RXERR]</description>
107986 <description>Transmit FIFO Level Interrupt Enable</description>
107993 <description>No effect</description>
107998 … <description>Clear the Transmit FIFO Level Interrupt Enable bit FIFOINTENSET[TXLVL]</description>
108005 <description>Receive FIFO Level Interrupt Enable</description>
108012 <description>No effect</description>
108017 … <description>Clear the Receive FIFO Level Interrupt Enable bit FIFOINTENSET[RXLVL]</description>
108024 <description>Receive Timeout</description>
108031 <description>No effect</description>
108036 <description>Clear the interrupt</description>
108045 <description>FIFO Interrupt Status Register</description>
108054 <description>TX FIFO Error Interrupt Status</description>
108061 <description>Not pending</description>
108066 <description>Pending</description>
108073 <description>RX FIFO Error Interrupt Status</description>
108080 <description>Not pending</description>
108085 <description>Pending</description>
108092 <description>Transmit FIFO Level Interrupt Status</description>
108099 <description>Not pending</description>
108104 <description>Pending</description>
108111 <description>Receive FIFO Level Interrupt Status</description>
108118 <description>Not pending</description>
108123 <description>Pending</description>
108130 <description>Peripheral Interrupt Status</description>
108137 <description>Not pending</description>
108142 <description>Pending</description>
108149 <description>Receive Timeout Status</description>
108156 <description>Not pending</description>
108161 <description>Pending</description>
108170 <description>FIFO Write Data Register</description>
108179 <description>Transmit Data to the FIFO</description>
108186 <description>Transmit Slave Select 0</description>
108193 <description>SSEL0 is asserted</description>
108198 <description>SSEL0 is not asserted</description>
108205 <description>Transmit Slave Select 1</description>
108212 <description>SSEL1 is asserted</description>
108217 <description>SSEL1 is not asserted</description>
108224 <description>Transmit Slave Select 2</description>
108231 <description>SSEL2 is asserted</description>
108236 <description>SSEL2 is not asserted</description>
108243 <description>Transmit Slave Select 3</description>
108250 <description>SSEL3 is asserted</description>
108255 <description>SSEL3 is not asserted</description>
108262 <description>End of Transfer</description>
108269 …description>SSEL is not deasserted. This piece of data is not treated as the end of a transfer. SS…
108274 …description>SSEL is deasserted. This piece of data is treated as the end of a transfer. SSEL will …
108281 <description>End of Frame</description>
108288 …<description>Data not EOF. This piece of data transmitted is not treated as the end of a frame.</d…
108293 …description>Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay…
108300 <description>Receive Ignore</description>
108307 …description>Read received data. Received data must be read, to allow transmission to proceed. SPI …
108312 …description>Ignore received data. Received data is ignored, allowing transmission without reading …
108319 <description>Transmit Ignore</description>
108326 <description>Write transmit data</description>
108331 <description>Ignore transmit data</description>
108338 <description>Data Length</description>
108345 <description>Data transfer is 4 bits in length</description>
108350 <description>Data transfer is 5 bits in length</description>
108355 <description>Data transfer is 16 bits in length</description>
108364 <description>FIFO Read Data Register</description>
108373 <description>Received Data from the FIFO</description>
108380 <description>Slave Select 0 for Receive</description>
108387 <description>Slave Select 0 is active</description>
108392 <description>Slave Select 0 is not active</description>
108399 <description>Slave Select 1 for Receive</description>
108406 <description>Slave Select 1 is active</description>
108411 <description>Slave Select 1 is not active</description>
108418 <description>Slave Select 2 for Receive</description>
108425 <description>Slave Select 2 is active</description>
108430 <description>Slave Select 2 is not active</description>
108437 <description>Slave Select 3 for Receive</description>
108444 <description>Slave Select 3 is active</description>
108449 <description>Slave Select 3 is not active</description>
108456 <description>Start of Transfer Flag</description>
108463 …<description>This is not the 1st data after the SSELs went from deasserted to asserted</descriptio…
108468 …description>This is the 1st data after the SSELs went from deasserted to asserted (i.e., any previ…
108477 <description>FIFO Data Read with no FIFO Pop Register</description>
108486 <description>Received Data from the FIFO</description>
108493 <description>Slave Select 0 for Receive</description>
108500 <description>Not selected</description>
108505 <description>Selected</description>
108512 <description>Slave Select 1 for Receive</description>
108519 <description>Not selected</description>
108524 <description>Selected</description>
108531 <description>Slave Select 2 for Receive</description>
108538 <description>Not selected</description>
108543 <description>Selected</description>
108550 <description>Slave Select 3 for Receive</description>
108557 <description>Not selected</description>
108562 <description>Selected</description>
108569 <description>Start of Transfer Flag</description>
108576 <description>Not active</description>
108581 <description>Active</description>
108590 <description>FIFO Size Register</description>
108599 <description>FIFO Size</description>
108608 <description>FIFO Receive Timeout Configuration</description>
108617 <description>Receive Timeout Counter Clock Prescaler</description>
108624 <description>Receive Timeout Value</description>
108631 <description>Receive Timeout Enable</description>
108638 <description>Disable RX FIFO timeout</description>
108643 <description>Enable RX FIFO timeout</description>
108650 <description>Receive Timeout Continue On Write</description>
108657 …<description>RX FIFO timeout counter is reset every time data is transferred from the peripheral i…
108662 …<description>RX FIFO timeout counter is not reset every time data is transferred from the peripher…
108669 <description>Receive Timeout Continue On Empty</description>
108676 … <description>RX FIFO timeout counter is reset when the RX FIFO becomes empty.</description>
108681 … <description>RX FIFO timeout counter is not reset when the RX FIFO becomes empty.</description>
108690 <description>FIFO Receive Timeout Counter</description>
108699 <description>Current RX FIFO timeout counter value</description>
108708 <description>Peripheral Identification Register</description>
108717 <description>Aperture</description>
108724 <description>Minor revision of module implementation</description>
108731 <description>Major revision of module implementation</description>
108738 <description>Module identifier for the selected function</description>
108749 <description>Serial Peripheral Interfaces (SPI)</description>
108765 <description>Serial Peripheral Interfaces (SPI)</description>
108781 <description>Serial Peripheral Interfaces (SPI)</description>
108797 <description>Serial Peripheral Interfaces (SPI)</description>
108813 <description>Serial Peripheral Interfaces (SPI)</description>
108829 <description>Serial Peripheral Interfaces (SPI)</description>
108845 <description>Serial Peripheral Interfaces (SPI)</description>
108861 <description>Serial Peripheral Interfaces (SPI)</description>
108877 <description>Flexcomm USART</description>
108894 <description>USART Configuration</description>
108903 <description>USART Enable</description>
108910 <description>Disabled</description>
108915 <description>Enabled. The USART is enabled for operation.</description>
108922 <description>Data Length. Selects the data size for the USART.</description>
108929 <description>7 bit data length</description>
108934 <description>8 bit data length</description>
108939 …<description>9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See…
108946 … <description>Parity Select. Selects what type of parity is used by the USART.</description>
108953 <description>No parity</description>
108958 <description>Even parity</description>
108963 <description>Odd parity</description>
108970 <description>Stop Length</description>
108977 <description>1 stop bit</description>
108982 …<description>2 stop bits. This setting should be used only for asynchronous communication.</descri…
108989 <description>Mode 32 kHz</description>
108996 <description>Disabled. USART uses standard clocking.</description>
109001 <description>Enabled</description>
109008 <description>LIN Break Mode Enable</description>
109015 … <description>Disabled. Break detect and generate is configured for normal operation.</description>
109020 … <description>Enabled. Break detect and generate is configured for LIN bus operation.</description>
109027 <description>CTS Enable</description>
109034 …<description>No flow control. The transmitter does not receive any automatic flow control signal.<…
109039 …<description>Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback m…
109046 … <description>Synchronous Enable. Selects synchronous or asynchronous operation.</description>
109053 <description>Asynchronous mode</description>
109058 <description>Synchronous mode</description>
109065 <description>Clock Polarity</description>
109072 … <description>Falling edge. RXD is sampled on the falling edge of SCLK.</description>
109077 <description>Rising edge. RXD is sampled on the rising edge of SCLK.</description>
109084 <description>Synchronous mode Master Select</description>
109091 … <description>Slave. When synchronous mode is enabled, the USART is a slave.</description>
109096 … <description>Master. When synchronous mode is enabled, the USART is a master.</description>
109103 <description>Loopback Mode</description>
109110 <description>Normal operation</description>
109115 <description>Loopback mode</description>
109122 <description>Output Enable Turnaround Time Enable for RS-485 Operation.</description>
109129 <description>Disabled</description>
109134 <description>Enabled</description>
109141 <description>Automatic Address Matching Enable</description>
109148 <description>Disabled</description>
109153 <description>Enabled</description>
109160 <description>Output Enable Select</description>
109167 … <description>Standard. The RTS signal is used as the standard flow control function.</description>
109172 …<description>RS-485. The RTS signal is configured to provide an output enable signal to control an…
109179 <description>Output Enable Polarity</description>
109186 … <description>Low. If selected by OESEL, the output enable is active low.</description>
109191 … <description>High. If selected by OESEL, the output enable is active high.</description>
109198 <description>Receive Data Polarity</description>
109205 <description>Standard</description>
109210 <description>Inverted</description>
109217 <description>Transmit data polarity</description>
109224 <description>Standard</description>
109229 <description>Inverted</description>
109238 <description>USART Control</description>
109247 <description>Break Enable</description>
109254 <description>Normal operation</description>
109259 <description>Continuous break</description>
109266 <description>Enable Address Detect Mode</description>
109273 <description>Disabled. The USART presents all incoming data.</description>
109278 <description>Enabled</description>
109285 <description>Transmit Disable</description>
109292 <description>Not disabled. USART transmitter is not disabled.</description>
109297 …description>Disabled. USART transmitter is disabled after any character currently being transmitte…
109304 <description>Continuous Clock Generation</description>
109311 <description>Clock on character</description>
109316 <description>Continuous clock</description>
109323 <description>Clear Continuous Clock</description>
109330 <description>No effect. No effect on the CC bit.</description>
109335 <description>Auto-clear</description>
109342 <description>Autobaud Enable</description>
109349 <description>Disabled</description>
109354 <description>Enabled</description>
109363 <description>USART Status</description>
109372 <description>Receiver Idle</description>
109379 <description>The receiver is currently receiving data.</description>
109384 <description>The receiver is not currently receiving data.</description>
109391 <description>Transmitter Idle</description>
109398 <description>The transmitter is currently sending data.</description>
109403 <description>The transmitter is not currently sending data.</description>
109410 <description>CTS value</description>
109417 <description>Delta CTS</description>
109425 <description>Transmitter Disabled Status Flag</description>
109432 …<description>Not Idle. Indicates that the USART transmitter is NOT fully idle after being disabled…
109437 …<description>Idle. Indicates that the USART transmitter is fully idle after being disabled (CTL[TX…
109444 <description>Received Break</description>
109451 <description>Delta Received Break</description>
109459 <description>Start</description>
109467 <description>Framing Error Interrupt Flag</description>
109475 <description>Parity Error Interrupt Flag</description>
109483 <description>Received Noise Interrupt Flag</description>
109491 <description>Auto Baud Error</description>
109501 <description>Interrupt Enable Read and Set for USART (not FIFO) Status</description>
109510 <description>Transmit Idle Flag</description>
109517 …<description>Enables an interrupt when the transmitter becomes idle (STAT[TXIDLE] = 1).</descripti…
109524 <description>Delta CTS Input Flag</description>
109531 …<description>Enables an interrupt when there is a change in the state of the CTS input.</descripti…
109538 <description>Transmit Disabled Flag</description>
109545 …description>Enables an interrupt when the transmitter is fully disabled as indicated by the STAT[T…
109552 <description>Delta Receive Break Enable</description>
109559 <description>Enable</description>
109566 <description>Start Enable</description>
109573 … <description>Enables an interrupt when a received start bit has been detected.</description>
109580 <description>Frame Error Enable</description>
109587 … <description>Enables an interrupt when a framing error has been detected.</description>
109594 <description>Parity Error Enble</description>
109601 … <description>Enables an interrupt when a parity error has been detected.</description>
109608 <description>Receive Noise Enable</description>
109615 …<description>Enables an interrupt when noise is detected. See the description of the CTL[RXNOISEIN…
109622 <description>Auto Baud Error Enable</description>
109629 <description>Enables an interrupt when an auto baud error occurs.</description>
109638 <description>Interrupt Enable Clear</description>
109647 <description>Transmit Idle Clear</description>
109654 <description>Delta CTS Clear</description>
109661 <description>Transmit Disable Clear</description>
109668 <description>Delta Receive Break Clear</description>
109675 <description>Start Clear</description>
109682 <description>Frame Error Clear</description>
109689 <description>Parity Error Clear</description>
109696 <description>Receive Noise Clear</description>
109703 <description>Auto Baud Error Clear</description>
109712 <description>Baud Rate Generator</description>
109721 <description>Baud Rate Generator Value</description>
109728 <description>FCLK is used directly by the USART function.</description>
109733 <description>FCLK is divided by 2 before use by the USART function.</description>
109738 <description>FCLK is divided by 3 before use by the USART function.</description>
109743 … <description>FCLK is divided by 65,536 before use by the USART function.</description>
109752 <description>Interrupt Status</description>
109761 <description>Transmitter Idle Flag</description>
109768 <description>Delta CTS Change Flag</description>
109775 <description>Transmitter Disabled Interrupt Flag</description>
109782 <description>Delta Receiver Break Change Flag</description>
109789 <description>Start Detected on Receiver Flag</description>
109796 <description>Framing Error Interrupt Flag</description>
109803 <description>Parity Error Interrupt Flag</description>
109810 <description>Received Noise Interrupt Flag</description>
109817 <description>Auto Baud Error Interrupt Flag</description>
109826 <description>Oversample Selection Register for Asynchronous Communication</description>
109835 <description>Oversample Selection Value</description>
109842 <description>Not supported</description>
109847 <description>Not supported</description>
109852 <description>Not supported</description>
109857 <description>Not supported</description>
109862 … <description>5 function clocks are used to transmit and receive each data bit.</description>
109867 … <description>6 function clocks are used to transmit and receive each data bit.</description>
109872 … <description>16 function clocks are used to transmit and receive each data bit.</description>
109881 <description>Address Register for Automatic Address Matching</description>
109890 <description>Address</description>
109899 <description>FIFO Configuration</description>
109908 <description>Enable the Transmit FIFO.</description>
109915 <description>The transmit FIFO is not enabled.</description>
109920 <description>The transmit FIFO is enabled.</description>
109927 <description>Enable the Receive FIFO</description>
109934 <description>The receive FIFO is not enabled.</description>
109939 <description>The receive FIFO is enabled.</description>
109946 <description>FIFO Size Configuration</description>
109953 <description>FIFO is configured as 16 entries of 8 bits.</description>
109958 <description>Not used</description>
109963 <description>Not used</description>
109968 <description>Not used</description>
109975 <description>DMA Configuration for Transmit</description>
109982 <description>DMA is not used for the transmit function.</description>
109987 …description>Triggers DMA for the transmit function if the FIFO is not full. Generally, data interr…
109994 <description>DMA Configuration for Receive</description>
110001 <description>DMA is not used for the receive function.</description>
110006 …description>Triggers DMA for the receive function if the FIFO is not empty. Generally, data interr…
110013 <description>Wake-up for Transmit FIFO Level</description>
110020 … <description>Only enabled interrupts will wake up the device from low power modes.</description>
110025 …description>A device wake-up for DMA will occur if the transmit FIFO level reaches the value speci…
110032 <description>Wake-up for Receive FIFO Level</description>
110039 … <description>Only enabled interrupts will wake up the device from low power modes.</description>
110044 …description>A device wake-up for DMA will occur if the receive FIFO level reaches the value specif…
110051 <description>Empty Command for the Transmit FIFO</description>
110058 <description>No effect</description>
110063 <description>The TX FIFO is emptied.</description>
110070 <description>Empty Command for the Receive FIFO</description>
110077 <description>No effect</description>
110082 <description>The RX FIFO is emptied.</description>
110089 <description>Pop FIFO for Debug Reads</description>
110096 <description>Debug reads of the FIFO do not pop the FIFO.</description>
110101 <description>A debug read will cause the FIFO to pop.</description>
110110 <description>FIFO Status</description>
110119 <description>TX FIFO Error</description>
110126 <description>A transmit FIFO error has not occurred.</description>
110131 …description>A transmit FIFO error has occurred. This error could be an overflow caused by pushing …
110138 <description>RX FIFO Error</description>
110145 <description>A receive FIFO overflow has not occurred</description>
110150 …<description>A receive FIFO overflow has occurred, caused by software or DMA not emptying the FIFO…
110157 <description>Peripheral Interrupt</description>
110164 <description>No Peripheral Interrupt</description>
110169 <description>Peripheral Interrupt</description>
110176 <description>Transmit FIFO Empty</description>
110183 <description>The transmit FIFO is not empty.</description>
110188 …<description>The transmit FIFO is empty, although the peripheral may still be processing the last …
110195 <description>Transmit FIFO is Not Full</description>
110202 … <description>The transmit FIFO is full and another write would cause it to overflow.</description>
110207 … <description>The transmit FIFO is not full, so more data can be written.</description>
110214 <description>Receive FIFO is Not Empty</description>
110221 <description>The receive FIFO is empty.</description>
110226 <description>The receive FIFO is not empty, so data can be read.</description>
110233 <description>Receive FIFO is Full</description>
110240 <description>The receive FIFO is not full.</description>
110245 <description>The receive FIFO is full.</description>
110252 <description>Transmit FIFO Current Level</description>
110259 <description>Receive FIFO Current Level</description>
110266 <description>Receive FIFO Timeout</description>
110274 <description>RX FIFO on</description>
110279 …<description>RX FIFO has timed out, based on the timeout configuration in the FIFORXTIMEOUTCFG reg…
110288 <description>FIFO Trigger Settings for Interrupt and DMA Request</description>
110297 <description>Transmit FIFO Level Trigger Enable.</description>
110304 … <description>Transmit FIFO level does not generate a FIFO level trigger.</description>
110309 …<description>A trigger will be generated if the transmit FIFO level reaches the value specified by…
110316 <description>Receive FIFO Level Trigger Enable</description>
110323 … <description>Receive FIFO level does not generate a FIFO level trigger.</description>
110328 …<description>An trigger will be generated if the receive FIFO level reaches the value specified by…
110335 <description>Transmit FIFO Level Trigger Point</description>
110342 <description>Trigger when the TX FIFO becomes empty</description>
110347 <description>Trigger when the TX FIFO level decreases to 1 entry</description>
110352 …<description>Trigger when the TX FIFO level decreases to 15 entries (is no longer full)</descripti…
110359 <description>Receive FIFO Level Trigger Point</description>
110366 … <description>Trigger when the RX FIFO has received 1 entry (is no longer empty)</description>
110371 <description>Trigger when the RX FIFO has received 2 entries</description>
110376 … <description>Trigger when the RX FIFO has received 16 entries (has become full)</description>
110385 <description>FIFO Interrupt Enable</description>
110394 <description>Transmit Error Interrupt Enable</description>
110401 <description>No interrupt will be generated for a transmit error.</description>
110406 … <description>An interrupt will be generated when a transmit error occurs.</description>
110413 <description>Receive Error Interrupt Enable</description>
110420 <description>No interrupt will be generated for a receive error.</description>
110425 … <description>An interrupt will be generated when a receive error occurs.</description>
110432 <description>Transmit FIFO Level Interrupt Enable</description>
110439 … <description>No interrupt will be generated based on the TX FIFO level.</description>
110444 …description>If FIFOTRIG[TXLVLENA] = 1, then an interrupt will be generated when the TX FIFO level …
110451 <description>Receive FIFO Level Interrupt Enable</description>
110458 … <description>No interrupt will be generated based on the RX FIFO level.</description>
110463 …description>If FIFOTRIG[RXLVLENA] = 1, an interrupt will be generated when the when the RX FIFO le…
110470 <description>Receive Timeout</description>
110477 <description>No RX interrupt will be generated.</description>
110482 <description>Asserts RX interrupt if RX FIFO Timeout event occurs.</description>
110491 <description>FIFO Interrupt Enable Clear</description>
110500 <description>Transmit Error Interrupt Enable</description>
110507 <description>No effect</description>
110512 <description>Clear the interrupt</description>
110519 <description>Receive Error Interrupt Enable</description>
110526 <description>No effect</description>
110531 <description>Clear the interrupt</description>
110538 <description>Transmit FIFO Level Interrupt Enable</description>
110545 <description>No effect</description>
110550 <description>Clear the interrupt</description>
110557 <description>Receive FIFO Level Interrupt Enable</description>
110564 <description>No effect</description>
110569 <description>Clear the interrupt</description>
110576 <description>Receive Timeout</description>
110583 <description>No effect</description>
110588 <description>Clear the interrupt</description>
110597 <description>FIFO Interrupt Status</description>
110606 <description>TX FIFO Error Interrupt Status</description>
110613 <description>Not pending</description>
110618 <description>Pending</description>
110625 <description>RX FIFO Error Interrupt Status</description>
110632 <description>Not pending</description>
110637 <description>Pending</description>
110644 <description>Transmit FIFO Level Interrupt Status</description>
110651 <description>Not pending</description>
110656 <description>Pending</description>
110663 <description>Receive FIFO Level Interrupt Status</description>
110670 <description>Not pending</description>
110675 <description>Pending</description>
110682 <description>Peripheral Interrupt Status</description>
110689 <description>Not pending</description>
110694 <description>Pending</description>
110701 <description>Receive Timeout Status</description>
110708 <description>Not pending</description>
110713 <description>Pending</description>
110722 <description>FIFO Write Data</description>
110731 <description>Transmit data to the FIFO</description>
110740 <description>FIFO Read Data</description>
110749 <description>Received Data from the FIFO</description>
110756 <description>Framing Error Status Flag</description>
110763 <description>Parity Error Status Flag</description>
110770 <description>Received Noise Flag</description>
110779 <description>FIFO Data Read with No FIFO Pop</description>
110788 <description>Received Data from the FIFO</description>
110795 <description>Framing Error Status Flag</description>
110802 <description>Parity Error Status Flag</description>
110809 <description>Received Noise Flag</description>
110818 <description>FIFO Size</description>
110827 <description>FIFO Size</description>
110836 <description>FIFO Receive Timeout Configuration</description>
110845 <description>Receive Timeout Counter Clock Prescaler</description>
110852 <description>Receive Timeout Value</description>
110859 <description>Receive Timeout Enable</description>
110866 <description>Disable RX FIFO timeout</description>
110871 <description>Enable RX FIFO timeout</description>
110878 <description>Receive Timeout Continue On Write</description>
110885 …<description>RX FIFO timeout counter is reset every time data is transferred from the peripheral i…
110890 …<description>RX FIFO timeout counter is not reset every time data is transferred from the peripher…
110897 <description>Receive Timeout Continue On Empty</description>
110904 … <description>RX FIFO timeout counter is reset when the RX FIFO becomes empty.</description>
110909 … <description>RX FIFO timeout counter is not reset when the RX FIFO becomes empty.</description>
110918 <description>FIFO Receive Timeout Counter</description>
110927 <description>Current RX FIFO timeout counter value</description>
110936 <description>Peripheral Identification</description>
110945 <description>Aperture</description>
110952 <description>Minor revision of module implementation</description>
110959 <description>Major revision of module implementation</description>
110966 <description>Module identifier for the selected function</description>
110977 <description>Flexcomm USART</description>
110993 <description>Flexcomm USART</description>
111009 <description>Flexcomm USART</description>
111025 <description>Flexcomm USART</description>
111041 <description>Flexcomm USART</description>
111057 <description>Flexcomm USART</description>
111073 <description>Flexcomm USART</description>
111089 <description>Inter-CPU Mailbox</description>
111100 <description>Cortex-M33 (CPU0) interrupt register</description>
111109 <description>Interrupt request</description>
111118 <description>Cortex-M33 (CPU0) interrupt set register</description>
111127 <description>Set bits in IRQ1.</description>
111136 <description>Cortex-M33 (CPU0) interrupt clear register</description>
111145 <description>Clear bits in IRQ1.</description>
111154 <description>Mutual exclusion register</description>
111163 … <description>Cleared when read, set when written. See usage description above.</description>
111174 <description>GPIO General Purpose I/O (GPIO)</description>
111187 <description>no description available</description>
111193 <description>Byte pin registers for all port GPIO pins</description>
111202 <description>Port Byte</description>
111214 <description>no description available</description>
111220 <description>Word pin registers for all port GPIO pins</description>
111229 <description>PWORD</description>
111241 <description>Port direction</description>
111250 <description>Selects pin direction for pin PIOa_b.</description>
111258 <description>Input</description>
111263 <description>Output</description>
111270 <description>Selects pin direction for pin PIOa_b.</description>
111278 <description>Input</description>
111283 <description>Output</description>
111290 <description>Selects pin direction for pin PIOa_b.</description>
111298 <description>Input</description>
111303 <description>Output</description>
111310 <description>Selects pin direction for pin PIOa_b.</description>
111318 <description>Input</description>
111323 <description>Output</description>
111330 <description>Selects pin direction for pin PIOa_b.</description>
111338 <description>Input</description>
111343 <description>Output</description>
111350 <description>Selects pin direction for pin PIOa_b.</description>
111358 <description>Input</description>
111363 <description>Output</description>
111370 <description>Selects pin direction for pin PIOa_b.</description>
111378 <description>Input</description>
111383 <description>Output</description>
111390 <description>Selects pin direction for pin PIOa_b.</description>
111398 <description>Input</description>
111403 <description>Output</description>
111410 <description>Selects pin direction for pin PIOa_b.</description>
111418 <description>Input</description>
111423 <description>Output</description>
111430 <description>Selects pin direction for pin PIOa_b.</description>
111438 <description>Input</description>
111443 <description>Output</description>
111450 <description>Selects pin direction for pin PIOa_b.</description>
111458 <description>Input</description>
111463 <description>Output</description>
111470 <description>Selects pin direction for pin PIOa_b.</description>
111478 <description>Input</description>
111483 <description>Output</description>
111490 <description>Selects pin direction for pin PIOa_b.</description>
111498 <description>Input</description>
111503 <description>Output</description>
111510 <description>Selects pin direction for pin PIOa_b.</description>
111518 <description>Input</description>
111523 <description>Output</description>
111530 <description>Selects pin direction for pin PIOa_b.</description>
111538 <description>Input</description>
111543 <description>Output</description>
111550 <description>Selects pin direction for pin PIOa_b.</description>
111558 <description>Input</description>
111563 <description>Output</description>
111570 <description>Selects pin direction for pin PIOa_b.</description>
111578 <description>Input</description>
111583 <description>Output</description>
111590 <description>Selects pin direction for pin PIOa_b.</description>
111598 <description>Input</description>
111603 <description>Output</description>
111610 <description>Selects pin direction for pin PIOa_b.</description>
111618 <description>Input</description>
111623 <description>Output</description>
111630 <description>Selects pin direction for pin PIOa_b.</description>
111638 <description>Input</description>
111643 <description>Output</description>
111650 <description>Selects pin direction for pin PIOa_b.</description>
111658 <description>Input</description>
111663 <description>Output</description>
111670 <description>Selects pin direction for pin PIOa_b.</description>
111678 <description>Input</description>
111683 <description>Output</description>
111690 <description>Selects pin direction for pin PIOa_b.</description>
111698 <description>Input</description>
111703 <description>Output</description>
111710 <description>Selects pin direction for pin PIOa_b.</description>
111718 <description>Input</description>
111723 <description>Output</description>
111730 <description>Selects pin direction for pin PIOa_b.</description>
111738 <description>Input</description>
111743 <description>Output</description>
111750 <description>Selects pin direction for pin PIOa_b.</description>
111758 <description>Input</description>
111763 <description>Output</description>
111770 <description>Selects pin direction for pin PIOa_b.</description>
111778 <description>Input</description>
111783 <description>Output</description>
111790 <description>Selects pin direction for pin PIOa_b.</description>
111798 <description>Input</description>
111803 <description>Output</description>
111810 <description>Selects pin direction for pin PIOa_b.</description>
111818 <description>Input</description>
111823 <description>Output</description>
111830 <description>Selects pin direction for pin PIOa_b.</description>
111838 <description>Input</description>
111843 <description>Output</description>
111850 <description>Selects pin direction for pin PIOa_b.</description>
111858 <description>Input</description>
111863 <description>Output</description>
111870 <description>Selects pin direction for pin PIOa_b.</description>
111878 <description>Input</description>
111883 <description>Output</description>
111894 <description>Port mask</description>
111903 <description>Port Mask</description>
111910 <description>Read MPIN: pin state; write MPIN: load output bit</description>
111915 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
111922 <description>Port Mask</description>
111929 <description>Read MPIN: pin state; write MPIN: load output bit</description>
111934 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
111941 <description>Port Mask</description>
111948 <description>Read MPIN: pin state; write MPIN: load output bit</description>
111953 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
111960 <description>Port Mask</description>
111967 <description>Read MPIN: pin state; write MPIN: load output bit</description>
111972 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
111979 <description>Port Mask</description>
111986 <description>Read MPIN: pin state; write MPIN: load output bit</description>
111991 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
111998 <description>Port Mask</description>
112005 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112010 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112017 <description>Port Mask</description>
112024 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112029 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112036 <description>Port Mask</description>
112043 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112048 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112055 <description>Port Mask</description>
112062 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112067 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112074 <description>Port Mask</description>
112081 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112086 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112093 <description>Port Mask</description>
112100 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112105 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112112 <description>Port Mask</description>
112119 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112124 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112131 <description>Port Mask</description>
112138 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112143 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112150 <description>Port Mask</description>
112157 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112162 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112169 <description>Port Mask</description>
112176 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112181 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112188 <description>Port Mask</description>
112195 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112200 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112207 <description>Port Mask</description>
112214 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112219 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112226 <description>Port Mask</description>
112233 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112238 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112245 <description>Port Mask</description>
112252 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112257 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112264 <description>Port Mask</description>
112271 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112276 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112283 <description>Port Mask</description>
112290 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112295 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112302 <description>Port Mask</description>
112309 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112314 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112321 <description>Port Mask</description>
112328 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112333 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112340 <description>Port Mask</description>
112347 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112352 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112359 <description>Port Mask</description>
112366 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112371 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112378 <description>Port Mask</description>
112385 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112390 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112397 <description>Port Mask</description>
112404 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112409 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112416 <description>Port Mask</description>
112423 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112428 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112435 <description>Port Mask</description>
112442 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112447 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112454 <description>Port Mask</description>
112461 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112466 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112473 <description>Port Mask</description>
112480 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112485 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112492 <description>Port Mask</description>
112499 <description>Read MPIN: pin state; write MPIN: load output bit</description>
112504 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
112515 <description>Port pin</description>
112524 <description>Port pins</description>
112531 <description>Read- pin is low; Write- clear output bit</description>
112536 <description>Read- pin is high; Write- set output bit</description>
112543 <description>Port pins</description>
112550 <description>Read- pin is low; Write- clear output bit</description>
112555 <description>Read- pin is high; Write- set output bit</description>
112562 <description>Port pins</description>
112569 <description>Read- pin is low; Write- clear output bit</description>
112574 <description>Read- pin is high; Write- set output bit</description>
112581 <description>Port pins</description>
112588 <description>Read- pin is low; Write- clear output bit</description>
112593 <description>Read- pin is high; Write- set output bit</description>
112600 <description>Port pins</description>
112607 <description>Read- pin is low; Write- clear output bit</description>
112612 <description>Read- pin is high; Write- set output bit</description>
112619 <description>Port pins</description>
112626 <description>Read- pin is low; Write- clear output bit</description>
112631 <description>Read- pin is high; Write- set output bit</description>
112638 <description>Port pins</description>
112645 <description>Read- pin is low; Write- clear output bit</description>
112650 <description>Read- pin is high; Write- set output bit</description>
112657 <description>Port pins</description>
112664 <description>Read- pin is low; Write- clear output bit</description>
112669 <description>Read- pin is high; Write- set output bit</description>
112676 <description>Port pins</description>
112683 <description>Read- pin is low; Write- clear output bit</description>
112688 <description>Read- pin is high; Write- set output bit</description>
112695 <description>Port pins</description>
112702 <description>Read- pin is low; Write- clear output bit</description>
112707 <description>Read- pin is high; Write- set output bit</description>
112714 <description>Port pins</description>
112721 <description>Read- pin is low; Write- clear output bit</description>
112726 <description>Read- pin is high; Write- set output bit</description>
112733 <description>Port pins</description>
112740 <description>Read- pin is low; Write- clear output bit</description>
112745 <description>Read- pin is high; Write- set output bit</description>
112752 <description>Port pins</description>
112759 <description>Read- pin is low; Write- clear output bit</description>
112764 <description>Read- pin is high; Write- set output bit</description>
112771 <description>Port pins</description>
112778 <description>Read- pin is low; Write- clear output bit</description>
112783 <description>Read- pin is high; Write- set output bit</description>
112790 <description>Port pins</description>
112797 <description>Read- pin is low; Write- clear output bit</description>
112802 <description>Read- pin is high; Write- set output bit</description>
112809 <description>Port pins</description>
112816 <description>Read- pin is low; Write- clear output bit</description>
112821 <description>Read- pin is high; Write- set output bit</description>
112828 <description>Port pins</description>
112835 <description>Read- pin is low; Write- clear output bit</description>
112840 <description>Read- pin is high; Write- set output bit</description>
112847 <description>Port pins</description>
112854 <description>Read- pin is low; Write- clear output bit</description>
112859 <description>Read- pin is high; Write- set output bit</description>
112866 <description>Port pins</description>
112873 <description>Read- pin is low; Write- clear output bit</description>
112878 <description>Read- pin is high; Write- set output bit</description>
112885 <description>Port pins</description>
112892 <description>Read- pin is low; Write- clear output bit</description>
112897 <description>Read- pin is high; Write- set output bit</description>
112904 <description>Port pins</description>
112911 <description>Read- pin is low; Write- clear output bit</description>
112916 <description>Read- pin is high; Write- set output bit</description>
112923 <description>Port pins</description>
112930 <description>Read- pin is low; Write- clear output bit</description>
112935 <description>Read- pin is high; Write- set output bit</description>
112942 <description>Port pins</description>
112949 <description>Read- pin is low; Write- clear output bit</description>
112954 <description>Read- pin is high; Write- set output bit</description>
112961 <description>Port pins</description>
112968 <description>Read- pin is low; Write- clear output bit</description>
112973 <description>Read- pin is high; Write- set output bit</description>
112980 <description>Port pins</description>
112987 <description>Read- pin is low; Write- clear output bit</description>
112992 <description>Read- pin is high; Write- set output bit</description>
112999 <description>Port pins</description>
113006 <description>Read- pin is low; Write- clear output bit</description>
113011 <description>Read- pin is high; Write- set output bit</description>
113018 <description>Port pins</description>
113025 <description>Read- pin is low; Write- clear output bit</description>
113030 <description>Read- pin is high; Write- set output bit</description>
113037 <description>Port pins</description>
113044 <description>Read- pin is low; Write- clear output bit</description>
113049 <description>Read- pin is high; Write- set output bit</description>
113056 <description>Port pins</description>
113063 <description>Read- pin is low; Write- clear output bit</description>
113068 <description>Read- pin is high; Write- set output bit</description>
113075 <description>Port pins</description>
113082 <description>Read- pin is low; Write- clear output bit</description>
113087 <description>Read- pin is high; Write- set output bit</description>
113094 <description>Port pins</description>
113101 <description>Read- pin is low; Write- clear output bit</description>
113106 <description>Read- pin is high; Write- set output bit</description>
113113 <description>Port pins</description>
113120 <description>Read- pin is low; Write- clear output bit</description>
113125 <description>Read- pin is high; Write- set output bit</description>
113136 <description>Masked Port Pin</description>
113145 <description>Mask bits for port pins</description>
113152 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113157 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113164 <description>Mask bits for port pins</description>
113171 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113176 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113183 <description>Mask bits for port pins</description>
113190 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113195 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113202 <description>Mask bits for port pins</description>
113209 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113214 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113221 <description>Mask bits for port pins</description>
113228 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113233 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113240 <description>Mask bits for port pins</description>
113247 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113252 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113259 <description>Mask bits for port pins</description>
113266 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113271 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113278 <description>Mask bits for port pins</description>
113285 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113290 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113297 <description>Mask bits for port pins</description>
113304 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113309 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113316 <description>Mask bits for port pins</description>
113323 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113328 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113335 <description>Mask bits for port pins</description>
113342 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113347 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113354 <description>Mask bits for port pins</description>
113361 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113366 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113373 <description>Mask bits for port pins</description>
113380 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113385 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113392 <description>Mask bits for port pins</description>
113399 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113404 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113411 <description>Mask bits for port pins</description>
113418 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113423 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113430 <description>Mask bits for port pins</description>
113437 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113442 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113449 <description>Mask bits for port pins</description>
113456 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113461 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113468 <description>Mask bits for port pins</description>
113475 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113480 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113487 <description>Mask bits for port pins</description>
113494 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113499 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113506 <description>Mask bits for port pins</description>
113513 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113518 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113525 <description>Mask bits for port pins</description>
113532 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113537 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113544 <description>Mask bits for port pins</description>
113551 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113556 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113563 <description>Mask bits for port pins</description>
113570 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113575 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113582 <description>Mask bits for port pins</description>
113589 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113594 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113601 <description>Mask bits for port pins</description>
113608 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113613 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113620 <description>Mask bits for port pins</description>
113627 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113632 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113639 <description>Mask bits for port pins</description>
113646 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113651 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113658 <description>Mask bits for port pins</description>
113665 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113670 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113677 <description>Mask bits for port pins</description>
113684 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113689 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113696 <description>Mask bits for port pins</description>
113703 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113708 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113715 <description>Mask bits for port pins</description>
113722 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113727 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113734 <description>Mask bits for port pins</description>
113741 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
113746 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
113757 <description>Port set</description>
113766 <description>Read or set output bits</description>
113774 <description>Read- output bit; write- no operation</description>
113779 <description>Read- output bit; write- set output bit</description>
113790 <description>Port clear</description>
113799 <description>Clear output bits</description>
113807 <description>No operation</description>
113812 <description>Clears output bit</description>
113819 <description>Clear output bits</description>
113827 <description>No operation</description>
113832 <description>Clears output bit</description>
113839 <description>Clear output bits</description>
113847 <description>No operation</description>
113852 <description>Clears output bit</description>
113859 <description>Clear output bits</description>
113867 <description>No operation</description>
113872 <description>Clears output bit</description>
113879 <description>Clear output bits</description>
113887 <description>No operation</description>
113892 <description>Clears output bit</description>
113899 <description>Clear output bits</description>
113907 <description>No operation</description>
113912 <description>Clears output bit</description>
113919 <description>Clear output bits</description>
113927 <description>No operation</description>
113932 <description>Clears output bit</description>
113939 <description>Clear output bits</description>
113947 <description>No operation</description>
113952 <description>Clears output bit</description>
113959 <description>Clear output bits</description>
113967 <description>No operation</description>
113972 <description>Clears output bit</description>
113979 <description>Clear output bits</description>
113987 <description>No operation</description>
113992 <description>Clears output bit</description>
113999 <description>Clear output bits</description>
114007 <description>No operation</description>
114012 <description>Clears output bit</description>
114019 <description>Clear output bits</description>
114027 <description>No operation</description>
114032 <description>Clears output bit</description>
114039 <description>Clear output bits</description>
114047 <description>No operation</description>
114052 <description>Clears output bit</description>
114059 <description>Clear output bits</description>
114067 <description>No operation</description>
114072 <description>Clears output bit</description>
114079 <description>Clear output bits</description>
114087 <description>No operation</description>
114092 <description>Clears output bit</description>
114099 <description>Clear output bits</description>
114107 <description>No operation</description>
114112 <description>Clears output bit</description>
114119 <description>Clear output bits</description>
114127 <description>No operation</description>
114132 <description>Clears output bit</description>
114139 <description>Clear output bits</description>
114147 <description>No operation</description>
114152 <description>Clears output bit</description>
114159 <description>Clear output bits</description>
114167 <description>No operation</description>
114172 <description>Clears output bit</description>
114179 <description>Clear output bits</description>
114187 <description>No operation</description>
114192 <description>Clears output bit</description>
114199 <description>Clear output bits</description>
114207 <description>No operation</description>
114212 <description>Clears output bit</description>
114219 <description>Clear output bits</description>
114227 <description>No operation</description>
114232 <description>Clears output bit</description>
114239 <description>Clear output bits</description>
114247 <description>No operation</description>
114252 <description>Clears output bit</description>
114259 <description>Clear output bits</description>
114267 <description>No operation</description>
114272 <description>Clears output bit</description>
114279 <description>Clear output bits</description>
114287 <description>No operation</description>
114292 <description>Clears output bit</description>
114299 <description>Clear output bits</description>
114307 <description>No operation</description>
114312 <description>Clears output bit</description>
114319 <description>Clear output bits</description>
114327 <description>No operation</description>
114332 <description>Clears output bit</description>
114339 <description>Clear output bits</description>
114347 <description>No operation</description>
114352 <description>Clears output bit</description>
114359 <description>Clear output bits</description>
114367 <description>No operation</description>
114372 <description>Clears output bit</description>
114379 <description>Clear output bits</description>
114387 <description>No operation</description>
114392 <description>Clears output bit</description>
114399 <description>Clear output bits</description>
114407 <description>No operation</description>
114412 <description>Clears output bit</description>
114419 <description>Clear output bits</description>
114427 <description>No operation</description>
114432 <description>Clears output bit</description>
114443 <description>Port toggle</description>
114452 <description>Toggle output bits</description>
114459 <description>No operation</description>
114464 <description>Toggle output bit</description>
114471 <description>Toggle output bits</description>
114478 <description>No operation</description>
114483 <description>Toggle output bit</description>
114490 <description>Toggle output bits</description>
114497 <description>No operation</description>
114502 <description>Toggle output bit</description>
114509 <description>Toggle output bits</description>
114516 <description>No operation</description>
114521 <description>Toggle output bit</description>
114528 <description>Toggle output bits</description>
114535 <description>No operation</description>
114540 <description>Toggle output bit</description>
114547 <description>Toggle output bits</description>
114554 <description>No operation</description>
114559 <description>Toggle output bit</description>
114566 <description>Toggle output bits</description>
114573 <description>No operation</description>
114578 <description>Toggle output bit</description>
114585 <description>Toggle output bits</description>
114592 <description>No operation</description>
114597 <description>Toggle output bit</description>
114604 <description>Toggle output bits</description>
114611 <description>No operation</description>
114616 <description>Toggle output bit</description>
114623 <description>Toggle output bits</description>
114630 <description>No operation</description>
114635 <description>Toggle output bit</description>
114642 <description>Toggle output bits</description>
114649 <description>No operation</description>
114654 <description>Toggle output bit</description>
114661 <description>Toggle output bits</description>
114668 <description>No operation</description>
114673 <description>Toggle output bit</description>
114680 <description>Toggle output bits</description>
114687 <description>No operation</description>
114692 <description>Toggle output bit</description>
114699 <description>Toggle output bits</description>
114706 <description>No operation</description>
114711 <description>Toggle output bit</description>
114718 <description>Toggle output bits</description>
114725 <description>No operation</description>
114730 <description>Toggle output bit</description>
114737 <description>Toggle output bits</description>
114744 <description>No operation</description>
114749 <description>Toggle output bit</description>
114756 <description>Toggle output bits</description>
114763 <description>No operation</description>
114768 <description>Toggle output bit</description>
114775 <description>Toggle output bits</description>
114782 <description>No operation</description>
114787 <description>Toggle output bit</description>
114794 <description>Toggle output bits</description>
114801 <description>No operation</description>
114806 <description>Toggle output bit</description>
114813 <description>Toggle output bits</description>
114820 <description>No operation</description>
114825 <description>Toggle output bit</description>
114832 <description>Toggle output bits</description>
114839 <description>No operation</description>
114844 <description>Toggle output bit</description>
114851 <description>Toggle output bits</description>
114858 <description>No operation</description>
114863 <description>Toggle output bit</description>
114870 <description>Toggle output bits</description>
114877 <description>No operation</description>
114882 <description>Toggle output bit</description>
114889 <description>Toggle output bits</description>
114896 <description>No operation</description>
114901 <description>Toggle output bit</description>
114908 <description>Toggle output bits</description>
114915 <description>No operation</description>
114920 <description>Toggle output bit</description>
114927 <description>Toggle output bits</description>
114934 <description>No operation</description>
114939 <description>Toggle output bit</description>
114946 <description>Toggle output bits</description>
114953 <description>No operation</description>
114958 <description>Toggle output bit</description>
114965 <description>Toggle output bits</description>
114972 <description>No operation</description>
114977 <description>Toggle output bit</description>
114984 <description>Toggle output bits</description>
114991 <description>No operation</description>
114996 <description>Toggle output bit</description>
115003 <description>Toggle output bits</description>
115010 <description>No operation</description>
115015 <description>Toggle output bit</description>
115022 <description>Toggle output bits</description>
115029 <description>No operation</description>
115034 <description>Toggle output bit</description>
115041 <description>Toggle output bits</description>
115048 <description>No operation</description>
115053 <description>Toggle output bit</description>
115064 <description>Port direction set</description>
115073 <description>Direction set bits for Port pins</description>
115081 <description>No operation</description>
115086 <description>Sets direction bit</description>
115093 <description>Direction set bits for Port pins</description>
115101 <description>No operation</description>
115106 <description>Sets direction bit</description>
115113 <description>Direction set bits for Port pins</description>
115121 <description>No operation</description>
115126 <description>Sets direction bit</description>
115133 <description>Direction set bits for Port pins</description>
115141 <description>No operation</description>
115146 <description>Sets direction bit</description>
115153 <description>Direction set bits for Port pins</description>
115161 <description>No operation</description>
115166 <description>Sets direction bit</description>
115173 <description>Direction set bits for Port pins</description>
115181 <description>No operation</description>
115186 <description>Sets direction bit</description>
115193 <description>Direction set bits for Port pins</description>
115201 <description>No operation</description>
115206 <description>Sets direction bit</description>
115213 <description>Direction set bits for Port pins</description>
115221 <description>No operation</description>
115226 <description>Sets direction bit</description>
115233 <description>Direction set bits for Port pins</description>
115241 <description>No operation</description>
115246 <description>Sets direction bit</description>
115253 <description>Direction set bits for Port pins</description>
115261 <description>No operation</description>
115266 <description>Sets direction bit</description>
115273 <description>Direction set bits for Port pins</description>
115281 <description>No operation</description>
115286 <description>Sets direction bit</description>
115293 <description>Direction set bits for Port pins</description>
115301 <description>No operation</description>
115306 <description>Sets direction bit</description>
115313 <description>Direction set bits for Port pins</description>
115321 <description>No operation</description>
115326 <description>Sets direction bit</description>
115333 <description>Direction set bits for Port pins</description>
115341 <description>No operation</description>
115346 <description>Sets direction bit</description>
115353 <description>Direction set bits for Port pins</description>
115361 <description>No operation</description>
115366 <description>Sets direction bit</description>
115373 <description>Direction set bits for Port pins</description>
115381 <description>No operation</description>
115386 <description>Sets direction bit</description>
115393 <description>Direction set bits for Port pins</description>
115401 <description>No operation</description>
115406 <description>Sets direction bit</description>
115413 <description>Direction set bits for Port pins</description>
115421 <description>No operation</description>
115426 <description>Sets direction bit</description>
115433 <description>Direction set bits for Port pins</description>
115441 <description>No operation</description>
115446 <description>Sets direction bit</description>
115453 <description>Direction set bits for Port pins</description>
115461 <description>No operation</description>
115466 <description>Sets direction bit</description>
115473 <description>Direction set bits for Port pins</description>
115481 <description>No operation</description>
115486 <description>Sets direction bit</description>
115493 <description>Direction set bits for Port pins</description>
115501 <description>No operation</description>
115506 <description>Sets direction bit</description>
115513 <description>Direction set bits for Port pins</description>
115521 <description>No operation</description>
115526 <description>Sets direction bit</description>
115533 <description>Direction set bits for Port pins</description>
115541 <description>No operation</description>
115546 <description>Sets direction bit</description>
115553 <description>Direction set bits for Port pins</description>
115561 <description>No operation</description>
115566 <description>Sets direction bit</description>
115573 <description>Direction set bits for Port pins</description>
115581 <description>No operation</description>
115586 <description>Sets direction bit</description>
115593 <description>Direction set bits for Port pins</description>
115601 <description>No operation</description>
115606 <description>Sets direction bit</description>
115613 <description>Direction set bits for Port pins</description>
115621 <description>No operation</description>
115626 <description>Sets direction bit</description>
115633 <description>Direction set bits for Port pins</description>
115641 <description>No operation</description>
115646 <description>Sets direction bit</description>
115653 <description>Direction set bits for Port pins</description>
115661 <description>No operation</description>
115666 <description>Sets direction bit</description>
115673 <description>Direction set bits for Port pins</description>
115681 <description>No operation</description>
115686 <description>Sets direction bit</description>
115693 <description>Direction set bits for Port pins</description>
115701 <description>No operation</description>
115706 <description>Sets direction bit</description>
115717 <description>Port direction clear</description>
115726 <description>Clear direction bits.</description>
115734 <description>No operation</description>
115739 <description>Clears direction bits</description>
115746 <description>Clear direction bits.</description>
115754 <description>No operation</description>
115759 <description>Clears direction bits</description>
115766 <description>Clear direction bits.</description>
115774 <description>No operation</description>
115779 <description>Clears direction bits</description>
115786 <description>Clear direction bits.</description>
115794 <description>No operation</description>
115799 <description>Clears direction bits</description>
115806 <description>Clear direction bits.</description>
115814 <description>No operation</description>
115819 <description>Clears direction bits</description>
115826 <description>Clear direction bits.</description>
115834 <description>No operation</description>
115839 <description>Clears direction bits</description>
115846 <description>Clear direction bits.</description>
115854 <description>No operation</description>
115859 <description>Clears direction bits</description>
115866 <description>Clear direction bits.</description>
115874 <description>No operation</description>
115879 <description>Clears direction bits</description>
115886 <description>Clear direction bits.</description>
115894 <description>No operation</description>
115899 <description>Clears direction bits</description>
115906 <description>Clear direction bits.</description>
115914 <description>No operation</description>
115919 <description>Clears direction bits</description>
115926 <description>Clear direction bits.</description>
115934 <description>No operation</description>
115939 <description>Clears direction bits</description>
115946 <description>Clear direction bits.</description>
115954 <description>No operation</description>
115959 <description>Clears direction bits</description>
115966 <description>Clear direction bits.</description>
115974 <description>No operation</description>
115979 <description>Clears direction bits</description>
115986 <description>Clear direction bits.</description>
115994 <description>No operation</description>
115999 <description>Clears direction bits</description>
116006 <description>Clear direction bits.</description>
116014 <description>No operation</description>
116019 <description>Clears direction bits</description>
116026 <description>Clear direction bits.</description>
116034 <description>No operation</description>
116039 <description>Clears direction bits</description>
116046 <description>Clear direction bits.</description>
116054 <description>No operation</description>
116059 <description>Clears direction bits</description>
116066 <description>Clear direction bits.</description>
116074 <description>No operation</description>
116079 <description>Clears direction bits</description>
116086 <description>Clear direction bits.</description>
116094 <description>No operation</description>
116099 <description>Clears direction bits</description>
116106 <description>Clear direction bits.</description>
116114 <description>No operation</description>
116119 <description>Clears direction bits</description>
116126 <description>Clear direction bits.</description>
116134 <description>No operation</description>
116139 <description>Clears direction bits</description>
116146 <description>Clear direction bits.</description>
116154 <description>No operation</description>
116159 <description>Clears direction bits</description>
116166 <description>Clear direction bits.</description>
116174 <description>No operation</description>
116179 <description>Clears direction bits</description>
116186 <description>Clear direction bits.</description>
116194 <description>No operation</description>
116199 <description>Clears direction bits</description>
116206 <description>Clear direction bits.</description>
116214 <description>No operation</description>
116219 <description>Clears direction bits</description>
116226 <description>Clear direction bits.</description>
116234 <description>No operation</description>
116239 <description>Clears direction bits</description>
116246 <description>Clear direction bits.</description>
116254 <description>No operation</description>
116259 <description>Clears direction bits</description>
116266 <description>Clear direction bits.</description>
116274 <description>No operation</description>
116279 <description>Clears direction bits</description>
116286 <description>Clear direction bits.</description>
116294 <description>No operation</description>
116299 <description>Clears direction bits</description>
116306 <description>Clear direction bits.</description>
116314 <description>No operation</description>
116319 <description>Clears direction bits</description>
116326 <description>Clear direction bits.</description>
116334 <description>No operation</description>
116339 <description>Clears direction bits</description>
116346 <description>Clear direction bits.</description>
116354 <description>No operation</description>
116359 <description>Clears direction bits</description>
116370 <description>Port direction toggle</description>
116379 <description>Toggle direction bits.</description>
116386 <description>No operation</description>
116391 <description>Toggles direction bit</description>
116402 <description>Interrupt A enable control</description>
116411 <description>Interrupt A enable bits.</description>
116418 <description>Pin does not contribute to GPIO interrupt A</description>
116423 <description>Pin contributes to GPIO interrupt A</description>
116430 <description>Interrupt A enable bits.</description>
116437 <description>Pin does not contribute to GPIO interrupt A</description>
116442 <description>Pin contributes to GPIO interrupt A</description>
116449 <description>Interrupt A enable bits.</description>
116456 <description>Pin does not contribute to GPIO interrupt A</description>
116461 <description>Pin contributes to GPIO interrupt A</description>
116468 <description>Interrupt A enable bits.</description>
116475 <description>Pin does not contribute to GPIO interrupt A</description>
116480 <description>Pin contributes to GPIO interrupt A</description>
116487 <description>Interrupt A enable bits.</description>
116494 <description>Pin does not contribute to GPIO interrupt A</description>
116499 <description>Pin contributes to GPIO interrupt A</description>
116506 <description>Interrupt A enable bits.</description>
116513 <description>Pin does not contribute to GPIO interrupt A</description>
116518 <description>Pin contributes to GPIO interrupt A</description>
116525 <description>Interrupt A enable bits.</description>
116532 <description>Pin does not contribute to GPIO interrupt A</description>
116537 <description>Pin contributes to GPIO interrupt A</description>
116544 <description>Interrupt A enable bits.</description>
116551 <description>Pin does not contribute to GPIO interrupt A</description>
116556 <description>Pin contributes to GPIO interrupt A</description>
116563 <description>Interrupt A enable bits.</description>
116570 <description>Pin does not contribute to GPIO interrupt A</description>
116575 <description>Pin contributes to GPIO interrupt A</description>
116582 <description>Interrupt A enable bits.</description>
116589 <description>Pin does not contribute to GPIO interrupt A</description>
116594 <description>Pin contributes to GPIO interrupt A</description>
116601 <description>Interrupt A enable bits.</description>
116608 <description>Pin does not contribute to GPIO interrupt A</description>
116613 <description>Pin contributes to GPIO interrupt A</description>
116620 <description>Interrupt A enable bits.</description>
116627 <description>Pin does not contribute to GPIO interrupt A</description>
116632 <description>Pin contributes to GPIO interrupt A</description>
116639 <description>Interrupt A enable bits.</description>
116646 <description>Pin does not contribute to GPIO interrupt A</description>
116651 <description>Pin contributes to GPIO interrupt A</description>
116658 <description>Interrupt A enable bits.</description>
116665 <description>Pin does not contribute to GPIO interrupt A</description>
116670 <description>Pin contributes to GPIO interrupt A</description>
116677 <description>Interrupt A enable bits.</description>
116684 <description>Pin does not contribute to GPIO interrupt A</description>
116689 <description>Pin contributes to GPIO interrupt A</description>
116696 <description>Interrupt A enable bits.</description>
116703 <description>Pin does not contribute to GPIO interrupt A</description>
116708 <description>Pin contributes to GPIO interrupt A</description>
116715 <description>Interrupt A enable bits.</description>
116722 <description>Pin does not contribute to GPIO interrupt A</description>
116727 <description>Pin contributes to GPIO interrupt A</description>
116734 <description>Interrupt A enable bits.</description>
116741 <description>Pin does not contribute to GPIO interrupt A</description>
116746 <description>Pin contributes to GPIO interrupt A</description>
116753 <description>Interrupt A enable bits.</description>
116760 <description>Pin does not contribute to GPIO interrupt A</description>
116765 <description>Pin contributes to GPIO interrupt A</description>
116772 <description>Interrupt A enable bits.</description>
116779 <description>Pin does not contribute to GPIO interrupt A</description>
116784 <description>Pin contributes to GPIO interrupt A</description>
116791 <description>Interrupt A enable bits.</description>
116798 <description>Pin does not contribute to GPIO interrupt A</description>
116803 <description>Pin contributes to GPIO interrupt A</description>
116810 <description>Interrupt A enable bits.</description>
116817 <description>Pin does not contribute to GPIO interrupt A</description>
116822 <description>Pin contributes to GPIO interrupt A</description>
116829 <description>Interrupt A enable bits.</description>
116836 <description>Pin does not contribute to GPIO interrupt A</description>
116841 <description>Pin contributes to GPIO interrupt A</description>
116848 <description>Interrupt A enable bits.</description>
116855 <description>Pin does not contribute to GPIO interrupt A</description>
116860 <description>Pin contributes to GPIO interrupt A</description>
116867 <description>Interrupt A enable bits.</description>
116874 <description>Pin does not contribute to GPIO interrupt A</description>
116879 <description>Pin contributes to GPIO interrupt A</description>
116886 <description>Interrupt A enable bits.</description>
116893 <description>Pin does not contribute to GPIO interrupt A</description>
116898 <description>Pin contributes to GPIO interrupt A</description>
116905 <description>Interrupt A enable bits.</description>
116912 <description>Pin does not contribute to GPIO interrupt A</description>
116917 <description>Pin contributes to GPIO interrupt A</description>
116924 <description>Interrupt A enable bits.</description>
116931 <description>Pin does not contribute to GPIO interrupt A</description>
116936 <description>Pin contributes to GPIO interrupt A</description>
116943 <description>Interrupt A enable bits.</description>
116950 <description>Pin does not contribute to GPIO interrupt A</description>
116955 <description>Pin contributes to GPIO interrupt A</description>
116962 <description>Interrupt A enable bits.</description>
116969 <description>Pin does not contribute to GPIO interrupt A</description>
116974 <description>Pin contributes to GPIO interrupt A</description>
116981 <description>Interrupt A enable bits.</description>
116988 <description>Pin does not contribute to GPIO interrupt A</description>
116993 <description>Pin contributes to GPIO interrupt A</description>
117000 <description>Interrupt A enable bits.</description>
117007 <description>Pin does not contribute to GPIO interrupt A</description>
117012 <description>Pin contributes to GPIO interrupt A</description>
117023 <description>Interrupt B enable control</description>
117032 <description>Interrupt B enable bits.</description>
117039 <description>Pin does not contribute to GPIO interrupt B</description>
117044 <description>Pin contributes to GPIO interrupt B</description>
117051 <description>Interrupt B enable bits.</description>
117058 <description>Pin does not contribute to GPIO interrupt B</description>
117063 <description>Pin contributes to GPIO interrupt B</description>
117070 <description>Interrupt B enable bits.</description>
117077 <description>Pin does not contribute to GPIO interrupt B</description>
117082 <description>Pin contributes to GPIO interrupt B</description>
117089 <description>Interrupt B enable bits.</description>
117096 <description>Pin does not contribute to GPIO interrupt B</description>
117101 <description>Pin contributes to GPIO interrupt B</description>
117108 <description>Interrupt B enable bits.</description>
117115 <description>Pin does not contribute to GPIO interrupt B</description>
117120 <description>Pin contributes to GPIO interrupt B</description>
117127 <description>Interrupt B enable bits.</description>
117134 <description>Pin does not contribute to GPIO interrupt B</description>
117139 <description>Pin contributes to GPIO interrupt B</description>
117146 <description>Interrupt B enable bits.</description>
117153 <description>Pin does not contribute to GPIO interrupt B</description>
117158 <description>Pin contributes to GPIO interrupt B</description>
117165 <description>Interrupt B enable bits.</description>
117172 <description>Pin does not contribute to GPIO interrupt B</description>
117177 <description>Pin contributes to GPIO interrupt B</description>
117184 <description>Interrupt B enable bits.</description>
117191 <description>Pin does not contribute to GPIO interrupt B</description>
117196 <description>Pin contributes to GPIO interrupt B</description>
117203 <description>Interrupt B enable bits.</description>
117210 <description>Pin does not contribute to GPIO interrupt B</description>
117215 <description>Pin contributes to GPIO interrupt B</description>
117222 <description>Interrupt B enable bits.</description>
117229 <description>Pin does not contribute to GPIO interrupt B</description>
117234 <description>Pin contributes to GPIO interrupt B</description>
117241 <description>Interrupt B enable bits.</description>
117248 <description>Pin does not contribute to GPIO interrupt B</description>
117253 <description>Pin contributes to GPIO interrupt B</description>
117260 <description>Interrupt B enable bits.</description>
117267 <description>Pin does not contribute to GPIO interrupt B</description>
117272 <description>Pin contributes to GPIO interrupt B</description>
117279 <description>Interrupt B enable bits.</description>
117286 <description>Pin does not contribute to GPIO interrupt B</description>
117291 <description>Pin contributes to GPIO interrupt B</description>
117298 <description>Interrupt B enable bits.</description>
117305 <description>Pin does not contribute to GPIO interrupt B</description>
117310 <description>Pin contributes to GPIO interrupt B</description>
117317 <description>Interrupt B enable bits.</description>
117324 <description>Pin does not contribute to GPIO interrupt B</description>
117329 <description>Pin contributes to GPIO interrupt B</description>
117336 <description>Interrupt B enable bits.</description>
117343 <description>Pin does not contribute to GPIO interrupt B</description>
117348 <description>Pin contributes to GPIO interrupt B</description>
117355 <description>Interrupt B enable bits.</description>
117362 <description>Pin does not contribute to GPIO interrupt B</description>
117367 <description>Pin contributes to GPIO interrupt B</description>
117374 <description>Interrupt B enable bits.</description>
117381 <description>Pin does not contribute to GPIO interrupt B</description>
117386 <description>Pin contributes to GPIO interrupt B</description>
117393 <description>Interrupt B enable bits.</description>
117400 <description>Pin does not contribute to GPIO interrupt B</description>
117405 <description>Pin contributes to GPIO interrupt B</description>
117412 <description>Interrupt B enable bits.</description>
117419 <description>Pin does not contribute to GPIO interrupt B</description>
117424 <description>Pin contributes to GPIO interrupt B</description>
117431 <description>Interrupt B enable bits.</description>
117438 <description>Pin does not contribute to GPIO interrupt B</description>
117443 <description>Pin contributes to GPIO interrupt B</description>
117450 <description>Interrupt B enable bits.</description>
117457 <description>Pin does not contribute to GPIO interrupt B</description>
117462 <description>Pin contributes to GPIO interrupt B</description>
117469 <description>Interrupt B enable bits.</description>
117476 <description>Pin does not contribute to GPIO interrupt B</description>
117481 <description>Pin contributes to GPIO interrupt B</description>
117488 <description>Interrupt B enable bits.</description>
117495 <description>Pin does not contribute to GPIO interrupt B</description>
117500 <description>Pin contributes to GPIO interrupt B</description>
117507 <description>Interrupt B enable bits.</description>
117514 <description>Pin does not contribute to GPIO interrupt B</description>
117519 <description>Pin contributes to GPIO interrupt B</description>
117526 <description>Interrupt B enable bits.</description>
117533 <description>Pin does not contribute to GPIO interrupt B</description>
117538 <description>Pin contributes to GPIO interrupt B</description>
117545 <description>Interrupt B enable bits.</description>
117552 <description>Pin does not contribute to GPIO interrupt B</description>
117557 <description>Pin contributes to GPIO interrupt B</description>
117564 <description>Interrupt B enable bits.</description>
117571 <description>Pin does not contribute to GPIO interrupt B</description>
117576 <description>Pin contributes to GPIO interrupt B</description>
117583 <description>Interrupt B enable bits.</description>
117590 <description>Pin does not contribute to GPIO interrupt B</description>
117595 <description>Pin contributes to GPIO interrupt B</description>
117602 <description>Interrupt B enable bits.</description>
117609 <description>Pin does not contribute to GPIO interrupt B</description>
117614 <description>Pin contributes to GPIO interrupt B</description>
117621 <description>Interrupt B enable bits.</description>
117628 <description>Pin does not contribute to GPIO interrupt B</description>
117633 <description>Pin contributes to GPIO interrupt B</description>
117644 <description>Interupt polarity control</description>
117653 <description>Polarity control for each pin</description>
117660 <description>High level or rising edge triggered</description>
117665 <description>Low level or falling edge triggered</description>
117672 <description>Polarity control for each pin</description>
117679 <description>High level or rising edge triggered</description>
117684 <description>Low level or falling edge triggered</description>
117691 <description>Polarity control for each pin</description>
117698 <description>High level or rising edge triggered</description>
117703 <description>Low level or falling edge triggered</description>
117710 <description>Polarity control for each pin</description>
117717 <description>High level or rising edge triggered</description>
117722 <description>Low level or falling edge triggered</description>
117729 <description>Polarity control for each pin</description>
117736 <description>High level or rising edge triggered</description>
117741 <description>Low level or falling edge triggered</description>
117748 <description>Polarity control for each pin</description>
117755 <description>High level or rising edge triggered</description>
117760 <description>Low level or falling edge triggered</description>
117767 <description>Polarity control for each pin</description>
117774 <description>High level or rising edge triggered</description>
117779 <description>Low level or falling edge triggered</description>
117786 <description>Polarity control for each pin</description>
117793 <description>High level or rising edge triggered</description>
117798 <description>Low level or falling edge triggered</description>
117805 <description>Polarity control for each pin</description>
117812 <description>High level or rising edge triggered</description>
117817 <description>Low level or falling edge triggered</description>
117824 <description>Polarity control for each pin</description>
117831 <description>High level or rising edge triggered</description>
117836 <description>Low level or falling edge triggered</description>
117843 <description>Polarity control for each pin</description>
117850 <description>High level or rising edge triggered</description>
117855 <description>Low level or falling edge triggered</description>
117862 <description>Polarity control for each pin</description>
117869 <description>High level or rising edge triggered</description>
117874 <description>Low level or falling edge triggered</description>
117881 <description>Polarity control for each pin</description>
117888 <description>High level or rising edge triggered</description>
117893 <description>Low level or falling edge triggered</description>
117900 <description>Polarity control for each pin</description>
117907 <description>High level or rising edge triggered</description>
117912 <description>Low level or falling edge triggered</description>
117919 <description>Polarity control for each pin</description>
117926 <description>High level or rising edge triggered</description>
117931 <description>Low level or falling edge triggered</description>
117938 <description>Polarity control for each pin</description>
117945 <description>High level or rising edge triggered</description>
117950 <description>Low level or falling edge triggered</description>
117957 <description>Polarity control for each pin</description>
117964 <description>High level or rising edge triggered</description>
117969 <description>Low level or falling edge triggered</description>
117976 <description>Polarity control for each pin</description>
117983 <description>High level or rising edge triggered</description>
117988 <description>Low level or falling edge triggered</description>
117995 <description>Polarity control for each pin</description>
118002 <description>High level or rising edge triggered</description>
118007 <description>Low level or falling edge triggered</description>
118014 <description>Polarity control for each pin</description>
118021 <description>High level or rising edge triggered</description>
118026 <description>Low level or falling edge triggered</description>
118033 <description>Polarity control for each pin</description>
118040 <description>High level or rising edge triggered</description>
118045 <description>Low level or falling edge triggered</description>
118052 <description>Polarity control for each pin</description>
118059 <description>High level or rising edge triggered</description>
118064 <description>Low level or falling edge triggered</description>
118071 <description>Polarity control for each pin</description>
118078 <description>High level or rising edge triggered</description>
118083 <description>Low level or falling edge triggered</description>
118090 <description>Polarity control for each pin</description>
118097 <description>High level or rising edge triggered</description>
118102 <description>Low level or falling edge triggered</description>
118109 <description>Polarity control for each pin</description>
118116 <description>High level or rising edge triggered</description>
118121 <description>Low level or falling edge triggered</description>
118128 <description>Polarity control for each pin</description>
118135 <description>High level or rising edge triggered</description>
118140 <description>Low level or falling edge triggered</description>
118147 <description>Polarity control for each pin</description>
118154 <description>High level or rising edge triggered</description>
118159 <description>Low level or falling edge triggered</description>
118166 <description>Polarity control for each pin</description>
118173 <description>High level or rising edge triggered</description>
118178 <description>Low level or falling edge triggered</description>
118185 <description>Polarity control for each pin</description>
118192 <description>High level or rising edge triggered</description>
118197 <description>Low level or falling edge triggered</description>
118204 <description>Polarity control for each pin</description>
118211 <description>High level or rising edge triggered</description>
118216 <description>Low level or falling edge triggered</description>
118223 <description>Polarity control for each pin</description>
118230 <description>High level or rising edge triggered</description>
118235 <description>Low level or falling edge triggered</description>
118242 <description>Polarity control for each pin</description>
118249 <description>High level or rising edge triggered</description>
118254 <description>Low level or falling edge triggered</description>
118265 <description>Interrupt edge select</description>
118274 <description>Edge or level mode select bits.</description>
118281 <description>Level mode</description>
118286 <description>Edge mode</description>
118293 <description>Edge or level mode select bits.</description>
118300 <description>Level mode</description>
118305 <description>Edge mode</description>
118312 <description>Edge or level mode select bits.</description>
118319 <description>Level mode</description>
118324 <description>Edge mode</description>
118331 <description>Edge or level mode select bits.</description>
118338 <description>Level mode</description>
118343 <description>Edge mode</description>
118350 <description>Edge or level mode select bits.</description>
118357 <description>Level mode</description>
118362 <description>Edge mode</description>
118369 <description>Edge or level mode select bits.</description>
118376 <description>Level mode</description>
118381 <description>Edge mode</description>
118388 <description>Edge or level mode select bits.</description>
118395 <description>Level mode</description>
118400 <description>Edge mode</description>
118407 <description>Edge or level mode select bits.</description>
118414 <description>Level mode</description>
118419 <description>Edge mode</description>
118426 <description>Edge or level mode select bits.</description>
118433 <description>Level mode</description>
118438 <description>Edge mode</description>
118445 <description>Edge or level mode select bits.</description>
118452 <description>Level mode</description>
118457 <description>Edge mode</description>
118464 <description>Edge or level mode select bits.</description>
118471 <description>Level mode</description>
118476 <description>Edge mode</description>
118483 <description>Edge or level mode select bits.</description>
118490 <description>Level mode</description>
118495 <description>Edge mode</description>
118502 <description>Edge or level mode select bits.</description>
118509 <description>Level mode</description>
118514 <description>Edge mode</description>
118521 <description>Edge or level mode select bits.</description>
118528 <description>Level mode</description>
118533 <description>Edge mode</description>
118540 <description>Edge or level mode select bits.</description>
118547 <description>Level mode</description>
118552 <description>Edge mode</description>
118559 <description>Edge or level mode select bits.</description>
118566 <description>Level mode</description>
118571 <description>Edge mode</description>
118578 <description>Edge or level mode select bits.</description>
118585 <description>Level mode</description>
118590 <description>Edge mode</description>
118597 <description>Edge or level mode select bits.</description>
118604 <description>Level mode</description>
118609 <description>Edge mode</description>
118616 <description>Edge or level mode select bits.</description>
118623 <description>Level mode</description>
118628 <description>Edge mode</description>
118635 <description>Edge or level mode select bits.</description>
118642 <description>Level mode</description>
118647 <description>Edge mode</description>
118654 <description>Edge or level mode select bits.</description>
118661 <description>Level mode</description>
118666 <description>Edge mode</description>
118673 <description>Edge or level mode select bits.</description>
118680 <description>Level mode</description>
118685 <description>Edge mode</description>
118692 <description>Edge or level mode select bits.</description>
118699 <description>Level mode</description>
118704 <description>Edge mode</description>
118711 <description>Edge or level mode select bits.</description>
118718 <description>Level mode</description>
118723 <description>Edge mode</description>
118730 <description>Edge or level mode select bits.</description>
118737 <description>Level mode</description>
118742 <description>Edge mode</description>
118749 <description>Edge or level mode select bits.</description>
118756 <description>Level mode</description>
118761 <description>Edge mode</description>
118768 <description>Edge or level mode select bits.</description>
118775 <description>Level mode</description>
118780 <description>Edge mode</description>
118787 <description>Edge or level mode select bits.</description>
118794 <description>Level mode</description>
118799 <description>Edge mode</description>
118806 <description>Edge or level mode select bits.</description>
118813 <description>Level mode</description>
118818 <description>Edge mode</description>
118825 <description>Edge or level mode select bits.</description>
118832 <description>Level mode</description>
118837 <description>Edge mode</description>
118844 <description>Edge or level mode select bits.</description>
118851 <description>Level mode</description>
118856 <description>Edge mode</description>
118863 <description>Edge or level mode select bits.</description>
118870 <description>Level mode</description>
118875 <description>Edge mode</description>
118886 <description>Interrupt status for interrupt A</description>
118895 <description>Interrupt status.</description>
118907 <description>Interrupt status for interrupt B</description>
118916 <description>Interrupt status</description>
118928 <description>DMIC</description>
118949 <description>no description available</description>
118953 <description>Oversample Rate</description>
118962 <description>Oversample Rate</description>
118971 <description>DMIC Clock</description>
118980 <description>PDM Clock Divider Value</description>
118987 <description>Divide by 1</description>
118992 <description>Divide by 2</description>
118997 <description>Divide by 3</description>
119002 <description>Divide by 4</description>
119007 <description>Divide by 6</description>
119012 <description>Divide by 8</description>
119017 <description>Divide by 12</description>
119022 <description>Divide by 16</description>
119027 <description>Divide by 24</description>
119032 <description>Divide by 32</description>
119037 <description>Divide by 48</description>
119042 <description>Divide by 64</description>
119047 <description>Divide by 96</description>
119052 <description>Divide by 128</description>
119061 <description>Compensation Filter for 2 FS</description>
119070 <description>Compensation value</description>
119077 <description>Compensation = 0. This is the recommended setting.</description>
119082 <description>Compensation = -0.16</description>
119087 <description>Compensation = -0.15</description>
119092 <description>Compensation = -0.13</description>
119101 <description>Compensation Filter for 4 FS</description>
119110 <description>Compensation value</description>
119117 <description>Compensation = 0. This is the recommended setting.</description>
119122 <description>Compensation = -0.16</description>
119127 <description>Compensation = -0.15</description>
119132 <description>Compensation = -0.13</description>
119141 <description>Decimator Gain Shift</description>
119150 <description>Gain</description>
119159 <description>FIFO Control</description>
119168 <description>FIFO Enable.</description>
119175 <description>Disabled.</description>
119180 …<description>FIFO is enabled. The FIFO must be enabled in order for the CPU or DMA to read data fr…
119187 <description>FIFO Reset</description>
119194 … <description>Reset the FIFO. This must be cleared before resuming operation.</description>
119199 <description>Normal operation</description>
119206 <description>Interrupt Enable.</description>
119213 <description>FIFO level interrupts are not enabled.</description>
119218 <description>FIFO level interrupts are enabled.</description>
119225 <description>DMA Enable</description>
119232 <description>DMA requests are not enabled.</description>
119237 <description>DMA requests based on FIFO level are enabled.</description>
119244 <description>FIFO Trigger Level for Interrupt</description>
119251 … <description>Trigger when the FIFO has received one entry (is no longer empty).</description>
119256 <description>Trigger when the FIFO has received two entries.</description>
119261 <description>Trigger when the FIFO has received 15 entries.</description>
119266 … <description>Trigger when the FIFO has received 16 entries (has become full).</description>
119275 <description>FIFO Status</description>
119284 <description>Status of Interrupt (write 1 to clear)</description>
119292 <description>Overrun Detected (write 1 to clear)</description>
119300 <description>Underrun Detected (write 1 to clear)</description>
119310 <description>FIFO Data</description>
119319 <description>PCM Data</description>
119328 <description>Physical Control</description>
119337 <description>Capture DMIC on Falling edge (0 means on rising)</description>
119344 <description>Capture PDM_DATA on the rising edge of PDM_CLK.</description>
119349 <description>Capture PDM_DATA on the falling edge of PDM_CLK.</description>
119356 …<description>Use Half rate sampling (ie Clock to dmic is sent at half the speed than the decimator…
119363 …<description>Standard half rate sampling. The clock to the DMIC is sent at the same rate as the de…
119368 …<description>Use half rate sampling. The clock to the DMIC is sent at half the rate that the decim…
119377 <description>DC Filter Control</description>
119386 <description>DC Block Filter</description>
119393 <description>Flat Response, no filter</description>
119398 <description>155 Hz</description>
119403 <description>78 Hz</description>
119408 <description>39 Hz</description>
119415 <description>DC Gain</description>
119422 <description>Saturate at 16 Bit</description>
119429 … <description>Do not Saturate. Results roll over if out range and do not saturate.</description>
119434 …<description>Saturate. If the result overflows, it saturates at 0xFFFF for positive overflow and 0…
119441 <description>Sign Extend</description>
119448 <description>Disabled</description>
119453 <description>Enabled</description>
119463 <description>Channel Enable</description>
119472 <description>Enable Channel n</description>
119479 <description>PDM channel n is disabled.</description>
119484 <description>PDM channel n is enabled.</description>
119491 <description>Enable Channel n</description>
119498 <description>PDM channel n is disabled.</description>
119503 <description>PDM channel n is enabled.</description>
119512 <description>Use 2 FS register</description>
119521 <description>Use 2FS register</description>
119528 <description>Use 1 FS output for PCM data.</description>
119533 <description>Use 2 FS output for PCM data.</description>
119542 <description>Global Channel Synchronization Enable</description>
119551 <description>Channel synch enable</description>
119560 <description>Global channel synchronization counter value</description>
119569 <description>Channel Counter Value</description>
119578 <description>DMIC decimator reset</description>
119587 <description>Decimator reset</description>
119594 <description>Disable</description>
119599 <description>Enable</description>
119608 <description>HWVAD Input Gain</description>
119617 <description>Input Gain</description>
119624 <description>-10 bits</description>
119629 <description>-8 bits</description>
119634 <description>-6 bits</description>
119639 <description>-4 bits</description>
119644 <description>-2 bits</description>
119649 <description>0 bits (default)</description>
119654 <description>+2 bits</description>
119659 <description>+4 bits</description>
119664 <description>+6 bits</description>
119669 <description>+8 bits</description>
119674 <description>+10 bits</description>
119679 <description>+12 bits</description>
119684 <description>+14 bits</description>
119693 <description>HWVAD Filter Control</description>
119702 … <description>The HPFS field chooses the High Pass filter in first part of HWVAD.</description>
119709 <description>Bypass</description>
119714 <description>High Pass 1750 Hz</description>
119719 <description>High Pass 215 Hz</description>
119728 <description>HWVAD Control</description>
119737 <description>STAGE 1</description>
119744 … <description>Normal operation, waiting for HWVAD trigger event (stage 0).</description>
119749 … <description>Reset internal interrupt flag by writing a '1' (stage 1) pulse.</description>
119758 <description>HWVAD Filter Reset</description>
119767 <description>Reset HWVAD</description>
119776 <description>HWVAD Noise Estimator Gain</description>
119785 <description>Gain Factor for Noise Estimator</description>
119794 <description>HWVAD Signal Estimator Gain</description>
119803 <description>Signal Gain Factor</description>
119812 <description>HWVAD Noise Envelope Estimator</description>
119821 <description>Average Noise-floor Value</description>
119832 <description>CRC</description>
119843 <description>CRC DATA register</description>
119852 <description>CRC Low Lower Byte</description>
119859 <description>CRC Low Upper Byte</description>
119866 <description>CRC High Lower Byte</description>
119873 <description>CRC High Upper Byte</description>
119882 <description>CRC Polynomial register</description>
119891 <description>Low Polynominal Half-word</description>
119898 <description>High Polynominal Half-word</description>
119907 <description>CRC Control register</description>
119916 <description>TCRC</description>
119923 <description>16-bit CRC protocol.</description>
119928 <description>32-bit CRC protocol.</description>
119935 <description>Write CRC DATA register As Seed</description>
119942 <description>Writes to the CRC DATA register are data values.</description>
119947 <description>Writes to the CRC DATA register are seed values.</description>
119954 <description>Complement Read Of CRC DATA register</description>
119961 <description>No XOR on reading.</description>
119966 … <description>Invert or complement the read value of the CRC DATA register.</description>
119973 <description>Type Of Transpose For Read</description>
119980 <description>No transposition.</description>
119985 <description>Bits in bytes are transposed; bytes are not transposed.</description>
119990 <description>Both bits in bytes and bytes are transposed.</description>
119995 … <description>Only bytes are transposed; no bits in a byte are transposed.</description>
120002 <description>Type Of Transpose For Writes</description>
120009 <description>No transposition.</description>
120014 <description>Bits in bytes are transposed; bytes are not transposed.</description>
120019 <description>Both bits in bytes and bytes are transposed.</description>
120024 … <description>Only bytes are transposed; no bits in a byte are transposed.</description>
120035 <description>Debug</description>
120046 <description>Command and status word</description>
120055 <description>Re-synchronization Request</description>
120062 <description>No Request</description>
120067 <description>Request for re-synchronization</description>
120074 <description>Request Pending</description>
120081 <description>No Request Pending</description>
120086 <description>Request for Re-synchronization Pending</description>
120093 <description>Debug Overrun Error</description>
120100 <description>No Debug Overrun error</description>
120105 <description>Debug Overrun Error. A debug overrun occurred.</description>
120112 <description>AHB Overrun Error</description>
120119 <description>No AHB Overrun Error</description>
120124 <description>AHB Overrun Error. An AHB overrun occurred.</description>
120131 <description>Soft Reset</description>
120138 <description>Chip Reset Request</description>
120147 <description>Request Value</description>
120156 <description>Request Value</description>
120165 <description>Return Value</description>
120174 <description>Return Value</description>
120183 <description>Identification</description>
120192 <description>Identification Value</description>
120203 <description>MCAN</description>
120222 <description>Data Bit Timing and Prescaler</description>
120231 <description>Data (Re)Synchronization Jump Width</description>
120238 <description>Data Time Segment After Sample Point</description>
120245 <description>Data Time Segment Before Sample Point</description>
120252 <description>Data Bit Rate Prescaler</description>
120259 <description>Transmitter Delay Compensation</description>
120266 <description>Transmitter delay compensation disabled</description>
120271 <description>Transmitter delay compensation enabled</description>
120280 <description>Test</description>
120289 <description>Loop Back Mode</description>
120296 <description>Loop back mode is disabled.</description>
120301 <description>Loop back mode is enabled.</description>
120308 <description>Control of Transmit Pin</description>
120315 <description>Loop back mode is disabled.</description>
120320 <description>The sample point can be monitored at the CAN_TXD.</description>
120325 <description>CAN_TXD pin is driven LOW/dominant.</description>
120330 <description>CAN_TXD is driven HIGH/recessive.</description>
120337 <description>Monitors the Actual Value of the CAN_RXD</description>
120344 <description>The CAN bus is dominant (CAN_RXD = 0).</description>
120349 <description>The CAN bus is recessive (CAN_RXD = 1).</description>
120358 <description>CC Control</description>
120367 <description>Initialization</description>
120374 <description>Normal operation</description>
120379 <description>Initialization is started</description>
120386 <description>Configuration Change Enable</description>
120393 …<description>No write access. The CPU has no write access to the protected configuration registers…
120398 …<description>Write access. The CPU has write access to the protected configuration registers.</des…
120405 <description>Restricted Operational Mode</description>
120412 <description>Normal CAN operation</description>
120417 <description>Restricted operation mode active</description>
120424 <description>Clock Stop Acknowledge</description>
120431 <description>No clock stop acknowledged.</description>
120436 …<description>MCAN may be set in Power Down mode by stopping the internal MCAN clocks.</description>
120443 <description>Clock Stop Request</description>
120450 <description>No clock stop is requested.</description>
120455 …description>Clock stop requested. When clock stop is requested, first INIT and then CSA will be se…
120462 <description>Bus Monitoring Mode</description>
120469 <description>Bus Monitoring mode is disabled.</description>
120474 <description>Bus Monitoring mode is enabled.</description>
120481 <description>Disable Automatic Retransmission</description>
120488 …<description>Automatic retransmission of messages not transmitted successfully enabled.</descripti…
120493 <description>Automatic retransmission disabled.</description>
120500 <description>Test Mode Enable</description>
120507 <description>Normal operation</description>
120512 <description>Test mode enabled</description>
120519 <description>CAN FD Operation Enable</description>
120526 <description>CAN FD operation is disabled.</description>
120531 <description>CAN FD operation is enabled.</description>
120538 <description>Bit Rate Switching Enable</description>
120545 <description>Bit rate switching for transmissions is disabled.</description>
120550 <description>Bit rate switching for transmission is enabled.</description>
120557 <description>Protocol Exception Handling Disable</description>
120564 <description>Protocol exception handling is enabled.</description>
120569 <description>Protocol exception handling is disabled.</description>
120576 <description>Edge Filtering During Bus Integration</description>
120583 <description>Edge filtering is disabled.</description>
120588 …<description>Two consecutive dominant quanta required to detect an edge for hard synchronization.<…
120595 <description>Transmit Pause</description>
120602 <description>Transmit pause is disabled.</description>
120607 <description>Transmit pause is enabled.</description>
120614 <description>Non ISO Operation</description>
120621 … <description>CAN FD frame format will follow according to ISO11898-1.</description>
120626 …<description>CAN FD frame format will follow according to Bosch CAN FD Specification V1.0.</descri…
120635 <description>Nominal Bit Timing and Prescaler</description>
120644 <description>Nominal Time Segment After Sample Point</description>
120651 <description>Nominal Time Segment Before Sample Point</description>
120658 <description>Nominal Bit Rate Prescaler</description>
120665 <description>Nominal (Re)Synchronization Jump Width</description>
120674 <description>Timestamp Counter Configuration</description>
120683 <description>Timestamp Select</description>
120690 <description>Timestamp counter value static at 0x0000</description>
120695 … <description>Timestamp counter value incremented according to TCP bits</description>
120700 <description>External timestamp counter value used</description>
120705 <description>Timestamp counter value static at 0x0000</description>
120712 <description>Timestamp Counter Prescaler</description>
120721 <description>Timestamp Counter Value</description>
120730 <description>Timestamp Counter</description>
120739 <description>Timeout Counter Configuration</description>
120748 <description>Enable Timeout Counter</description>
120755 <description>Timeout counter is disabled.</description>
120760 <description>Timeout counter is enabled.</description>
120767 <description>Timeout Select</description>
120774 <description>Continuous operation</description>
120779 <description>Timeout is controlled by Tx event FIFO.</description>
120784 <description>Timeout is controlled by Rx FIFO 0.</description>
120789 <description>Timeout is controlled by Rx FIFO 1.</description>
120796 <description>Timeout Period</description>
120805 <description>Timeout Counter Value</description>
120814 <description>Timeout Counter</description>
120823 <description>Error Counter</description>
120832 <description>Transmit Error Counter</description>
120839 <description>Receive Error Counter</description>
120846 <description>Receive Error Passive</description>
120853 …<description>Below error level. The receive counter is below the error passive level of 128.</desc…
120858 …<description>At error level. The receive counter has reached the error passive level of 128.</desc…
120865 <description>CAN Error Logging</description>
120874 <description>Protocol Status</description>
120883 <description>Last Error Code</description>
120890 …<description>No error: No error has occurred since the LEC bits has been reset by successful recep…
120895 …<description>Stuff error: More than 5 equal bits in a sequence have occurred in a part of a receiv…
120900 …<description>Form error: A fixed format part of a received frame has the wrong format.</descriptio…
120905 …<description>AckError: The message transmitted by the MCAN was not acknowledged by another node.</…
120910 …description>Bit1Error: During the transmission of a message (with the exception of the arbitration…
120915 …description>Bit0Error: During the transmission of a message (or acknowledge bit, or active error f…
120920 …description>CRCError: The CRC check sum of a received message was incorrect. The CRC of an incomin…
120925 …description>NoChange: Any read access to the protocol status register re-initializes the LEC bits …
120932 <description>Activity</description>
120939 … <description>Synchronizing - node is synchronizing on CAN communication.</description>
120944 <description>Idle - node is neither receiver nor transmitter.</description>
120949 <description>Receiver - node is operating as receiver.</description>
120954 <description>Transmitter - node is operating as transmitter.</description>
120961 <description>Error Passive</description>
120968 …description>The MCAN is in Error_Active state. It normally takes part in bus communication and sen…
120973 <description>The MCAN is in the Error_Passive state.</description>
120980 <description>Warning Status</description>
120987 … <description>Both error counters are below the Error_Warning limit of 96.</description>
120992 …<description>At least one of error counter has reached the Error_Warning limit of 96.</description>
120999 <description>Bus Off Status</description>
121006 <description>Disabled</description>
121011 <description>Enabled</description>
121018 <description>Data Phase Last Error Code</description>
121025 <description>ESI Flag of the Last Received CAN FD Message</description>
121032 … <description>Last received CAN FD message did not have its ESI flag set.</description>
121037 <description>Last received CAN FD message had its ESI flag set.</description>
121044 <description>BRS Flag of Last Received CAN FD Message</description>
121051 … <description>Last received CAN FD message did not have its BRS flag set.</description>
121056 <description>Last received CAN FD message had its BRS flag set.</description>
121063 <description>Received a CAN FD Message</description>
121070 <description>No CAN FD message received since the last CPU reset.</description>
121075 … <description>Message in CAN FD format with FDF flag set has been received.</description>
121082 <description>Protocol Exception Event</description>
121089 … <description>No protocol exception event occurred since last read access.</description>
121094 <description>Protocol exception event occurred.</description>
121101 <description>Transmitter Delay Compensation Value</description>
121110 <description>Transmitter Delay Compensator</description>
121119 <description>Transmitter Delay Compensation Filter Window Length</description>
121126 <description>Transmitter Delay Compensation Offset</description>
121135 <description>Interrupt</description>
121144 <description>Rx FIFO 0 New Message</description>
121151 <description>No new message written to Rx FIFO 0.</description>
121156 <description>New message written to Rx FIFO 0.</description>
121163 <description>Rx FIFO 0 Watermark Reached</description>
121170 <description>Rx FIFO 0 fill level below watermark.</description>
121175 <description>Rx FIFO 0 fill level reached watermark.</description>
121182 <description>Rx FIFO 0 Full</description>
121189 <description>Rx FIFO 0 not full.</description>
121194 <description>Rx FIFO 0 full.</description>
121201 <description>Rx FIFO 0 Message Lost</description>
121208 <description>No Rx FIFO 0 message lost.</description>
121213 …<description>Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero.</desc…
121220 <description>Rx FIFO 1 New Message</description>
121227 <description>No new message written to Rx FIFO 1.</description>
121232 <description>New message written to Rx FIFO 1.</description>
121239 <description>Rx FIFO 1 Watermark Reached</description>
121246 <description>Rx FIFO 1 fill level below watermark.</description>
121251 <description>Rx FIFO 1 fill level reached watermark.</description>
121258 <description>Rx FIFO 1 Full</description>
121265 <description>Rx FIFO 1 not full.</description>
121270 <description>Rx FIFO 1 full.</description>
121277 <description>Rx FIFO 1 Message Lost</description>
121284 <description>No Rx FIFO 1 message lost.</description>
121289 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.</desc…
121296 <description>High Priority Message</description>
121303 <description>No high priority message received.</description>
121308 <description>High priority message received.</description>
121315 <description>Transmission Completed</description>
121322 <description>No transmission completed.</description>
121327 <description>Transmission completed.</description>
121334 <description>Transmission Cancellation Finished</description>
121341 <description>No transmission cancellation finished.</description>
121346 <description>Transmission cancellation finished.</description>
121353 <description>Tx FIFO Empty</description>
121360 <description>Tx FIFO non-empty.</description>
121365 <description>Tx FIFO empty.</description>
121372 <description>Tx Event FIFO New Entry</description>
121379 <description>Tx event FIFO unchanged.</description>
121384 <description>Tx Handler wrote Tx event FIFO element.</description>
121391 <description>Tx Event FIFO Watermark Reached</description>
121398 <description>Tx event FIFO fill level below watermark.</description>
121403 <description>Tx event FIFO fill level reached watermark.</description>
121410 <description>Tx Event FIFO Full</description>
121417 <description>Tx event FIFO not full.</description>
121422 <description>Tx event FIFO full.</description>
121429 <description>Tx Event FIFO Element Lost</description>
121436 <description>No Tx event FIFO element lost.</description>
121441 …<description>Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zer…
121448 <description>Timestamp Wraparound</description>
121455 <description>No timestamp counter wraparound.</description>
121460 <description>Timestamp counter wrapped around.</description>
121467 <description>Message RAM Access Failure</description>
121474 <description>No message RAM access failure occurred.</description>
121479 <description>Message RAM access failure occurred.</description>
121486 <description>Timeout Occurred</description>
121493 <description>No timeout.</description>
121498 <description>Timeout reached.</description>
121505 <description>Message Stored in Dedicated Rx Buffer</description>
121512 <description>No Rx buffer updated.</description>
121517 <description>At least one received message stored into an Rx buffer.</description>
121524 <description>Bit Error Corrected</description>
121531 <description>No bit error detected when reading from message RAM.</description>
121536 <description>Bit error detected and corrected (example, ECC).</description>
121543 <description>Bit Error Uncorrected</description>
121550 <description>No bit error detected when reading from message RAM.</description>
121555 … <description>Bit error detected, uncorrected (example, parity logic).</description>
121562 <description>Error Logging Overflow</description>
121569 <description>CAN error logging counter did not overflow.</description>
121574 <description>Overflow of CAN error logging counter occurred.</description>
121581 <description>Error Passive</description>
121588 <description>Error_Passive status unchanged.</description>
121593 <description>Error_Passive status changed.</description>
121600 <description>Warning Status</description>
121607 <description>Error_Warning status unchanged.</description>
121612 <description>Error_Warning status changed.</description>
121619 <description>Bus_Off Status</description>
121626 <description>Bus_Off status unchanged.</description>
121631 <description>Bus_Off status changed.</description>
121638 <description>Watchdog Interrupt</description>
121645 <description>No message RAM watchdog event occurred.</description>
121650 <description>Message RAM watchdog event due to missing READY.</description>
121657 <description>Protocol Error in Arbitration Phase</description>
121664 <description>No protocol error in arbitration phase.</description>
121669 <description>Protocol error in arbitration phase detected.</description>
121676 <description>Protocol Error in Data Phase</description>
121683 <description>No protocol error in data phase.</description>
121688 <description>Protocol error in data phase detected.</description>
121695 <description>Access to Reserved Address</description>
121702 <description>No access to reserved address occurred.</description>
121707 <description>Access to reserved address occurred.</description>
121716 <description>Interrupt Enable</description>
121725 <description>Rx FIFO 0 New Message Interrupt Enable</description>
121732 <description>Interrupt disabled</description>
121737 <description>Interrupt enabled</description>
121744 <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
121751 <description>Interrupt disabled</description>
121756 <description>Interrupt enabled</description>
121763 <description>Rx FIFO 0 Full Interrupt Enable</description>
121770 <description>Interrupt disabled</description>
121775 <description>Interrupt enabled</description>
121782 <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
121789 <description>Interrupt disabled</description>
121794 <description>Interrupt enabled</description>
121801 <description>Rx FIFO 1 New Message Interrupt Enable</description>
121808 <description>Interrupt disabled</description>
121813 <description>Interrupt enabled</description>
121820 <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
121827 <description>Interrupt disabled</description>
121832 <description>Interrupt enabled</description>
121839 <description>Rx FIFO 1 Full Interrupt Enable</description>
121846 <description>Interrupt disabled</description>
121851 <description>Interrupt enabled</description>
121858 <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
121865 <description>Interrupt disabled</description>
121870 <description>Interrupt enabled</description>
121877 <description>High Priority Message Interrupt Enable</description>
121884 <description>Interrupt disabled</description>
121889 <description>Interrupt enabled</description>
121896 <description>Transmission Completed Interrupt Enable</description>
121903 <description>Interrupt disabled</description>
121908 <description>Interrupt enabled</description>
121915 <description>Transmission Cancellation Finished Interrupt Enable</description>
121922 <description>Interrupt disabled</description>
121927 <description>Interrupt enabled</description>
121934 <description>Tx FIFO Empty Interrupt Enable</description>
121941 <description>Interrupt disabled</description>
121946 <description>Interrupt enabled</description>
121953 <description>Tx Event FIFO New Entry Interrupt Enable</description>
121960 <description>Interrupt disabled</description>
121965 <description>Interrupt enabled</description>
121972 <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
121979 <description>Interrupt disabled</description>
121984 <description>Interrupt enabled</description>
121991 <description>Tx Event FIFO Full Interrupt Enable</description>
121998 <description>Interrupt disabled</description>
122003 <description>Interrupt enabled</description>
122010 <description>Tx Event FIFO Element Lost Interrupt Enable</description>
122017 <description>Interrupt disabled</description>
122022 <description>Interrupt enabled</description>
122029 <description>Timestamp Wraparound Interrupt Enable</description>
122036 <description>Interrupt disabled</description>
122041 <description>Interrupt enabled</description>
122048 <description>Message RAM Access Failure Interrupt Enable</description>
122055 <description>Interrupt disabled</description>
122060 <description>Interrupt enabled</description>
122067 <description>Timeout Occurred Interrupt Enable</description>
122074 <description>Interrupt disabled</description>
122079 <description>Interrupt enabled</description>
122086 <description>Message Stored in Dedicated Rx Buffer Interrupt Enable</description>
122093 <description>Interrupt disabled</description>
122098 <description>Interrupt enabled</description>
122105 <description>Bit Error Corrected Interrupt Enable</description>
122112 <description>Interrupt disabled</description>
122117 <description>Interrupt enabled</description>
122124 <description>Bit Error Uncorrected Interrupt Enable</description>
122131 <description>Interrupt disabled</description>
122136 <description>Interrupt enabled</description>
122143 <description>Error Logging Overflow Interrupt Enable</description>
122150 <description>Interrupt disabled</description>
122155 <description>Interrupt enabled</description>
122162 <description>Error Passive Interrupt Enable</description>
122169 <description>Interrupt disabled</description>
122174 <description>Interrupt enabled</description>
122181 <description>Warning Status Interrupt Enable</description>
122188 <description>Interrupt disabled</description>
122193 <description>Interrupt enabled</description>
122200 <description>Bus_Off Status Interrupt Enable</description>
122207 <description>Interrupt disabled</description>
122212 <description>Interrupt enabled</description>
122219 <description>Watchdog Interrupt Enable</description>
122226 <description>Interrupt disabled</description>
122231 <description>Interrupt enabled</description>
122238 <description>Protocol Error in Arbitration Phase Interrupt Enable</description>
122245 <description>Interrupt disabled</description>
122250 <description>Interrupt enabled</description>
122257 <description>Protocol Error in Data Phase Interrupt Enable</description>
122264 <description>Interrupt disabled</description>
122269 <description>Interrupt enabled</description>
122276 <description>Access to Reserved Address Interrupt Enable</description>
122283 <description>Interrupt disabled</description>
122288 <description>Interrupt enabled</description>
122297 <description>Interrupt Line Select</description>
122306 <description>Rx FIFO 0 New Message Interrupt Line</description>
122313 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122318 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122325 <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
122332 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122337 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122344 <description>Rx FIFO 0 Full Interrupt Line</description>
122351 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122356 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122363 <description>Rx FIFO 0 Message Lost Interrupt Line</description>
122370 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122375 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122382 <description>Rx FIFO 1 New Message Interrupt Line</description>
122389 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122394 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122401 <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
122408 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122413 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122420 <description>Rx FIFO 1 Full Interrupt Line</description>
122427 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122432 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122439 <description>Rx FIFO 1 Message Lost Interrupt Line</description>
122446 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122451 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122458 <description>High Priority Message Interrupt Line</description>
122465 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122470 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122477 <description>Transmission Completed Interrupt Line</description>
122484 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122489 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122496 <description>Transmission Cancellation Finished Interrupt Line</description>
122503 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122508 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122515 <description>Tx FIFO Empty Interrupt Line</description>
122522 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122527 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122534 <description>Tx Event FIFO New Entry Interrupt Line</description>
122541 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122546 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122553 <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
122560 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122565 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122572 <description>Tx Event FIFO Full Interrupt Line</description>
122579 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122584 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122591 <description>Tx Event FIFO Element Lost Interrupt Line</description>
122598 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122603 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122610 <description>Timestamp Wraparound Interrupt Line</description>
122617 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122622 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122629 <description>Message RAM Access Failure Interrupt Line</description>
122636 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122641 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122648 <description>Timeout Occurred Interrupt Line</description>
122655 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122660 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122667 <description>Message Stored in Dedicated Rx Buffer Interrupt Line</description>
122674 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122679 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122686 <description>Bit Error Corrected Interrupt Line</description>
122693 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122698 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122705 <description>Bit Error Uncorrected Interrupt Line</description>
122712 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122717 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122724 <description>Error Logging Overflow Interrupt Line</description>
122731 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122736 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122743 <description>Error Passive Interrupt Line</description>
122750 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122755 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122762 <description>Warning Status Interrupt Line</description>
122769 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122774 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122781 <description>Bus_Off Status Interrupt Line</description>
122788 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122793 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122800 <description>Watchdog Interrupt Line</description>
122807 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122812 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122819 <description>Protocol Error in Arbitration Phase Interrupt Line</description>
122826 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122831 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122838 <description>Protocol Error in Data Phase Interrupt Line</description>
122845 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122850 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122857 <description>Access to Reserved Address Interrupt Line</description>
122864 <description>Interrupt assigned to interrupt line MCANx_INT0</description>
122869 <description>Interrupt assigned to interrupt line MCANx_INT1</description>
122878 <description>Interrupt Line Enable</description>
122887 <description>Enable Interrupt Line 0</description>
122894 <description>Interrupt line to MCANx_INT0 is disabled.</description>
122899 <description>Interrupt line to MCANx_INT0 is enabled.</description>
122906 <description>Enable Interrupt Line 1</description>
122913 <description>Interrupt line to MCANx_INT1 is disabled.</description>
122918 <description>Interrupt line to MCANx_INT1 is enabled.</description>
122927 <description>Global Filter Configuration</description>
122936 <description>Reject Remote Frames Extended</description>
122943 <description>Filter remote frames with 29-bit extended IDs</description>
122948 <description>Reject all remote frames with 29-bit extended IDs</description>
122955 <description>Reject Remote Frames Standard</description>
122962 <description>Filter remote frames with 11-bit standard IDs</description>
122967 <description>Reject all remote frames with 11-bit standard IDs</description>
122974 <description>Accept Non-matching Frames Extended</description>
122981 <description>Accept in Rx FIFO 0</description>
122986 <description>Accept in Rx FIFO 1</description>
122991 <description>Reject</description>
122996 <description>Reject</description>
123003 <description>Accept Non-matching Frames Standard</description>
123010 <description>Accept in Rx FIFO 0</description>
123015 <description>Accept in Rx FIFO 1</description>
123020 <description>Reject</description>
123025 <description>Reject</description>
123034 <description>Standard ID Filter Configuration</description>
123043 <description>Filter List Standard Start Address</description>
123050 <description>List Size Standard</description>
123059 <description>Extended ID Filter Configuration</description>
123068 <description>Filter List Extended Start Address</description>
123075 <description>List Size Extended</description>
123084 <description>Extended ID AND Mask</description>
123093 <description>Extended ID Mask</description>
123102 <description>High Priority Message Status</description>
123111 <description>Buffer Index</description>
123118 <description>Message Storage Indicator</description>
123125 <description>No FIFO selected</description>
123130 <description>FIFO message lost</description>
123135 <description>Message stored in FIFO 0</description>
123140 <description>Message stored in FIFO 1</description>
123147 <description>Filter Index</description>
123154 <description>Filter List</description>
123161 <description>Standard filter list</description>
123166 <description>Extended filter list</description>
123175 <description>New Data 1</description>
123184 <description>New Data</description>
123193 <description>New Data 2</description>
123202 <description>New Data</description>
123211 <description>Rx FIFO 0 Configuration</description>
123220 <description>Rx FIFO 0 Start Address</description>
123227 <description>Rx FIFO 0 Size</description>
123234 <description>Rx FIFO 0 Watermark</description>
123241 <description>FIFO 0 Operation Mode</description>
123248 <description>FIFO 0 blocking mode</description>
123253 <description>FIFO 0 overwrite mode</description>
123262 <description>Rx FIFO 0 Status</description>
123271 <description>Rx FIFO 0 Fill Level</description>
123278 <description>Rx FIFO 0 Get Index</description>
123285 <description>Rx FIFO 0 Put Index</description>
123292 <description>Rx FIFO 0 Full</description>
123299 <description>Rx FIFO 0 not full</description>
123304 <description>Rx FIFO 0 full</description>
123311 <description>Rx FIFO 0 Message Lost</description>
123320 <description>Rx FIFO 0 Acknowledge</description>
123329 <description>Rx FIFO 0 Acknowledge Index</description>
123338 <description>Rx Buffer Configuration</description>
123347 <description>Rx Buffer Start Address</description>
123356 <description>Rx FIFO 1 Configuration</description>
123365 <description>Rx FIFO 1 Start Address</description>
123372 <description>Rx FIFO 1 Size</description>
123379 <description>Rx FIFO 1 Watermark</description>
123386 <description>FIFO 1 Operation Mode</description>
123393 <description>FIFO 1 blocking mode</description>
123398 <description>FIFO 1 overwrite mode</description>
123407 <description>Rx FIFO 1 Status</description>
123416 <description>Rx FIFO 1 Fill Level</description>
123423 <description>Rx FIFO 1 Get Index</description>
123430 <description>Rx FIFO 1 Put Index</description>
123437 <description>Rx FIFO 1 Full</description>
123444 <description>Rx FIFO 1 not full</description>
123449 <description>Rx FIFO 1 full</description>
123456 <description>Rx FIFO 1 message lost.</description>
123463 <description>No Rx FIFO 1 message lost.</description>
123468 …<description>Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero.</desc…
123477 <description>Rx FIFO 1 Acknowledge</description>
123486 <description>Rx FIFO 1 Acknowledge Index</description>
123495 <description>Rx Buffer and FIFO Element Size Configuration</description>
123504 <description>Rx FIFO 0 Data Field Size</description>
123511 <description>8 byte data field</description>
123516 <description>12 byte data field</description>
123521 <description>16 byte data field</description>
123526 <description>20 byte data field</description>
123531 <description>24 byte data field</description>
123536 <description>32 byte data field</description>
123541 <description>48 byte data field</description>
123546 <description>64 byte data field</description>
123553 <description>Rx FIFO 1 Data Field Size</description>
123560 <description>8 byte data field</description>
123565 <description>12 byte data field</description>
123570 <description>16 byte data field</description>
123575 <description>20 byte data field</description>
123580 <description>24 byte data field</description>
123585 <description>32 byte data field</description>
123590 <description>48 byte data field</description>
123595 <description>64 byte data field</description>
123602 <description>Rx Buffer Data Field Size</description>
123609 <description>8 byte data field</description>
123614 <description>12 byte data field</description>
123619 <description>16 byte data field</description>
123624 <description>20 byte data field</description>
123629 <description>24 byte data field</description>
123634 <description>32 byte data field</description>
123639 <description>48 byte data field</description>
123644 <description>64 byte data field</description>
123653 <description>Tx Buffer Configuration</description>
123662 <description>Tx Buffers Start Address</description>
123669 <description>Number of Dedicated Transmit Buffers</description>
123676 <description>Transmit FIFO/Queue Size</description>
123683 <description>Tx FIFO/Queue Mode</description>
123690 <description>Tx FIFO operation</description>
123695 <description>Tx queue operation</description>
123704 <description>Tx FIFO/Queue Status</description>
123713 <description>Tx FIFO Get Index</description>
123720 <description>Tx FIFO/Queue Put Index</description>
123727 <description>Tx FIFO/Queue Full</description>
123734 <description>Tx FIFO/Queue not full</description>
123739 <description>Tx FIFO/Queue full</description>
123748 <description>Tx Buffer Element Size Configuration</description>
123757 <description>Tx Buffer Data Field Size</description>
123764 <description>8 byte data field</description>
123769 <description>12 byte data field</description>
123774 <description>16 byte data field</description>
123779 <description>20 byte data field</description>
123784 <description>24 byte data field</description>
123789 <description>32 byte data field</description>
123794 <description>48 byte data field</description>
123799 <description>64 byte data field</description>
123808 <description>Tx Buffer Request Pending</description>
123817 <description>Transmission Request Pending</description>
123826 <description>Tx Buffer Add Request</description>
123835 <description>Add Request</description>
123844 <description>Tx Buffer Cancellation Request</description>
123853 <description>Cancellation Request</description>
123862 <description>Tx Buffer Transmission Occurred</description>
123871 <description>Transmission Occurred</description>
123880 <description>Tx Buffer Cancellation Finished</description>
123889 <description>Cancellation Finished</description>
123898 <description>Tx Buffer Transmission Interrupt Enable</description>
123907 <description>Transmission Interrupt Enable</description>
123916 <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
123925 <description>Cancellation Finished Interrupt Enable</description>
123934 <description>Tx Event FIFO Configuration</description>
123943 <description>Event FIFO Start Address</description>
123950 <description>Event FIFO Size</description>
123957 <description>Event FIFO Watermark</description>
123966 <description>Tx Event FIFO Status</description>
123975 <description>Event FIFO Fill Level</description>
123982 <description>Event FIFO Get Index</description>
123989 <description>Event FIFO Put Index</description>
123996 <description>Event FIFO Full</description>
124003 <description>Tx event FIFO not full</description>
124008 <description>Tx event FIFO full</description>
124015 <description>Tx Event FIFO Element Lost</description>
124022 <description>No Tx event FIFO element lost.</description>
124027 …<description>Tx event FIFO element lost, also set after write attempt to Tx event FIFO of size zer…
124036 <description>Tx Event FIFO Acknowledge</description>
124045 <description>Event FIFO Acknowledge Index</description>
124054 <description>Message RAM Base Address</description>
124063 <description>Base Address for the message RAM in the chip memory map.</description>
124072 <description>External Timestamp Counter Configuration</description>
124081 <description>External Timestamp Prescaler Value</description>
124088 <description>External Timestamp Counter Enable</description>
124095 <description>External timestamp counter is disabled</description>
124100 <description>External timestamp counter is enabled</description>
124109 <description>External Timestamp Counter Value</description>
124118 <description>External Timestamp Counter</description>
124129 <description>ADC</description>
124145 <description>Version ID Register</description>
124154 <description>Resolution</description>
124161 … <description>Up to 13-bit differential/12-bit single ended resolution supported.</description>
124166 … <description>Up to 16-bit differential/16-bit single ended resolution supported.</description>
124173 <description>Differential Supported</description>
124180 <description>Differential operation not supported.</description>
124185 …<description>Differential operation supported. CMDLa[CTYPE] controls fields implemented.</descript…
124192 <description>Multi Vref Implemented</description>
124199 <description>Single voltage reference high (VREFH) input supported.</description>
124204 … <description>Multiple voltage reference high (VREFH) inputs supported.</description>
124211 <description>Channel Scale Width</description>
124218 <description>Channel scaling not supported.</description>
124223 <description>Channel scaling supported. 1-bit CSCALE control field.</description>
124228 <description>Channel scaling supported. 6-bit CSCALE control field.</description>
124235 <description>Voltage Reference 1 Range Control Bit Implemented</description>
124242 … <description>Range control not required. CFG[VREF1RNG] is not implemented.</description>
124247 <description>Range control required. CFG[VREF1RNG] is implemented.</description>
124254 <description>Internal ADC Clock implemented</description>
124261 <description>Internal clock source not implemented.</description>
124266 <description>Internal clock source (and CFG[ADCKEN]) implemented.</description>
124273 <description>Calibration Function Implemented</description>
124280 <description>Calibration Not Implemented.</description>
124285 <description>Calibration Implemented.</description>
124292 <description>Number of Single Ended Outputs Supported</description>
124299 … <description>This design supports one single ended conversion at a time.</description>
124304 … <description>This design supports two simultanious single ended conversions.</description>
124311 <description>Number of FIFOs</description>
124318 <description>N/A</description>
124323 <description>This design supports one result FIFO.</description>
124328 <description>This design supports two result FIFOs.</description>
124333 <description>This design supports three result FIFOs.</description>
124338 <description>This design supports four result FIFOs.</description>
124345 <description>Minor Version Number</description>
124352 <description>Major Version Number</description>
124361 <description>Parameter Register</description>
124370 <description>Trigger Number</description>
124377 <description>Result FIFO Depth</description>
124384 <description>Result FIFO depth = 1 dataword.</description>
124389 <description>Result FIFO depth = 4 datawords.</description>
124394 <description>Result FIFO depth = 8 datawords.</description>
124399 <description>Result FIFO depth = 16 datawords.</description>
124404 <description>Result FIFO depth = 32 datawords.</description>
124409 <description>Result FIFO depth = 64 datawords.</description>
124416 <description>Compare Value Number</description>
124423 <description>Command Buffer Number</description>
124432 <description>ADC Control Register</description>
124441 <description>ADC Enable</description>
124448 <description>ADC is disabled.</description>
124453 <description>ADC is enabled.</description>
124460 <description>Software Reset</description>
124467 <description>ADC logic is not reset.</description>
124472 <description>ADC logic is reset.</description>
124479 <description>Doze Enable</description>
124486 <description>ADC is enabled in Doze mode.</description>
124491 <description>ADC is disabled in Doze mode.</description>
124498 <description>Auto-Calibration Request</description>
124505 <description>No request for auto-calibration has been made.</description>
124510 <description>A request for auto-calibration has been made</description>
124517 <description>Configure for offset calibration function</description>
124524 <description>Calibration function disabled</description>
124529 <description>Request for offset calibration function</description>
124536 <description>Reset FIFO 0</description>
124543 <description>No effect.</description>
124548 <description>FIFO 0 is reset.</description>
124555 <description>Reset FIFO 1</description>
124562 <description>No effect.</description>
124567 <description>FIFO 1 is reset.</description>
124574 <description>Auto-Calibration Averages</description>
124581 <description>Single conversion.</description>
124586 <description>2 conversions averaged.</description>
124591 <description>4 conversions averaged.</description>
124596 <description>8 conversions averaged.</description>
124601 <description>16 conversions averaged.</description>
124606 <description>32 conversions averaged.</description>
124611 <description>64 conversions averaged.</description>
124616 <description>128 conversions averaged.</description>
124625 <description>ADC Status Register</description>
124634 <description>Result FIFO 0 Ready Flag</description>
124641 <description>Result FIFO 0 data level not above watermark level.</description>
124646 <description>Result FIFO 0 holding data above watermark level.</description>
124653 <description>Result FIFO 0 Overflow Flag</description>
124661 …<description>No result FIFO 0 overflow has occurred since the last time the flag was cleared.</des…
124666 …<description>At least one result FIFO 0 overflow has occurred since the last time the flag was cle…
124673 <description>Result FIFO1 Ready Flag</description>
124680 <description>Result FIFO1 data level not above watermark level.</description>
124685 <description>Result FIFO1 holding data above watermark level.</description>
124692 <description>Result FIFO1 Overflow Flag</description>
124700 …<description>No result FIFO1 overflow has occurred since the last time the flag was cleared.</desc…
124705 …<description>At least one result FIFO1 overflow has occurred since the last time the flag was clea…
124712 <description>Interrupt Flag For High Priority Trigger Exception</description>
124720 <description>No trigger exceptions have occurred.</description>
124725 … <description>A trigger exception has occurred and is pending acknowledgement.</description>
124732 <description>Interrupt Flag For Trigger Completion</description>
124740 …<description>Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.</des…
124745 …<description>Trigger sequence has been completed and all data is stored in the associated FIFO.</d…
124752 <description>Calibration Ready</description>
124759 <description>Calibration is incomplete or hasn't been ran.</description>
124764 <description>The ADC is calibrated.</description>
124771 <description>ADC Active</description>
124778 …<description>The ADC is IDLE. There are no pending triggers to service and no active commands are …
124783 …<description>The ADC is processing a conversion, running through the power up delay, or servicing …
124790 <description>Trigger Active</description>
124797 … <description>Command (sequence) associated with Trigger 0 currently being executed.</description>
124802 … <description>Command (sequence) associated with Trigger 1 currently being executed.</description>
124807 … <description>Command (sequence) associated with Trigger 2 currently being executed.</description>
124812 … <description>Command (sequence) associated with Trigger 3 currently being executed.</description>
124819 <description>Command Active</description>
124826 <description>No command is currently in progress.</description>
124831 <description>Command 1 currently being executed.</description>
124836 <description>Command 2 currently being executed.</description>
124841 <description>Associated command number is currently being executed.</description>
124846 <description>Associated command number is currently being executed.</description>
124851 <description>Associated command number is currently being executed.</description>
124856 <description>Associated command number is currently being executed.</description>
124861 <description>Associated command number is currently being executed.</description>
124866 <description>Associated command number is currently being executed.</description>
124871 <description>Associated command number is currently being executed.</description>
124880 <description>Interrupt Enable Register</description>
124889 <description>FIFO 0 Watermark Interrupt Enable</description>
124896 <description>FIFO 0 watermark interrupts are not enabled.</description>
124901 <description>FIFO 0 watermark interrupts are enabled.</description>
124908 <description>Result FIFO 0 Overflow Interrupt Enable</description>
124915 <description>FIFO 0 overflow interrupts are not enabled.</description>
124920 <description>FIFO 0 overflow interrupts are enabled.</description>
124927 <description>FIFO1 Watermark Interrupt Enable</description>
124934 <description>FIFO1 watermark interrupts are not enabled.</description>
124939 <description>FIFO1 watermark interrupts are enabled.</description>
124946 <description>Result FIFO1 Overflow Interrupt Enable</description>
124953 …<description>No result FIFO1 overflow has occurred since the last time the flag was cleared.</desc…
124958 …<description>At least one result FIFO1 overflow has occurred since the last time the flag was clea…
124965 <description>Trigger Exception Interrupt Enable</description>
124972 <description>Trigger exception interrupts are disabled.</description>
124977 <description>Trigger exception interrupts are enabled.</description>
124984 <description>Trigger Completion Interrupt Enable</description>
124991 <description>Trigger completion interrupts are disabled.</description>
124996 … <description>Trigger completion interrupts are enabled for trigger source 0 only.</description>
125001 … <description>Trigger completion interrupts are enabled for trigger source 1 only.</description>
125006 <description>Associated trigger completion interrupts are enabled.</description>
125011 <description>Associated trigger completion interrupts are enabled.</description>
125016 <description>Associated trigger completion interrupts are enabled.</description>
125021 <description>Associated trigger completion interrupts are enabled.</description>
125026 <description>Associated trigger completion interrupts are enabled.</description>
125031 <description>Associated trigger completion interrupts are enabled.</description>
125036 <description>Associated trigger completion interrupts are enabled.</description>
125041 … <description>Trigger completion interrupts are enabled for every trigger source.</description>
125050 <description>DMA Enable Register</description>
125059 <description>FIFO 0 Watermark DMA Enable</description>
125066 <description>DMA request disabled.</description>
125071 <description>DMA request enabled.</description>
125078 <description>FIFO1 Watermark DMA Enable</description>
125085 <description>DMA request disabled.</description>
125090 <description>DMA request enabled.</description>
125099 <description>ADC Configuration Register</description>
125108 <description>ADC trigger priority control</description>
125115 …description>If a higher priority trigger is detected during command processing, the current conver…
125120 …description>If a higher priority trigger is received during command processing, the current comman…
125125 …description>If a higher priority trigger is received during command processing, the current comman…
125132 <description>Power Configuration Select</description>
125139 <description>Low power setting.</description>
125144 <description>High power setting.</description>
125151 <description>Voltage Reference Selection</description>
125158 <description>(Default) Option 1 setting.</description>
125163 <description>Option 2 setting.</description>
125168 <description>Option 3 setting.</description>
125175 <description>Trigger Resume Enable</description>
125182 …<description>Trigger sequences interrupted by a high priority trigger exception are not automatica…
125187 …<description>Trigger sequences interrupted by a high priority trigger exception are automatically …
125194 <description>Trigger Command Resume</description>
125201 …<description>Trigger sequences interrupted by a high priority trigger exception is automatically r…
125206 …<description>Trigger sequences interrupted by a high priority trigger exception is resumed from th…
125213 <description>High Priority Trigger Exception Disable</description>
125220 <description>High priority trigger exceptions are enabled.</description>
125225 <description>High priority trigger exceptions are disabled.</description>
125232 <description>Power Up Delay</description>
125239 <description>ADC Analog Pre-Enable</description>
125246 …<description>ADC analog circuits are only enabled while conversions are active. Performance is aff…
125251 …description>ADC analog circuits are pre-enabled and ready to execute conversions without startup d…
125260 <description>ADC Pause Register</description>
125269 <description>Pause Delay</description>
125276 <description>PAUSE Option Enable</description>
125283 <description>Pause operation disabled</description>
125288 <description>Pause operation enabled</description>
125297 <description>Software Trigger Register</description>
125306 <description>Software trigger 0 event</description>
125313 <description>No trigger 0 event generated.</description>
125318 <description>Trigger 0 event generated.</description>
125325 <description>Software trigger 1 event</description>
125332 <description>No trigger 1 event generated.</description>
125337 <description>Trigger 1 event generated.</description>
125344 <description>Software trigger 2 event</description>
125351 <description>No trigger 2 event generated.</description>
125356 <description>Trigger 2 event generated.</description>
125363 <description>Software trigger 3 event</description>
125370 <description>No trigger 3 event generated.</description>
125375 <description>Trigger 3 event generated.</description>
125384 <description>Trigger Status Register</description>
125393 <description>Trigger Exception Number</description>
125401 …<description>No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.</de…
125406 … <description>Trigger 0 has been interrupted by a high priority exception.</description>
125411 … <description>Trigger 1 has been interrupted by a high priority exception.</description>
125416 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125421 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125426 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125431 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125436 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125441 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125446 …<description>Associated trigger sequence has interrupted by a high priority exception.</descriptio…
125451 …<description>Every trigger sequence has been interrupted by a high priority exception.</descriptio…
125458 <description>Trigger Completion Flag</description>
125466 …<description>No triggers have been completed. Trigger completion interrupts are disabled.</descrip…
125471 …<description>Trigger 0 has been completed and triger 0 has enabled completion interrupts.</descrip…
125476 …<description>Trigger 1 has been completed and triger 1 has enabled completion interrupts.</descrip…
125481 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125486 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125491 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125496 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125501 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125506 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125511 …<description>Associated trigger sequence has completed and has enabled completion interrupts.</des…
125516 …<description>Every trigger sequence has been completed and every trigger has enabled completion in…
125525 <description>ADC Offset Trim Register</description>
125534 <description>Trim for offset</description>
125541 <description>Trim for offset</description>
125552 <description>Trigger Control Register</description>
125561 <description>Trigger enable</description>
125568 <description>Hardware trigger source disabled</description>
125573 <description>Hardware trigger source enabled</description>
125580 <description>SAR Result Destination For Channel A</description>
125587 <description>Result written to FIFO 0</description>
125592 <description>Result written to FIFO 1</description>
125599 <description>SAR Result Destination For Channel B</description>
125606 <description>Result written to FIFO 0</description>
125611 <description>Result written to FIFO 1</description>
125618 <description>Trigger priority setting</description>
125625 <description>Set to highest priority, Level 1</description>
125630 <description>Set to corresponding priority level</description>
125635 <description>Set to corresponding priority level</description>
125640 <description>Set to lowest priority, Level 4</description>
125647 <description>Trigger Resync</description>
125654 <description>Trigger delay select</description>
125661 <description>Trigger command select</description>
125668 …<description>Not a valid selection from the command buffer. Trigger event is ignored.</description>
125673 <description>CMD1 is executed</description>
125678 <description>Corresponding CMD is executed</description>
125683 <description>Corresponding CMD is executed</description>
125688 <description>Corresponding CMD is executed</description>
125693 <description>Corresponding CMD is executed</description>
125698 <description>Corresponding CMD is executed</description>
125703 <description>Corresponding CMD is executed</description>
125708 <description>Corresponding CMD is executed</description>
125713 <description>Corresponding CMD is executed</description>
125718 <description>CMD15 is executed</description>
125729 <description>FIFO Control Register</description>
125738 <description>Result FIFO counter</description>
125745 <description>Watermark level selection</description>
125756 <description>Gain Calibration Control</description>
125765 <description>Gain Calibration Value</description>
125772 <description>Gain Calibration Value Valid</description>
125779 …<description>The gain calibration value is invalid. Run the auto-calibration routine for this valu…
125784 …<description>The gain calibration value is valid. It should be used to update the GCRa[GCALR] regi…
125795 <description>Gain Calculation Result</description>
125804 <description>Gain Calculation Result</description>
125811 <description>Gain Calculation Ready</description>
125818 <description>The gain offset calculation value is invalid.</description>
125823 <description>The gain calibration value is valid.</description>
125832 <description>ADC Command Low Buffer Register</description>
125841 <description>Input channel select</description>
125848 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
125853 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
125858 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
125863 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
125868 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125873 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125878 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125883 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125888 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125893 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
125898 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
125903 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
125910 <description>Conversion Type</description>
125917 <description>Single-Ended Mode. Only A side channel is converted.</description>
125922 <description>Single-Ended Mode. Only B side channel is converted.</description>
125927 <description>Differential Mode. A-B.</description>
125932 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
125939 <description>Select resolution of conversions</description>
125946 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
125951 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
125958 <description>Alternate Channel B Input channel select</description>
125965 <description>Select CH0B</description>
125970 <description>Select CH1B</description>
125975 <description>Select CH2B</description>
125980 <description>Select CH3B</description>
125985 <description>Select corresponding channel CHnB</description>
125990 <description>Select corresponding channel CHnB</description>
125995 <description>Select corresponding channel CHnB</description>
126000 <description>Select corresponding channel CHnB</description>
126005 <description>Select corresponding channel CHnB</description>
126010 <description>Select corresponding channel CHnB</description>
126015 <description>Select CH30B</description>
126020 <description>Select CH31B</description>
126027 <description>Alternate Channel B Select Enable</description>
126034 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
126039 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
126048 <description>ADC Command High Buffer Register</description>
126057 <description>Compare Function Enable</description>
126064 <description>Compare disabled.</description>
126069 <description>Compare enabled. Store on true.</description>
126074 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
126081 <description>Wait for trigger assertion before execution.</description>
126088 <description>This command will be automatically executed.</description>
126093 …<description>The active trigger must be asserted again before executing this command.</description>
126100 <description>Loop with Increment</description>
126107 <description>Auto channel increment disabled</description>
126112 <description>Auto channel increment enabled</description>
126119 <description>Sample Time Select</description>
126126 <description>Minimum sample time of 3 ADCK cycles.</description>
126131 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
126136 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
126141 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
126146 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
126151 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
126156 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
126161 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
126168 <description>Hardware Average Select</description>
126175 <description>Single conversion.</description>
126180 <description>2 conversions averaged.</description>
126185 <description>4 conversions averaged.</description>
126190 <description>8 conversions averaged.</description>
126195 <description>16 conversions averaged.</description>
126200 <description>32 conversions averaged.</description>
126205 <description>64 conversions averaged.</description>
126210 <description>128 conversions averaged.</description>
126217 <description>Loop Count Select</description>
126224 <description>Looping not enabled. Command executes 1 time.</description>
126229 <description>Loop 1 time. Command executes 2 times.</description>
126234 <description>Loop 2 times. Command executes 3 times.</description>
126239 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126244 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126249 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126254 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126259 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126264 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126269 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126274 <description>Loop 15 times. Command executes 16 times.</description>
126281 <description>Next Command Select</description>
126288 …description>No next command defined. Terminate conversions at completion of current command. If lo…
126293 <description>Select CMD1 command buffer register as next command.</description>
126298 … <description>Select corresponding CMD command buffer register as next command</description>
126303 … <description>Select corresponding CMD command buffer register as next command</description>
126308 … <description>Select corresponding CMD command buffer register as next command</description>
126313 … <description>Select corresponding CMD command buffer register as next command</description>
126318 … <description>Select corresponding CMD command buffer register as next command</description>
126323 … <description>Select corresponding CMD command buffer register as next command</description>
126328 … <description>Select corresponding CMD command buffer register as next command</description>
126333 … <description>Select corresponding CMD command buffer register as next command</description>
126338 <description>Select CMD15 command buffer register as next command.</description>
126347 <description>ADC Command Low Buffer Register</description>
126356 <description>Input channel select</description>
126363 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
126368 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
126373 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
126378 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
126383 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126388 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126393 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126398 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126403 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126408 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126413 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
126418 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
126425 <description>Conversion Type</description>
126432 <description>Single-Ended Mode. Only A side channel is converted.</description>
126437 <description>Single-Ended Mode. Only B side channel is converted.</description>
126442 <description>Differential Mode. A-B.</description>
126447 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
126454 <description>Select resolution of conversions</description>
126461 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
126466 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
126473 <description>Alternate Channel B Input channel select</description>
126480 <description>Select CH0B</description>
126485 <description>Select CH1B</description>
126490 <description>Select CH2B</description>
126495 <description>Select CH3B</description>
126500 <description>Select corresponding channel CHnB</description>
126505 <description>Select corresponding channel CHnB</description>
126510 <description>Select corresponding channel CHnB</description>
126515 <description>Select corresponding channel CHnB</description>
126520 <description>Select corresponding channel CHnB</description>
126525 <description>Select corresponding channel CHnB</description>
126530 <description>Select CH30B</description>
126535 <description>Select CH31B</description>
126542 <description>Alternate Channel B Select Enable</description>
126549 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
126554 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
126563 <description>ADC Command High Buffer Register</description>
126572 <description>Compare Function Enable</description>
126579 <description>Compare disabled.</description>
126584 <description>Compare enabled. Store on true.</description>
126589 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
126596 <description>Wait for trigger assertion before execution.</description>
126603 <description>This command will be automatically executed.</description>
126608 …<description>The active trigger must be asserted again before executing this command.</description>
126615 <description>Loop with Increment</description>
126622 <description>Auto channel increment disabled</description>
126627 <description>Auto channel increment enabled</description>
126634 <description>Sample Time Select</description>
126641 <description>Minimum sample time of 3 ADCK cycles.</description>
126646 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
126651 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
126656 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
126661 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
126666 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
126671 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
126676 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
126683 <description>Hardware Average Select</description>
126690 <description>Single conversion.</description>
126695 <description>2 conversions averaged.</description>
126700 <description>4 conversions averaged.</description>
126705 <description>8 conversions averaged.</description>
126710 <description>16 conversions averaged.</description>
126715 <description>32 conversions averaged.</description>
126720 <description>64 conversions averaged.</description>
126725 <description>128 conversions averaged.</description>
126732 <description>Loop Count Select</description>
126739 <description>Looping not enabled. Command executes 1 time.</description>
126744 <description>Loop 1 time. Command executes 2 times.</description>
126749 <description>Loop 2 times. Command executes 3 times.</description>
126754 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126759 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126764 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126769 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126774 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126779 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126784 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
126789 <description>Loop 15 times. Command executes 16 times.</description>
126796 <description>Next Command Select</description>
126803 …description>No next command defined. Terminate conversions at completion of current command. If lo…
126808 <description>Select CMD1 command buffer register as next command.</description>
126813 … <description>Select corresponding CMD command buffer register as next command</description>
126818 … <description>Select corresponding CMD command buffer register as next command</description>
126823 … <description>Select corresponding CMD command buffer register as next command</description>
126828 … <description>Select corresponding CMD command buffer register as next command</description>
126833 … <description>Select corresponding CMD command buffer register as next command</description>
126838 … <description>Select corresponding CMD command buffer register as next command</description>
126843 … <description>Select corresponding CMD command buffer register as next command</description>
126848 … <description>Select corresponding CMD command buffer register as next command</description>
126853 <description>Select CMD15 command buffer register as next command.</description>
126862 <description>ADC Command Low Buffer Register</description>
126871 <description>Input channel select</description>
126878 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
126883 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
126888 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
126893 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
126898 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126903 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126908 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126913 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126918 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126923 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
126928 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
126933 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
126940 <description>Conversion Type</description>
126947 <description>Single-Ended Mode. Only A side channel is converted.</description>
126952 <description>Single-Ended Mode. Only B side channel is converted.</description>
126957 <description>Differential Mode. A-B.</description>
126962 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
126969 <description>Select resolution of conversions</description>
126976 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
126981 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
126988 <description>Alternate Channel B Input channel select</description>
126995 <description>Select CH0B</description>
127000 <description>Select CH1B</description>
127005 <description>Select CH2B</description>
127010 <description>Select CH3B</description>
127015 <description>Select corresponding channel CHnB</description>
127020 <description>Select corresponding channel CHnB</description>
127025 <description>Select corresponding channel CHnB</description>
127030 <description>Select corresponding channel CHnB</description>
127035 <description>Select corresponding channel CHnB</description>
127040 <description>Select corresponding channel CHnB</description>
127045 <description>Select CH30B</description>
127050 <description>Select CH31B</description>
127057 <description>Alternate Channel B Select Enable</description>
127064 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
127069 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
127078 <description>ADC Command High Buffer Register</description>
127087 <description>Compare Function Enable</description>
127094 <description>Compare disabled.</description>
127099 <description>Compare enabled. Store on true.</description>
127104 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
127111 <description>Wait for trigger assertion before execution.</description>
127118 <description>This command will be automatically executed.</description>
127123 …<description>The active trigger must be asserted again before executing this command.</description>
127130 <description>Loop with Increment</description>
127137 <description>Auto channel increment disabled</description>
127142 <description>Auto channel increment enabled</description>
127149 <description>Sample Time Select</description>
127156 <description>Minimum sample time of 3 ADCK cycles.</description>
127161 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
127166 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
127171 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
127176 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
127181 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
127186 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
127191 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
127198 <description>Hardware Average Select</description>
127205 <description>Single conversion.</description>
127210 <description>2 conversions averaged.</description>
127215 <description>4 conversions averaged.</description>
127220 <description>8 conversions averaged.</description>
127225 <description>16 conversions averaged.</description>
127230 <description>32 conversions averaged.</description>
127235 <description>64 conversions averaged.</description>
127240 <description>128 conversions averaged.</description>
127247 <description>Loop Count Select</description>
127254 <description>Looping not enabled. Command executes 1 time.</description>
127259 <description>Loop 1 time. Command executes 2 times.</description>
127264 <description>Loop 2 times. Command executes 3 times.</description>
127269 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127274 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127279 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127284 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127289 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127294 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127299 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127304 <description>Loop 15 times. Command executes 16 times.</description>
127311 <description>Next Command Select</description>
127318 …description>No next command defined. Terminate conversions at completion of current command. If lo…
127323 <description>Select CMD1 command buffer register as next command.</description>
127328 … <description>Select corresponding CMD command buffer register as next command</description>
127333 … <description>Select corresponding CMD command buffer register as next command</description>
127338 … <description>Select corresponding CMD command buffer register as next command</description>
127343 … <description>Select corresponding CMD command buffer register as next command</description>
127348 … <description>Select corresponding CMD command buffer register as next command</description>
127353 … <description>Select corresponding CMD command buffer register as next command</description>
127358 … <description>Select corresponding CMD command buffer register as next command</description>
127363 … <description>Select corresponding CMD command buffer register as next command</description>
127368 <description>Select CMD15 command buffer register as next command.</description>
127377 <description>ADC Command Low Buffer Register</description>
127386 <description>Input channel select</description>
127393 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
127398 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
127403 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
127408 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
127413 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127418 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127423 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127428 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127433 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127438 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127443 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
127448 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
127455 <description>Conversion Type</description>
127462 <description>Single-Ended Mode. Only A side channel is converted.</description>
127467 <description>Single-Ended Mode. Only B side channel is converted.</description>
127472 <description>Differential Mode. A-B.</description>
127477 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
127484 <description>Select resolution of conversions</description>
127491 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
127496 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
127503 <description>Alternate Channel B Input channel select</description>
127510 <description>Select CH0B</description>
127515 <description>Select CH1B</description>
127520 <description>Select CH2B</description>
127525 <description>Select CH3B</description>
127530 <description>Select corresponding channel CHnB</description>
127535 <description>Select corresponding channel CHnB</description>
127540 <description>Select corresponding channel CHnB</description>
127545 <description>Select corresponding channel CHnB</description>
127550 <description>Select corresponding channel CHnB</description>
127555 <description>Select corresponding channel CHnB</description>
127560 <description>Select CH30B</description>
127565 <description>Select CH31B</description>
127572 <description>Alternate Channel B Select Enable</description>
127579 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
127584 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
127593 <description>ADC Command High Buffer Register</description>
127602 <description>Compare Function Enable</description>
127609 <description>Compare disabled.</description>
127614 <description>Compare enabled. Store on true.</description>
127619 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
127626 <description>Wait for trigger assertion before execution.</description>
127633 <description>This command will be automatically executed.</description>
127638 …<description>The active trigger must be asserted again before executing this command.</description>
127645 <description>Loop with Increment</description>
127652 <description>Auto channel increment disabled</description>
127657 <description>Auto channel increment enabled</description>
127664 <description>Sample Time Select</description>
127671 <description>Minimum sample time of 3 ADCK cycles.</description>
127676 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
127681 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
127686 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
127691 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
127696 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
127701 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
127706 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
127713 <description>Hardware Average Select</description>
127720 <description>Single conversion.</description>
127725 <description>2 conversions averaged.</description>
127730 <description>4 conversions averaged.</description>
127735 <description>8 conversions averaged.</description>
127740 <description>16 conversions averaged.</description>
127745 <description>32 conversions averaged.</description>
127750 <description>64 conversions averaged.</description>
127755 <description>128 conversions averaged.</description>
127762 <description>Loop Count Select</description>
127769 <description>Looping not enabled. Command executes 1 time.</description>
127774 <description>Loop 1 time. Command executes 2 times.</description>
127779 <description>Loop 2 times. Command executes 3 times.</description>
127784 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127789 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127794 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127799 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127804 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127809 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127814 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
127819 <description>Loop 15 times. Command executes 16 times.</description>
127826 <description>Next Command Select</description>
127833 …description>No next command defined. Terminate conversions at completion of current command. If lo…
127838 <description>Select CMD1 command buffer register as next command.</description>
127843 … <description>Select corresponding CMD command buffer register as next command</description>
127848 … <description>Select corresponding CMD command buffer register as next command</description>
127853 … <description>Select corresponding CMD command buffer register as next command</description>
127858 … <description>Select corresponding CMD command buffer register as next command</description>
127863 … <description>Select corresponding CMD command buffer register as next command</description>
127868 … <description>Select corresponding CMD command buffer register as next command</description>
127873 … <description>Select corresponding CMD command buffer register as next command</description>
127878 … <description>Select corresponding CMD command buffer register as next command</description>
127883 <description>Select CMD15 command buffer register as next command.</description>
127892 <description>ADC Command Low Buffer Register</description>
127901 <description>Input channel select</description>
127908 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
127913 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
127918 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
127923 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
127928 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127933 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127938 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127943 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127948 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127953 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
127958 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
127963 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
127970 <description>Conversion Type</description>
127977 <description>Single-Ended Mode. Only A side channel is converted.</description>
127982 <description>Single-Ended Mode. Only B side channel is converted.</description>
127987 <description>Differential Mode. A-B.</description>
127992 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
127999 <description>Select resolution of conversions</description>
128006 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
128011 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
128018 <description>Alternate Channel B Input channel select</description>
128025 <description>Select CH0B</description>
128030 <description>Select CH1B</description>
128035 <description>Select CH2B</description>
128040 <description>Select CH3B</description>
128045 <description>Select corresponding channel CHnB</description>
128050 <description>Select corresponding channel CHnB</description>
128055 <description>Select corresponding channel CHnB</description>
128060 <description>Select corresponding channel CHnB</description>
128065 <description>Select corresponding channel CHnB</description>
128070 <description>Select corresponding channel CHnB</description>
128075 <description>Select CH30B</description>
128080 <description>Select CH31B</description>
128087 <description>Alternate Channel B Select Enable</description>
128094 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
128099 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
128108 <description>ADC Command High Buffer Register</description>
128117 <description>Compare Function Enable</description>
128124 <description>Compare disabled.</description>
128129 <description>Compare enabled. Store on true.</description>
128134 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
128141 <description>Wait for trigger assertion before execution.</description>
128148 <description>This command will be automatically executed.</description>
128153 …<description>The active trigger must be asserted again before executing this command.</description>
128160 <description>Loop with Increment</description>
128167 <description>Auto channel increment disabled</description>
128172 <description>Auto channel increment enabled</description>
128179 <description>Sample Time Select</description>
128186 <description>Minimum sample time of 3 ADCK cycles.</description>
128191 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
128196 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
128201 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
128206 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
128211 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
128216 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
128221 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
128228 <description>Hardware Average Select</description>
128235 <description>Single conversion.</description>
128240 <description>2 conversions averaged.</description>
128245 <description>4 conversions averaged.</description>
128250 <description>8 conversions averaged.</description>
128255 <description>16 conversions averaged.</description>
128260 <description>32 conversions averaged.</description>
128265 <description>64 conversions averaged.</description>
128270 <description>128 conversions averaged.</description>
128277 <description>Loop Count Select</description>
128284 <description>Looping not enabled. Command executes 1 time.</description>
128289 <description>Loop 1 time. Command executes 2 times.</description>
128294 <description>Loop 2 times. Command executes 3 times.</description>
128299 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128304 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128309 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128314 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128319 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128324 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128329 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128334 <description>Loop 15 times. Command executes 16 times.</description>
128341 <description>Next Command Select</description>
128348 …description>No next command defined. Terminate conversions at completion of current command. If lo…
128353 <description>Select CMD1 command buffer register as next command.</description>
128358 … <description>Select corresponding CMD command buffer register as next command</description>
128363 … <description>Select corresponding CMD command buffer register as next command</description>
128368 … <description>Select corresponding CMD command buffer register as next command</description>
128373 … <description>Select corresponding CMD command buffer register as next command</description>
128378 … <description>Select corresponding CMD command buffer register as next command</description>
128383 … <description>Select corresponding CMD command buffer register as next command</description>
128388 … <description>Select corresponding CMD command buffer register as next command</description>
128393 … <description>Select corresponding CMD command buffer register as next command</description>
128398 <description>Select CMD15 command buffer register as next command.</description>
128407 <description>ADC Command Low Buffer Register</description>
128416 <description>Input channel select</description>
128423 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
128428 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
128433 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
128438 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
128443 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128448 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128453 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128458 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128463 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128468 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128473 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
128478 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
128485 <description>Conversion Type</description>
128492 <description>Single-Ended Mode. Only A side channel is converted.</description>
128497 <description>Single-Ended Mode. Only B side channel is converted.</description>
128502 <description>Differential Mode. A-B.</description>
128507 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
128514 <description>Select resolution of conversions</description>
128521 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
128526 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
128533 <description>Alternate Channel B Input channel select</description>
128540 <description>Select CH0B</description>
128545 <description>Select CH1B</description>
128550 <description>Select CH2B</description>
128555 <description>Select CH3B</description>
128560 <description>Select corresponding channel CHnB</description>
128565 <description>Select corresponding channel CHnB</description>
128570 <description>Select corresponding channel CHnB</description>
128575 <description>Select corresponding channel CHnB</description>
128580 <description>Select corresponding channel CHnB</description>
128585 <description>Select corresponding channel CHnB</description>
128590 <description>Select CH30B</description>
128595 <description>Select CH31B</description>
128602 <description>Alternate Channel B Select Enable</description>
128609 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
128614 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
128623 <description>ADC Command High Buffer Register</description>
128632 <description>Compare Function Enable</description>
128639 <description>Compare disabled.</description>
128644 <description>Compare enabled. Store on true.</description>
128649 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
128656 <description>Wait for trigger assertion before execution.</description>
128663 <description>This command will be automatically executed.</description>
128668 …<description>The active trigger must be asserted again before executing this command.</description>
128675 <description>Loop with Increment</description>
128682 <description>Auto channel increment disabled</description>
128687 <description>Auto channel increment enabled</description>
128694 <description>Sample Time Select</description>
128701 <description>Minimum sample time of 3 ADCK cycles.</description>
128706 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
128711 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
128716 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
128721 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
128726 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
128731 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
128736 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
128743 <description>Hardware Average Select</description>
128750 <description>Single conversion.</description>
128755 <description>2 conversions averaged.</description>
128760 <description>4 conversions averaged.</description>
128765 <description>8 conversions averaged.</description>
128770 <description>16 conversions averaged.</description>
128775 <description>32 conversions averaged.</description>
128780 <description>64 conversions averaged.</description>
128785 <description>128 conversions averaged.</description>
128792 <description>Loop Count Select</description>
128799 <description>Looping not enabled. Command executes 1 time.</description>
128804 <description>Loop 1 time. Command executes 2 times.</description>
128809 <description>Loop 2 times. Command executes 3 times.</description>
128814 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128819 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128824 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128829 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128834 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128839 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128844 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
128849 <description>Loop 15 times. Command executes 16 times.</description>
128856 <description>Next Command Select</description>
128863 …description>No next command defined. Terminate conversions at completion of current command. If lo…
128868 <description>Select CMD1 command buffer register as next command.</description>
128873 … <description>Select corresponding CMD command buffer register as next command</description>
128878 … <description>Select corresponding CMD command buffer register as next command</description>
128883 … <description>Select corresponding CMD command buffer register as next command</description>
128888 … <description>Select corresponding CMD command buffer register as next command</description>
128893 … <description>Select corresponding CMD command buffer register as next command</description>
128898 … <description>Select corresponding CMD command buffer register as next command</description>
128903 … <description>Select corresponding CMD command buffer register as next command</description>
128908 … <description>Select corresponding CMD command buffer register as next command</description>
128913 <description>Select CMD15 command buffer register as next command.</description>
128922 <description>ADC Command Low Buffer Register</description>
128931 <description>Input channel select</description>
128938 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
128943 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
128948 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
128953 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
128958 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128963 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128968 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128973 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128978 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128983 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
128988 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
128993 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
129000 <description>Conversion Type</description>
129007 <description>Single-Ended Mode. Only A side channel is converted.</description>
129012 <description>Single-Ended Mode. Only B side channel is converted.</description>
129017 <description>Differential Mode. A-B.</description>
129022 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
129029 <description>Select resolution of conversions</description>
129036 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
129041 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
129048 <description>Alternate Channel B Input channel select</description>
129055 <description>Select CH0B</description>
129060 <description>Select CH1B</description>
129065 <description>Select CH2B</description>
129070 <description>Select CH3B</description>
129075 <description>Select corresponding channel CHnB</description>
129080 <description>Select corresponding channel CHnB</description>
129085 <description>Select corresponding channel CHnB</description>
129090 <description>Select corresponding channel CHnB</description>
129095 <description>Select corresponding channel CHnB</description>
129100 <description>Select corresponding channel CHnB</description>
129105 <description>Select CH30B</description>
129110 <description>Select CH31B</description>
129117 <description>Alternate Channel B Select Enable</description>
129124 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
129129 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
129138 <description>ADC Command High Buffer Register</description>
129147 <description>Compare Function Enable</description>
129154 <description>Compare disabled.</description>
129159 <description>Compare enabled. Store on true.</description>
129164 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
129171 <description>Wait for trigger assertion before execution.</description>
129178 <description>This command will be automatically executed.</description>
129183 …<description>The active trigger must be asserted again before executing this command.</description>
129190 <description>Loop with Increment</description>
129197 <description>Auto channel increment disabled</description>
129202 <description>Auto channel increment enabled</description>
129209 <description>Sample Time Select</description>
129216 <description>Minimum sample time of 3 ADCK cycles.</description>
129221 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
129226 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
129231 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
129236 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
129241 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
129246 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
129251 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
129258 <description>Hardware Average Select</description>
129265 <description>Single conversion.</description>
129270 <description>2 conversions averaged.</description>
129275 <description>4 conversions averaged.</description>
129280 <description>8 conversions averaged.</description>
129285 <description>16 conversions averaged.</description>
129290 <description>32 conversions averaged.</description>
129295 <description>64 conversions averaged.</description>
129300 <description>128 conversions averaged.</description>
129307 <description>Loop Count Select</description>
129314 <description>Looping not enabled. Command executes 1 time.</description>
129319 <description>Loop 1 time. Command executes 2 times.</description>
129324 <description>Loop 2 times. Command executes 3 times.</description>
129329 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129334 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129339 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129344 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129349 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129354 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129359 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129364 <description>Loop 15 times. Command executes 16 times.</description>
129371 <description>Next Command Select</description>
129378 …description>No next command defined. Terminate conversions at completion of current command. If lo…
129383 <description>Select CMD1 command buffer register as next command.</description>
129388 … <description>Select corresponding CMD command buffer register as next command</description>
129393 … <description>Select corresponding CMD command buffer register as next command</description>
129398 … <description>Select corresponding CMD command buffer register as next command</description>
129403 … <description>Select corresponding CMD command buffer register as next command</description>
129408 … <description>Select corresponding CMD command buffer register as next command</description>
129413 … <description>Select corresponding CMD command buffer register as next command</description>
129418 … <description>Select corresponding CMD command buffer register as next command</description>
129423 … <description>Select corresponding CMD command buffer register as next command</description>
129428 <description>Select CMD15 command buffer register as next command.</description>
129437 <description>ADC Command Low Buffer Register</description>
129446 <description>Input channel select</description>
129453 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
129458 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
129463 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
129468 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
129473 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129478 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129483 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129488 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129493 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129498 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129503 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
129508 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
129515 <description>Conversion Type</description>
129522 <description>Single-Ended Mode. Only A side channel is converted.</description>
129527 <description>Single-Ended Mode. Only B side channel is converted.</description>
129532 <description>Differential Mode. A-B.</description>
129537 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
129544 <description>Select resolution of conversions</description>
129551 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
129556 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
129563 <description>Alternate Channel B Input channel select</description>
129570 <description>Select CH0B</description>
129575 <description>Select CH1B</description>
129580 <description>Select CH2B</description>
129585 <description>Select CH3B</description>
129590 <description>Select corresponding channel CHnB</description>
129595 <description>Select corresponding channel CHnB</description>
129600 <description>Select corresponding channel CHnB</description>
129605 <description>Select corresponding channel CHnB</description>
129610 <description>Select corresponding channel CHnB</description>
129615 <description>Select corresponding channel CHnB</description>
129620 <description>Select CH30B</description>
129625 <description>Select CH31B</description>
129632 <description>Alternate Channel B Select Enable</description>
129639 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
129644 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
129653 <description>ADC Command High Buffer Register</description>
129662 <description>Compare Function Enable</description>
129669 <description>Compare disabled.</description>
129674 <description>Compare enabled. Store on true.</description>
129679 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
129686 <description>Wait for trigger assertion before execution.</description>
129693 <description>This command will be automatically executed.</description>
129698 …<description>The active trigger must be asserted again before executing this command.</description>
129705 <description>Loop with Increment</description>
129712 <description>Auto channel increment disabled</description>
129717 <description>Auto channel increment enabled</description>
129724 <description>Sample Time Select</description>
129731 <description>Minimum sample time of 3 ADCK cycles.</description>
129736 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
129741 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
129746 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
129751 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
129756 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
129761 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
129766 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
129773 <description>Hardware Average Select</description>
129780 <description>Single conversion.</description>
129785 <description>2 conversions averaged.</description>
129790 <description>4 conversions averaged.</description>
129795 <description>8 conversions averaged.</description>
129800 <description>16 conversions averaged.</description>
129805 <description>32 conversions averaged.</description>
129810 <description>64 conversions averaged.</description>
129815 <description>128 conversions averaged.</description>
129822 <description>Loop Count Select</description>
129829 <description>Looping not enabled. Command executes 1 time.</description>
129834 <description>Loop 1 time. Command executes 2 times.</description>
129839 <description>Loop 2 times. Command executes 3 times.</description>
129844 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129849 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129854 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129859 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129864 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129869 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129874 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
129879 <description>Loop 15 times. Command executes 16 times.</description>
129886 <description>Next Command Select</description>
129893 …description>No next command defined. Terminate conversions at completion of current command. If lo…
129898 <description>Select CMD1 command buffer register as next command.</description>
129903 … <description>Select corresponding CMD command buffer register as next command</description>
129908 … <description>Select corresponding CMD command buffer register as next command</description>
129913 … <description>Select corresponding CMD command buffer register as next command</description>
129918 … <description>Select corresponding CMD command buffer register as next command</description>
129923 … <description>Select corresponding CMD command buffer register as next command</description>
129928 … <description>Select corresponding CMD command buffer register as next command</description>
129933 … <description>Select corresponding CMD command buffer register as next command</description>
129938 … <description>Select corresponding CMD command buffer register as next command</description>
129943 <description>Select CMD15 command buffer register as next command.</description>
129952 <description>ADC Command Low Buffer Register</description>
129961 <description>Input channel select</description>
129968 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
129973 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
129978 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
129983 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
129988 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129993 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
129998 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130003 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130008 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130013 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130018 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
130023 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
130030 <description>Conversion Type</description>
130037 <description>Single-Ended Mode. Only A side channel is converted.</description>
130042 <description>Single-Ended Mode. Only B side channel is converted.</description>
130047 <description>Differential Mode. A-B.</description>
130052 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
130059 <description>Select resolution of conversions</description>
130066 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
130071 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
130078 <description>Alternate Channel B Input channel select</description>
130085 <description>Select CH0B</description>
130090 <description>Select CH1B</description>
130095 <description>Select CH2B</description>
130100 <description>Select CH3B</description>
130105 <description>Select corresponding channel CHnB</description>
130110 <description>Select corresponding channel CHnB</description>
130115 <description>Select corresponding channel CHnB</description>
130120 <description>Select corresponding channel CHnB</description>
130125 <description>Select corresponding channel CHnB</description>
130130 <description>Select corresponding channel CHnB</description>
130135 <description>Select CH30B</description>
130140 <description>Select CH31B</description>
130147 <description>Alternate Channel B Select Enable</description>
130154 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
130159 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
130168 <description>ADC Command High Buffer Register</description>
130177 <description>Compare Function Enable</description>
130184 <description>Compare disabled.</description>
130189 <description>Compare enabled. Store on true.</description>
130194 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
130201 <description>Wait for trigger assertion before execution.</description>
130208 <description>This command will be automatically executed.</description>
130213 …<description>The active trigger must be asserted again before executing this command.</description>
130220 <description>Loop with Increment</description>
130227 <description>Auto channel increment disabled</description>
130232 <description>Auto channel increment enabled</description>
130239 <description>Sample Time Select</description>
130246 <description>Minimum sample time of 3 ADCK cycles.</description>
130251 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
130256 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
130261 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
130266 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
130271 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
130276 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
130281 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
130288 <description>Hardware Average Select</description>
130295 <description>Single conversion.</description>
130300 <description>2 conversions averaged.</description>
130305 <description>4 conversions averaged.</description>
130310 <description>8 conversions averaged.</description>
130315 <description>16 conversions averaged.</description>
130320 <description>32 conversions averaged.</description>
130325 <description>64 conversions averaged.</description>
130330 <description>128 conversions averaged.</description>
130337 <description>Loop Count Select</description>
130344 <description>Looping not enabled. Command executes 1 time.</description>
130349 <description>Loop 1 time. Command executes 2 times.</description>
130354 <description>Loop 2 times. Command executes 3 times.</description>
130359 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130364 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130369 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130374 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130379 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130384 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130389 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130394 <description>Loop 15 times. Command executes 16 times.</description>
130401 <description>Next Command Select</description>
130408 …description>No next command defined. Terminate conversions at completion of current command. If lo…
130413 <description>Select CMD1 command buffer register as next command.</description>
130418 … <description>Select corresponding CMD command buffer register as next command</description>
130423 … <description>Select corresponding CMD command buffer register as next command</description>
130428 … <description>Select corresponding CMD command buffer register as next command</description>
130433 … <description>Select corresponding CMD command buffer register as next command</description>
130438 … <description>Select corresponding CMD command buffer register as next command</description>
130443 … <description>Select corresponding CMD command buffer register as next command</description>
130448 … <description>Select corresponding CMD command buffer register as next command</description>
130453 … <description>Select corresponding CMD command buffer register as next command</description>
130458 <description>Select CMD15 command buffer register as next command.</description>
130467 <description>ADC Command Low Buffer Register</description>
130476 <description>Input channel select</description>
130483 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
130488 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
130493 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
130498 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
130503 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130508 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130513 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130518 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130523 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130528 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
130533 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
130538 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
130545 <description>Conversion Type</description>
130552 <description>Single-Ended Mode. Only A side channel is converted.</description>
130557 <description>Single-Ended Mode. Only B side channel is converted.</description>
130562 <description>Differential Mode. A-B.</description>
130567 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
130574 <description>Select resolution of conversions</description>
130581 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
130586 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
130593 <description>Alternate Channel B Input channel select</description>
130600 <description>Select CH0B</description>
130605 <description>Select CH1B</description>
130610 <description>Select CH2B</description>
130615 <description>Select CH3B</description>
130620 <description>Select corresponding channel CHnB</description>
130625 <description>Select corresponding channel CHnB</description>
130630 <description>Select corresponding channel CHnB</description>
130635 <description>Select corresponding channel CHnB</description>
130640 <description>Select corresponding channel CHnB</description>
130645 <description>Select corresponding channel CHnB</description>
130650 <description>Select CH30B</description>
130655 <description>Select CH31B</description>
130662 <description>Alternate Channel B Select Enable</description>
130669 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
130674 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
130683 <description>ADC Command High Buffer Register</description>
130692 <description>Compare Function Enable</description>
130699 <description>Compare disabled.</description>
130704 <description>Compare enabled. Store on true.</description>
130709 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
130716 <description>Wait for trigger assertion before execution.</description>
130723 <description>This command will be automatically executed.</description>
130728 …<description>The active trigger must be asserted again before executing this command.</description>
130735 <description>Loop with Increment</description>
130742 <description>Auto channel increment disabled</description>
130747 <description>Auto channel increment enabled</description>
130754 <description>Sample Time Select</description>
130761 <description>Minimum sample time of 3 ADCK cycles.</description>
130766 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
130771 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
130776 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
130781 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
130786 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
130791 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
130796 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
130803 <description>Hardware Average Select</description>
130810 <description>Single conversion.</description>
130815 <description>2 conversions averaged.</description>
130820 <description>4 conversions averaged.</description>
130825 <description>8 conversions averaged.</description>
130830 <description>16 conversions averaged.</description>
130835 <description>32 conversions averaged.</description>
130840 <description>64 conversions averaged.</description>
130845 <description>128 conversions averaged.</description>
130852 <description>Loop Count Select</description>
130859 <description>Looping not enabled. Command executes 1 time.</description>
130864 <description>Loop 1 time. Command executes 2 times.</description>
130869 <description>Loop 2 times. Command executes 3 times.</description>
130874 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130879 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130884 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130889 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130894 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130899 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130904 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
130909 <description>Loop 15 times. Command executes 16 times.</description>
130916 <description>Next Command Select</description>
130923 …description>No next command defined. Terminate conversions at completion of current command. If lo…
130928 <description>Select CMD1 command buffer register as next command.</description>
130933 … <description>Select corresponding CMD command buffer register as next command</description>
130938 … <description>Select corresponding CMD command buffer register as next command</description>
130943 … <description>Select corresponding CMD command buffer register as next command</description>
130948 … <description>Select corresponding CMD command buffer register as next command</description>
130953 … <description>Select corresponding CMD command buffer register as next command</description>
130958 … <description>Select corresponding CMD command buffer register as next command</description>
130963 … <description>Select corresponding CMD command buffer register as next command</description>
130968 … <description>Select corresponding CMD command buffer register as next command</description>
130973 <description>Select CMD15 command buffer register as next command.</description>
130982 <description>ADC Command Low Buffer Register</description>
130991 <description>Input channel select</description>
130998 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
131003 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
131008 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
131013 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
131018 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131023 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131028 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131033 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131038 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131043 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131048 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
131053 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
131060 <description>Conversion Type</description>
131067 <description>Single-Ended Mode. Only A side channel is converted.</description>
131072 <description>Single-Ended Mode. Only B side channel is converted.</description>
131077 <description>Differential Mode. A-B.</description>
131082 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
131089 <description>Select resolution of conversions</description>
131096 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
131101 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
131108 <description>Alternate Channel B Input channel select</description>
131115 <description>Select CH0B</description>
131120 <description>Select CH1B</description>
131125 <description>Select CH2B</description>
131130 <description>Select CH3B</description>
131135 <description>Select corresponding channel CHnB</description>
131140 <description>Select corresponding channel CHnB</description>
131145 <description>Select corresponding channel CHnB</description>
131150 <description>Select corresponding channel CHnB</description>
131155 <description>Select corresponding channel CHnB</description>
131160 <description>Select corresponding channel CHnB</description>
131165 <description>Select CH30B</description>
131170 <description>Select CH31B</description>
131177 <description>Alternate Channel B Select Enable</description>
131184 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
131189 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
131198 <description>ADC Command High Buffer Register</description>
131207 <description>Compare Function Enable</description>
131214 <description>Compare disabled.</description>
131219 <description>Compare enabled. Store on true.</description>
131224 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
131231 <description>Wait for trigger assertion before execution.</description>
131238 <description>This command will be automatically executed.</description>
131243 …<description>The active trigger must be asserted again before executing this command.</description>
131250 <description>Loop with Increment</description>
131257 <description>Auto channel increment disabled</description>
131262 <description>Auto channel increment enabled</description>
131269 <description>Sample Time Select</description>
131276 <description>Minimum sample time of 3 ADCK cycles.</description>
131281 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
131286 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
131291 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
131296 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
131301 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
131306 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
131311 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
131318 <description>Hardware Average Select</description>
131325 <description>Single conversion.</description>
131330 <description>2 conversions averaged.</description>
131335 <description>4 conversions averaged.</description>
131340 <description>8 conversions averaged.</description>
131345 <description>16 conversions averaged.</description>
131350 <description>32 conversions averaged.</description>
131355 <description>64 conversions averaged.</description>
131360 <description>128 conversions averaged.</description>
131367 <description>Loop Count Select</description>
131374 <description>Looping not enabled. Command executes 1 time.</description>
131379 <description>Loop 1 time. Command executes 2 times.</description>
131384 <description>Loop 2 times. Command executes 3 times.</description>
131389 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131394 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131399 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131404 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131409 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131414 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131419 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131424 <description>Loop 15 times. Command executes 16 times.</description>
131431 <description>Next Command Select</description>
131438 …description>No next command defined. Terminate conversions at completion of current command. If lo…
131443 <description>Select CMD1 command buffer register as next command.</description>
131448 … <description>Select corresponding CMD command buffer register as next command</description>
131453 … <description>Select corresponding CMD command buffer register as next command</description>
131458 … <description>Select corresponding CMD command buffer register as next command</description>
131463 … <description>Select corresponding CMD command buffer register as next command</description>
131468 … <description>Select corresponding CMD command buffer register as next command</description>
131473 … <description>Select corresponding CMD command buffer register as next command</description>
131478 … <description>Select corresponding CMD command buffer register as next command</description>
131483 … <description>Select corresponding CMD command buffer register as next command</description>
131488 <description>Select CMD15 command buffer register as next command.</description>
131497 <description>ADC Command Low Buffer Register</description>
131506 <description>Input channel select</description>
131513 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
131518 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
131523 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
131528 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
131533 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131538 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131543 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131548 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131553 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131558 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
131563 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
131568 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
131575 <description>Conversion Type</description>
131582 <description>Single-Ended Mode. Only A side channel is converted.</description>
131587 <description>Single-Ended Mode. Only B side channel is converted.</description>
131592 <description>Differential Mode. A-B.</description>
131597 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
131604 <description>Select resolution of conversions</description>
131611 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
131616 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
131623 <description>Alternate Channel B Input channel select</description>
131630 <description>Select CH0B</description>
131635 <description>Select CH1B</description>
131640 <description>Select CH2B</description>
131645 <description>Select CH3B</description>
131650 <description>Select corresponding channel CHnB</description>
131655 <description>Select corresponding channel CHnB</description>
131660 <description>Select corresponding channel CHnB</description>
131665 <description>Select corresponding channel CHnB</description>
131670 <description>Select corresponding channel CHnB</description>
131675 <description>Select corresponding channel CHnB</description>
131680 <description>Select CH30B</description>
131685 <description>Select CH31B</description>
131692 <description>Alternate Channel B Select Enable</description>
131699 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
131704 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
131713 <description>ADC Command High Buffer Register</description>
131722 <description>Compare Function Enable</description>
131729 <description>Compare disabled.</description>
131734 <description>Compare enabled. Store on true.</description>
131739 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
131746 <description>Wait for trigger assertion before execution.</description>
131753 <description>This command will be automatically executed.</description>
131758 …<description>The active trigger must be asserted again before executing this command.</description>
131765 <description>Loop with Increment</description>
131772 <description>Auto channel increment disabled</description>
131777 <description>Auto channel increment enabled</description>
131784 <description>Sample Time Select</description>
131791 <description>Minimum sample time of 3 ADCK cycles.</description>
131796 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
131801 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
131806 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
131811 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
131816 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
131821 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
131826 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
131833 <description>Hardware Average Select</description>
131840 <description>Single conversion.</description>
131845 <description>2 conversions averaged.</description>
131850 <description>4 conversions averaged.</description>
131855 <description>8 conversions averaged.</description>
131860 <description>16 conversions averaged.</description>
131865 <description>32 conversions averaged.</description>
131870 <description>64 conversions averaged.</description>
131875 <description>128 conversions averaged.</description>
131882 <description>Loop Count Select</description>
131889 <description>Looping not enabled. Command executes 1 time.</description>
131894 <description>Loop 1 time. Command executes 2 times.</description>
131899 <description>Loop 2 times. Command executes 3 times.</description>
131904 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131909 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131914 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131919 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131924 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131929 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131934 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
131939 <description>Loop 15 times. Command executes 16 times.</description>
131946 <description>Next Command Select</description>
131953 …description>No next command defined. Terminate conversions at completion of current command. If lo…
131958 <description>Select CMD1 command buffer register as next command.</description>
131963 … <description>Select corresponding CMD command buffer register as next command</description>
131968 … <description>Select corresponding CMD command buffer register as next command</description>
131973 … <description>Select corresponding CMD command buffer register as next command</description>
131978 … <description>Select corresponding CMD command buffer register as next command</description>
131983 … <description>Select corresponding CMD command buffer register as next command</description>
131988 … <description>Select corresponding CMD command buffer register as next command</description>
131993 … <description>Select corresponding CMD command buffer register as next command</description>
131998 … <description>Select corresponding CMD command buffer register as next command</description>
132003 <description>Select CMD15 command buffer register as next command.</description>
132012 <description>ADC Command Low Buffer Register</description>
132021 <description>Input channel select</description>
132028 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
132033 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
132038 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
132043 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
132048 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132053 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132058 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132063 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132068 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132073 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132078 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
132083 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
132090 <description>Conversion Type</description>
132097 <description>Single-Ended Mode. Only A side channel is converted.</description>
132102 <description>Single-Ended Mode. Only B side channel is converted.</description>
132107 <description>Differential Mode. A-B.</description>
132112 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
132119 <description>Select resolution of conversions</description>
132126 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
132131 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
132138 <description>Alternate Channel B Input channel select</description>
132145 <description>Select CH0B</description>
132150 <description>Select CH1B</description>
132155 <description>Select CH2B</description>
132160 <description>Select CH3B</description>
132165 <description>Select corresponding channel CHnB</description>
132170 <description>Select corresponding channel CHnB</description>
132175 <description>Select corresponding channel CHnB</description>
132180 <description>Select corresponding channel CHnB</description>
132185 <description>Select corresponding channel CHnB</description>
132190 <description>Select corresponding channel CHnB</description>
132195 <description>Select CH30B</description>
132200 <description>Select CH31B</description>
132207 <description>Alternate Channel B Select Enable</description>
132214 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
132219 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
132228 <description>ADC Command High Buffer Register</description>
132237 <description>Compare Function Enable</description>
132244 <description>Compare disabled.</description>
132249 <description>Compare enabled. Store on true.</description>
132254 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
132261 <description>Wait for trigger assertion before execution.</description>
132268 <description>This command will be automatically executed.</description>
132273 …<description>The active trigger must be asserted again before executing this command.</description>
132280 <description>Loop with Increment</description>
132287 <description>Auto channel increment disabled</description>
132292 <description>Auto channel increment enabled</description>
132299 <description>Sample Time Select</description>
132306 <description>Minimum sample time of 3 ADCK cycles.</description>
132311 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
132316 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
132321 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
132326 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
132331 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
132336 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
132341 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
132348 <description>Hardware Average Select</description>
132355 <description>Single conversion.</description>
132360 <description>2 conversions averaged.</description>
132365 <description>4 conversions averaged.</description>
132370 <description>8 conversions averaged.</description>
132375 <description>16 conversions averaged.</description>
132380 <description>32 conversions averaged.</description>
132385 <description>64 conversions averaged.</description>
132390 <description>128 conversions averaged.</description>
132397 <description>Loop Count Select</description>
132404 <description>Looping not enabled. Command executes 1 time.</description>
132409 <description>Loop 1 time. Command executes 2 times.</description>
132414 <description>Loop 2 times. Command executes 3 times.</description>
132419 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132424 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132429 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132434 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132439 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132444 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132449 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132454 <description>Loop 15 times. Command executes 16 times.</description>
132461 <description>Next Command Select</description>
132468 …description>No next command defined. Terminate conversions at completion of current command. If lo…
132473 <description>Select CMD1 command buffer register as next command.</description>
132478 … <description>Select corresponding CMD command buffer register as next command</description>
132483 … <description>Select corresponding CMD command buffer register as next command</description>
132488 … <description>Select corresponding CMD command buffer register as next command</description>
132493 … <description>Select corresponding CMD command buffer register as next command</description>
132498 … <description>Select corresponding CMD command buffer register as next command</description>
132503 … <description>Select corresponding CMD command buffer register as next command</description>
132508 … <description>Select corresponding CMD command buffer register as next command</description>
132513 … <description>Select corresponding CMD command buffer register as next command</description>
132518 <description>Select CMD15 command buffer register as next command.</description>
132527 <description>ADC Command Low Buffer Register</description>
132536 <description>Input channel select</description>
132543 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
132548 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
132553 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
132558 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
132563 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132568 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132573 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132578 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132583 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132588 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
132593 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
132598 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
132605 <description>Conversion Type</description>
132612 <description>Single-Ended Mode. Only A side channel is converted.</description>
132617 <description>Single-Ended Mode. Only B side channel is converted.</description>
132622 <description>Differential Mode. A-B.</description>
132627 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
132634 <description>Select resolution of conversions</description>
132641 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
132646 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
132653 <description>Alternate Channel B Input channel select</description>
132660 <description>Select CH0B</description>
132665 <description>Select CH1B</description>
132670 <description>Select CH2B</description>
132675 <description>Select CH3B</description>
132680 <description>Select corresponding channel CHnB</description>
132685 <description>Select corresponding channel CHnB</description>
132690 <description>Select corresponding channel CHnB</description>
132695 <description>Select corresponding channel CHnB</description>
132700 <description>Select corresponding channel CHnB</description>
132705 <description>Select corresponding channel CHnB</description>
132710 <description>Select CH30B</description>
132715 <description>Select CH31B</description>
132722 <description>Alternate Channel B Select Enable</description>
132729 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
132734 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
132743 <description>ADC Command High Buffer Register</description>
132752 <description>Compare Function Enable</description>
132759 <description>Compare disabled.</description>
132764 <description>Compare enabled. Store on true.</description>
132769 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
132776 <description>Wait for trigger assertion before execution.</description>
132783 <description>This command will be automatically executed.</description>
132788 …<description>The active trigger must be asserted again before executing this command.</description>
132795 <description>Loop with Increment</description>
132802 <description>Auto channel increment disabled</description>
132807 <description>Auto channel increment enabled</description>
132814 <description>Sample Time Select</description>
132821 <description>Minimum sample time of 3 ADCK cycles.</description>
132826 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
132831 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
132836 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
132841 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
132846 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
132851 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
132856 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
132863 <description>Hardware Average Select</description>
132870 <description>Single conversion.</description>
132875 <description>2 conversions averaged.</description>
132880 <description>4 conversions averaged.</description>
132885 <description>8 conversions averaged.</description>
132890 <description>16 conversions averaged.</description>
132895 <description>32 conversions averaged.</description>
132900 <description>64 conversions averaged.</description>
132905 <description>128 conversions averaged.</description>
132912 <description>Loop Count Select</description>
132919 <description>Looping not enabled. Command executes 1 time.</description>
132924 <description>Loop 1 time. Command executes 2 times.</description>
132929 <description>Loop 2 times. Command executes 3 times.</description>
132934 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132939 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132944 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132949 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132954 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132959 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132964 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
132969 <description>Loop 15 times. Command executes 16 times.</description>
132976 <description>Next Command Select</description>
132983 …description>No next command defined. Terminate conversions at completion of current command. If lo…
132988 <description>Select CMD1 command buffer register as next command.</description>
132993 … <description>Select corresponding CMD command buffer register as next command</description>
132998 … <description>Select corresponding CMD command buffer register as next command</description>
133003 … <description>Select corresponding CMD command buffer register as next command</description>
133008 … <description>Select corresponding CMD command buffer register as next command</description>
133013 … <description>Select corresponding CMD command buffer register as next command</description>
133018 … <description>Select corresponding CMD command buffer register as next command</description>
133023 … <description>Select corresponding CMD command buffer register as next command</description>
133028 … <description>Select corresponding CMD command buffer register as next command</description>
133033 <description>Select CMD15 command buffer register as next command.</description>
133042 <description>ADC Command Low Buffer Register</description>
133051 <description>Input channel select</description>
133058 <description>Select CH0A or CH0B or CH0A/CH0B pair.</description>
133063 <description>Select CH1A or CH1B or CH1A/CH1B pair.</description>
133068 <description>Select CH2A or CH2B or CH2A/CH2B pair.</description>
133073 <description>Select CH3A or CH3B or CH3A/CH3B pair.</description>
133078 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133083 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133088 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133093 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133098 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133103 … <description>Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.</description>
133108 <description>Select CH30A or CH30B or CH30A/CH30B pair.</description>
133113 <description>Select CH31A or CH31B or CH31A/CH31B pair.</description>
133120 <description>Conversion Type</description>
133127 <description>Single-Ended Mode. Only A side channel is converted.</description>
133132 <description>Single-Ended Mode. Only B side channel is converted.</description>
133137 <description>Differential Mode. A-B.</description>
133142 …<description>Dual-Single-Ended Mode. Both A side and B side channels are converted independently.<…
133149 <description>Select resolution of conversions</description>
133156 …<description>Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion w…
133161 …<description>High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with …
133168 <description>Alternate Channel B Input channel select</description>
133175 <description>Select CH0B</description>
133180 <description>Select CH1B</description>
133185 <description>Select CH2B</description>
133190 <description>Select CH3B</description>
133195 <description>Select corresponding channel CHnB</description>
133200 <description>Select corresponding channel CHnB</description>
133205 <description>Select corresponding channel CHnB</description>
133210 <description>Select corresponding channel CHnB</description>
133215 <description>Select corresponding channel CHnB</description>
133220 <description>Select corresponding channel CHnB</description>
133225 <description>Select CH30B</description>
133230 <description>Select CH31B</description>
133237 <description>Alternate Channel B Select Enable</description>
133244 …<description>ALTBEN_ADCH disabled. Channel A and Channel B inputs are selected based on ADCH setti…
133249 …<description>ALTBEN_ADCH enabled. Channel A inputs selected by ADCH setting and Channel B inputs s…
133258 <description>ADC Command High Buffer Register</description>
133267 <description>Compare Function Enable</description>
133274 <description>Compare disabled.</description>
133279 <description>Compare enabled. Store on true.</description>
133284 …<description>Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.</des…
133291 <description>Wait for trigger assertion before execution.</description>
133298 <description>This command will be automatically executed.</description>
133303 …<description>The active trigger must be asserted again before executing this command.</description>
133310 <description>Loop with Increment</description>
133317 <description>Auto channel increment disabled</description>
133322 <description>Auto channel increment enabled</description>
133329 <description>Sample Time Select</description>
133336 <description>Minimum sample time of 3 ADCK cycles.</description>
133341 <description>3 + 21 ADCK cycles; 5 ADCK cycles total sample time.</description>
133346 <description>3 + 22 ADCK cycles; 7 ADCK cycles total sample time.</description>
133351 <description>3 + 23 ADCK cycles; 11 ADCK cycles total sample time.</description>
133356 <description>3 + 24 ADCK cycles; 19 ADCK cycles total sample time.</description>
133361 <description>3 + 25 ADCK cycles; 35 ADCK cycles total sample time.</description>
133366 <description>3 + 26 ADCK cycles; 67 ADCK cycles total sample time.</description>
133371 <description>3 + 27 ADCK cycles; 131 ADCK cycles total sample time.</description>
133378 <description>Hardware Average Select</description>
133385 <description>Single conversion.</description>
133390 <description>2 conversions averaged.</description>
133395 <description>4 conversions averaged.</description>
133400 <description>8 conversions averaged.</description>
133405 <description>16 conversions averaged.</description>
133410 <description>32 conversions averaged.</description>
133415 <description>64 conversions averaged.</description>
133420 <description>128 conversions averaged.</description>
133427 <description>Loop Count Select</description>
133434 <description>Looping not enabled. Command executes 1 time.</description>
133439 <description>Loop 1 time. Command executes 2 times.</description>
133444 <description>Loop 2 times. Command executes 3 times.</description>
133449 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133454 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133459 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133464 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133469 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133474 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133479 … <description>Loop corresponding number of times. Command executes LOOP+1 times.</description>
133484 <description>Loop 15 times. Command executes 16 times.</description>
133491 <description>Next Command Select</description>
133498 …description>No next command defined. Terminate conversions at completion of current command. If lo…
133503 <description>Select CMD1 command buffer register as next command.</description>
133508 … <description>Select corresponding CMD command buffer register as next command</description>
133513 … <description>Select corresponding CMD command buffer register as next command</description>
133518 … <description>Select corresponding CMD command buffer register as next command</description>
133523 … <description>Select corresponding CMD command buffer register as next command</description>
133528 … <description>Select corresponding CMD command buffer register as next command</description>
133533 … <description>Select corresponding CMD command buffer register as next command</description>
133538 … <description>Select corresponding CMD command buffer register as next command</description>
133543 … <description>Select corresponding CMD command buffer register as next command</description>
133548 <description>Select CMD15 command buffer register as next command.</description>
133560 <description>Compare Value Register</description>
133569 <description>Compare Value Low.</description>
133576 <description>Compare Value High.</description>
133587 <description>ADC Data Result FIFO Register</description>
133596 <description>Data result</description>
133603 <description>Trigger Source</description>
133610 <description>Trigger source 0 initiated this conversion.</description>
133615 <description>Trigger source 1 initiated this conversion.</description>
133620 <description>Corresponding trigger source initiated this conversion.</description>
133625 <description>Trigger source 3 initiated this conversion.</description>
133632 <description>Loop count value</description>
133639 <description>Result is from initial conversion in command.</description>
133644 <description>Result is from second conversion in command.</description>
133649 <description>Result is from LOOPCNT+1 conversion in command.</description>
133654 <description>Result is from LOOPCNT+1 conversion in command.</description>
133659 <description>Result is from LOOPCNT+1 conversion in command.</description>
133664 <description>Result is from LOOPCNT+1 conversion in command.</description>
133669 <description>Result is from LOOPCNT+1 conversion in command.</description>
133674 <description>Result is from LOOPCNT+1 conversion in command.</description>
133679 <description>Result is from LOOPCNT+1 conversion in command.</description>
133684 <description>Result is from LOOPCNT+1 conversion in command.</description>
133689 <description>Result is from 16th conversion in command.</description>
133696 <description>Command Buffer Source</description>
133703 …description>Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial…
133708 … <description>CMD1 buffer used as control settings for this conversion.</description>
133713 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133718 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133723 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133728 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133733 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133738 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133743 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133748 …<description>Corresponding command buffer used as control settings for this conversion.</descripti…
133753 … <description>CMD15 buffer used as control settings for this conversion.</description>
133760 <description>FIFO entry is valid</description>
133767 <description>FIFO is empty. Discard any read from RESFIFO.</description>
133772 <description>FIFO record read from RESFIFO is valid.</description>
133783 <description>Calibration General A-Side Registers</description>
133792 <description>Calibration General A Side Register Element</description>
133803 <description>Calibration General B-Side Registers</description>
133812 <description>Calibration General B Side Register Element</description>
133821 <description>ADC Test Register</description>
133830 <description>Calibration Sample Time Long</description>
133837 … <description>Normal sample time. Minimum sample time of 3 ADCK cycles.</description>
133842 … <description>Increased sample time. 67 ADCK cycles total sample time.</description>
133849 <description>Force M-side positive offset</description>
133856 <description>Normal operation. No forced offset.</description>
133861 <description>Test configuration. Forced positive offset on MDAC.</description>
133868 <description>Force P-side positive offset</description>
133875 <description>Normal operation. No forced offset.</description>
133880 <description>Test configuration. Forced positive offset on PDAC.</description>
133887 <description>Force M-side negative offset</description>
133894 <description>Normal operation. No forced offset.</description>
133899 <description>Test configuration. Forced negative offset on MDAC.</description>
133906 <description>Force P-side negative offset</description>
133913 <description>Normal operation. No forced offset.</description>
133918 <description>Test configuration. Forced negative offset on PDAC.</description>
133925 <description>Enable test configuration</description>
133932 <description>Normal operation. Test configuration not enabled.</description>
133937 <description>Hardware BIST Test in progress.</description>
133948 <description>ADC</description>
133963 <description>CDOG</description>
133974 <description>Control</description>
133983 <description>Lock control</description>
133990 <description>Locked</description>
133995 <description>Unlocked</description>
134002 <description>TIMEOUT fault control</description>
134009 <description>Enable reset</description>
134014 <description>Enable interrupt</description>
134019 <description>Disable both reset and interrupt</description>
134026 <description>MISCOMPARE fault control</description>
134033 <description>Enable reset</description>
134038 <description>Enable interrupt</description>
134043 <description>Disable both reset and interrupt</description>
134050 <description>SEQUENCE fault control</description>
134057 <description>Enable reset</description>
134062 <description>Enable interrupt</description>
134067 <description>Disable both reset and interrupt</description>
134074 <description>CONTROL fault control</description>
134081 <description>Enable reset</description>
134086 <description>Disable reset</description>
134093 <description>STATE fault control</description>
134100 <description>Enable reset</description>
134105 <description>Enable interrupt</description>
134110 <description>Disable both reset and interrupt</description>
134117 <description>ADDRESS fault control</description>
134124 <description>Enable reset</description>
134129 <description>Enable interrupt</description>
134134 <description>Disable both reset and interrupt</description>
134141 <description>IRQ pause control</description>
134148 <description>Keep the timer running</description>
134153 <description>Stop the timer</description>
134160 <description>DEBUG_HALT control</description>
134167 <description>Keep the timer running</description>
134172 <description>Stop the timer</description>
134181 <description>Instruction Timer reload</description>
134190 <description>Instruction Timer reload value</description>
134199 <description>Instruction Timer</description>
134208 <description>Current value of the Instruction Timer</description>
134217 <description>Secure Counter</description>
134226 <description>Secure Counter</description>
134235 <description>Status 1</description>
134244 <description>Number of TIMEOUT faults since the last POR</description>
134251 <description>Number of MISCOMPARE faults since the last POR</description>
134258 <description>Number of SEQUENCE faults since the last POR</description>
134265 <description>Current State</description>
134274 <description>Status 2</description>
134283 <description>Number of CONTROL faults since the last POR</description>
134290 <description>Number of STATE faults since the last POR</description>
134297 <description>Number of ADDRESS faults since the last POR</description>
134306 <description>Flags</description>
134315 <description>TIMEOUT fault flag</description>
134322 <description>A TIMEOUT fault has not occurred</description>
134327 <description>A TIMEOUT fault has occurred</description>
134334 <description>MISCOMPARE fault flag</description>
134341 <description>A MISCOMPARE fault has not occurred</description>
134346 <description>A MISCOMPARE fault has occurred</description>
134353 <description>SEQUENCE fault flag</description>
134360 <description>A SEQUENCE fault has not occurred</description>
134365 <description>A SEQUENCE fault has occurred</description>
134372 <description>CONTROL fault flag</description>
134379 <description>A CONTROL fault has not occurred</description>
134384 <description>A CONTROL fault has occurred</description>
134391 <description>STATE fault flag</description>
134398 <description>A STATE fault has not occurred</description>
134403 <description>A STATE fault has occurred</description>
134410 <description>ADDRESS fault flag</description>
134417 <description>An ADDRESS fault has not occurred</description>
134422 <description>An ADDRESS fault has occurred</description>
134429 <description>Power-on reset flag</description>
134436 <description>A Power-on reset event has not occurred</description>
134441 <description>A Power-on reset event has occurred</description>
134450 <description>Persistent Data Storage</description>
134459 <description>Persistent Storage</description>
134468 <description>START Command</description>
134477 <description>Start command</description>
134486 <description>STOP Command</description>
134495 <description>Stop command</description>
134504 <description>RESTART Command</description>
134513 <description>Restart command</description>
134522 <description>ADD Command</description>
134531 <description>ADD Write Value</description>
134540 <description>ADD1 Command</description>
134549 <description>ADD 1</description>
134558 <description>ADD16 Command</description>
134567 <description>ADD 16</description>
134576 <description>ADD256 Command</description>
134585 <description>ADD 256</description>
134594 <description>SUB Command</description>
134603 <description>Subtract Write Value</description>
134612 <description>SUB1 Command</description>
134621 <description>Subtract 1</description>
134630 <description>SUB16 Command</description>
134639 <description>Subtract 16</description>
134648 <description>SUB256 Command</description>
134657 <description>Subtract 256</description>
134668 <description>PowerQuad</description>
134679 <description>Output Base</description>
134688 <description>Base address register for the output region</description>
134697 <description>Output Format</description>
134706 <description>Output Internal Format</description>
134713 <description>Output External Format</description>
134720 <description>Output Scaler Value</description>
134729 <description>Temporary Base</description>
134738 <description>Base address register for the temporary region</description>
134747 <description>Temporary Format</description>
134756 <description>Temporary Internal Format</description>
134763 <description>Temporary External Format</description>
134770 <description>Temporary Scaler Value</description>
134779 <description>Input A Base</description>
134788 <description>Input A Base</description>
134797 <description>Input A Format</description>
134806 <description>Input A Internal Format</description>
134813 <description>Input A External Format</description>
134820 <description>Input A Scaler Value</description>
134829 <description>Input B Base</description>
134838 <description>Input B Base</description>
134847 <description>Input B Format</description>
134856 <description>Input B Internal Format</description>
134863 <description>Input B External Format</description>
134870 <description>Input B Scaler Value</description>
134879 <description>Control</description>
134888 <description>Decode Opcode</description>
134895 <description>Decode Machine</description>
134902 <description>Instruction Busy</description>
134911 <description>Length</description>
134920 <description>Instruction Length</description>
134929 <description>Coprocessor Pre-scale</description>
134938 <description>Input</description>
134945 <description>Output</description>
134952 <description>Saturation</description>
134959 <description>No saturation</description>
134964 <description>Forces sub-32 bit saturation</description>
134971 <description>Saturation 8</description>
134978 <description>8 bits</description>
134983 <description>16 bits</description>
134992 <description>Miscellaneous</description>
135001 <description>For Matrix : Used for scaling factor</description>
135010 <description>Cursory</description>
135019 <description>Cursory Mode</description>
135026 <description>Disable Cursory mode</description>
135031 <description>Enable Cursory Mode</description>
135040 <description>Cordic input X</description>
135049 <description>Cordic Input x</description>
135058 <description>Cordic Input Y</description>
135067 <description>Cordic Input y</description>
135076 <description>Cordic Input Z</description>
135085 <description>Cordic Input z</description>
135094 <description>Error Status</description>
135103 <description>Floating Point Overflow</description>
135110 <description>No Error</description>
135115 <description>Error on Floating Point Overflow</description>
135122 <description>Floating Point NaN</description>
135129 <description>No Error</description>
135134 <description>Error on Floating Point NaN</description>
135141 <description>Fixed Point Overflow</description>
135148 <description>No Error</description>
135153 <description>Error on Fixed Point Overflow</description>
135160 <description>Underflow</description>
135167 <description>No Error</description>
135172 <description>Error on Underflow</description>
135179 <description>Bus Error</description>
135186 <description>No Error</description>
135191 <description>Error on Bus</description>
135200 <description>Interrupt Enable</description>
135209 <description>Interrupt Floating Point Overflow</description>
135216 <description>Disable</description>
135221 <description>Enable interrupt on floating point overflow</description>
135228 <description>Interrupt Floating Point NaN</description>
135235 <description>Disable</description>
135240 <description>Enable interrupt on floating point NaN</description>
135247 <description>Interrupt on Fixed Point Overflow</description>
135254 <description>Disable</description>
135259 <description>Enable interrupt on fixed point overflow</description>
135266 <description>Interrupt on Subnormal Truncation</description>
135273 <description>Disable</description>
135278 <description>Enable interrupt on subnormal truncation</description>
135285 <description>Interrupt on AHBM Bus Error</description>
135292 <description>Disable</description>
135297 <description>Enable interrupt on AHBM Bus Error</description>
135304 <description>Interrupt on Instruction Completion</description>
135311 <description>Disable</description>
135316 <description>Enable interrupt on instruction completion</description>
135325 <description>Event Enable</description>
135334 <description>Event Trigger on Floating Point Overflow</description>
135341 <description>Disable</description>
135346 <description>Enable event trigger on Floating point overflow</description>
135353 <description>Event Trigger on Floating Point NaN</description>
135360 <description>Disable</description>
135365 <description>Enable event trigger on floating point NaN</description>
135372 <description>Event Trigger on Fixed Point Overflow</description>
135379 <description>Disable</description>
135384 <description>Enable event trigger on fixed point overflow</description>
135391 <description>Event Trigger on Subnormal Truncation</description>
135398 <description>Disable</description>
135403 <description>Enable event trigger on subnormal truncation</description>
135410 <description>Event Trigger on AHBM Bus Error</description>
135417 <description>Disable</description>
135422 <description>Enable event trigger on AHBM bus error</description>
135429 <description>Event Trigger on Instruction Completion</description>
135436 <description>Disable</description>
135441 <description>Enable event trigger on instruction completion</description>
135450 <description>Interrupt Status</description>
135459 <description>Interrupt Status</description>
135466 <description>No new interrupt</description>
135471 <description>Interrupt captured</description>
135482 <description>General Purpose Register Bank n</description>
135491 <description>General Purpose Register Bank</description>
135502 <description>Compute Register Bank n</description>
135511 <description>Compute Register Bank</description>
135522 <description>DMA1 controller</description>
135537 <description>DMA control</description>
135546 <description>DMA controller master enable.</description>
135553 <description>DMA controller is disabled.</description>
135558 <description>Enabled.</description>
135567 <description>Interrupt status</description>
135576 …<description>Summarizes whether any enabled interrupts (other than error interrupts) are pending.<…
135583 <description>No enabled interrupts are pending.</description>
135588 <description>At least one enabled interrupt is pending.</description>
135595 <description>Summarizes whether any error interrupts are pending.</description>
135602 <description>No error interrupts are pending.</description>
135607 <description>At least one error interrupt is pending.</description>
135616 <description>SRAM address of the channel configuration table</description>
135625 <description>Offset</description>
135634 <description>Channel Enable read and set for all DMA channels</description>
135643 <description>Enable for DMA channel</description>
135650 <description>DMA channel is disabled.</description>
135655 <description>DMA channel is enabled.</description>
135662 <description>Enable for DMA channel</description>
135669 <description>DMA channel is disabled.</description>
135674 <description>DMA channel is enabled.</description>
135681 <description>Enable for DMA channel</description>
135688 <description>DMA channel is disabled.</description>
135693 <description>DMA channel is enabled.</description>
135700 <description>Enable for DMA channel</description>
135707 <description>DMA channel is disabled.</description>
135712 <description>DMA channel is enabled.</description>
135719 <description>Enable for DMA channel</description>
135726 <description>DMA channel is disabled.</description>
135731 <description>DMA channel is enabled.</description>
135738 <description>Enable for DMA channel</description>
135745 <description>DMA channel is disabled.</description>
135750 <description>DMA channel is enabled.</description>
135757 <description>Enable for DMA channel</description>
135764 <description>DMA channel is disabled.</description>
135769 <description>DMA channel is enabled.</description>
135776 <description>Enable for DMA channel</description>
135783 <description>DMA channel is disabled.</description>
135788 <description>DMA channel is enabled.</description>
135795 <description>Enable for DMA channel</description>
135802 <description>DMA channel is disabled.</description>
135807 <description>DMA channel is enabled.</description>
135814 <description>Enable for DMA channel</description>
135821 <description>DMA channel is disabled.</description>
135826 <description>DMA channel is enabled.</description>
135833 <description>Enable for DMA channel</description>
135840 <description>DMA channel is disabled.</description>
135845 <description>DMA channel is enabled.</description>
135852 <description>Enable for DMA channel</description>
135859 <description>DMA channel is disabled.</description>
135864 <description>DMA channel is enabled.</description>
135871 <description>Enable for DMA channel</description>
135878 <description>DMA channel is disabled.</description>
135883 <description>DMA channel is enabled.</description>
135890 <description>Enable for DMA channel</description>
135897 <description>DMA channel is disabled.</description>
135902 <description>DMA channel is enabled.</description>
135909 <description>Enable for DMA channel</description>
135916 <description>DMA channel is disabled.</description>
135921 <description>DMA channel is enabled.</description>
135928 <description>Enable for DMA channel</description>
135935 <description>DMA channel is disabled.</description>
135940 <description>DMA channel is enabled.</description>
135949 <description>Channel Enable Clear for all DMA channels</description>
135958 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
135966 <description>No effect.</description>
135971 <description>DMA channel is cleared.</description>
135978 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
135986 <description>No effect.</description>
135991 <description>DMA channel is cleared.</description>
135998 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136006 <description>No effect.</description>
136011 <description>DMA channel is cleared.</description>
136018 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136026 <description>No effect.</description>
136031 <description>DMA channel is cleared.</description>
136038 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136046 <description>No effect.</description>
136051 <description>DMA channel is cleared.</description>
136058 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136066 <description>No effect.</description>
136071 <description>DMA channel is cleared.</description>
136078 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136086 <description>No effect.</description>
136091 <description>DMA channel is cleared.</description>
136098 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136106 <description>No effect.</description>
136111 <description>DMA channel is cleared.</description>
136118 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136126 <description>No effect.</description>
136131 <description>DMA channel is cleared.</description>
136138 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136146 <description>No effect.</description>
136151 <description>DMA channel is cleared.</description>
136158 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136166 <description>No effect.</description>
136171 <description>DMA channel is cleared.</description>
136178 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136186 <description>No effect.</description>
136191 <description>DMA channel is cleared.</description>
136198 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136206 <description>No effect.</description>
136211 <description>DMA channel is cleared.</description>
136218 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136226 <description>No effect.</description>
136231 <description>DMA channel is cleared.</description>
136238 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136246 <description>No effect.</description>
136251 <description>DMA channel is cleared.</description>
136258 …<description>Writing ones to this register clears the corresponding bits in ENABLESET0.</descripti…
136266 <description>No effect.</description>
136271 <description>DMA channel is cleared.</description>
136280 <description>Channel Active status for all DMA channels</description>
136289 <description>Active flag for DMA channel.</description>
136296 <description>DMA channel is not active.</description>
136301 <description>DMA channel is active.</description>
136308 <description>Active flag for DMA channel.</description>
136315 <description>DMA channel is not active.</description>
136320 <description>DMA channel is active.</description>
136327 <description>Active flag for DMA channel.</description>
136334 <description>DMA channel is not active.</description>
136339 <description>DMA channel is active.</description>
136346 <description>Active flag for DMA channel.</description>
136353 <description>DMA channel is not active.</description>
136358 <description>DMA channel is active.</description>
136365 <description>Active flag for DMA channel.</description>
136372 <description>DMA channel is not active.</description>
136377 <description>DMA channel is active.</description>
136384 <description>Active flag for DMA channel.</description>
136391 <description>DMA channel is not active.</description>
136396 <description>DMA channel is active.</description>
136403 <description>Active flag for DMA channel.</description>
136410 <description>DMA channel is not active.</description>
136415 <description>DMA channel is active.</description>
136422 <description>Active flag for DMA channel.</description>
136429 <description>DMA channel is not active.</description>
136434 <description>DMA channel is active.</description>
136441 <description>Active flag for DMA channel.</description>
136448 <description>DMA channel is not active.</description>
136453 <description>DMA channel is active.</description>
136460 <description>Active flag for DMA channel.</description>
136467 <description>DMA channel is not active.</description>
136472 <description>DMA channel is active.</description>
136479 <description>Active flag for DMA channel.</description>
136486 <description>DMA channel is not active.</description>
136491 <description>DMA channel is active.</description>
136498 <description>Active flag for DMA channel.</description>
136505 <description>DMA channel is not active.</description>
136510 <description>DMA channel is active.</description>
136517 <description>Active flag for DMA channel.</description>
136524 <description>DMA channel is not active.</description>
136529 <description>DMA channel is active.</description>
136536 <description>Active flag for DMA channel.</description>
136543 <description>DMA channel is not active.</description>
136548 <description>DMA channel is active.</description>
136555 <description>Active flag for DMA channel.</description>
136562 <description>DMA channel is not active.</description>
136567 <description>DMA channel is active.</description>
136574 <description>Active flag for DMA channel.</description>
136581 <description>DMA channel is not active.</description>
136586 <description>DMA channel is active.</description>
136595 <description>Channel Busy status for all DMA channels</description>
136604 <description>Busy flag for DMA channel.</description>
136611 <description>DMA channel is not busy.</description>
136616 <description>DMA channel is busy.</description>
136623 <description>Busy flag for DMA channel.</description>
136630 <description>DMA channel is not busy.</description>
136635 <description>DMA channel is busy.</description>
136642 <description>Busy flag for DMA channel.</description>
136649 <description>DMA channel is not busy.</description>
136654 <description>DMA channel is busy.</description>
136661 <description>Busy flag for DMA channel.</description>
136668 <description>DMA channel is not busy.</description>
136673 <description>DMA channel is busy.</description>
136680 <description>Busy flag for DMA channel.</description>
136687 <description>DMA channel is not busy.</description>
136692 <description>DMA channel is busy.</description>
136699 <description>Busy flag for DMA channel.</description>
136706 <description>DMA channel is not busy.</description>
136711 <description>DMA channel is busy.</description>
136718 <description>Busy flag for DMA channel.</description>
136725 <description>DMA channel is not busy.</description>
136730 <description>DMA channel is busy.</description>
136737 <description>Busy flag for DMA channel.</description>
136744 <description>DMA channel is not busy.</description>
136749 <description>DMA channel is busy.</description>
136756 <description>Busy flag for DMA channel.</description>
136763 <description>DMA channel is not busy.</description>
136768 <description>DMA channel is busy.</description>
136775 <description>Busy flag for DMA channel.</description>
136782 <description>DMA channel is not busy.</description>
136787 <description>DMA channel is busy.</description>
136794 <description>Busy flag for DMA channel.</description>
136801 <description>DMA channel is not busy.</description>
136806 <description>DMA channel is busy.</description>
136813 <description>Busy flag for DMA channel.</description>
136820 <description>DMA channel is not busy.</description>
136825 <description>DMA channel is busy.</description>
136832 <description>Busy flag for DMA channel.</description>
136839 <description>DMA channel is not busy.</description>
136844 <description>DMA channel is busy.</description>
136851 <description>Busy flag for DMA channel.</description>
136858 <description>DMA channel is not busy.</description>
136863 <description>DMA channel is busy.</description>
136870 <description>Busy flag for DMA channel.</description>
136877 <description>DMA channel is not busy.</description>
136882 <description>DMA channel is busy.</description>
136889 <description>Busy flag for DMA channel.</description>
136896 <description>DMA channel is not busy.</description>
136901 <description>DMA channel is busy.</description>
136910 <description>Error Interrupt status for all DMA channels</description>
136919 <description>Error Interrupt flag for DMA channel.</description>
136926 <description>The Error Interrupt is not active for DMA channel.</description>
136931 <description>The Error Interrupt is pending for DMA channel.</description>
136938 <description>Error Interrupt flag for DMA channel.</description>
136945 <description>The Error Interrupt is not active for DMA channel.</description>
136950 <description>The Error Interrupt is pending for DMA channel.</description>
136957 <description>Error Interrupt flag for DMA channel.</description>
136964 <description>The Error Interrupt is not active for DMA channel.</description>
136969 <description>The Error Interrupt is pending for DMA channel.</description>
136976 <description>Error Interrupt flag for DMA channel.</description>
136983 <description>The Error Interrupt is not active for DMA channel.</description>
136988 <description>The Error Interrupt is pending for DMA channel.</description>
136995 <description>Error Interrupt flag for DMA channel.</description>
137002 <description>The Error Interrupt is not active for DMA channel.</description>
137007 <description>The Error Interrupt is pending for DMA channel.</description>
137014 <description>Error Interrupt flag for DMA channel.</description>
137021 <description>The Error Interrupt is not active for DMA channel.</description>
137026 <description>The Error Interrupt is pending for DMA channel.</description>
137033 <description>Error Interrupt flag for DMA channel.</description>
137040 <description>The Error Interrupt is not active for DMA channel.</description>
137045 <description>The Error Interrupt is pending for DMA channel.</description>
137052 <description>Error Interrupt flag for DMA channel.</description>
137059 <description>The Error Interrupt is not active for DMA channel.</description>
137064 <description>The Error Interrupt is pending for DMA channel.</description>
137071 <description>Error Interrupt flag for DMA channel.</description>
137078 <description>The Error Interrupt is not active for DMA channel.</description>
137083 <description>The Error Interrupt is pending for DMA channel.</description>
137090 <description>Error Interrupt flag for DMA channel.</description>
137097 <description>The Error Interrupt is not active for DMA channel.</description>
137102 <description>The Error Interrupt is pending for DMA channel.</description>
137109 <description>Error Interrupt flag for DMA channel.</description>
137116 <description>The Error Interrupt is not active for DMA channel.</description>
137121 <description>The Error Interrupt is pending for DMA channel.</description>
137128 <description>Error Interrupt flag for DMA channel.</description>
137135 <description>The Error Interrupt is not active for DMA channel.</description>
137140 <description>The Error Interrupt is pending for DMA channel.</description>
137147 <description>Error Interrupt flag for DMA channel.</description>
137154 <description>The Error Interrupt is not active for DMA channel.</description>
137159 <description>The Error Interrupt is pending for DMA channel.</description>
137166 <description>Error Interrupt flag for DMA channel.</description>
137173 <description>The Error Interrupt is not active for DMA channel.</description>
137178 <description>The Error Interrupt is pending for DMA channel.</description>
137185 <description>Error Interrupt flag for DMA channel.</description>
137192 <description>The Error Interrupt is not active for DMA channel.</description>
137197 <description>The Error Interrupt is pending for DMA channel.</description>
137204 <description>Error Interrupt flag for DMA channel.</description>
137211 <description>The Error Interrupt is not active for DMA channel.</description>
137216 <description>The Error Interrupt is pending for DMA channel.</description>
137225 <description>Interrupt Enable read and Set for all DMA channels</description>
137234 <description>Interrupt Enable read and set for DMA channel.</description>
137241 <description>The Interrupt for DMA channel is disabled.</description>
137246 <description>The Interrupt for DMA channel is enabled.</description>
137253 <description>Interrupt Enable read and set for DMA channel.</description>
137260 <description>The Interrupt for DMA channel is disabled.</description>
137265 <description>The Interrupt for DMA channel is enabled.</description>
137272 <description>Interrupt Enable read and set for DMA channel.</description>
137279 <description>The Interrupt for DMA channel is disabled.</description>
137284 <description>The Interrupt for DMA channel is enabled.</description>
137291 <description>Interrupt Enable read and set for DMA channel.</description>
137298 <description>The Interrupt for DMA channel is disabled.</description>
137303 <description>The Interrupt for DMA channel is enabled.</description>
137310 <description>Interrupt Enable read and set for DMA channel.</description>
137317 <description>The Interrupt for DMA channel is disabled.</description>
137322 <description>The Interrupt for DMA channel is enabled.</description>
137329 <description>Interrupt Enable read and set for DMA channel.</description>
137336 <description>The Interrupt for DMA channel is disabled.</description>
137341 <description>The Interrupt for DMA channel is enabled.</description>
137348 <description>Interrupt Enable read and set for DMA channel.</description>
137355 <description>The Interrupt for DMA channel is disabled.</description>
137360 <description>The Interrupt for DMA channel is enabled.</description>
137367 <description>Interrupt Enable read and set for DMA channel.</description>
137374 <description>The Interrupt for DMA channel is disabled.</description>
137379 <description>The Interrupt for DMA channel is enabled.</description>
137386 <description>Interrupt Enable read and set for DMA channel.</description>
137393 <description>The Interrupt for DMA channel is disabled.</description>
137398 <description>The Interrupt for DMA channel is enabled.</description>
137405 <description>Interrupt Enable read and set for DMA channel.</description>
137412 <description>The Interrupt for DMA channel is disabled.</description>
137417 <description>The Interrupt for DMA channel is enabled.</description>
137424 <description>Interrupt Enable read and set for DMA channel.</description>
137431 <description>The Interrupt for DMA channel is disabled.</description>
137436 <description>The Interrupt for DMA channel is enabled.</description>
137443 <description>Interrupt Enable read and set for DMA channel.</description>
137450 <description>The Interrupt for DMA channel is disabled.</description>
137455 <description>The Interrupt for DMA channel is enabled.</description>
137462 <description>Interrupt Enable read and set for DMA channel.</description>
137469 <description>The Interrupt for DMA channel is disabled.</description>
137474 <description>The Interrupt for DMA channel is enabled.</description>
137481 <description>Interrupt Enable read and set for DMA channel.</description>
137488 <description>The Interrupt for DMA channel is disabled.</description>
137493 <description>The Interrupt for DMA channel is enabled.</description>
137500 <description>Interrupt Enable read and set for DMA channel.</description>
137507 <description>The Interrupt for DMA channel is disabled.</description>
137512 <description>The Interrupt for DMA channel is enabled.</description>
137519 <description>Interrupt Enable read and set for DMA channel.</description>
137526 <description>The Interrupt for DMA channel is disabled.</description>
137531 <description>The Interrupt for DMA channel is enabled.</description>
137540 <description>Interrupt Enable Clear for all DMA channels</description>
137549 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137556 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137563 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137570 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137577 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137584 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137591 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137598 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137605 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137612 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137619 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137626 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137633 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137640 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137647 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137654 …<description>Writing ones to this register clears corresponding bits in the DMAIntEnSet0.</descrip…
137663 <description>Interrupt A status for all DMA channels</description>
137672 <description>Interrupt A status for DMA channel.</description>
137679 <description>The DMA channel interrupt A is not active.</description>
137684 <description>The DMA channel interrupt A is active.</description>
137691 <description>Interrupt A status for DMA channel.</description>
137698 <description>The DMA channel interrupt A is not active.</description>
137703 <description>The DMA channel interrupt A is active.</description>
137710 <description>Interrupt A status for DMA channel.</description>
137717 <description>The DMA channel interrupt A is not active.</description>
137722 <description>The DMA channel interrupt A is active.</description>
137729 <description>Interrupt A status for DMA channel.</description>
137736 <description>The DMA channel interrupt A is not active.</description>
137741 <description>The DMA channel interrupt A is active.</description>
137748 <description>Interrupt A status for DMA channel.</description>
137755 <description>The DMA channel interrupt A is not active.</description>
137760 <description>The DMA channel interrupt A is active.</description>
137767 <description>Interrupt A status for DMA channel.</description>
137774 <description>The DMA channel interrupt A is not active.</description>
137779 <description>The DMA channel interrupt A is active.</description>
137786 <description>Interrupt A status for DMA channel.</description>
137793 <description>The DMA channel interrupt A is not active.</description>
137798 <description>The DMA channel interrupt A is active.</description>
137805 <description>Interrupt A status for DMA channel.</description>
137812 <description>The DMA channel interrupt A is not active.</description>
137817 <description>The DMA channel interrupt A is active.</description>
137824 <description>Interrupt A status for DMA channel.</description>
137831 <description>The DMA channel interrupt A is not active.</description>
137836 <description>The DMA channel interrupt A is active.</description>
137843 <description>Interrupt A status for DMA channel.</description>
137850 <description>The DMA channel interrupt A is not active.</description>
137855 <description>The DMA channel interrupt A is active.</description>
137862 <description>Interrupt A status for DMA channel.</description>
137869 <description>The DMA channel interrupt A is not active.</description>
137874 <description>The DMA channel interrupt A is active.</description>
137881 <description>Interrupt A status for DMA channel.</description>
137888 <description>The DMA channel interrupt A is not active.</description>
137893 <description>The DMA channel interrupt A is active.</description>
137900 <description>Interrupt A status for DMA channel.</description>
137907 <description>The DMA channel interrupt A is not active.</description>
137912 <description>The DMA channel interrupt A is active.</description>
137919 <description>Interrupt A status for DMA channel.</description>
137926 <description>The DMA channel interrupt A is not active.</description>
137931 <description>The DMA channel interrupt A is active.</description>
137938 <description>Interrupt A status for DMA channel.</description>
137945 <description>The DMA channel interrupt A is not active.</description>
137950 <description>The DMA channel interrupt A is active.</description>
137957 <description>Interrupt A status for DMA channel.</description>
137964 <description>The DMA channel interrupt A is not active.</description>
137969 <description>The DMA channel interrupt A is active.</description>
137978 <description>Interrupt B status for all DMA channels</description>
137987 <description>Interrupt B status for DMA channel.</description>
137994 <description>The DMA channel interrupt B is not active.</description>
137999 <description>The DMA channel interrupt B is active.</description>
138006 <description>Interrupt B status for DMA channel.</description>
138013 <description>The DMA channel interrupt B is not active.</description>
138018 <description>The DMA channel interrupt B is active.</description>
138025 <description>Interrupt B status for DMA channel.</description>
138032 <description>The DMA channel interrupt B is not active.</description>
138037 <description>The DMA channel interrupt B is active.</description>
138044 <description>Interrupt B status for DMA channel.</description>
138051 <description>The DMA channel interrupt B is not active.</description>
138056 <description>The DMA channel interrupt B is active.</description>
138063 <description>Interrupt B status for DMA channel.</description>
138070 <description>The DMA channel interrupt B is not active.</description>
138075 <description>The DMA channel interrupt B is active.</description>
138082 <description>Interrupt B status for DMA channel.</description>
138089 <description>The DMA channel interrupt B is not active.</description>
138094 <description>The DMA channel interrupt B is active.</description>
138101 <description>Interrupt B status for DMA channel.</description>
138108 <description>The DMA channel interrupt B is not active.</description>
138113 <description>The DMA channel interrupt B is active.</description>
138120 <description>Interrupt B status for DMA channel.</description>
138127 <description>The DMA channel interrupt B is not active.</description>
138132 <description>The DMA channel interrupt B is active.</description>
138139 <description>Interrupt B status for DMA channel.</description>
138146 <description>The DMA channel interrupt B is not active.</description>
138151 <description>The DMA channel interrupt B is active.</description>
138158 <description>Interrupt B status for DMA channel.</description>
138165 <description>The DMA channel interrupt B is not active.</description>
138170 <description>The DMA channel interrupt B is active.</description>
138177 <description>Interrupt B status for DMA channel.</description>
138184 <description>The DMA channel interrupt B is not active.</description>
138189 <description>The DMA channel interrupt B is active.</description>
138196 <description>Interrupt B status for DMA channel.</description>
138203 <description>The DMA channel interrupt B is not active.</description>
138208 <description>The DMA channel interrupt B is active.</description>
138215 <description>Interrupt B status for DMA channel.</description>
138222 <description>The DMA channel interrupt B is not active.</description>
138227 <description>The DMA channel interrupt B is active.</description>
138234 <description>Interrupt B status for DMA channel.</description>
138241 <description>The DMA channel interrupt B is not active.</description>
138246 <description>The DMA channel interrupt B is active.</description>
138253 <description>Interrupt B status for DMA channel.</description>
138260 <description>The DMA channel interrupt B is not active.</description>
138265 <description>The DMA channel interrupt B is active.</description>
138272 <description>Interrupt B status for DMA channel.</description>
138279 <description>The DMA channel interrupt B is not active.</description>
138284 <description>The DMA channel interrupt B is active.</description>
138293 <description>Set ValidPending control bits for all DMA channels</description>
138302 <description>SetValid control for DMA channel.</description>
138309 <description>No effect.</description>
138314 <description>Sets the ValidPending control bit for DMA channel.</description>
138321 <description>SetValid control for DMA channel.</description>
138328 <description>No effect.</description>
138333 <description>Sets the ValidPending control bit for DMA channel.</description>
138340 <description>SetValid control for DMA channel.</description>
138347 <description>No effect.</description>
138352 <description>Sets the ValidPending control bit for DMA channel.</description>
138359 <description>SetValid control for DMA channel.</description>
138366 <description>No effect.</description>
138371 <description>Sets the ValidPending control bit for DMA channel.</description>
138378 <description>SetValid control for DMA channel.</description>
138385 <description>No effect.</description>
138390 <description>Sets the ValidPending control bit for DMA channel.</description>
138397 <description>SetValid control for DMA channel.</description>
138404 <description>No effect.</description>
138409 <description>Sets the ValidPending control bit for DMA channel.</description>
138416 <description>SetValid control for DMA channel.</description>
138423 <description>No effect.</description>
138428 <description>Sets the ValidPending control bit for DMA channel.</description>
138435 <description>SetValid control for DMA channel.</description>
138442 <description>No effect.</description>
138447 <description>Sets the ValidPending control bit for DMA channel.</description>
138454 <description>SetValid control for DMA channel.</description>
138461 <description>No effect.</description>
138466 <description>Sets the ValidPending control bit for DMA channel.</description>
138473 <description>SetValid control for DMA channel.</description>
138480 <description>No effect.</description>
138485 <description>Sets the ValidPending control bit for DMA channel.</description>
138492 <description>SetValid control for DMA channel.</description>
138499 <description>No effect.</description>
138504 <description>Sets the ValidPending control bit for DMA channel.</description>
138511 <description>SetValid control for DMA channel.</description>
138518 <description>No effect.</description>
138523 <description>Sets the ValidPending control bit for DMA channel.</description>
138530 <description>SetValid control for DMA channel.</description>
138537 <description>No effect.</description>
138542 <description>Sets the ValidPending control bit for DMA channel.</description>
138549 <description>SetValid control for DMA channel.</description>
138556 <description>No effect.</description>
138561 <description>Sets the ValidPending control bit for DMA channel.</description>
138568 <description>SetValid control for DMA channel.</description>
138575 <description>No effect.</description>
138580 <description>Sets the ValidPending control bit for DMA channel.</description>
138587 <description>SetValid control for DMA channel.</description>
138594 <description>No effect.</description>
138599 <description>Sets the ValidPending control bit for DMA channel.</description>
138608 <description>Set Trigger control bits for all DMA channels</description>
138617 <description>Set Trigger control bit for DMA channel.</description>
138624 <description>No effect.</description>
138629 <description>Sets the Trig bit for DMA channel.</description>
138636 <description>Set Trigger control bit for DMA channel.</description>
138643 <description>No effect.</description>
138648 <description>Sets the Trig bit for DMA channel.</description>
138655 <description>Set Trigger control bit for DMA channel.</description>
138662 <description>No effect.</description>
138667 <description>Sets the Trig bit for DMA channel.</description>
138674 <description>Set Trigger control bit for DMA channel.</description>
138681 <description>No effect.</description>
138686 <description>Sets the Trig bit for DMA channel.</description>
138693 <description>Set Trigger control bit for DMA channel.</description>
138700 <description>No effect.</description>
138705 <description>Sets the Trig bit for DMA channel.</description>
138712 <description>Set Trigger control bit for DMA channel.</description>
138719 <description>No effect.</description>
138724 <description>Sets the Trig bit for DMA channel.</description>
138731 <description>Set Trigger control bit for DMA channel.</description>
138738 <description>No effect.</description>
138743 <description>Sets the Trig bit for DMA channel.</description>
138750 <description>Set Trigger control bit for DMA channel.</description>
138757 <description>No effect.</description>
138762 <description>Sets the Trig bit for DMA channel.</description>
138769 <description>Set Trigger control bit for DMA channel.</description>
138776 <description>No effect.</description>
138781 <description>Sets the Trig bit for DMA channel.</description>
138788 <description>Set Trigger control bit for DMA channel.</description>
138795 <description>No effect.</description>
138800 <description>Sets the Trig bit for DMA channel.</description>
138807 <description>Set Trigger control bit for DMA channel.</description>
138814 <description>No effect.</description>
138819 <description>Sets the Trig bit for DMA channel.</description>
138826 <description>Set Trigger control bit for DMA channel.</description>
138833 <description>No effect.</description>
138838 <description>Sets the Trig bit for DMA channel.</description>
138845 <description>Set Trigger control bit for DMA channel.</description>
138852 <description>No effect.</description>
138857 <description>Sets the Trig bit for DMA channel.</description>
138864 <description>Set Trigger control bit for DMA channel.</description>
138871 <description>No effect.</description>
138876 <description>Sets the Trig bit for DMA channel.</description>
138883 <description>Set Trigger control bit for DMA channel.</description>
138890 <description>No effect.</description>
138895 <description>Sets the Trig bit for DMA channel.</description>
138902 <description>Set Trigger control bit for DMA channel.</description>
138909 <description>No effect.</description>
138914 <description>Sets the Trig bit for DMA channel.</description>
138923 <description>Channel Abort control for all DMA channels</description>
138932 <description>Abort control for DMA channel.</description>
138939 <description>No effect.</description>
138944 <description>Aborts DMA operations on channel.</description>
138951 <description>Abort control for DMA channel.</description>
138958 <description>No effect.</description>
138963 <description>Aborts DMA operations on channel.</description>
138970 <description>Abort control for DMA channel.</description>
138977 <description>No effect.</description>
138982 <description>Aborts DMA operations on channel.</description>
138989 <description>Abort control for DMA channel.</description>
138996 <description>No effect.</description>
139001 <description>Aborts DMA operations on channel.</description>
139008 <description>Abort control for DMA channel.</description>
139015 <description>No effect.</description>
139020 <description>Aborts DMA operations on channel.</description>
139027 <description>Abort control for DMA channel.</description>
139034 <description>No effect.</description>
139039 <description>Aborts DMA operations on channel.</description>
139046 <description>Abort control for DMA channel.</description>
139053 <description>No effect.</description>
139058 <description>Aborts DMA operations on channel.</description>
139065 <description>Abort control for DMA channel.</description>
139072 <description>No effect.</description>
139077 <description>Aborts DMA operations on channel.</description>
139084 <description>Abort control for DMA channel.</description>
139091 <description>No effect.</description>
139096 <description>Aborts DMA operations on channel.</description>
139103 <description>Abort control for DMA channel.</description>
139110 <description>No effect.</description>
139115 <description>Aborts DMA operations on channel.</description>
139122 <description>Abort control for DMA channel.</description>
139129 <description>No effect.</description>
139134 <description>Aborts DMA operations on channel.</description>
139141 <description>Abort control for DMA channel.</description>
139148 <description>No effect.</description>
139153 <description>Aborts DMA operations on channel.</description>
139160 <description>Abort control for DMA channel.</description>
139167 <description>No effect.</description>
139172 <description>Aborts DMA operations on channel.</description>
139179 <description>Abort control for DMA channel.</description>
139186 <description>No effect.</description>
139191 <description>Aborts DMA operations on channel.</description>
139198 <description>Abort control for DMA channel.</description>
139205 <description>No effect.</description>
139210 <description>Aborts DMA operations on channel.</description>
139217 <description>Abort control for DMA channel.</description>
139224 <description>No effect.</description>
139229 <description>Aborts DMA operations on channel.</description>
139240 <description>no description available</description>
139244 <description>Configuration register for DMA channel</description>
139253 <description>Peripheral request Enable.</description>
139260 <description>Peripheral DMA requests disabled.</description>
139265 <description>Peripheral DMA requests enabled.</description>
139272 <description>Hardware Triggering Enable for channel.</description>
139279 <description>Hardware triggering not used for channel.</description>
139284 <description>Hardware triggering used for channel.</description>
139291 <description>Trigger Polarity.</description>
139298 …<description>Active low - falling edge. Hardware trigger is active low or falling edge triggered, …
139303 …<description>Active high - rising edge. Hardware trigger is active high or rising edge triggered, …
139310 <description>Trigger Type.</description>
139317 …<description>Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, …
139322 <description>Level.</description>
139329 <description>Trigger Burst.</description>
139336 <description>Single transfer.</description>
139341 <description>Burst transfer.</description>
139348 <description>Burst Power.</description>
139355 <description>Source Burst Wrap.</description>
139362 <description>Disabled.</description>
139367 <description>Enabled.</description>
139374 <description>Destination Burst Wrap.</description>
139381 …<description>Disabled. Destination burst wrapping is not enabled for this DMA channel.</descriptio…
139386 … <description>Enabled. Destination burst wrapping is enabled for this DMA channel.</description>
139393 … <description>Priority of channel when multiple DMA requests are pending.</description>
139402 <description>Control and status register for DMA channel</description>
139411 <description>Valid pending flag for this channel.</description>
139418 <description>No effect on DMA operation.</description>
139423 <description>Valid pending.</description>
139430 <description>Trigger flag.</description>
139437 …<description>Not triggered. The trigger for this DMA channel is not set. DMA operations will not b…
139442 …<description>Triggered. The trigger for this DMA channel is set. DMA operations will be carried ou…
139451 <description>Transfer configuration register for DMA channel</description>
139460 <description>Configuration Valid flag.</description>
139467 <description>Not valid.</description>
139472 <description>Valid.</description>
139479 <description>Reload.</description>
139486 …<description>Disabled. The channels' control structure should not be reloaded when the current des…
139491 …<description>Enabled. The channels' control structure should be reloaded when the current descript…
139498 <description>Software Trigger.</description>
139505 <description>Not set.</description>
139510 <description>Set.</description>
139517 <description>Clear Trigger.</description>
139524 <description>Not cleared.</description>
139529 <description>Cleared.</description>
139536 <description>Set Interrupt flag A for channel.</description>
139543 <description>No effect.</description>
139548 …<description>Set. The INTA flag for this channel will be set when the current descriptor is exhaus…
139555 <description>Set Interrupt flag B for channel.</description>
139562 <description>No effect.</description>
139567 …<description>Set. The INTB flag for this channel will be set when the current descriptor is exhaus…
139574 <description>Transfer width used for this DMA channel.</description>
139581 <description>8-bit.</description>
139586 <description>16-bit.</description>
139591 <description>32-bit.</description>
139598 <description>Source address increment</description>
139605 <description>No increment.</description>
139610 <description>1 x width.</description>
139615 <description>2 x width.</description>
139620 <description>4 x width.</description>
139627 <description>Destination address increment</description>
139634 <description>No increment.</description>
139639 <description>1 x width.</description>
139644 <description>2 x width.</description>
139649 <description>4 x width.</description>
139656 … <description>Total number of transfers to be performed, minus 1 encoded.</description>
139668 <description>SECGPIO General Purpose I/O (GPIO)</description>
139679 <description>Byte pin registers for all port GPIO pins</description>
139688 <description>Port Byte</description>
139697 <description>Byte pin registers for all port GPIO pins</description>
139706 <description>Port Byte</description>
139715 <description>Byte pin registers for all port GPIO pins</description>
139724 <description>Port Byte</description>
139733 <description>Byte pin registers for all port GPIO pins</description>
139742 <description>Port Byte</description>
139751 <description>Byte pin registers for all port GPIO pins</description>
139760 <description>Port Byte</description>
139769 <description>Byte pin registers for all port GPIO pins</description>
139778 <description>Port Byte</description>
139787 <description>Byte pin registers for all port GPIO pins</description>
139796 <description>Port Byte</description>
139805 <description>Byte pin registers for all port GPIO pins</description>
139814 <description>Port Byte</description>
139823 <description>Byte pin registers for all port GPIO pins</description>
139832 <description>Port Byte</description>
139841 <description>Byte pin registers for all port GPIO pins</description>
139850 <description>Port Byte</description>
139859 <description>Byte pin registers for all port GPIO pins</description>
139868 <description>Port Byte</description>
139877 <description>Byte pin registers for all port GPIO pins</description>
139886 <description>Port Byte</description>
139895 <description>Byte pin registers for all port GPIO pins</description>
139904 <description>Port Byte</description>
139913 <description>Byte pin registers for all port GPIO pins</description>
139922 <description>Port Byte</description>
139931 <description>Byte pin registers for all port GPIO pins</description>
139940 <description>Port Byte</description>
139949 <description>Byte pin registers for all port GPIO pins</description>
139958 <description>Port Byte</description>
139967 <description>Byte pin registers for all port GPIO pins</description>
139976 <description>Port Byte</description>
139985 <description>Byte pin registers for all port GPIO pins</description>
139994 <description>Port Byte</description>
140003 <description>Byte pin registers for all port GPIO pins</description>
140012 <description>Port Byte</description>
140021 <description>Byte pin registers for all port GPIO pins</description>
140030 <description>Port Byte</description>
140039 <description>Byte pin registers for all port GPIO pins</description>
140048 <description>Port Byte</description>
140057 <description>Byte pin registers for all port GPIO pins</description>
140066 <description>Port Byte</description>
140075 <description>Byte pin registers for all port GPIO pins</description>
140084 <description>Port Byte</description>
140093 <description>Byte pin registers for all port GPIO pins</description>
140102 <description>Port Byte</description>
140111 <description>Byte pin registers for all port GPIO pins</description>
140120 <description>Port Byte</description>
140129 <description>Byte pin registers for all port GPIO pins</description>
140138 <description>Port Byte</description>
140147 <description>Byte pin registers for all port GPIO pins</description>
140156 <description>Port Byte</description>
140165 <description>Byte pin registers for all port GPIO pins</description>
140174 <description>Port Byte</description>
140183 <description>Byte pin registers for all port GPIO pins</description>
140192 <description>Port Byte</description>
140201 <description>Byte pin registers for all port GPIO pins</description>
140210 <description>Port Byte</description>
140219 <description>Byte pin registers for all port GPIO pins</description>
140228 <description>Port Byte</description>
140237 <description>Byte pin registers for all port GPIO pins</description>
140246 <description>Port Byte</description>
140255 <description>Word pin registers for all port GPIO pins</description>
140264 <description>PWORD</description>
140273 <description>Word pin registers for all port GPIO pins</description>
140282 <description>PWORD</description>
140291 <description>Word pin registers for all port GPIO pins</description>
140300 <description>PWORD</description>
140309 <description>Word pin registers for all port GPIO pins</description>
140318 <description>PWORD</description>
140327 <description>Word pin registers for all port GPIO pins</description>
140336 <description>PWORD</description>
140345 <description>Word pin registers for all port GPIO pins</description>
140354 <description>PWORD</description>
140363 <description>Word pin registers for all port GPIO pins</description>
140372 <description>PWORD</description>
140381 <description>Word pin registers for all port GPIO pins</description>
140390 <description>PWORD</description>
140399 <description>Word pin registers for all port GPIO pins</description>
140408 <description>PWORD</description>
140417 <description>Word pin registers for all port GPIO pins</description>
140426 <description>PWORD</description>
140435 <description>Word pin registers for all port GPIO pins</description>
140444 <description>PWORD</description>
140453 <description>Word pin registers for all port GPIO pins</description>
140462 <description>PWORD</description>
140471 <description>Word pin registers for all port GPIO pins</description>
140480 <description>PWORD</description>
140489 <description>Word pin registers for all port GPIO pins</description>
140498 <description>PWORD</description>
140507 <description>Word pin registers for all port GPIO pins</description>
140516 <description>PWORD</description>
140525 <description>Word pin registers for all port GPIO pins</description>
140534 <description>PWORD</description>
140543 <description>Word pin registers for all port GPIO pins</description>
140552 <description>PWORD</description>
140561 <description>Word pin registers for all port GPIO pins</description>
140570 <description>PWORD</description>
140579 <description>Word pin registers for all port GPIO pins</description>
140588 <description>PWORD</description>
140597 <description>Word pin registers for all port GPIO pins</description>
140606 <description>PWORD</description>
140615 <description>Word pin registers for all port GPIO pins</description>
140624 <description>PWORD</description>
140633 <description>Word pin registers for all port GPIO pins</description>
140642 <description>PWORD</description>
140651 <description>Word pin registers for all port GPIO pins</description>
140660 <description>PWORD</description>
140669 <description>Word pin registers for all port GPIO pins</description>
140678 <description>PWORD</description>
140687 <description>Word pin registers for all port GPIO pins</description>
140696 <description>PWORD</description>
140705 <description>Word pin registers for all port GPIO pins</description>
140714 <description>PWORD</description>
140723 <description>Word pin registers for all port GPIO pins</description>
140732 <description>PWORD</description>
140741 <description>Word pin registers for all port GPIO pins</description>
140750 <description>PWORD</description>
140759 <description>Word pin registers for all port GPIO pins</description>
140768 <description>PWORD</description>
140777 <description>Word pin registers for all port GPIO pins</description>
140786 <description>PWORD</description>
140795 <description>Word pin registers for all port GPIO pins</description>
140804 <description>PWORD</description>
140813 <description>Word pin registers for all port GPIO pins</description>
140822 <description>PWORD</description>
140831 <description>Port direction</description>
140840 <description>Selects pin direction for pin PIOa_b.</description>
140848 <description>Input</description>
140853 <description>Output</description>
140860 <description>Selects pin direction for pin PIOa_b.</description>
140868 <description>Input</description>
140873 <description>Output</description>
140880 <description>Selects pin direction for pin PIOa_b.</description>
140888 <description>Input</description>
140893 <description>Output</description>
140900 <description>Selects pin direction for pin PIOa_b.</description>
140908 <description>Input</description>
140913 <description>Output</description>
140920 <description>Selects pin direction for pin PIOa_b.</description>
140928 <description>Input</description>
140933 <description>Output</description>
140940 <description>Selects pin direction for pin PIOa_b.</description>
140948 <description>Input</description>
140953 <description>Output</description>
140960 <description>Selects pin direction for pin PIOa_b.</description>
140968 <description>Input</description>
140973 <description>Output</description>
140980 <description>Selects pin direction for pin PIOa_b.</description>
140988 <description>Input</description>
140993 <description>Output</description>
141000 <description>Selects pin direction for pin PIOa_b.</description>
141008 <description>Input</description>
141013 <description>Output</description>
141020 <description>Selects pin direction for pin PIOa_b.</description>
141028 <description>Input</description>
141033 <description>Output</description>
141040 <description>Selects pin direction for pin PIOa_b.</description>
141048 <description>Input</description>
141053 <description>Output</description>
141060 <description>Selects pin direction for pin PIOa_b.</description>
141068 <description>Input</description>
141073 <description>Output</description>
141080 <description>Selects pin direction for pin PIOa_b.</description>
141088 <description>Input</description>
141093 <description>Output</description>
141100 <description>Selects pin direction for pin PIOa_b.</description>
141108 <description>Input</description>
141113 <description>Output</description>
141120 <description>Selects pin direction for pin PIOa_b.</description>
141128 <description>Input</description>
141133 <description>Output</description>
141140 <description>Selects pin direction for pin PIOa_b.</description>
141148 <description>Input</description>
141153 <description>Output</description>
141160 <description>Selects pin direction for pin PIOa_b.</description>
141168 <description>Input</description>
141173 <description>Output</description>
141180 <description>Selects pin direction for pin PIOa_b.</description>
141188 <description>Input</description>
141193 <description>Output</description>
141200 <description>Selects pin direction for pin PIOa_b.</description>
141208 <description>Input</description>
141213 <description>Output</description>
141220 <description>Selects pin direction for pin PIOa_b.</description>
141228 <description>Input</description>
141233 <description>Output</description>
141240 <description>Selects pin direction for pin PIOa_b.</description>
141248 <description>Input</description>
141253 <description>Output</description>
141260 <description>Selects pin direction for pin PIOa_b.</description>
141268 <description>Input</description>
141273 <description>Output</description>
141280 <description>Selects pin direction for pin PIOa_b.</description>
141288 <description>Input</description>
141293 <description>Output</description>
141300 <description>Selects pin direction for pin PIOa_b.</description>
141308 <description>Input</description>
141313 <description>Output</description>
141320 <description>Selects pin direction for pin PIOa_b.</description>
141328 <description>Input</description>
141333 <description>Output</description>
141340 <description>Selects pin direction for pin PIOa_b.</description>
141348 <description>Input</description>
141353 <description>Output</description>
141360 <description>Selects pin direction for pin PIOa_b.</description>
141368 <description>Input</description>
141373 <description>Output</description>
141380 <description>Selects pin direction for pin PIOa_b.</description>
141388 <description>Input</description>
141393 <description>Output</description>
141400 <description>Selects pin direction for pin PIOa_b.</description>
141408 <description>Input</description>
141413 <description>Output</description>
141420 <description>Selects pin direction for pin PIOa_b.</description>
141428 <description>Input</description>
141433 <description>Output</description>
141440 <description>Selects pin direction for pin PIOa_b.</description>
141448 <description>Input</description>
141453 <description>Output</description>
141460 <description>Selects pin direction for pin PIOa_b.</description>
141468 <description>Input</description>
141473 <description>Output</description>
141482 <description>Port mask</description>
141491 <description>Port Mask</description>
141498 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141503 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141510 <description>Port Mask</description>
141517 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141522 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141529 <description>Port Mask</description>
141536 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141541 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141548 <description>Port Mask</description>
141555 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141560 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141567 <description>Port Mask</description>
141574 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141579 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141586 <description>Port Mask</description>
141593 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141598 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141605 <description>Port Mask</description>
141612 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141617 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141624 <description>Port Mask</description>
141631 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141636 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141643 <description>Port Mask</description>
141650 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141655 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141662 <description>Port Mask</description>
141669 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141674 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141681 <description>Port Mask</description>
141688 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141693 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141700 <description>Port Mask</description>
141707 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141712 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141719 <description>Port Mask</description>
141726 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141731 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141738 <description>Port Mask</description>
141745 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141750 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141757 <description>Port Mask</description>
141764 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141769 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141776 <description>Port Mask</description>
141783 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141788 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141795 <description>Port Mask</description>
141802 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141807 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141814 <description>Port Mask</description>
141821 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141826 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141833 <description>Port Mask</description>
141840 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141845 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141852 <description>Port Mask</description>
141859 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141864 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141871 <description>Port Mask</description>
141878 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141883 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141890 <description>Port Mask</description>
141897 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141902 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141909 <description>Port Mask</description>
141916 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141921 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141928 <description>Port Mask</description>
141935 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141940 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141947 <description>Port Mask</description>
141954 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141959 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141966 <description>Port Mask</description>
141973 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141978 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
141985 <description>Port Mask</description>
141992 <description>Read MPIN: pin state; write MPIN: load output bit</description>
141997 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142004 <description>Port Mask</description>
142011 <description>Read MPIN: pin state; write MPIN: load output bit</description>
142016 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142023 <description>Port Mask</description>
142030 <description>Read MPIN: pin state; write MPIN: load output bit</description>
142035 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142042 <description>Port Mask</description>
142049 <description>Read MPIN: pin state; write MPIN: load output bit</description>
142054 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142061 <description>Port Mask</description>
142068 <description>Read MPIN: pin state; write MPIN: load output bit</description>
142073 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142080 <description>Port Mask</description>
142087 <description>Read MPIN: pin state; write MPIN: load output bit</description>
142092 <description>Read MPIN: 0; write MPIN: output bit not affected</description>
142101 <description>Port pin</description>
142110 <description>Port pins</description>
142117 <description>Read- pin is low; Write- clear output bit</description>
142122 <description>Read- pin is high; Write- set output bit</description>
142129 <description>Port pins</description>
142136 <description>Read- pin is low; Write- clear output bit</description>
142141 <description>Read- pin is high; Write- set output bit</description>
142148 <description>Port pins</description>
142155 <description>Read- pin is low; Write- clear output bit</description>
142160 <description>Read- pin is high; Write- set output bit</description>
142167 <description>Port pins</description>
142174 <description>Read- pin is low; Write- clear output bit</description>
142179 <description>Read- pin is high; Write- set output bit</description>
142186 <description>Port pins</description>
142193 <description>Read- pin is low; Write- clear output bit</description>
142198 <description>Read- pin is high; Write- set output bit</description>
142205 <description>Port pins</description>
142212 <description>Read- pin is low; Write- clear output bit</description>
142217 <description>Read- pin is high; Write- set output bit</description>
142224 <description>Port pins</description>
142231 <description>Read- pin is low; Write- clear output bit</description>
142236 <description>Read- pin is high; Write- set output bit</description>
142243 <description>Port pins</description>
142250 <description>Read- pin is low; Write- clear output bit</description>
142255 <description>Read- pin is high; Write- set output bit</description>
142262 <description>Port pins</description>
142269 <description>Read- pin is low; Write- clear output bit</description>
142274 <description>Read- pin is high; Write- set output bit</description>
142281 <description>Port pins</description>
142288 <description>Read- pin is low; Write- clear output bit</description>
142293 <description>Read- pin is high; Write- set output bit</description>
142300 <description>Port pins</description>
142307 <description>Read- pin is low; Write- clear output bit</description>
142312 <description>Read- pin is high; Write- set output bit</description>
142319 <description>Port pins</description>
142326 <description>Read- pin is low; Write- clear output bit</description>
142331 <description>Read- pin is high; Write- set output bit</description>
142338 <description>Port pins</description>
142345 <description>Read- pin is low; Write- clear output bit</description>
142350 <description>Read- pin is high; Write- set output bit</description>
142357 <description>Port pins</description>
142364 <description>Read- pin is low; Write- clear output bit</description>
142369 <description>Read- pin is high; Write- set output bit</description>
142376 <description>Port pins</description>
142383 <description>Read- pin is low; Write- clear output bit</description>
142388 <description>Read- pin is high; Write- set output bit</description>
142395 <description>Port pins</description>
142402 <description>Read- pin is low; Write- clear output bit</description>
142407 <description>Read- pin is high; Write- set output bit</description>
142414 <description>Port pins</description>
142421 <description>Read- pin is low; Write- clear output bit</description>
142426 <description>Read- pin is high; Write- set output bit</description>
142433 <description>Port pins</description>
142440 <description>Read- pin is low; Write- clear output bit</description>
142445 <description>Read- pin is high; Write- set output bit</description>
142452 <description>Port pins</description>
142459 <description>Read- pin is low; Write- clear output bit</description>
142464 <description>Read- pin is high; Write- set output bit</description>
142471 <description>Port pins</description>
142478 <description>Read- pin is low; Write- clear output bit</description>
142483 <description>Read- pin is high; Write- set output bit</description>
142490 <description>Port pins</description>
142497 <description>Read- pin is low; Write- clear output bit</description>
142502 <description>Read- pin is high; Write- set output bit</description>
142509 <description>Port pins</description>
142516 <description>Read- pin is low; Write- clear output bit</description>
142521 <description>Read- pin is high; Write- set output bit</description>
142528 <description>Port pins</description>
142535 <description>Read- pin is low; Write- clear output bit</description>
142540 <description>Read- pin is high; Write- set output bit</description>
142547 <description>Port pins</description>
142554 <description>Read- pin is low; Write- clear output bit</description>
142559 <description>Read- pin is high; Write- set output bit</description>
142566 <description>Port pins</description>
142573 <description>Read- pin is low; Write- clear output bit</description>
142578 <description>Read- pin is high; Write- set output bit</description>
142585 <description>Port pins</description>
142592 <description>Read- pin is low; Write- clear output bit</description>
142597 <description>Read- pin is high; Write- set output bit</description>
142604 <description>Port pins</description>
142611 <description>Read- pin is low; Write- clear output bit</description>
142616 <description>Read- pin is high; Write- set output bit</description>
142623 <description>Port pins</description>
142630 <description>Read- pin is low; Write- clear output bit</description>
142635 <description>Read- pin is high; Write- set output bit</description>
142642 <description>Port pins</description>
142649 <description>Read- pin is low; Write- clear output bit</description>
142654 <description>Read- pin is high; Write- set output bit</description>
142661 <description>Port pins</description>
142668 <description>Read- pin is low; Write- clear output bit</description>
142673 <description>Read- pin is high; Write- set output bit</description>
142680 <description>Port pins</description>
142687 <description>Read- pin is low; Write- clear output bit</description>
142692 <description>Read- pin is high; Write- set output bit</description>
142699 <description>Port pins</description>
142706 <description>Read- pin is low; Write- clear output bit</description>
142711 <description>Read- pin is high; Write- set output bit</description>
142720 <description>Masked Port Pin</description>
142729 <description>Mask bits for port pins</description>
142736 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142741 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142748 <description>Mask bits for port pins</description>
142755 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142760 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142767 <description>Mask bits for port pins</description>
142774 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142779 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142786 <description>Mask bits for port pins</description>
142793 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142798 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142805 <description>Mask bits for port pins</description>
142812 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142817 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142824 <description>Mask bits for port pins</description>
142831 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142836 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142843 <description>Mask bits for port pins</description>
142850 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142855 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142862 <description>Mask bits for port pins</description>
142869 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142874 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142881 <description>Mask bits for port pins</description>
142888 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142893 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142900 <description>Mask bits for port pins</description>
142907 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142912 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142919 <description>Mask bits for port pins</description>
142926 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142931 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142938 <description>Mask bits for port pins</description>
142945 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142950 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142957 <description>Mask bits for port pins</description>
142964 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142969 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142976 <description>Mask bits for port pins</description>
142983 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
142988 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
142995 <description>Mask bits for port pins</description>
143002 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143007 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143014 <description>Mask bits for port pins</description>
143021 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143026 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143033 <description>Mask bits for port pins</description>
143040 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143045 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143052 <description>Mask bits for port pins</description>
143059 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143064 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143071 <description>Mask bits for port pins</description>
143078 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143083 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143090 <description>Mask bits for port pins</description>
143097 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143102 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143109 <description>Mask bits for port pins</description>
143116 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143121 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143128 <description>Mask bits for port pins</description>
143135 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143140 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143147 <description>Mask bits for port pins</description>
143154 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143159 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143166 <description>Mask bits for port pins</description>
143173 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143178 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143185 <description>Mask bits for port pins</description>
143192 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143197 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143204 <description>Mask bits for port pins</description>
143211 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143216 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143223 <description>Mask bits for port pins</description>
143230 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143235 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143242 <description>Mask bits for port pins</description>
143249 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143254 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143261 <description>Mask bits for port pins</description>
143268 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143273 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143280 <description>Mask bits for port pins</description>
143287 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143292 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143299 <description>Mask bits for port pins</description>
143306 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143311 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143318 <description>Mask bits for port pins</description>
143325 …description>Read- pin is LOW and/or the corresponding bit in the MASK register is 1; write- clear …
143330 …description>Read- pin is HIGH and the corresponding bit in the MASK register is 0; write- set outp…
143339 <description>Port set</description>
143348 <description>Read or set output bits</description>
143356 <description>Read- output bit; write- no operation</description>
143361 <description>Read- output bit; write- set output bit</description>
143370 <description>Port clear</description>
143379 <description>Clear output bits</description>
143387 <description>No operation</description>
143392 <description>Clears output bit</description>
143399 <description>Clear output bits</description>
143407 <description>No operation</description>
143412 <description>Clears output bit</description>
143419 <description>Clear output bits</description>
143427 <description>No operation</description>
143432 <description>Clears output bit</description>
143439 <description>Clear output bits</description>
143447 <description>No operation</description>
143452 <description>Clears output bit</description>
143459 <description>Clear output bits</description>
143467 <description>No operation</description>
143472 <description>Clears output bit</description>
143479 <description>Clear output bits</description>
143487 <description>No operation</description>
143492 <description>Clears output bit</description>
143499 <description>Clear output bits</description>
143507 <description>No operation</description>
143512 <description>Clears output bit</description>
143519 <description>Clear output bits</description>
143527 <description>No operation</description>
143532 <description>Clears output bit</description>
143539 <description>Clear output bits</description>
143547 <description>No operation</description>
143552 <description>Clears output bit</description>
143559 <description>Clear output bits</description>
143567 <description>No operation</description>
143572 <description>Clears output bit</description>
143579 <description>Clear output bits</description>
143587 <description>No operation</description>
143592 <description>Clears output bit</description>
143599 <description>Clear output bits</description>
143607 <description>No operation</description>
143612 <description>Clears output bit</description>
143619 <description>Clear output bits</description>
143627 <description>No operation</description>
143632 <description>Clears output bit</description>
143639 <description>Clear output bits</description>
143647 <description>No operation</description>
143652 <description>Clears output bit</description>
143659 <description>Clear output bits</description>
143667 <description>No operation</description>
143672 <description>Clears output bit</description>
143679 <description>Clear output bits</description>
143687 <description>No operation</description>
143692 <description>Clears output bit</description>
143699 <description>Clear output bits</description>
143707 <description>No operation</description>
143712 <description>Clears output bit</description>
143719 <description>Clear output bits</description>
143727 <description>No operation</description>
143732 <description>Clears output bit</description>
143739 <description>Clear output bits</description>
143747 <description>No operation</description>
143752 <description>Clears output bit</description>
143759 <description>Clear output bits</description>
143767 <description>No operation</description>
143772 <description>Clears output bit</description>
143779 <description>Clear output bits</description>
143787 <description>No operation</description>
143792 <description>Clears output bit</description>
143799 <description>Clear output bits</description>
143807 <description>No operation</description>
143812 <description>Clears output bit</description>
143819 <description>Clear output bits</description>
143827 <description>No operation</description>
143832 <description>Clears output bit</description>
143839 <description>Clear output bits</description>
143847 <description>No operation</description>
143852 <description>Clears output bit</description>
143859 <description>Clear output bits</description>
143867 <description>No operation</description>
143872 <description>Clears output bit</description>
143879 <description>Clear output bits</description>
143887 <description>No operation</description>
143892 <description>Clears output bit</description>
143899 <description>Clear output bits</description>
143907 <description>No operation</description>
143912 <description>Clears output bit</description>
143919 <description>Clear output bits</description>
143927 <description>No operation</description>
143932 <description>Clears output bit</description>
143939 <description>Clear output bits</description>
143947 <description>No operation</description>
143952 <description>Clears output bit</description>
143959 <description>Clear output bits</description>
143967 <description>No operation</description>
143972 <description>Clears output bit</description>
143979 <description>Clear output bits</description>
143987 <description>No operation</description>
143992 <description>Clears output bit</description>
143999 <description>Clear output bits</description>
144007 <description>No operation</description>
144012 <description>Clears output bit</description>
144021 <description>Port toggle</description>
144030 <description>Toggle output bits</description>
144037 <description>No operation</description>
144042 <description>Toggle output bit</description>
144049 <description>Toggle output bits</description>
144056 <description>No operation</description>
144061 <description>Toggle output bit</description>
144068 <description>Toggle output bits</description>
144075 <description>No operation</description>
144080 <description>Toggle output bit</description>
144087 <description>Toggle output bits</description>
144094 <description>No operation</description>
144099 <description>Toggle output bit</description>
144106 <description>Toggle output bits</description>
144113 <description>No operation</description>
144118 <description>Toggle output bit</description>
144125 <description>Toggle output bits</description>
144132 <description>No operation</description>
144137 <description>Toggle output bit</description>
144144 <description>Toggle output bits</description>
144151 <description>No operation</description>
144156 <description>Toggle output bit</description>
144163 <description>Toggle output bits</description>
144170 <description>No operation</description>
144175 <description>Toggle output bit</description>
144182 <description>Toggle output bits</description>
144189 <description>No operation</description>
144194 <description>Toggle output bit</description>
144201 <description>Toggle output bits</description>
144208 <description>No operation</description>
144213 <description>Toggle output bit</description>
144220 <description>Toggle output bits</description>
144227 <description>No operation</description>
144232 <description>Toggle output bit</description>
144239 <description>Toggle output bits</description>
144246 <description>No operation</description>
144251 <description>Toggle output bit</description>
144258 <description>Toggle output bits</description>
144265 <description>No operation</description>
144270 <description>Toggle output bit</description>
144277 <description>Toggle output bits</description>
144284 <description>No operation</description>
144289 <description>Toggle output bit</description>
144296 <description>Toggle output bits</description>
144303 <description>No operation</description>
144308 <description>Toggle output bit</description>
144315 <description>Toggle output bits</description>
144322 <description>No operation</description>
144327 <description>Toggle output bit</description>
144334 <description>Toggle output bits</description>
144341 <description>No operation</description>
144346 <description>Toggle output bit</description>
144353 <description>Toggle output bits</description>
144360 <description>No operation</description>
144365 <description>Toggle output bit</description>
144372 <description>Toggle output bits</description>
144379 <description>No operation</description>
144384 <description>Toggle output bit</description>
144391 <description>Toggle output bits</description>
144398 <description>No operation</description>
144403 <description>Toggle output bit</description>
144410 <description>Toggle output bits</description>
144417 <description>No operation</description>
144422 <description>Toggle output bit</description>
144429 <description>Toggle output bits</description>
144436 <description>No operation</description>
144441 <description>Toggle output bit</description>
144448 <description>Toggle output bits</description>
144455 <description>No operation</description>
144460 <description>Toggle output bit</description>
144467 <description>Toggle output bits</description>
144474 <description>No operation</description>
144479 <description>Toggle output bit</description>
144486 <description>Toggle output bits</description>
144493 <description>No operation</description>
144498 <description>Toggle output bit</description>
144505 <description>Toggle output bits</description>
144512 <description>No operation</description>
144517 <description>Toggle output bit</description>
144524 <description>Toggle output bits</description>
144531 <description>No operation</description>
144536 <description>Toggle output bit</description>
144543 <description>Toggle output bits</description>
144550 <description>No operation</description>
144555 <description>Toggle output bit</description>
144562 <description>Toggle output bits</description>
144569 <description>No operation</description>
144574 <description>Toggle output bit</description>
144581 <description>Toggle output bits</description>
144588 <description>No operation</description>
144593 <description>Toggle output bit</description>
144600 <description>Toggle output bits</description>
144607 <description>No operation</description>
144612 <description>Toggle output bit</description>
144619 <description>Toggle output bits</description>
144626 <description>No operation</description>
144631 <description>Toggle output bit</description>
144640 <description>Port direction set</description>
144649 <description>Direction set bits for Port pins</description>
144657 <description>No operation</description>
144662 <description>Sets direction bit</description>
144669 <description>Direction set bits for Port pins</description>
144677 <description>No operation</description>
144682 <description>Sets direction bit</description>
144689 <description>Direction set bits for Port pins</description>
144697 <description>No operation</description>
144702 <description>Sets direction bit</description>
144709 <description>Direction set bits for Port pins</description>
144717 <description>No operation</description>
144722 <description>Sets direction bit</description>
144729 <description>Direction set bits for Port pins</description>
144737 <description>No operation</description>
144742 <description>Sets direction bit</description>
144749 <description>Direction set bits for Port pins</description>
144757 <description>No operation</description>
144762 <description>Sets direction bit</description>
144769 <description>Direction set bits for Port pins</description>
144777 <description>No operation</description>
144782 <description>Sets direction bit</description>
144789 <description>Direction set bits for Port pins</description>
144797 <description>No operation</description>
144802 <description>Sets direction bit</description>
144809 <description>Direction set bits for Port pins</description>
144817 <description>No operation</description>
144822 <description>Sets direction bit</description>
144829 <description>Direction set bits for Port pins</description>
144837 <description>No operation</description>
144842 <description>Sets direction bit</description>
144849 <description>Direction set bits for Port pins</description>
144857 <description>No operation</description>
144862 <description>Sets direction bit</description>
144869 <description>Direction set bits for Port pins</description>
144877 <description>No operation</description>
144882 <description>Sets direction bit</description>
144889 <description>Direction set bits for Port pins</description>
144897 <description>No operation</description>
144902 <description>Sets direction bit</description>
144909 <description>Direction set bits for Port pins</description>
144917 <description>No operation</description>
144922 <description>Sets direction bit</description>
144929 <description>Direction set bits for Port pins</description>
144937 <description>No operation</description>
144942 <description>Sets direction bit</description>
144949 <description>Direction set bits for Port pins</description>
144957 <description>No operation</description>
144962 <description>Sets direction bit</description>
144969 <description>Direction set bits for Port pins</description>
144977 <description>No operation</description>
144982 <description>Sets direction bit</description>
144989 <description>Direction set bits for Port pins</description>
144997 <description>No operation</description>
145002 <description>Sets direction bit</description>
145009 <description>Direction set bits for Port pins</description>
145017 <description>No operation</description>
145022 <description>Sets direction bit</description>
145029 <description>Direction set bits for Port pins</description>
145037 <description>No operation</description>
145042 <description>Sets direction bit</description>
145049 <description>Direction set bits for Port pins</description>
145057 <description>No operation</description>
145062 <description>Sets direction bit</description>
145069 <description>Direction set bits for Port pins</description>
145077 <description>No operation</description>
145082 <description>Sets direction bit</description>
145089 <description>Direction set bits for Port pins</description>
145097 <description>No operation</description>
145102 <description>Sets direction bit</description>
145109 <description>Direction set bits for Port pins</description>
145117 <description>No operation</description>
145122 <description>Sets direction bit</description>
145129 <description>Direction set bits for Port pins</description>
145137 <description>No operation</description>
145142 <description>Sets direction bit</description>
145149 <description>Direction set bits for Port pins</description>
145157 <description>No operation</description>
145162 <description>Sets direction bit</description>
145169 <description>Direction set bits for Port pins</description>
145177 <description>No operation</description>
145182 <description>Sets direction bit</description>
145189 <description>Direction set bits for Port pins</description>
145197 <description>No operation</description>
145202 <description>Sets direction bit</description>
145209 <description>Direction set bits for Port pins</description>
145217 <description>No operation</description>
145222 <description>Sets direction bit</description>
145229 <description>Direction set bits for Port pins</description>
145237 <description>No operation</description>
145242 <description>Sets direction bit</description>
145249 <description>Direction set bits for Port pins</description>
145257 <description>No operation</description>
145262 <description>Sets direction bit</description>
145269 <description>Direction set bits for Port pins</description>
145277 <description>No operation</description>
145282 <description>Sets direction bit</description>
145291 <description>Port direction clear</description>
145300 <description>Clear direction bits.</description>
145308 <description>No operation</description>
145313 <description>Clears direction bits</description>
145320 <description>Clear direction bits.</description>
145328 <description>No operation</description>
145333 <description>Clears direction bits</description>
145340 <description>Clear direction bits.</description>
145348 <description>No operation</description>
145353 <description>Clears direction bits</description>
145360 <description>Clear direction bits.</description>
145368 <description>No operation</description>
145373 <description>Clears direction bits</description>
145380 <description>Clear direction bits.</description>
145388 <description>No operation</description>
145393 <description>Clears direction bits</description>
145400 <description>Clear direction bits.</description>
145408 <description>No operation</description>
145413 <description>Clears direction bits</description>
145420 <description>Clear direction bits.</description>
145428 <description>No operation</description>
145433 <description>Clears direction bits</description>
145440 <description>Clear direction bits.</description>
145448 <description>No operation</description>
145453 <description>Clears direction bits</description>
145460 <description>Clear direction bits.</description>
145468 <description>No operation</description>
145473 <description>Clears direction bits</description>
145480 <description>Clear direction bits.</description>
145488 <description>No operation</description>
145493 <description>Clears direction bits</description>
145500 <description>Clear direction bits.</description>
145508 <description>No operation</description>
145513 <description>Clears direction bits</description>
145520 <description>Clear direction bits.</description>
145528 <description>No operation</description>
145533 <description>Clears direction bits</description>
145540 <description>Clear direction bits.</description>
145548 <description>No operation</description>
145553 <description>Clears direction bits</description>
145560 <description>Clear direction bits.</description>
145568 <description>No operation</description>
145573 <description>Clears direction bits</description>
145580 <description>Clear direction bits.</description>
145588 <description>No operation</description>
145593 <description>Clears direction bits</description>
145600 <description>Clear direction bits.</description>
145608 <description>No operation</description>
145613 <description>Clears direction bits</description>
145620 <description>Clear direction bits.</description>
145628 <description>No operation</description>
145633 <description>Clears direction bits</description>
145640 <description>Clear direction bits.</description>
145648 <description>No operation</description>
145653 <description>Clears direction bits</description>
145660 <description>Clear direction bits.</description>
145668 <description>No operation</description>
145673 <description>Clears direction bits</description>
145680 <description>Clear direction bits.</description>
145688 <description>No operation</description>
145693 <description>Clears direction bits</description>
145700 <description>Clear direction bits.</description>
145708 <description>No operation</description>
145713 <description>Clears direction bits</description>
145720 <description>Clear direction bits.</description>
145728 <description>No operation</description>
145733 <description>Clears direction bits</description>
145740 <description>Clear direction bits.</description>
145748 <description>No operation</description>
145753 <description>Clears direction bits</description>
145760 <description>Clear direction bits.</description>
145768 <description>No operation</description>
145773 <description>Clears direction bits</description>
145780 <description>Clear direction bits.</description>
145788 <description>No operation</description>
145793 <description>Clears direction bits</description>
145800 <description>Clear direction bits.</description>
145808 <description>No operation</description>
145813 <description>Clears direction bits</description>
145820 <description>Clear direction bits.</description>
145828 <description>No operation</description>
145833 <description>Clears direction bits</description>
145840 <description>Clear direction bits.</description>
145848 <description>No operation</description>
145853 <description>Clears direction bits</description>
145860 <description>Clear direction bits.</description>
145868 <description>No operation</description>
145873 <description>Clears direction bits</description>
145880 <description>Clear direction bits.</description>
145888 <description>No operation</description>
145893 <description>Clears direction bits</description>
145900 <description>Clear direction bits.</description>
145908 <description>No operation</description>
145913 <description>Clears direction bits</description>
145920 <description>Clear direction bits.</description>
145928 <description>No operation</description>
145933 <description>Clears direction bits</description>
145942 <description>Port direction toggle</description>
145951 <description>Toggle direction bits.</description>
145958 <description>No operation</description>
145963 <description>Toggles direction bit</description>
145972 <description>Interrupt A enable control</description>
145981 <description>Interrupt A enable bits.</description>
145988 <description>Pin does not contribute to GPIO interrupt A</description>
145993 <description>Pin contributes to GPIO interrupt A</description>
146000 <description>Interrupt A enable bits.</description>
146007 <description>Pin does not contribute to GPIO interrupt A</description>
146012 <description>Pin contributes to GPIO interrupt A</description>
146019 <description>Interrupt A enable bits.</description>
146026 <description>Pin does not contribute to GPIO interrupt A</description>
146031 <description>Pin contributes to GPIO interrupt A</description>
146038 <description>Interrupt A enable bits.</description>
146045 <description>Pin does not contribute to GPIO interrupt A</description>
146050 <description>Pin contributes to GPIO interrupt A</description>
146057 <description>Interrupt A enable bits.</description>
146064 <description>Pin does not contribute to GPIO interrupt A</description>
146069 <description>Pin contributes to GPIO interrupt A</description>
146076 <description>Interrupt A enable bits.</description>
146083 <description>Pin does not contribute to GPIO interrupt A</description>
146088 <description>Pin contributes to GPIO interrupt A</description>
146095 <description>Interrupt A enable bits.</description>
146102 <description>Pin does not contribute to GPIO interrupt A</description>
146107 <description>Pin contributes to GPIO interrupt A</description>
146114 <description>Interrupt A enable bits.</description>
146121 <description>Pin does not contribute to GPIO interrupt A</description>
146126 <description>Pin contributes to GPIO interrupt A</description>
146133 <description>Interrupt A enable bits.</description>
146140 <description>Pin does not contribute to GPIO interrupt A</description>
146145 <description>Pin contributes to GPIO interrupt A</description>
146152 <description>Interrupt A enable bits.</description>
146159 <description>Pin does not contribute to GPIO interrupt A</description>
146164 <description>Pin contributes to GPIO interrupt A</description>
146171 <description>Interrupt A enable bits.</description>
146178 <description>Pin does not contribute to GPIO interrupt A</description>
146183 <description>Pin contributes to GPIO interrupt A</description>
146190 <description>Interrupt A enable bits.</description>
146197 <description>Pin does not contribute to GPIO interrupt A</description>
146202 <description>Pin contributes to GPIO interrupt A</description>
146209 <description>Interrupt A enable bits.</description>
146216 <description>Pin does not contribute to GPIO interrupt A</description>
146221 <description>Pin contributes to GPIO interrupt A</description>
146228 <description>Interrupt A enable bits.</description>
146235 <description>Pin does not contribute to GPIO interrupt A</description>
146240 <description>Pin contributes to GPIO interrupt A</description>
146247 <description>Interrupt A enable bits.</description>
146254 <description>Pin does not contribute to GPIO interrupt A</description>
146259 <description>Pin contributes to GPIO interrupt A</description>
146266 <description>Interrupt A enable bits.</description>
146273 <description>Pin does not contribute to GPIO interrupt A</description>
146278 <description>Pin contributes to GPIO interrupt A</description>
146285 <description>Interrupt A enable bits.</description>
146292 <description>Pin does not contribute to GPIO interrupt A</description>
146297 <description>Pin contributes to GPIO interrupt A</description>
146304 <description>Interrupt A enable bits.</description>
146311 <description>Pin does not contribute to GPIO interrupt A</description>
146316 <description>Pin contributes to GPIO interrupt A</description>
146323 <description>Interrupt A enable bits.</description>
146330 <description>Pin does not contribute to GPIO interrupt A</description>
146335 <description>Pin contributes to GPIO interrupt A</description>
146342 <description>Interrupt A enable bits.</description>
146349 <description>Pin does not contribute to GPIO interrupt A</description>
146354 <description>Pin contributes to GPIO interrupt A</description>
146361 <description>Interrupt A enable bits.</description>
146368 <description>Pin does not contribute to GPIO interrupt A</description>
146373 <description>Pin contributes to GPIO interrupt A</description>
146380 <description>Interrupt A enable bits.</description>
146387 <description>Pin does not contribute to GPIO interrupt A</description>
146392 <description>Pin contributes to GPIO interrupt A</description>
146399 <description>Interrupt A enable bits.</description>
146406 <description>Pin does not contribute to GPIO interrupt A</description>
146411 <description>Pin contributes to GPIO interrupt A</description>
146418 <description>Interrupt A enable bits.</description>
146425 <description>Pin does not contribute to GPIO interrupt A</description>
146430 <description>Pin contributes to GPIO interrupt A</description>
146437 <description>Interrupt A enable bits.</description>
146444 <description>Pin does not contribute to GPIO interrupt A</description>
146449 <description>Pin contributes to GPIO interrupt A</description>
146456 <description>Interrupt A enable bits.</description>
146463 <description>Pin does not contribute to GPIO interrupt A</description>
146468 <description>Pin contributes to GPIO interrupt A</description>
146475 <description>Interrupt A enable bits.</description>
146482 <description>Pin does not contribute to GPIO interrupt A</description>
146487 <description>Pin contributes to GPIO interrupt A</description>
146494 <description>Interrupt A enable bits.</description>
146501 <description>Pin does not contribute to GPIO interrupt A</description>
146506 <description>Pin contributes to GPIO interrupt A</description>
146513 <description>Interrupt A enable bits.</description>
146520 <description>Pin does not contribute to GPIO interrupt A</description>
146525 <description>Pin contributes to GPIO interrupt A</description>
146532 <description>Interrupt A enable bits.</description>
146539 <description>Pin does not contribute to GPIO interrupt A</description>
146544 <description>Pin contributes to GPIO interrupt A</description>
146551 <description>Interrupt A enable bits.</description>
146558 <description>Pin does not contribute to GPIO interrupt A</description>
146563 <description>Pin contributes to GPIO interrupt A</description>
146570 <description>Interrupt A enable bits.</description>
146577 <description>Pin does not contribute to GPIO interrupt A</description>
146582 <description>Pin contributes to GPIO interrupt A</description>
146591 <description>Interrupt B enable control</description>
146600 <description>Interrupt B enable bits.</description>
146607 <description>Pin does not contribute to GPIO interrupt B</description>
146612 <description>Pin contributes to GPIO interrupt B</description>
146619 <description>Interrupt B enable bits.</description>
146626 <description>Pin does not contribute to GPIO interrupt B</description>
146631 <description>Pin contributes to GPIO interrupt B</description>
146638 <description>Interrupt B enable bits.</description>
146645 <description>Pin does not contribute to GPIO interrupt B</description>
146650 <description>Pin contributes to GPIO interrupt B</description>
146657 <description>Interrupt B enable bits.</description>
146664 <description>Pin does not contribute to GPIO interrupt B</description>
146669 <description>Pin contributes to GPIO interrupt B</description>
146676 <description>Interrupt B enable bits.</description>
146683 <description>Pin does not contribute to GPIO interrupt B</description>
146688 <description>Pin contributes to GPIO interrupt B</description>
146695 <description>Interrupt B enable bits.</description>
146702 <description>Pin does not contribute to GPIO interrupt B</description>
146707 <description>Pin contributes to GPIO interrupt B</description>
146714 <description>Interrupt B enable bits.</description>
146721 <description>Pin does not contribute to GPIO interrupt B</description>
146726 <description>Pin contributes to GPIO interrupt B</description>
146733 <description>Interrupt B enable bits.</description>
146740 <description>Pin does not contribute to GPIO interrupt B</description>
146745 <description>Pin contributes to GPIO interrupt B</description>
146752 <description>Interrupt B enable bits.</description>
146759 <description>Pin does not contribute to GPIO interrupt B</description>
146764 <description>Pin contributes to GPIO interrupt B</description>
146771 <description>Interrupt B enable bits.</description>
146778 <description>Pin does not contribute to GPIO interrupt B</description>
146783 <description>Pin contributes to GPIO interrupt B</description>
146790 <description>Interrupt B enable bits.</description>
146797 <description>Pin does not contribute to GPIO interrupt B</description>
146802 <description>Pin contributes to GPIO interrupt B</description>
146809 <description>Interrupt B enable bits.</description>
146816 <description>Pin does not contribute to GPIO interrupt B</description>
146821 <description>Pin contributes to GPIO interrupt B</description>
146828 <description>Interrupt B enable bits.</description>
146835 <description>Pin does not contribute to GPIO interrupt B</description>
146840 <description>Pin contributes to GPIO interrupt B</description>
146847 <description>Interrupt B enable bits.</description>
146854 <description>Pin does not contribute to GPIO interrupt B</description>
146859 <description>Pin contributes to GPIO interrupt B</description>
146866 <description>Interrupt B enable bits.</description>
146873 <description>Pin does not contribute to GPIO interrupt B</description>
146878 <description>Pin contributes to GPIO interrupt B</description>
146885 <description>Interrupt B enable bits.</description>
146892 <description>Pin does not contribute to GPIO interrupt B</description>
146897 <description>Pin contributes to GPIO interrupt B</description>
146904 <description>Interrupt B enable bits.</description>
146911 <description>Pin does not contribute to GPIO interrupt B</description>
146916 <description>Pin contributes to GPIO interrupt B</description>
146923 <description>Interrupt B enable bits.</description>
146930 <description>Pin does not contribute to GPIO interrupt B</description>
146935 <description>Pin contributes to GPIO interrupt B</description>
146942 <description>Interrupt B enable bits.</description>
146949 <description>Pin does not contribute to GPIO interrupt B</description>
146954 <description>Pin contributes to GPIO interrupt B</description>
146961 <description>Interrupt B enable bits.</description>
146968 <description>Pin does not contribute to GPIO interrupt B</description>
146973 <description>Pin contributes to GPIO interrupt B</description>
146980 <description>Interrupt B enable bits.</description>
146987 <description>Pin does not contribute to GPIO interrupt B</description>
146992 <description>Pin contributes to GPIO interrupt B</description>
146999 <description>Interrupt B enable bits.</description>
147006 <description>Pin does not contribute to GPIO interrupt B</description>
147011 <description>Pin contributes to GPIO interrupt B</description>
147018 <description>Interrupt B enable bits.</description>
147025 <description>Pin does not contribute to GPIO interrupt B</description>
147030 <description>Pin contributes to GPIO interrupt B</description>
147037 <description>Interrupt B enable bits.</description>
147044 <description>Pin does not contribute to GPIO interrupt B</description>
147049 <description>Pin contributes to GPIO interrupt B</description>
147056 <description>Interrupt B enable bits.</description>
147063 <description>Pin does not contribute to GPIO interrupt B</description>
147068 <description>Pin contributes to GPIO interrupt B</description>
147075 <description>Interrupt B enable bits.</description>
147082 <description>Pin does not contribute to GPIO interrupt B</description>
147087 <description>Pin contributes to GPIO interrupt B</description>
147094 <description>Interrupt B enable bits.</description>
147101 <description>Pin does not contribute to GPIO interrupt B</description>
147106 <description>Pin contributes to GPIO interrupt B</description>
147113 <description>Interrupt B enable bits.</description>
147120 <description>Pin does not contribute to GPIO interrupt B</description>
147125 <description>Pin contributes to GPIO interrupt B</description>
147132 <description>Interrupt B enable bits.</description>
147139 <description>Pin does not contribute to GPIO interrupt B</description>
147144 <description>Pin contributes to GPIO interrupt B</description>
147151 <description>Interrupt B enable bits.</description>
147158 <description>Pin does not contribute to GPIO interrupt B</description>
147163 <description>Pin contributes to GPIO interrupt B</description>
147170 <description>Interrupt B enable bits.</description>
147177 <description>Pin does not contribute to GPIO interrupt B</description>
147182 <description>Pin contributes to GPIO interrupt B</description>
147189 <description>Interrupt B enable bits.</description>
147196 <description>Pin does not contribute to GPIO interrupt B</description>
147201 <description>Pin contributes to GPIO interrupt B</description>
147210 <description>Interupt polarity control</description>
147219 <description>Polarity control for each pin</description>
147226 <description>High level or rising edge triggered</description>
147231 <description>Low level or falling edge triggered</description>
147238 <description>Polarity control for each pin</description>
147245 <description>High level or rising edge triggered</description>
147250 <description>Low level or falling edge triggered</description>
147257 <description>Polarity control for each pin</description>
147264 <description>High level or rising edge triggered</description>
147269 <description>Low level or falling edge triggered</description>
147276 <description>Polarity control for each pin</description>
147283 <description>High level or rising edge triggered</description>
147288 <description>Low level or falling edge triggered</description>
147295 <description>Polarity control for each pin</description>
147302 <description>High level or rising edge triggered</description>
147307 <description>Low level or falling edge triggered</description>
147314 <description>Polarity control for each pin</description>
147321 <description>High level or rising edge triggered</description>
147326 <description>Low level or falling edge triggered</description>
147333 <description>Polarity control for each pin</description>
147340 <description>High level or rising edge triggered</description>
147345 <description>Low level or falling edge triggered</description>
147352 <description>Polarity control for each pin</description>
147359 <description>High level or rising edge triggered</description>
147364 <description>Low level or falling edge triggered</description>
147371 <description>Polarity control for each pin</description>
147378 <description>High level or rising edge triggered</description>
147383 <description>Low level or falling edge triggered</description>
147390 <description>Polarity control for each pin</description>
147397 <description>High level or rising edge triggered</description>
147402 <description>Low level or falling edge triggered</description>
147409 <description>Polarity control for each pin</description>
147416 <description>High level or rising edge triggered</description>
147421 <description>Low level or falling edge triggered</description>
147428 <description>Polarity control for each pin</description>
147435 <description>High level or rising edge triggered</description>
147440 <description>Low level or falling edge triggered</description>
147447 <description>Polarity control for each pin</description>
147454 <description>High level or rising edge triggered</description>
147459 <description>Low level or falling edge triggered</description>
147466 <description>Polarity control for each pin</description>
147473 <description>High level or rising edge triggered</description>
147478 <description>Low level or falling edge triggered</description>
147485 <description>Polarity control for each pin</description>
147492 <description>High level or rising edge triggered</description>
147497 <description>Low level or falling edge triggered</description>
147504 <description>Polarity control for each pin</description>
147511 <description>High level or rising edge triggered</description>
147516 <description>Low level or falling edge triggered</description>
147523 <description>Polarity control for each pin</description>
147530 <description>High level or rising edge triggered</description>
147535 <description>Low level or falling edge triggered</description>
147542 <description>Polarity control for each pin</description>
147549 <description>High level or rising edge triggered</description>
147554 <description>Low level or falling edge triggered</description>
147561 <description>Polarity control for each pin</description>
147568 <description>High level or rising edge triggered</description>
147573 <description>Low level or falling edge triggered</description>
147580 <description>Polarity control for each pin</description>
147587 <description>High level or rising edge triggered</description>
147592 <description>Low level or falling edge triggered</description>
147599 <description>Polarity control for each pin</description>
147606 <description>High level or rising edge triggered</description>
147611 <description>Low level or falling edge triggered</description>
147618 <description>Polarity control for each pin</description>
147625 <description>High level or rising edge triggered</description>
147630 <description>Low level or falling edge triggered</description>
147637 <description>Polarity control for each pin</description>
147644 <description>High level or rising edge triggered</description>
147649 <description>Low level or falling edge triggered</description>
147656 <description>Polarity control for each pin</description>
147663 <description>High level or rising edge triggered</description>
147668 <description>Low level or falling edge triggered</description>
147675 <description>Polarity control for each pin</description>
147682 <description>High level or rising edge triggered</description>
147687 <description>Low level or falling edge triggered</description>
147694 <description>Polarity control for each pin</description>
147701 <description>High level or rising edge triggered</description>
147706 <description>Low level or falling edge triggered</description>
147713 <description>Polarity control for each pin</description>
147720 <description>High level or rising edge triggered</description>
147725 <description>Low level or falling edge triggered</description>
147732 <description>Polarity control for each pin</description>
147739 <description>High level or rising edge triggered</description>
147744 <description>Low level or falling edge triggered</description>
147751 <description>Polarity control for each pin</description>
147758 <description>High level or rising edge triggered</description>
147763 <description>Low level or falling edge triggered</description>
147770 <description>Polarity control for each pin</description>
147777 <description>High level or rising edge triggered</description>
147782 <description>Low level or falling edge triggered</description>
147789 <description>Polarity control for each pin</description>
147796 <description>High level or rising edge triggered</description>
147801 <description>Low level or falling edge triggered</description>
147808 <description>Polarity control for each pin</description>
147815 <description>High level or rising edge triggered</description>
147820 <description>Low level or falling edge triggered</description>
147829 <description>Interrupt edge select</description>
147838 <description>Edge or level mode select bits.</description>
147845 <description>Level mode</description>
147850 <description>Edge mode</description>
147857 <description>Edge or level mode select bits.</description>
147864 <description>Level mode</description>
147869 <description>Edge mode</description>
147876 <description>Edge or level mode select bits.</description>
147883 <description>Level mode</description>
147888 <description>Edge mode</description>
147895 <description>Edge or level mode select bits.</description>
147902 <description>Level mode</description>
147907 <description>Edge mode</description>
147914 <description>Edge or level mode select bits.</description>
147921 <description>Level mode</description>
147926 <description>Edge mode</description>
147933 <description>Edge or level mode select bits.</description>
147940 <description>Level mode</description>
147945 <description>Edge mode</description>
147952 <description>Edge or level mode select bits.</description>
147959 <description>Level mode</description>
147964 <description>Edge mode</description>
147971 <description>Edge or level mode select bits.</description>
147978 <description>Level mode</description>
147983 <description>Edge mode</description>
147990 <description>Edge or level mode select bits.</description>
147997 <description>Level mode</description>
148002 <description>Edge mode</description>
148009 <description>Edge or level mode select bits.</description>
148016 <description>Level mode</description>
148021 <description>Edge mode</description>
148028 <description>Edge or level mode select bits.</description>
148035 <description>Level mode</description>
148040 <description>Edge mode</description>
148047 <description>Edge or level mode select bits.</description>
148054 <description>Level mode</description>
148059 <description>Edge mode</description>
148066 <description>Edge or level mode select bits.</description>
148073 <description>Level mode</description>
148078 <description>Edge mode</description>
148085 <description>Edge or level mode select bits.</description>
148092 <description>Level mode</description>
148097 <description>Edge mode</description>
148104 <description>Edge or level mode select bits.</description>
148111 <description>Level mode</description>
148116 <description>Edge mode</description>
148123 <description>Edge or level mode select bits.</description>
148130 <description>Level mode</description>
148135 <description>Edge mode</description>
148142 <description>Edge or level mode select bits.</description>
148149 <description>Level mode</description>
148154 <description>Edge mode</description>
148161 <description>Edge or level mode select bits.</description>
148168 <description>Level mode</description>
148173 <description>Edge mode</description>
148180 <description>Edge or level mode select bits.</description>
148187 <description>Level mode</description>
148192 <description>Edge mode</description>
148199 <description>Edge or level mode select bits.</description>
148206 <description>Level mode</description>
148211 <description>Edge mode</description>
148218 <description>Edge or level mode select bits.</description>
148225 <description>Level mode</description>
148230 <description>Edge mode</description>
148237 <description>Edge or level mode select bits.</description>
148244 <description>Level mode</description>
148249 <description>Edge mode</description>
148256 <description>Edge or level mode select bits.</description>
148263 <description>Level mode</description>
148268 <description>Edge mode</description>
148275 <description>Edge or level mode select bits.</description>
148282 <description>Level mode</description>
148287 <description>Edge mode</description>
148294 <description>Edge or level mode select bits.</description>
148301 <description>Level mode</description>
148306 <description>Edge mode</description>
148313 <description>Edge or level mode select bits.</description>
148320 <description>Level mode</description>
148325 <description>Edge mode</description>
148332 <description>Edge or level mode select bits.</description>
148339 <description>Level mode</description>
148344 <description>Edge mode</description>
148351 <description>Edge or level mode select bits.</description>
148358 <description>Level mode</description>
148363 <description>Edge mode</description>
148370 <description>Edge or level mode select bits.</description>
148377 <description>Level mode</description>
148382 <description>Edge mode</description>
148389 <description>Edge or level mode select bits.</description>
148396 <description>Level mode</description>
148401 <description>Edge mode</description>
148408 <description>Edge or level mode select bits.</description>
148415 <description>Level mode</description>
148420 <description>Edge mode</description>
148427 <description>Edge or level mode select bits.</description>
148434 <description>Level mode</description>
148439 <description>Edge mode</description>
148448 <description>Interrupt status for interrupt A</description>
148457 <description>Interrupt status.</description>
148467 <description>Interrupt status for interrupt B</description>
148476 <description>Interrupt status</description>
148488 <description>AHBSC</description>
148501 <description>AHB Slave Port 0 Rule</description>
148510 <description>Rule 0</description>
148517 <description>Non-secure and non-privilege user access allowed</description>
148522 <description>Non-secure and privilege access allowed</description>
148527 <description>Secure and non-privilege user access allowed</description>
148532 <description>Secure and privilege user access allowed</description>
148539 <description>Rule 1</description>
148546 <description>Non-secure and non-privilege user access allowed</description>
148551 <description>Non-secure and privilege access allowed</description>
148556 <description>Secure and non-privilege user access allowed</description>
148561 <description>Secure and privilege user access allowed</description>
148568 <description>Rule 2</description>
148575 <description>Non-secure and non-privilege user access allowed</description>
148580 <description>Non-secure and privilege access allowed</description>
148585 <description>Secure and non-privilege user access allowed</description>
148590 <description>Secure and privilege user access allowed</description>
148597 <description>Rule 3</description>
148604 <description>Non-secure and non-privilege user access allowed</description>
148609 <description>Non-secure and privilege access allowed</description>
148614 <description>Secure and non-privilege user access allowed</description>
148619 <description>Secure and privilege user access allowed</description>
148626 <description>Rule 4</description>
148633 <description>Non-secure and non-privilege user access allowed</description>
148638 <description>Non-secure and privilege access allowed</description>
148643 <description>Secure and non-privilege user access allowed</description>
148648 <description>Secure and privilege user access allowed</description>
148655 <description>Rule 5</description>
148662 <description>Non-secure and non-privilege user access allowed</description>
148667 <description>Non-secure and privilege access allowed</description>
148672 <description>Secure and non-privilege user access allowed</description>
148677 <description>Secure and privilege user access allowed</description>
148684 <description>Rule 6</description>
148691 <description>Non-secure and non-privilege user access allowed</description>
148696 <description>Non-secure and privilege access allowed</description>
148701 <description>Secure and non-privilege user access allowed</description>
148706 <description>Secure and privilege user access allowed</description>
148713 <description>Rule 7</description>
148720 <description>Non-secure and non-privilege user access allowed</description>
148725 <description>Non-secure and privilege access allowed</description>
148730 <description>Secure and non-privilege user access allowed</description>
148735 <description>Secure and privilege user access allowed</description>
148746 <description>Flash Memory Rule</description>
148755 <description>Rule 0</description>
148762 <description>Non-secure and non-privilege user access allowed</description>
148767 <description>Non-secure and privilege access allowed</description>
148772 <description>Secure and non-privilege user access allowed</description>
148777 <description>Secure and privilege user access allowed</description>
148784 <description>Rule 1</description>
148791 <description>Non-secure and non-privilege user access allowed</description>
148796 <description>Non-secure and privilege access allowed</description>
148801 <description>Secure and non-privilege user access allowed</description>
148806 <description>Secure and privilege user access allowed</description>
148813 <description>Rule 2</description>
148820 <description>Non-secure and non-privilege user access allowed</description>
148825 <description>Non-secure and privilege access allowed</description>
148830 <description>Secure and non-privilege user access allowed</description>
148835 <description>Secure and privilege user access allowed</description>
148842 <description>Rule 3</description>
148849 <description>Non-secure and non-privilege user access allowed</description>
148854 <description>Non-secure and privilege access allowed</description>
148859 <description>Secure and non-privilege user access allowed</description>
148864 <description>Secure and privilege user access allowed</description>
148871 <description>Rule 4</description>
148878 <description>Non-secure and non-privilege user access allowed</description>
148883 <description>Non-secure and privilege access allowed</description>
148888 <description>Secure and non-privilege user access allowed</description>
148893 <description>Secure and privilege user access allowed</description>
148900 <description>Rule 5</description>
148907 <description>Non-secure and non-privilege user access allowed</description>
148912 <description>Non-secure and privilege access allowed</description>
148917 <description>Secure and non-privilege user access allowed</description>
148922 <description>Secure and privilege user access allowed</description>
148929 <description>Rule 6</description>
148936 <description>Non-secure and non-privilege user access allowed</description>
148941 <description>Non-secure and privilege access allowed</description>
148946 <description>Secure and non-privilege user access allowed</description>
148951 <description>Secure and privilege user access allowed</description>
148958 <description>Rule 7</description>
148965 <description>Non-secure and non-privilege user access allowed</description>
148970 <description>Non-secure and privilege access allowed</description>
148975 <description>Secure and non-privilege user access allowed</description>
148980 <description>Secure and privilege user access allowed</description>
148991 <description>ROM Memory Rule</description>
149000 <description>Rule 0</description>
149007 <description>Non-secure and non-privilege user access allowed</description>
149012 <description>Non-secure and privilege access allowed</description>
149017 <description>Secure and non-privilege user access allowed</description>
149022 <description>Secure and privilege user access allowed</description>
149029 <description>Rule 1</description>
149036 <description>Non-secure and non-privilege user access allowed</description>
149041 <description>Non-secure and privilege access allowed</description>
149046 <description>Secure and non-privilege user access allowed</description>
149051 <description>Secure and privilege user access allowed</description>
149058 <description>Rule 2</description>
149065 <description>Non-secure and non-privilege user access allowed</description>
149070 <description>Non-secure and privilege access allowed</description>
149075 <description>Secure and non-privilege user access allowed</description>
149080 <description>Secure and privilege user access allowed</description>
149087 <description>Rule 3</description>
149094 <description>Non-secure and non-privilege user access allowed</description>
149099 <description>Non-secure and privilege access allowed</description>
149104 <description>Secure and non-privilege user access allowed</description>
149109 <description>Secure and privilege user access allowed</description>
149116 <description>Rule 4</description>
149123 <description>Non-secure and non-privilege user access allowed</description>
149128 <description>Non-secure and privilege access allowed</description>
149133 <description>Secure and non-privilege user access allowed</description>
149138 <description>Secure and privilege user access allowed</description>
149145 <description>Rule 5</description>
149152 <description>Non-secure and non-privilege user access allowed</description>
149157 <description>Non-secure and privilege access allowed</description>
149162 <description>Secure and non-privilege user access allowed</description>
149167 <description>Secure and privilege user access allowed</description>
149174 <description>Rule 6</description>
149181 <description>Non-secure and non-privilege user access allowed</description>
149186 <description>Non-secure and privilege access allowed</description>
149191 <description>Secure and non-privilege user access allowed</description>
149196 <description>Secure and privilege user access allowed</description>
149203 <description>Rule 7</description>
149210 <description>Non-secure and non-privilege user access allowed</description>
149215 <description>Non-secure and privilege access allowed</description>
149220 <description>Secure and non-privilege user access allowed</description>
149225 <description>Secure and privilege user access allowed</description>
149236 <description>AHB Slave Port 1 Rule</description>
149245 <description>Rule 0</description>
149252 <description>Non-secure and non-privilege user access allowed</description>
149257 <description>Non-secure and privilege access allowed</description>
149262 <description>Secure and non-privilege user access allowed</description>
149267 <description>Secure and privilege user access allowed</description>
149274 <description>Rule 1</description>
149281 <description>Non-secure and non-privilege user access allowed</description>
149286 <description>Non-secure and privilege access allowed</description>
149291 <description>Secure and non-privilege user access allowed</description>
149296 <description>Secure and privilege user access allowed</description>
149303 <description>Rule 2</description>
149310 <description>Non-secure and non-privilege user access allowed</description>
149315 <description>Non-secure and privilege access allowed</description>
149320 <description>Secure and non-privilege user access allowed</description>
149325 <description>Secure and privilege user access allowed</description>
149332 <description>Rule 3</description>
149339 <description>Non-secure and non-privilege user access allowed</description>
149344 <description>Non-secure and privilege access allowed</description>
149349 <description>Secure and non-privilege user access allowed</description>
149354 <description>Secure and privilege user access allowed</description>
149361 <description>Rule 4</description>
149368 <description>Non-secure and non-privilege user access allowed</description>
149373 <description>Non-secure and privilege access allowed</description>
149378 <description>Secure and non-privilege user access allowed</description>
149383 <description>Secure and privilege user access allowed</description>
149390 <description>Rule 5</description>
149397 <description>Non-secure and non-privilege user access allowed</description>
149402 <description>Non-secure and privilege access allowed</description>
149407 <description>Secure and non-privilege user access allowed</description>
149412 <description>Secure and privilege user access allowed</description>
149419 <description>Rule 6</description>
149426 <description>Non-secure and non-privilege user access allowed</description>
149431 <description>Non-secure and privilege access allowed</description>
149436 <description>Secure and non-privilege user access allowed</description>
149441 <description>Secure and privilege user access allowed</description>
149448 <description>Rule 7</description>
149455 <description>Non-secure and non-privilege user access allowed</description>
149460 <description>Non-secure and privilege access allowed</description>
149465 <description>Secure and non-privilege user access allowed</description>
149470 <description>Secure and privilege user access allowed</description>
149479 <description>RAMX Memory Rule 0</description>
149488 <description>Rule 0</description>
149495 <description>Non-secure and non-privilege user access allowed</description>
149500 <description>Non-secure and privilege access allowed</description>
149505 <description>Secure and non-privilege user access allowed</description>
149510 <description>Secure and privilege user access allowed</description>
149517 <description>Rule 1</description>
149524 <description>Non-secure and non-privilege user access allowed</description>
149529 <description>Non-secure and privilege access allowed</description>
149534 <description>Secure and non-privilege user access allowed</description>
149539 <description>Secure and privilege user access allowed</description>
149546 <description>Rule 2</description>
149553 <description>Non-secure and non-privilege user access allowed</description>
149558 <description>Non-secure and privilege access allowed</description>
149563 <description>Secure and non-privilege user access allowed</description>
149568 <description>Secure and privilege user access allowed</description>
149575 <description>Rule 3</description>
149582 <description>Non-secure and non-privilege user access allowed</description>
149587 <description>Non-secure and privilege access allowed</description>
149592 <description>Secure and non-privilege user access allowed</description>
149597 <description>Secure and privilege user access allowed</description>
149608 <description>AHB Slave Port 2 Rule</description>
149617 <description>Rule 0</description>
149624 <description>Non-secure and non-privilege user access allowed</description>
149629 <description>Non-secure and privilege access allowed</description>
149634 <description>Secure and non-privilege user access allowed</description>
149639 <description>Secure and privilege user access allowed</description>
149646 <description>Rule 1</description>
149653 <description>Non-secure and non-privilege user access allowed</description>
149658 <description>Non-secure and privilege access allowed</description>
149663 <description>Secure and non-privilege user access allowed</description>
149668 <description>Secure and privilege user access allowed</description>
149675 <description>Rule 2</description>
149682 <description>Non-secure and non-privilege user access allowed</description>
149687 <description>Non-secure and privilege access allowed</description>
149692 <description>Secure and non-privilege user access allowed</description>
149697 <description>Secure and privilege user access allowed</description>
149704 <description>Rule 3</description>
149711 <description>Non-secure and non-privilege user access allowed</description>
149716 <description>Non-secure and privilege access allowed</description>
149721 <description>Secure and non-privilege user access allowed</description>
149726 <description>Secure and privilege user access allowed</description>
149733 <description>Rule 4</description>
149740 <description>Non-secure and non-privilege user access allowed</description>
149745 <description>Non-secure and privilege access allowed</description>
149750 <description>Secure and non-privilege user access allowed</description>
149755 <description>Secure and privilege user access allowed</description>
149762 <description>Rule 5</description>
149769 <description>Non-secure and non-privilege user access allowed</description>
149774 <description>Non-secure and privilege access allowed</description>
149779 <description>Secure and non-privilege user access allowed</description>
149784 <description>Secure and privilege user access allowed</description>
149791 <description>Rule 6</description>
149798 <description>Non-secure and non-privilege user access allowed</description>
149803 <description>Non-secure and privilege access allowed</description>
149808 <description>Secure and non-privilege user access allowed</description>
149813 <description>Secure and privilege user access allowed</description>
149820 <description>Rule 7</description>
149827 <description>Non-secure and non-privilege user access allowed</description>
149832 <description>Non-secure and privilege access allowed</description>
149837 <description>Secure and non-privilege user access allowed</description>
149842 <description>Secure and privilege user access allowed</description>
149853 <description>FLEXSPI0 Region 0 Memory Rule</description>
149862 <description>Rule 0</description>
149869 <description>Non-secure and non-privilege user access allowed</description>
149874 <description>Non-secure and privilege access allowed</description>
149879 <description>Secure and non-privilege user access allowed</description>
149884 <description>Secure and privilege user access allowed</description>
149891 <description>Rule 1</description>
149898 <description>Non-secure and non-privilege user access allowed</description>
149903 <description>Non-secure and privilege access allowed</description>
149908 <description>Secure and non-privilege user access allowed</description>
149913 <description>Secure and privilege user access allowed</description>
149920 <description>Rule 2</description>
149927 <description>Non-secure and non-privilege user access allowed</description>
149932 <description>Non-secure and privilege access allowed</description>
149937 <description>Secure and non-privilege user access allowed</description>
149942 <description>Secure and privilege user access allowed</description>
149949 <description>Rule 3</description>
149956 <description>Non-secure and non-privilege user access allowed</description>
149961 <description>Non-secure and privilege access allowed</description>
149966 <description>Secure and non-privilege user access allowed</description>
149971 <description>Secure and privilege user access allowed</description>
149978 <description>Rule 4</description>
149985 <description>Non-secure and non-privilege user access allowed</description>
149990 <description>Non-secure and privilege access allowed</description>
149995 <description>Secure and non-privilege user access allowed</description>
150000 <description>Secure and privilege user access allowed</description>
150007 <description>Rule 5</description>
150014 <description>Non-secure and non-privilege user access allowed</description>
150019 <description>Non-secure and privilege access allowed</description>
150024 <description>Secure and non-privilege user access allowed</description>
150029 <description>Secure and privilege user access allowed</description>
150036 <description>Rule 6</description>
150043 <description>Non-secure and non-privilege user access allowed</description>
150048 <description>Non-secure and privilege access allowed</description>
150053 <description>Secure and non-privilege user access allowed</description>
150058 <description>Secure and privilege user access allowed</description>
150065 <description>Rule 7</description>
150072 <description>Non-secure and non-privilege user access allowed</description>
150077 <description>Non-secure and privilege access allowed</description>
150082 <description>Secure and non-privilege user access allowed</description>
150087 <description>Secure and privilege user access allowed</description>
150098 <description>no description available</description>
150102 <description>FLEXSPI0 Region index Memory Rule 0</description>
150111 <description>Rule 0</description>
150118 <description>Non-secure and non-privilege user access allowed</description>
150123 <description>Non-secure and privilege access allowed</description>
150128 <description>Secure and non-privilege user access allowed</description>
150133 <description>Secure and privilege user access allowed</description>
150140 <description>Rule 1</description>
150147 <description>Non-secure and non-privilege user access allowed</description>
150152 <description>Non-secure and privilege access allowed</description>
150157 <description>Secure and non-privilege user access allowed</description>
150162 <description>Secure and privilege user access allowed</description>
150169 <description>Rule 2</description>
150176 <description>Non-secure and non-privilege user access allowed</description>
150181 <description>Non-secure and privilege access allowed</description>
150186 <description>Secure and non-privilege user access allowed</description>
150191 <description>Secure and privilege user access allowed</description>
150198 <description>Rule 3</description>
150205 <description>Non-secure and non-privilege user access allowed</description>
150210 <description>Non-secure and privilege access allowed</description>
150215 <description>Secure and non-privilege user access allowed</description>
150220 <description>Secure and privilege user access allowed</description>
150230 <description>RAM0 Slave Rule</description>
150239 <description>RAM0 Rule</description>
150246 <description>Non-secure and non-privilege user access allowed</description>
150251 <description>Non-secure and privilege access allowed</description>
150256 <description>Secure and non-privilege user access allowed</description>
150261 <description>Secure and privilege user access allowed</description>
150270 <description>SRAM0 Partition 0 Memory Rule</description>
150279 <description>Rule 0</description>
150286 <description>Non-secure and non-privilege user access allowed</description>
150291 <description>Non-secure and privilege access allowed</description>
150296 <description>Secure and non-privilege user access allowed</description>
150301 <description>Secure and privilege user access allowed</description>
150308 <description>Rule 1</description>
150315 <description>Non-secure and non-privilege user access allowed</description>
150320 <description>Non-secure and privilege access allowed</description>
150325 <description>Secure and non-privilege user access allowed</description>
150330 <description>Secure and privilege user access allowed</description>
150337 <description>Rule 2</description>
150344 <description>Non-secure and non-privilege user access allowed</description>
150349 <description>Non-secure and privilege access allowed</description>
150354 <description>Secure and non-privilege user access allowed</description>
150359 <description>Secure and privilege user access allowed</description>
150366 <description>Rule 3</description>
150373 <description>Non-secure and non-privilege user access allowed</description>
150378 <description>Non-secure and privilege access allowed</description>
150383 <description>Secure and non-privilege user access allowed</description>
150388 <description>Secure and privilege user access allowed</description>
150395 <description>Rule 4</description>
150402 <description>Non-secure and non-privilege user access allowed</description>
150407 <description>Non-secure and privilege access allowed</description>
150412 <description>Secure and non-privilege user access allowed</description>
150417 <description>Secure and privilege user access allowed</description>
150424 <description>Rule 5</description>
150431 <description>Non-secure and non-privilege user access allowed</description>
150436 <description>Non-secure and privilege access allowed</description>
150441 <description>Secure and non-privilege user access allowed</description>
150446 <description>Secure and privilege user access allowed</description>
150453 <description>Rule 6</description>
150460 <description>Non-secure and non-privilege user access allowed</description>
150465 <description>Non-secure and privilege access allowed</description>
150470 <description>Secure and non-privilege user access allowed</description>
150475 <description>Secure and privilege user access allowed</description>
150482 <description>Rule 7</description>
150489 <description>Non-secure and non-privilege user access allowed</description>
150494 <description>Non-secure and privilege access allowed</description>
150499 <description>Secure and non-privilege user access allowed</description>
150504 <description>Secure and privilege user access allowed</description>
150513 <description>RAM1 Slave Rule</description>
150522 <description>RAM1 Rule</description>
150529 <description>Non-secure and non-privilege user access allowed</description>
150534 <description>Non-secure and privilege access allowed</description>
150539 <description>Secure and non-privilege user access allowed</description>
150544 <description>Secure and privilege user access allowed</description>
150553 <description>SRAM1 Partition 0 Memory Rule</description>
150562 <description>Rule 0</description>
150569 <description>Non-secure and non-privilege user access allowed</description>
150574 <description>Non-secure and privilege access allowed</description>
150579 <description>Secure and non-privilege user access allowed</description>
150584 <description>Secure and privilege user access allowed</description>
150591 <description>Rule 1</description>
150598 <description>Non-secure and non-privilege user access allowed</description>
150603 <description>Non-secure and privilege access allowed</description>
150608 <description>Secure and non-privilege user access allowed</description>
150613 <description>Secure and privilege user access allowed</description>
150620 <description>Rule 2</description>
150627 <description>Non-secure and non-privilege user access allowed</description>
150632 <description>Non-secure and privilege access allowed</description>
150637 <description>Secure and non-privilege user access allowed</description>
150642 <description>Secure and privilege user access allowed</description>
150649 <description>Rule 3</description>
150656 <description>Non-secure and non-privilege user access allowed</description>
150661 <description>Non-secure and privilege access allowed</description>
150666 <description>Secure and non-privilege user access allowed</description>
150671 <description>Secure and privilege user access allowed</description>
150678 <description>Rule 4</description>
150685 <description>Non-secure and non-privilege user access allowed</description>
150690 <description>Non-secure and privilege access allowed</description>
150695 <description>Secure and non-privilege user access allowed</description>
150700 <description>Secure and privilege user access allowed</description>
150707 <description>Rule 5</description>
150714 <description>Non-secure and non-privilege user access allowed</description>
150719 <description>Non-secure and privilege access allowed</description>
150724 <description>Secure and non-privilege user access allowed</description>
150729 <description>Secure and privilege user access allowed</description>
150736 <description>Rule 6</description>
150743 <description>Non-secure and non-privilege user access allowed</description>
150748 <description>Non-secure and privilege access allowed</description>
150753 <description>Secure and non-privilege user access allowed</description>
150758 <description>Secure and privilege user access allowed</description>
150765 <description>Rule 7</description>
150772 <description>Non-secure and non-privilege user access allowed</description>
150777 <description>Non-secure and privilege access allowed</description>
150782 <description>Secure and non-privilege user access allowed</description>
150787 <description>Secure and privilege user access allowed</description>
150796 <description>RAM2 Slave Rule</description>
150805 <description>RAM2 Rule</description>
150812 <description>Non-secure and non-privilege user access allowed</description>
150817 <description>Non-secure and privilege access allowed</description>
150822 <description>Secure and non-privilege user access allowed</description>
150827 <description>Secure and privilege user access allowed</description>
150836 <description>SRAM2 Partition 0 Memory Rule</description>
150845 <description>Rule 0</description>
150852 <description>Non-secure and non-privilege user access allowed</description>
150857 <description>Non-secure and privilege access allowed</description>
150862 <description>Secure and non-privilege user access allowed</description>
150867 <description>Secure and privilege user access allowed</description>
150874 <description>Rule 1</description>
150881 <description>Non-secure and non-privilege user access allowed</description>
150886 <description>Non-secure and privilege access allowed</description>
150891 <description>Secure and non-privilege user access allowed</description>
150896 <description>Secure and privilege user access allowed</description>
150903 <description>Rule 2</description>
150910 <description>Non-secure and non-privilege user access allowed</description>
150915 <description>Non-secure and privilege access allowed</description>
150920 <description>Secure and non-privilege user access allowed</description>
150925 <description>Secure and privilege user access allowed</description>
150932 <description>Rule 3</description>
150939 <description>Non-secure and non-privilege user access allowed</description>
150944 <description>Non-secure and privilege access allowed</description>
150949 <description>Secure and non-privilege user access allowed</description>
150954 <description>Secure and privilege user access allowed</description>
150961 <description>Rule 4</description>
150968 <description>Non-secure and non-privilege user access allowed</description>
150973 <description>Non-secure and privilege access allowed</description>
150978 <description>Secure and non-privilege user access allowed</description>
150983 <description>Secure and privilege user access allowed</description>
150990 <description>Rule 5</description>
150997 <description>Non-secure and non-privilege user access allowed</description>
151002 <description>Non-secure and privilege access allowed</description>
151007 <description>Secure and non-privilege user access allowed</description>
151012 <description>Secure and privilege user access allowed</description>
151019 <description>Rule 6</description>
151026 <description>Non-secure and non-privilege user access allowed</description>
151031 <description>Non-secure and privilege access allowed</description>
151036 <description>Secure and non-privilege user access allowed</description>
151041 <description>Secure and privilege user access allowed</description>
151048 <description>Rule 7</description>
151055 <description>Non-secure and non-privilege user access allowed</description>
151060 <description>Non-secure and privilege access allowed</description>
151065 <description>Secure and non-privilege user access allowed</description>
151070 <description>Secure and privilege user access allowed</description>
151079 <description>RAM3 Slave Rule</description>
151088 <description>RAM3 Rule</description>
151095 <description>Non-secure and non-privilege user access allowed</description>
151100 <description>Non-secure and privilege access allowed</description>
151105 <description>Secure and non-privilege user access allowed</description>
151110 <description>Secure and privilege user access allowed</description>
151119 <description>SRAM Partition 0 Memory Rule</description>
151128 <description>Rule 0</description>
151135 <description>Non-secure and non-privilege user access allowed</description>
151140 <description>Non-secure and privilege access allowed</description>
151145 <description>Secure and non-privilege user access allowed</description>
151150 <description>Secure and privilege user access allowed</description>
151157 <description>Rule 1</description>
151164 <description>Non-secure and non-privilege user access allowed</description>
151169 <description>Non-secure and privilege access allowed</description>
151174 <description>Secure and non-privilege user access allowed</description>
151179 <description>Secure and privilege user access allowed</description>
151186 <description>Rule 2</description>
151193 <description>Non-secure and non-privilege user access allowed</description>
151198 <description>Non-secure and privilege access allowed</description>
151203 <description>Secure and non-privilege user access allowed</description>
151208 <description>Secure and privilege user access allowed</description>
151215 <description>Rule 3</description>
151222 <description>Non-secure and non-privilege user access allowed</description>
151227 <description>Non-secure and privilege access allowed</description>
151232 <description>Secure and non-privilege user access allowed</description>
151237 <description>Secure and privilege user access allowed</description>
151244 <description>Rule 4</description>
151251 <description>Non-secure and non-privilege user access allowed</description>
151256 <description>Non-secure and privilege access allowed</description>
151261 <description>Secure and non-privilege user access allowed</description>
151266 <description>Secure and privilege user access allowed</description>
151273 <description>Rule 5</description>
151280 <description>Non-secure and non-privilege user access allowed</description>
151285 <description>Non-secure and privilege access allowed</description>
151290 <description>Secure and non-privilege user access allowed</description>
151295 <description>Secure and privilege user access allowed</description>
151302 <description>Rule 6</description>
151309 <description>Non-secure and non-privilege user access allowed</description>
151314 <description>Non-secure and privilege access allowed</description>
151319 <description>Secure and non-privilege user access allowed</description>
151324 <description>Secure and privilege user access allowed</description>
151331 <description>Rule 7</description>
151338 <description>Non-secure and non-privilege user access allowed</description>
151343 <description>Non-secure and privilege access allowed</description>
151348 <description>Secure and non-privilege user access allowed</description>
151353 <description>Secure and privilege user access allowed</description>
151362 <description>RAM4 Slave Rule</description>
151371 <description>RAM4 Rule</description>
151378 <description>Non-secure and non-privilege user access allowed</description>
151383 <description>Non-secure and privilege access allowed</description>
151388 <description>Secure and non-privilege user access allowed</description>
151393 <description>Secure and privilege user access allowed</description>
151402 <description>SRAM4 Partition 0 Memory Rule</description>
151411 <description>Rule 0</description>
151418 <description>Non-secure and non-privilege user access allowed</description>
151423 <description>Non-secure and privilege access allowed</description>
151428 <description>Secure and non-privilege user access allowed</description>
151433 <description>Secure and privilege user access allowed</description>
151440 <description>Rule 1</description>
151447 <description>Non-secure and non-privilege user access allowed</description>
151452 <description>Non-secure and privilege access allowed</description>
151457 <description>Secure and non-privilege user access allowed</description>
151462 <description>Secure and privilege user access allowed</description>
151469 <description>Rule 2</description>
151476 <description>Non-secure and non-privilege user access allowed</description>
151481 <description>Non-secure and privilege access allowed</description>
151486 <description>Secure and non-privilege user access allowed</description>
151491 <description>Secure and privilege user access allowed</description>
151498 <description>Rule 3</description>
151505 <description>Non-secure and non-privilege user access allowed</description>
151510 <description>Non-secure and privilege access allowed</description>
151515 <description>Secure and non-privilege user access allowed</description>
151520 <description>Secure and privilege user access allowed</description>
151527 <description>Rule 4</description>
151534 <description>Non-secure and non-privilege user access allowed</description>
151539 <description>Non-secure and privilege access allowed</description>
151544 <description>Secure and non-privilege user access allowed</description>
151549 <description>Secure and privilege user access allowed</description>
151556 <description>Rule 5</description>
151563 <description>Non-secure and non-privilege user access allowed</description>
151568 <description>Non-secure and privilege access allowed</description>
151573 <description>Secure and non-privilege user access allowed</description>
151578 <description>Secure and privilege user access allowed</description>
151585 <description>Rule 6</description>
151592 <description>Non-secure and non-privilege user access allowed</description>
151597 <description>Non-secure and privilege access allowed</description>
151602 <description>Secure and non-privilege user access allowed</description>
151607 <description>Secure and privilege user access allowed</description>
151614 <description>Rule 7</description>
151621 <description>Non-secure and non-privilege user access allowed</description>
151626 <description>Non-secure and privilege access allowed</description>
151631 <description>Secure and non-privilege user access allowed</description>
151636 <description>Secure and privilege user access allowed</description>
151647 <description>APB Slave Port 8 Rule</description>
151656 <description>Rule 0</description>
151663 <description>Non-secure and non-privilege user access allowed</description>
151668 <description>Non-secure and privilege access allowed</description>
151673 <description>Secure and non-privilege user access allowed</description>
151678 <description>Secure and privilege user access allowed</description>
151685 <description>Rule 1</description>
151692 <description>Non-secure and non-privilege user access allowed</description>
151697 <description>Non-secure and privilege access allowed</description>
151702 <description>Secure and non-privilege user access allowed</description>
151707 <description>Secure and privilege user access allowed</description>
151714 <description>Rule 2</description>
151721 <description>Non-secure and non-privilege user access allowed</description>
151726 <description>Non-secure and privilege access allowed</description>
151731 <description>Secure and non-privilege user access allowed</description>
151736 <description>Secure and privilege user access allowed</description>
151743 <description>Rule 3</description>
151750 <description>Non-secure and non-privilege user access allowed</description>
151755 <description>Non-secure and privilege access allowed</description>
151760 <description>Secure and non-privilege user access allowed</description>
151765 <description>Secure and privilege user access allowed</description>
151772 <description>Rule 4</description>
151779 <description>Non-secure and non-privilege user access allowed</description>
151784 <description>Non-secure and privilege access allowed</description>
151789 <description>Secure and non-privilege user access allowed</description>
151794 <description>Secure and privilege user access allowed</description>
151801 <description>Rule 5</description>
151808 <description>Non-secure and non-privilege user access allowed</description>
151813 <description>Non-secure and privilege access allowed</description>
151818 <description>Secure and non-privilege user access allowed</description>
151823 <description>Secure and privilege user access allowed</description>
151830 <description>Rule 6</description>
151837 <description>Non-secure and non-privilege user access allowed</description>
151842 <description>Non-secure and privilege access allowed</description>
151847 <description>Secure and non-privilege user access allowed</description>
151852 <description>Secure and privilege user access allowed</description>
151859 <description>Rule 7</description>
151866 <description>Non-secure and non-privilege user access allowed</description>
151871 <description>Non-secure and privilege access allowed</description>
151876 <description>Secure and non-privilege user access allowed</description>
151881 <description>Secure and privilege user access allowed</description>
151890 <description>APB Bridge Group 0 Memory Rule 0</description>
151899 <description>SYSCON</description>
151906 <description>Non-secure and non-privilege user access allowed</description>
151911 <description>Non-secure and privilege access allowed</description>
151916 <description>Secure and non-privilege user access allowed</description>
151921 <description>Secure and privilege user access allowed</description>
151928 <description>IOCON</description>
151935 <description>Non-secure and non-privilege user access allowed</description>
151940 <description>Non-secure and privilege access allowed</description>
151945 <description>Secure and non-privilege user access allowed</description>
151950 <description>Secure and privilege user access allowed</description>
151957 <description>GPIO0</description>
151964 <description>Non-secure and non-privilege user access allowed</description>
151969 <description>Non-secure and privilege access allowed</description>
151974 <description>Secure and non-privilege user access allowed</description>
151979 <description>Secure and privilege user access allowed</description>
151986 <description>GPIO1</description>
151993 <description>Non-secure and non-privilege user access allowed</description>
151998 <description>Non-secure and privilege access allowed</description>
152003 <description>Secure and non-privilege user access allowed</description>
152008 <description>Secure and privilege user access allowed</description>
152015 <description>PINT0</description>
152022 <description>Non-secure and non-privilege user access allowed</description>
152027 <description>Non-secure and privilege access allowed</description>
152032 <description>Secure and non-privilege user access allowed</description>
152037 <description>Secure and privilege user access allowed</description>
152044 <description>Rule 5</description>
152051 <description>Non-secure and non-privilege user access allowed</description>
152056 <description>Non-secure and privilege access allowed</description>
152061 <description>Secure and non-privilege user access allowed</description>
152066 <description>Secure and privilege user access allowed</description>
152073 <description>GINT1</description>
152080 <description>Non-secure and non-privilege user access allowed</description>
152085 <description>Non-secure and privilege access allowed</description>
152090 <description>Secure and non-privilege user access allowed</description>
152095 <description>Secure and privilege user access allowed</description>
152104 <description>APB Bridge Group 0 Memory Rule 1</description>
152113 <description>CTIMER0</description>
152121 <description>Non-secure and non-privilege user access allowed</description>
152126 <description>Non-secure and privilege access allowed</description>
152131 <description>Secure and non-privilege user access allowed</description>
152136 <description>Secure and privilege user access allowed</description>
152143 <description>CTIMER 1</description>
152151 <description>Non-secure and non-privilege user access allowed</description>
152156 <description>Non-secure and privilege access allowed</description>
152161 <description>Secure and non-privilege user access allowed</description>
152166 <description>Secure and privilege user access allowed</description>
152173 <description>WWDT0</description>
152180 <description>Non-secure and non-privilege user access allowed</description>
152185 <description>Non-secure and privilege access allowed</description>
152190 <description>Secure and non-privilege user access allowed</description>
152195 <description>Secure and privilege user access allowed</description>
152202 <description>MRT0</description>
152209 <description>Non-secure and non-privilege user access allowed</description>
152214 <description>Non-secure and privilege access allowed</description>
152219 <description>Secure and non-privilege user access allowed</description>
152224 <description>Secure and privilege user access allowed</description>
152231 <description>MICRO_TICK</description>
152238 <description>Non-secure and non-privilege user access allowed</description>
152243 <description>Non-secure and privilege access allowed</description>
152248 <description>Secure and non-privilege user access allowed</description>
152253 <description>Secure and privilege user access allowed</description>
152260 <description>ITRC</description>
152267 <description>Non-secure and non-privilege user access allowed</description>
152272 <description>Non-secure and privilege access allowed</description>
152277 <description>Secure and non-privilege user access allowed</description>
152282 <description>Secure and privilege user access allowed</description>
152291 <description>APB Bridge Group 0 Rule 2</description>
152300 <description>Rule 0</description>
152307 <description>Non-secure and non-privilege user access allowed</description>
152312 <description>Non-secure and privilege access allowed</description>
152317 <description>Secure and non-privilege user access allowed</description>
152322 <description>Secure and privilege user access allowed</description>
152329 <description>Rule 1</description>
152336 <description>Non-secure and non-privilege user access allowed</description>
152341 <description>Non-secure and privilege access allowed</description>
152346 <description>Secure and non-privilege user access allowed</description>
152351 <description>Secure and privilege user access allowed</description>
152358 <description>I3C0</description>
152365 <description>Non-secure and non-privilege user access allowed</description>
152370 <description>Non-secure and privilege access allowed</description>
152375 <description>Secure and non-privilege user access allowed</description>
152380 <description>Secure and privilege user access allowed</description>
152389 <description>APB Bridge Group 0 Memory Rule 3</description>
152398 <description>EZH</description>
152405 <description>Non-secure and non-privilege user access allowed</description>
152410 <description>Non-secure and privilege access allowed</description>
152415 <description>Secure and non-privilege user access allowed</description>
152420 <description>Secure and privilege user access allowed</description>
152427 <description>PROBE_IS (SYNC)</description>
152434 <description>Non-secure and non-privilege user access allowed</description>
152439 <description>Non-secure and privilege access allowed</description>
152444 <description>Secure and non-privilege user access allowed</description>
152449 <description>Secure and privilege user access allowed</description>
152456 <description>PROBE_IS (XVC)</description>
152463 <description>Non-secure and non-privilege user access allowed</description>
152468 <description>Non-secure and privilege access allowed</description>
152473 <description>Secure and non-privilege user access allowed</description>
152478 <description>Secure and privilege user access allowed</description>
152487 <description>APB Bridge Group 1 Memory Rule 0</description>
152496 <description>PMC</description>
152503 <description>Non-secure and non-privilege user access allowed</description>
152508 <description>Non-secure and privilege access allowed</description>
152513 <description>Secure and non-privilege user access allowed</description>
152518 <description>Secure and privilege user access allowed</description>
152525 <description>PVT</description>
152532 <description>Non-secure and non-privilege user access allowed</description>
152537 <description>Non-secure and privilege access allowed</description>
152542 <description>Secure and non-privilege user access allowed</description>
152547 <description>Secure and privilege user access allowed</description>
152554 <description>SYSCTL(I2S Pin Sharing)</description>
152561 <description>Non-secure and non-privilege user access allowed</description>
152566 <description>Non-secure and privilege access allowed</description>
152571 <description>Secure and non-privilege user access allowed</description>
152576 <description>Secure and privilege user access allowed</description>
152583 <description>Rule 3</description>
152590 <description>Non-secure and non-privilege user access allowed</description>
152595 <description>Non-secure and privilege access allowed</description>
152600 <description>Secure and non-privilege user access allowed</description>
152605 <description>Secure and privilege user access allowed</description>
152614 <description>APB Bridge Group 1 Memory Rule 1</description>
152623 <description>CTIMER2</description>
152630 <description>Non-secure and non-privilege user access allowed</description>
152635 <description>Non-secure and privilege access allowed</description>
152640 <description>Secure and non-privilege user access allowed</description>
152645 <description>Secure and privilege user access allowed</description>
152652 <description>CTIMER3</description>
152659 <description>Non-secure and non-privilege user access allowed</description>
152664 <description>Non-secure and privilege access allowed</description>
152669 <description>Secure and non-privilege user access allowed</description>
152674 <description>Secure and privilege user access allowed</description>
152681 <description>CTIMER4</description>
152688 <description>Non-secure and non-privilege user access allowed</description>
152693 <description>Non-secure and privilege access allowed</description>
152698 <description>Secure and non-privilege user access allowed</description>
152703 <description>Secure and privilege user access allowed</description>
152710 <description>RTC</description>
152717 <description>Non-secure and non-privilege user access allowed</description>
152722 <description>Non-secure and privilege access allowed</description>
152727 <description>Secure and non-privilege user access allowed</description>
152732 <description>Secure and privilege user access allowed</description>
152739 <description>OS_EVENT_TIMER</description>
152746 <description>Non-secure and non-privilege user access allowed</description>
152751 <description>Non-secure and privilege access allowed</description>
152756 <description>Secure and non-privilege user access allowed</description>
152761 <description>Secure and privilege user access allowed</description>
152768 <description>CACHE64_POLSEL</description>
152775 <description>Non-secure and non-privilege user access allowed</description>
152780 <description>Non-secure and privilege access allowed</description>
152785 <description>Secure and non-privilege user access allowed</description>
152790 <description>Secure and privilege user access allowed</description>
152797 <description>PKC</description>
152804 <description>Non-secure and non-privilege user access allowed</description>
152809 <description>Non-secure and privilege access allowed</description>
152814 <description>Secure and non-privilege user access allowed</description>
152819 <description>Secure and privilege user access allowed</description>
152828 <description>APB Bridge Group 1 Memory Rule 2</description>
152837 <description>CSSV2MINI ALIAS0</description>
152844 <description>Non-secure and non-privilege user access allowed</description>
152849 <description>Non-secure and privilege access allowed</description>
152854 <description>Secure and non-privilege user access allowed</description>
152859 <description>Secure and privilege user access allowed</description>
152866 <description>CSSV2MINI ALIAS1</description>
152873 <description>Non-secure and non-privilege user access allowed</description>
152878 <description>Non-secure and privilege access allowed</description>
152883 <description>Secure and non-privilege user access allowed</description>
152888 <description>Secure and privilege user access allowed</description>
152895 <description>CSSV2MINI ALIAS2</description>
152902 <description>Non-secure and non-privilege user access allowed</description>
152907 <description>Non-secure and privilege access allowed</description>
152912 <description>Secure and non-privilege user access allowed</description>
152917 <description>Secure and privilege user access allowed</description>
152924 <description>CSSV2MINI ALIAS3</description>
152931 <description>Non-secure and non-privilege user access allowed</description>
152936 <description>Non-secure and privilege access allowed</description>
152941 <description>Secure and non-privilege user access allowed</description>
152946 <description>Secure and privilege user access allowed</description>
152953 <description>Flash controller</description>
152960 <description>Non-secure and non-privilege user access allowed</description>
152965 <description>Non-secure and privilege access allowed</description>
152970 <description>Secure and non-privilege user access allowed</description>
152975 <description>Secure and privilege user access allowed</description>
152982 <description>PRINCE0</description>
152989 <description>Non-secure and non-privilege user access allowed</description>
152994 <description>Non-secure and privilege access allowed</description>
152999 <description>Secure and non-privilege user access allowed</description>
153004 <description>Secure and privilege user access allowed</description>
153013 <description>APB Bridge Group 1 Memory Rule 3</description>
153022 <description>PUF_ALIAS0</description>
153029 <description>Non-secure and non-privilege user access allowed</description>
153034 <description>Non-secure and privilege access allowed</description>
153039 <description>Secure and non-privilege user access allowed</description>
153044 <description>Secure and privilege user access allowed</description>
153051 <description>PUF_ALIAS0</description>
153058 <description>Non-secure and non-privilege user access allowed</description>
153063 <description>Non-secure and privilege access allowed</description>
153068 <description>Secure and non-privilege user access allowed</description>
153073 <description>Secure and privilege user access allowed</description>
153080 <description>PUF_ALIAS2</description>
153087 <description>Non-secure and non-privilege user access allowed</description>
153092 <description>Non-secure and privilege access allowed</description>
153097 <description>Secure and non-privilege user access allowed</description>
153102 <description>Secure and privilege user access allowed</description>
153109 <description>PUF_ALIAS3</description>
153116 <description>Non-secure and non-privilege user access allowed</description>
153121 <description>Non-secure and privilege access allowed</description>
153126 <description>Secure and non-privilege user access allowed</description>
153131 <description>Secure and privilege user access allowed</description>
153138 <description>ROM</description>
153145 <description>Non-secure and non-privilege user access allowed</description>
153150 <description>Non-secure and privilege access allowed</description>
153155 <description>Secure and non-privilege user access allowed</description>
153160 <description>Secure and privilege user access allowed</description>
153171 <description>AHB Peripheral Port 9 Slave Rule</description>
153180 <description>Rule 0</description>
153187 <description>Non-secure and non-privilege user access allowed</description>
153192 <description>Non-secure and privilege access allowed</description>
153197 <description>Secure and non-privilege user access allowed</description>
153202 <description>Secure and privilege user access allowed</description>
153209 <description>Rule 1</description>
153216 <description>Non-secure and non-privilege user access allowed</description>
153221 <description>Non-secure and privilege access allowed</description>
153226 <description>Secure and non-privilege user access allowed</description>
153231 <description>Secure and privilege user access allowed</description>
153238 <description>Rule 2</description>
153245 <description>Non-secure and non-privilege user access allowed</description>
153250 <description>Non-secure and privilege access allowed</description>
153255 <description>Secure and non-privilege user access allowed</description>
153260 <description>Secure and privilege user access allowed</description>
153267 <description>Rule 3</description>
153274 <description>Non-secure and non-privilege user access allowed</description>
153279 <description>Non-secure and privilege access allowed</description>
153284 <description>Secure and non-privilege user access allowed</description>
153289 <description>Secure and privilege user access allowed</description>
153296 <description>Rule 4</description>
153303 <description>Non-secure and non-privilege user access allowed</description>
153308 <description>Non-secure and privilege access allowed</description>
153313 <description>Secure and non-privilege user access allowed</description>
153318 <description>Secure and privilege user access allowed</description>
153325 <description>Rule 5</description>
153332 <description>Non-secure and non-privilege user access allowed</description>
153337 <description>Non-secure and privilege access allowed</description>
153342 <description>Secure and non-privilege user access allowed</description>
153347 <description>Secure and privilege user access allowed</description>
153354 <description>Rule 6</description>
153361 <description>Non-secure and non-privilege user access allowed</description>
153366 <description>Non-secure and privilege access allowed</description>
153371 <description>Secure and non-privilege user access allowed</description>
153376 <description>Secure and privilege user access allowed</description>
153383 <description>Rule 7</description>
153390 <description>Non-secure and non-privilege user access allowed</description>
153395 <description>Non-secure and privilege access allowed</description>
153400 <description>Secure and non-privilege user access allowed</description>
153405 <description>Secure and privilege user access allowed</description>
153414 <description>AHB Peripheral 0 Memory Rule 0</description>
153423 <description>DMA0</description>
153430 <description>Non-secure and non-privilege user access allowed</description>
153435 <description>Non-secure and privilege access allowed</description>
153440 <description>Secure and non-privilege user access allowed</description>
153445 <description>Secure and privilege user access allowed</description>
153452 <description>DMA 0</description>
153459 <description>Non-secure and non-privilege user access allowed</description>
153464 <description>Non-secure and privilege access allowed</description>
153469 <description>Secure and non-privilege user access allowed</description>
153474 <description>Secure and privilege user access allowed</description>
153481 <description>DMA 1</description>
153488 <description>Non-secure and non-privilege user access allowed</description>
153493 <description>Non-secure and privilege access allowed</description>
153498 <description>Secure and non-privilege user access allowed</description>
153503 <description>Secure and privilege user access allowed</description>
153510 <description>FLEXCOMM 0</description>
153517 <description>Non-secure and non-privilege user access allowed</description>
153522 <description>Non-secure and privilege access allowed</description>
153527 <description>Secure and non-privilege user access allowed</description>
153532 <description>Secure and privilege user access allowed</description>
153539 <description>FLEXCOMM 1</description>
153546 <description>Non-secure and non-privilege user access allowed</description>
153551 <description>Non-secure and privilege access allowed</description>
153556 <description>Secure and non-privilege user access allowed</description>
153561 <description>Secure and privilege user access allowed</description>
153568 <description>FLEXCOMM 2</description>
153575 <description>Non-secure and non-privilege user access allowed</description>
153580 <description>Non-secure and privilege access allowed</description>
153585 <description>Secure and non-privilege user access allowed</description>
153590 <description>Secure and privilege user access allowed</description>
153597 <description>FLEXCOMM 3</description>
153604 <description>Non-secure and non-privilege user access allowed</description>
153609 <description>Non-secure and privilege access allowed</description>
153614 <description>Secure and non-privilege user access allowed</description>
153619 <description>Secure and privilege user access allowed</description>
153626 <description>FLEXCOMM4</description>
153633 <description>Non-secure and non-privilege user access allowed</description>
153638 <description>Non-secure and privilege access allowed</description>
153643 <description>Secure and non-privilege user access allowed</description>
153648 <description>Secure and privilege user access allowed</description>
153657 <description>AHB Peripheral 0 Memory Rule 1</description>
153666 <description>MAILBOX</description>
153673 <description>Non-secure and non-privilege user access allowed</description>
153678 <description>Non-secure and privilege access allowed</description>
153683 <description>Secure and non-privilege user access allowed</description>
153688 <description>Secure and privilege user access allowed</description>
153695 <description>GPIO</description>
153702 <description>Non-secure and non-privilege user access allowed</description>
153707 <description>Non-secure and privilege access allowed</description>
153712 <description>Secure and non-privilege user access allowed</description>
153717 <description>Secure and privilege user access allowed</description>
153728 <description>AHB Peripheral Port 10 Slave Rule</description>
153737 <description>Rule 0</description>
153744 <description>Non-secure and non-privilege user access allowed</description>
153749 <description>Non-secure and privilege access allowed</description>
153754 <description>Secure and non-privilege user access allowed</description>
153759 <description>Secure and privilege user access allowed</description>
153766 <description>Rule 1</description>
153773 <description>Non-secure and non-privilege user access allowed</description>
153778 <description>Non-secure and privilege access allowed</description>
153783 <description>Secure and non-privilege user access allowed</description>
153788 <description>Secure and privilege user access allowed</description>
153795 <description>Rule 2</description>
153802 <description>Non-secure and non-privilege user access allowed</description>
153807 <description>Non-secure and privilege access allowed</description>
153812 <description>Secure and non-privilege user access allowed</description>
153817 <description>Secure and privilege user access allowed</description>
153824 <description>Rule 3</description>
153831 <description>Non-secure and non-privilege user access allowed</description>
153836 <description>Non-secure and privilege access allowed</description>
153841 <description>Secure and non-privilege user access allowed</description>
153846 <description>Secure and privilege user access allowed</description>
153853 <description>Rule 4</description>
153860 <description>Non-secure and non-privilege user access allowed</description>
153865 <description>Non-secure and privilege access allowed</description>
153870 <description>Secure and non-privilege user access allowed</description>
153875 <description>Secure and privilege user access allowed</description>
153882 <description>Rule 5</description>
153889 <description>Non-secure and non-privilege user access allowed</description>
153894 <description>Non-secure and privilege access allowed</description>
153899 <description>Secure and non-privilege user access allowed</description>
153904 <description>Secure and privilege user access allowed</description>
153911 <description>Rule 6</description>
153918 <description>Non-secure and non-privilege user access allowed</description>
153923 <description>Non-secure and privilege access allowed</description>
153928 <description>Secure and non-privilege user access allowed</description>
153933 <description>Secure and privilege user access allowed</description>
153940 <description>Rule 7</description>
153947 <description>Non-secure and non-privilege user access allowed</description>
153952 <description>Non-secure and privilege access allowed</description>
153957 <description>Secure and non-privilege user access allowed</description>
153962 <description>Secure and privilege user access allowed</description>
153971 <description>AHB Peripheral 1 Memory Rule 0</description>
153980 <description>DMIC0</description>
153987 <description>Non-secure and non-privilege user access allowed</description>
153992 <description>Non-secure and privilege access allowed</description>
153997 <description>Secure and non-privilege user access allowed</description>
154002 <description>Secure and privilege user access allowed</description>
154009 <description>CRC</description>
154016 <description>Non-secure and non-privilege user access allowed</description>
154021 <description>Non-secure and privilege access allowed</description>
154026 <description>Secure and non-privilege user access allowed</description>
154031 <description>Secure and privilege user access allowed</description>
154038 <description>FLEXCOMM 5</description>
154045 <description>Non-secure and non-privilege user access allowed</description>
154050 <description>Non-secure and privilege access allowed</description>
154055 <description>Secure and non-privilege user access allowed</description>
154060 <description>Secure and privilege user access allowed</description>
154067 <description>FLEXCOMM 6</description>
154074 <description>Non-secure and non-privilege user access allowed</description>
154079 <description>Non-secure and privilege access allowed</description>
154084 <description>Secure and non-privilege user access allowed</description>
154089 <description>Secure and privilege user access allowed</description>
154096 <description>FLEXCOMM 7</description>
154103 <description>Non-secure and non-privilege user access allowed</description>
154108 <description>Non-secure and privilege access allowed</description>
154113 <description>Secure and non-privilege user access allowed</description>
154118 <description>Secure and privilege user access allowed</description>
154125 <description>FLEXCOMM 7</description>
154132 <description>Non-secure and non-privilege user access allowed</description>
154137 <description>Non-secure and privilege access allowed</description>
154142 <description>Secure and non-privilege user access allowed</description>
154147 <description>Secure and privilege user access allowed</description>
154154 <description>FLEXCOMM 14</description>
154161 <description>Non-secure and non-privilege user access allowed</description>
154166 <description>Non-secure and privilege access allowed</description>
154171 <description>Secure and non-privilege user access allowed</description>
154176 <description>Secure and privilege user access allowed</description>
154183 <description>FLEXCOMM 15</description>
154190 <description>Non-secure and non-privilege user access allowed</description>
154195 <description>Non-secure and privilege access allowed</description>
154200 <description>Secure and non-privilege user access allowed</description>
154205 <description>Secure and privilege user access allowed</description>
154216 <description>AHB Peripheral Port 11 Slave Rule</description>
154225 <description>Rule 0</description>
154232 <description>Non-secure and non-privilege user access allowed</description>
154237 <description>Non-secure and privilege access allowed</description>
154242 <description>Secure and non-privilege user access allowed</description>
154247 <description>Secure and privilege user access allowed</description>
154254 <description>Rule 1</description>
154261 <description>Non-secure and non-privilege user access allowed</description>
154266 <description>Non-secure and privilege access allowed</description>
154271 <description>Secure and non-privilege user access allowed</description>
154276 <description>Secure and privilege user access allowed</description>
154283 <description>Rule 2</description>
154290 <description>Non-secure and non-privilege user access allowed</description>
154295 <description>Non-secure and privilege access allowed</description>
154300 <description>Secure and non-privilege user access allowed</description>
154305 <description>Secure and privilege user access allowed</description>
154312 <description>Rule 3</description>
154319 <description>Non-secure and non-privilege user access allowed</description>
154324 <description>Non-secure and privilege access allowed</description>
154329 <description>Secure and non-privilege user access allowed</description>
154334 <description>Secure and privilege user access allowed</description>
154341 <description>Rule 4</description>
154348 <description>Non-secure and non-privilege user access allowed</description>
154353 <description>Non-secure and privilege access allowed</description>
154358 <description>Secure and non-privilege user access allowed</description>
154363 <description>Secure and privilege user access allowed</description>
154370 <description>Rule 5</description>
154377 <description>Non-secure and non-privilege user access allowed</description>
154382 <description>Non-secure and privilege access allowed</description>
154387 <description>Secure and non-privilege user access allowed</description>
154392 <description>Secure and privilege user access allowed</description>
154399 <description>Rule 6</description>
154406 <description>Non-secure and non-privilege user access allowed</description>
154411 <description>Non-secure and privilege access allowed</description>
154416 <description>Secure and non-privilege user access allowed</description>
154421 <description>Secure and privilege user access allowed</description>
154428 <description>Rule 7</description>
154435 <description>Non-secure and non-privilege user access allowed</description>
154440 <description>Non-secure and privilege access allowed</description>
154445 <description>Secure and non-privilege user access allowed</description>
154450 <description>Secure and privilege user access allowed</description>
154459 <description>AHB Peripheral 2 Memory Rule 0</description>
154468 <description>ADC</description>
154475 <description>Non-secure and non-privilege user access allowed</description>
154480 <description>Non-secure and privilege access allowed</description>
154485 <description>Secure and non-privilege user access allowed</description>
154490 <description>Secure and privilege user access allowed</description>
154497 <description>USB HS DEV</description>
154504 <description>Non-secure and non-privilege user access allowed</description>
154509 <description>Non-secure and privilege access allowed</description>
154514 <description>Secure and non-privilege user access allowed</description>
154519 <description>Secure and privilege user access allowed</description>
154526 <description>USB FS HOST</description>
154533 <description>Non-secure and non-privilege user access allowed</description>
154538 <description>Non-secure and privilege access allowed</description>
154543 <description>Secure and non-privilege user access allowed</description>
154548 <description>Secure and privilege user access allowed</description>
154555 <description>POWERQUAD</description>
154562 <description>Non-secure and non-privilege user access allowed</description>
154567 <description>Non-secure and privilege access allowed</description>
154572 <description>Secure and non-privilege user access allowed</description>
154577 <description>Secure and privilege user access allowed</description>
154584 <description>DMA1</description>
154591 <description>Non-secure and non-privilege user access allowed</description>
154596 <description>Non-secure and privilege access allowed</description>
154601 <description>Secure and non-privilege user access allowed</description>
154606 <description>Secure and privilege user access allowed</description>
154613 <description>SECGPIO</description>
154620 <description>Non-secure and non-privilege user access allowed</description>
154625 <description>Non-secure and privilege access allowed</description>
154630 <description>Secure and non-privilege user access allowed</description>
154635 <description>Secure and privilege user access allowed</description>
154642 <description>AHB_SECURE</description>
154649 <description>Non-secure and non-privilege user access allowed</description>
154654 <description>Non-secure and privilege access allowed</description>
154659 <description>Secure and non-privilege user access allowed</description>
154664 <description>Secure and privilege user access allowed</description>
154673 <description>AHB Secure Control Peripheral Rule 0</description>
154682 <description>Rule 0</description>
154689 <description>Non-secure and non-privilege user access allowed</description>
154694 <description>Non-secure and privilege access allowed</description>
154699 <description>Secure and non-privilege user access allowed</description>
154704 <description>Secure and privilege user access allowed</description>
154711 <description>Rule 1</description>
154718 <description>Non-secure and non-privilege user access allowed</description>
154723 <description>Non-secure and privilege access allowed</description>
154728 <description>Secure and non-privilege user access allowed</description>
154733 <description>Secure and privilege user access allowed</description>
154740 <description>Rule 2</description>
154747 <description>Non-secure and non-privilege user access allowed</description>
154752 <description>Non-secure and privilege access allowed</description>
154757 <description>Secure and non-privilege user access allowed</description>
154762 <description>Secure and privilege user access allowed</description>
154769 <description>Rule 3</description>
154776 <description>Non-secure and non-privilege user access allowed</description>
154781 <description>Non-secure and privilege access allowed</description>
154786 <description>Secure and non-privilege user access allowed</description>
154791 <description>Secure and privilege user access allowed</description>
154802 <description>AHB Peripheral Port 12 Slave Rule</description>
154811 <description>Rule 0</description>
154818 <description>Non-secure and non-privilege user access allowed</description>
154823 <description>Non-secure and privilege access allowed</description>
154828 <description>Secure and non-privilege user access allowed</description>
154833 <description>Secure and privilege user access allowed</description>
154840 <description>Rule 1</description>
154847 <description>Non-secure and non-privilege user access allowed</description>
154852 <description>Non-secure and privilege access allowed</description>
154857 <description>Secure and non-privilege user access allowed</description>
154862 <description>Secure and privilege user access allowed</description>
154869 <description>Rule 2</description>
154876 <description>Non-secure and non-privilege user access allowed</description>
154881 <description>Non-secure and privilege access allowed</description>
154886 <description>Secure and non-privilege user access allowed</description>
154891 <description>Secure and privilege user access allowed</description>
154898 <description>Rule 3</description>
154905 <description>Non-secure and non-privilege user access allowed</description>
154910 <description>Non-secure and privilege access allowed</description>
154915 <description>Secure and non-privilege user access allowed</description>
154920 <description>Secure and privilege user access allowed</description>
154927 <description>Rule 4</description>
154934 <description>Non-secure and non-privilege user access allowed</description>
154939 <description>Non-secure and privilege access allowed</description>
154944 <description>Secure and non-privilege user access allowed</description>
154949 <description>Secure and privilege user access allowed</description>
154956 <description>Rule 5</description>
154963 <description>Non-secure and non-privilege user access allowed</description>
154968 <description>Non-secure and privilege access allowed</description>
154973 <description>Secure and non-privilege user access allowed</description>
154978 <description>Secure and privilege user access allowed</description>
154985 <description>Rule 6</description>
154992 <description>Non-secure and non-privilege user access allowed</description>
154997 <description>Non-secure and privilege access allowed</description>
155002 <description>Secure and non-privilege user access allowed</description>
155007 <description>Secure and privilege user access allowed</description>
155014 <description>Rule 7</description>
155021 <description>Non-secure and non-privilege user access allowed</description>
155026 <description>Non-secure and privilege access allowed</description>
155031 <description>Secure and non-privilege user access allowed</description>
155036 <description>Secure and privilege user access allowed</description>
155045 <description>AIPS Bridge Group 0 Rule 0</description>
155054 <description>ADC1</description>
155061 <description>Non-secure and non-privilege user access allowed</description>
155066 <description>Non-secure and privilege access allowed</description>
155071 <description>Secure and non-privilege user access allowed</description>
155076 <description>Secure and privilege user access allowed</description>
155083 <description>DAC0</description>
155090 <description>Non-secure and non-privilege user access allowed</description>
155095 <description>Non-secure and privilege access allowed</description>
155100 <description>Secure and non-privilege user access allowed</description>
155105 <description>Secure and privilege user access allowed</description>
155112 <description>HSCOMP0</description>
155119 <description>Non-secure and non-privilege user access allowed</description>
155124 <description>Non-secure and privilege access allowed</description>
155129 <description>Secure and non-privilege user access allowed</description>
155134 <description>Secure and privilege user access allowed</description>
155141 <description>OPAMP0</description>
155148 <description>Non-secure and non-privilege user access allowed</description>
155153 <description>Non-secure and privilege access allowed</description>
155158 <description>Secure and non-privilege user access allowed</description>
155163 <description>Secure and privilege user access allowed</description>
155170 <description>VREF</description>
155177 <description>Non-secure and non-privilege user access allowed</description>
155182 <description>Non-secure and privilege access allowed</description>
155187 <description>Secure and non-privilege user access allowed</description>
155192 <description>Secure and privilege user access allowed</description>
155199 <description>DAC1</description>
155206 <description>Non-secure and non-privilege user access allowed</description>
155211 <description>Non-secure and privilege access allowed</description>
155216 <description>Secure and non-privilege user access allowed</description>
155221 <description>Secure and privilege user access allowed</description>
155228 <description>HSCOMP1</description>
155235 <description>Non-secure and non-privilege user access allowed</description>
155240 <description>Non-secure and privilege access allowed</description>
155245 <description>Secure and non-privilege user access allowed</description>
155250 <description>Secure and privilege user access allowed</description>
155259 <description>AIPS Bridge Group 0 Rule 1</description>
155268 <description>OPAMP1</description>
155275 <description>Non-secure and non-privilege user access allowed</description>
155280 <description>Non-secure and privilege access allowed</description>
155285 <description>Secure and non-privilege user access allowed</description>
155290 <description>Secure and privilege user access allowed</description>
155297 <description>DAC2</description>
155304 <description>Non-secure and non-privilege user access allowed</description>
155309 <description>Non-secure and privilege access allowed</description>
155314 <description>Secure and non-privilege user access allowed</description>
155319 <description>Secure and privilege user access allowed</description>
155326 <description>HSCOMP2</description>
155333 <description>Non-secure and non-privilege user access allowed</description>
155338 <description>Non-secure and privilege access allowed</description>
155343 <description>Secure and non-privilege user access allowed</description>
155348 <description>Secure and privilege user access allowed</description>
155355 <description>OPAMP2</description>
155362 <description>Non-secure and non-privilege user access allowed</description>
155367 <description>Non-secure and privilege access allowed</description>
155372 <description>Secure and non-privilege user access allowed</description>
155377 <description>Secure and privilege user access allowed</description>
155388 <description>AHB Peripheral Port 13 Slave Rule</description>
155397 <description>Rule 0</description>
155404 <description>Non-secure and non-privilege user access allowed</description>
155409 <description>Non-secure and privilege access allowed</description>
155414 <description>Secure and non-privilege user access allowed</description>
155419 <description>Secure and privilege user access allowed</description>
155426 <description>Rule 1</description>
155433 <description>Non-secure and non-privilege user access allowed</description>
155438 <description>Non-secure and privilege access allowed</description>
155443 <description>Secure and non-privilege user access allowed</description>
155448 <description>Secure and privilege user access allowed</description>
155455 <description>Rule 2</description>
155462 <description>Non-secure and non-privilege user access allowed</description>
155467 <description>Non-secure and privilege access allowed</description>
155472 <description>Secure and non-privilege user access allowed</description>
155477 <description>Secure and privilege user access allowed</description>
155484 <description>Rule 3</description>
155491 <description>Non-secure and non-privilege user access allowed</description>
155496 <description>Non-secure and privilege access allowed</description>
155501 <description>Secure and non-privilege user access allowed</description>
155506 <description>Secure and privilege user access allowed</description>
155513 <description>Rule 4</description>
155520 <description>Non-secure and non-privilege user access allowed</description>
155525 <description>Non-secure and privilege access allowed</description>
155530 <description>Secure and non-privilege user access allowed</description>
155535 <description>Secure and privilege user access allowed</description>
155542 <description>Rule 5</description>
155549 <description>Non-secure and non-privilege user access allowed</description>
155554 <description>Non-secure and privilege access allowed</description>
155559 <description>Secure and non-privilege user access allowed</description>
155564 <description>Secure and privilege user access allowed</description>
155571 <description>Rule 6</description>
155578 <description>Non-secure and non-privilege user access allowed</description>
155583 <description>Non-secure and privilege access allowed</description>
155588 <description>Secure and non-privilege user access allowed</description>
155593 <description>Secure and privilege user access allowed</description>
155600 <description>Rule 7</description>
155607 <description>Non-secure and non-privilege user access allowed</description>
155612 <description>Non-secure and privilege access allowed</description>
155617 <description>Secure and non-privilege user access allowed</description>
155622 <description>Secure and privilege user access allowed</description>
155631 <description>AIPS Bridge Group 1 Rule 0</description>
155640 <description>FLEXSPI0</description>
155647 <description>Non-secure and non-privilege user access allowed</description>
155652 <description>Non-secure and privilege access allowed</description>
155657 <description>Secure and non-privilege user access allowed</description>
155662 <description>Secure and privilege user access allowed</description>
155669 <description>FLEXSPI_CMX</description>
155676 <description>Non-secure and non-privilege user access allowed</description>
155681 <description>Non-secure and privilege access allowed</description>
155686 <description>Secure and non-privilege user access allowed</description>
155691 <description>Secure and privilege user access allowed</description>
155698 <description>LPCAC</description>
155705 <description>Non-secure and non-privilege user access allowed</description>
155710 <description>Non-secure and privilege access allowed</description>
155715 <description>Secure and non-privilege user access allowed</description>
155720 <description>Secure and privilege user access allowed</description>
155727 <description>FLEXPWM0</description>
155734 <description>Non-secure and non-privilege user access allowed</description>
155739 <description>Non-secure and privilege access allowed</description>
155744 <description>Secure and non-privilege user access allowed</description>
155749 <description>Secure and privilege user access allowed</description>
155756 <description>FLEXSPI0 Registers</description>
155763 <description>Non-secure and non-privilege user access allowed</description>
155768 <description>Non-secure and privilege access allowed</description>
155773 <description>Secure and non-privilege user access allowed</description>
155778 <description>Secure and privilege user access allowed</description>
155785 <description>FLEXSPI_PWM1</description>
155792 <description>Non-secure and non-privilege user access allowed</description>
155797 <description>Non-secure and privilege access allowed</description>
155802 <description>Secure and non-privilege user access allowed</description>
155807 <description>Secure and privilege user access allowed</description>
155814 <description>ENC1</description>
155821 <description>Non-secure and non-privilege user access allowed</description>
155826 <description>Non-secure and privilege access allowed</description>
155831 <description>Secure and non-privilege user access allowed</description>
155836 <description>Secure and privilege user access allowed</description>
155843 <description>AOI0</description>
155850 <description>Non-secure and non-privilege user access allowed</description>
155855 <description>Non-secure and privilege access allowed</description>
155860 <description>Secure and non-privilege user access allowed</description>
155865 <description>Secure and privilege user access allowed</description>
155874 <description>AIPS Bridge Group 1 Rule 1</description>
155883 <description>RNG (Random Number Generator)</description>
155890 <description>Non-secure and non-privilege user access allowed</description>
155895 <description>Non-secure and privilege access allowed</description>
155900 <description>Secure and non-privilege user access allowed</description>
155905 <description>Secure and privilege user access allowed</description>
155912 <description>ACMP 0</description>
155919 <description>Non-secure and non-privilege user access allowed</description>
155924 <description>Non-secure and privilege access allowed</description>
155929 <description>Secure and non-privilege user access allowed</description>
155934 <description>Secure and privilege user access allowed</description>
155941 <description>ADC 0</description>
155948 <description>Non-secure and non-privilege user access allowed</description>
155953 <description>Non-secure and privilege access allowed</description>
155958 <description>Secure and non-privilege user access allowed</description>
155963 <description>Secure and privilege user access allowed</description>
155970 <description>HS USB PHY</description>
155977 <description>Non-secure and non-privilege user access allowed</description>
155982 <description>Non-secure and privilege access allowed</description>
155987 <description>Secure and non-privilege user access allowed</description>
155992 <description>Secure and privilege user access allowed</description>
155999 <description>FLEXSPI1 Registers</description>
156006 <description>Non-secure and non-privilege user access allowed</description>
156011 <description>Non-secure and privilege access allowed</description>
156016 <description>Secure and non-privilege user access allowed</description>
156021 <description>Secure and privilege user access allowed</description>
156032 <description>Security Violation Address</description>
156041 <description>Security violation access read/write indicator</description>
156052 <description>Security Violation Miscellaneous Information at Address</description>
156061 <description>Security violation access read/write indicator</description>
156068 <description>Read access</description>
156073 <description>Write access</description>
156080 <description>Security Violation Info Data Access</description>
156087 <description>Code</description>
156092 <description>Data</description>
156099 <description>Security Violation Info Master Security Level</description>
156106 <description>Security violation master number</description>
156113 <description>M33 Code</description>
156118 <description>M33 System</description>
156123 <description>DMA0</description>
156128 <description>DMA1</description>
156133 <description>USBFS Device</description>
156138 <description>USBFS Host</description>
156143 <description>SMARTDMA Instruction</description>
156148 <description>SMARTDMA Data</description>
156153 <description>CSSV2</description>
156158 <description>MCAN</description>
156163 <description>PKC M0</description>
156168 <description>GPU</description>
156173 <description>DSP Data</description>
156178 <description>DSP Instruction</description>
156187 <description>Security Violation Info Validity for Address</description>
156196 <description>Violation information valid flag for AHB port 0</description>
156204 <description>Not valid</description>
156209 <description>Valid</description>
156216 <description>Violation information valid flag for AHB port 1</description>
156224 <description>Not valid</description>
156229 <description>Valid</description>
156236 <description>Violation information valid flag for AHB port 2</description>
156244 <description>Not valid</description>
156249 <description>Valid</description>
156256 <description>Violation information valid flag for AHB port 3</description>
156264 <description>Not valid</description>
156269 <description>Valid</description>
156276 <description>Violation information valid flag for AHB port 4</description>
156284 <description>Not valid</description>
156289 <description>Valid</description>
156296 <description>Violation information valid flag for AHB port 5</description>
156304 <description>Not valid</description>
156309 <description>Valid</description>
156316 <description>Violation information valid flag for AHB port 6</description>
156324 <description>Not valid</description>
156329 <description>Valid</description>
156336 <description>Violation information valid flag for AHB port 7</description>
156344 <description>Not valid</description>
156349 <description>Valid</description>
156356 <description>Violation information valid flag for AHB port 8</description>
156364 <description>Not valid</description>
156369 <description>Valid</description>
156376 <description>Violation information valid flag for AHB port 9</description>
156384 <description>Not valid</description>
156389 <description>Valid</description>
156396 <description>Violation information valid flag for AHB port 10</description>
156404 <description>Not valid</description>
156409 <description>Valid</description>
156416 <description>Violation information valid flag for AHB port 11</description>
156424 <description>Not valid</description>
156429 <description>Valid</description>
156436 <description>Violation information valid flag for AHB port 12</description>
156444 <description>Not valid</description>
156449 <description>Valid</description>
156456 <description>Violation information valid flag for AHB port 13</description>
156464 <description>Not valid</description>
156469 <description>Valid</description>
156476 <description>Violation information valid flag for AHB port 14</description>
156484 <description>Not valid</description>
156489 <description>Valid</description>
156496 <description>Violation information valid flag for AHB port 15</description>
156504 <description>Not valid</description>
156509 <description>Valid</description>
156516 <description>Violation information valid flag for AHB port 16</description>
156524 <description>Not valid</description>
156529 <description>Valid</description>
156536 <description>Violation information valid flag for AHB port 17</description>
156544 <description>Not valid</description>
156549 <description>Valid</description>
156556 <description>Violation information valid flag for AHB port 18</description>
156564 <description>Not valid</description>
156569 <description>Valid</description>
156580 <description>GPIO Mask for Port index</description>
156589 <description>Mask bit</description>
156596 <description>Masked</description>
156601 <description>Not masked</description>
156608 <description>Mask bit</description>
156615 <description>Masked</description>
156620 <description>Not masked</description>
156627 <description>Mask bit</description>
156634 <description>Masked</description>
156639 <description>Not masked</description>
156646 <description>Mask bit</description>
156653 <description>Masked</description>
156658 <description>Not masked</description>
156665 <description>Mask bit</description>
156672 <description>Masked</description>
156677 <description>Not masked</description>
156684 <description>Mask bit</description>
156691 <description>Masked</description>
156696 <description>Not masked</description>
156703 <description>Mask bit</description>
156710 <description>Masked</description>
156715 <description>Not masked</description>
156722 <description>Mask bit</description>
156729 <description>Masked</description>
156734 <description>Not masked</description>
156741 <description>Mask bit</description>
156748 <description>Masked</description>
156753 <description>Not masked</description>
156760 <description>Mask bit</description>
156767 <description>Masked</description>
156772 <description>Not masked</description>
156779 <description>Mask bit</description>
156786 <description>Masked</description>
156791 <description>Not masked</description>
156798 <description>Mask bit</description>
156805 <description>Masked</description>
156810 <description>Not masked</description>
156817 <description>Mask bit</description>
156824 <description>Masked</description>
156829 <description>Not masked</description>
156836 <description>Mask bit</description>
156843 <description>Masked</description>
156848 <description>Not masked</description>
156855 <description>Mask bit</description>
156862 <description>Masked</description>
156867 <description>Not masked</description>
156874 <description>Mask bit</description>
156881 <description>Masked</description>
156886 <description>Not masked</description>
156893 <description>Mask bit</description>
156900 <description>Masked</description>
156905 <description>Not masked</description>
156912 <description>Mask bit</description>
156919 <description>Masked</description>
156924 <description>Not masked</description>
156931 <description>Mask bit</description>
156938 <description>Masked</description>
156943 <description>Not masked</description>
156950 <description>Mask bit</description>
156957 <description>Masked</description>
156962 <description>Not masked</description>
156969 <description>Mask bit</description>
156976 <description>Masked</description>
156981 <description>Not masked</description>
156988 <description>Mask bit</description>
156995 <description>Masked</description>
157000 <description>Not masked</description>
157007 <description>Mask bit</description>
157014 <description>Masked</description>
157019 <description>Not masked</description>
157026 <description>Mask bit</description>
157033 <description>Masked</description>
157038 <description>Not masked</description>
157045 <description>Mask bit</description>
157052 <description>Masked</description>
157057 <description>Not masked</description>
157064 <description>Mask bit</description>
157071 <description>Masked</description>
157076 <description>Not masked</description>
157083 <description>Mask bit</description>
157090 <description>Masked</description>
157095 <description>Not masked</description>
157102 <description>Mask bit</description>
157109 <description>Masked</description>
157114 <description>Not masked</description>
157121 <description>Mask bit</description>
157128 <description>Masked</description>
157133 <description>Not masked</description>
157140 <description>Mask bit</description>
157147 <description>Masked</description>
157152 <description>Not masked</description>
157159 <description>Mask bit</description>
157166 <description>Masked</description>
157171 <description>Not masked</description>
157178 <description>Mask bit</description>
157185 <description>Masked</description>
157190 <description>Not masked</description>
157199 <description>Secure Mask Lock</description>
157208 <description>Secure GPIO _MASK0 Lock</description>
157215 <description>SEC_GPIO_MASK0 cannot be written</description>
157220 <description>SEC_GPIO_MASK0 can be written</description>
157227 <description>Secure GPIO _MASK1 Lock</description>
157234 <description>SEC_GPIO_MASK1 cannot be written</description>
157239 <description>SEC_GPIO_MASK1 can be written</description>
157246 <description>Secure GPIO _MASK2 Lock</description>
157253 <description>SEC_GPIO_MASK2 cannot be written</description>
157258 <description>SEC_GPIO_MASK2 can be written</description>
157265 <description>Secure GPIO _MASK3 Lock</description>
157272 <description>SEC_GPIO_MASK3 cannot be written</description>
157277 <description>SEC_GPIO_MASK3 can be written</description>
157284 <description>SEC_GPIO_MASK4 Lock</description>
157291 <description>SEC_GPIO_MASK4_LOCK cannot be written</description>
157296 <description>SEC_GPIO_MASK4_LOCK can be written</description>
157303 <description>SEC_GPIO_MASK5 Lock</description>
157310 <description>SEC_GPIO_MASK5 cannot be written</description>
157315 <description>SEC_GPIO_MASK5 can be written</description>
157322 <description>SEC_GPIO_MASK6 Lock</description>
157329 <description>SEC_GPIO_MASK6 cannot be written</description>
157334 <description>SEC_GPIO_MASK6 can be written</description>
157341 <description>SEC_GPIO_MASK7 Lock</description>
157348 <description>SEC_GPIO_MASK7 cannot be written</description>
157353 <description>SEC_GPIO_MASK7 can be written</description>
157360 <description>SEC_DSP_INT_MASK Lock</description>
157367 <description>SEC_DSP_INT_MASK cannot be written</description>
157372 <description>SEC_DSP_INT_MASK can be written</description>
157381 <description>Master Secure Level</description>
157390 <description>DMA0</description>
157397 <description>Non-secure and non-privileged Master</description>
157402 <description>Non-secure and privileged Master</description>
157407 <description>Secure and non-privileged Master</description>
157412 <description>Secure and privileged Master</description>
157419 <description>DMA1</description>
157426 <description>Non-secure and non-privileged Master</description>
157431 <description>Non-secure and privileged Master</description>
157436 <description>Secure and non-privileged Master</description>
157441 <description>Secure and privileged Master</description>
157448 <description>USBFS Device</description>
157455 <description>Non-secure and non-privileged Master</description>
157460 <description>Non-secure and privileged Master</description>
157465 <description>Secure and non-privileged Master</description>
157470 <description>Secure and privileged Master</description>
157477 <description>USBFS Host</description>
157484 <description>Non-secure and non-privileged Master</description>
157489 <description>Non-secure and privileged Master</description>
157494 <description>Secure and non-privileged Master</description>
157499 <description>Secure and privileged Master</description>
157506 <description>Smart DMA (SDMA) Instruction</description>
157513 <description>Non-secure and non-privileged Master</description>
157518 <description>Non-secure and privileged Master</description>
157523 <description>Secure and non-privileged Master</description>
157528 <description>Secure and privileged Master</description>
157535 <description>Smart DMA (SDMA) Data</description>
157542 <description>Non-secure and non-privileged Master</description>
157547 <description>Non-secure and privileged Master</description>
157552 <description>Secure and non-privileged Master</description>
157557 <description>Secure and privileged Master</description>
157564 <description>CSSV2M</description>
157571 <description>Non-secure and non-privileged Master</description>
157576 <description>Non-secure and privileged Master</description>
157581 <description>Secure and non-privileged Master</description>
157586 <description>Secure and privileged Master</description>
157593 <description>MCAN</description>
157600 <description>Non-secure and non-privileged Master</description>
157605 <description>Non-secure and privileged Master</description>
157610 <description>Secure and non-privileged Master</description>
157615 <description>Secure and privileged Master</description>
157622 <description>PKCM</description>
157629 <description>Non-secure and non-privileged Master</description>
157634 <description>Non-secure and privileged Master</description>
157639 <description>Secure and non-privileged Master</description>
157644 <description>Secure and privileged Master</description>
157651 <description>DSP Data</description>
157658 <description>DSP Instruction</description>
157665 <description>Master Security Level Lock</description>
157672 …<description>Lock writing to this register, including these (MASTER_SEC_LEVEL_LOCK) bits</descript…
157677 <description>This register can be written</description>
157686 <description>Master Secure Level</description>
157695 <description>DMA0</description>
157702 <description>Non-secure and non-privileged Master</description>
157707 <description>Non-secure and privileged Master</description>
157712 <description>Secure and non-privileged Master</description>
157717 <description>Secure and privileged Master</description>
157724 <description>DMA1</description>
157731 <description>Non-secure and non-privileged Master</description>
157736 <description>Non-secure and privileged Master</description>
157741 <description>Secure and non-privileged Master</description>
157746 <description>Secure and privileged Master</description>
157753 <description>USBFS Device</description>
157760 <description>Non-secure and non-privileged Master</description>
157765 <description>Non-secure and privileged Master</description>
157770 <description>Secure and non-privileged Master</description>
157775 <description>Secure and privileged Master</description>
157782 <description>USBFS Host</description>
157789 <description>Non-secure and non-privileged Master</description>
157794 <description>Non-secure and privileged Master</description>
157799 <description>Secure and non-privileged Master</description>
157804 <description>Secure and privileged Master</description>
157811 <description>Smart DMA (SDMA) Instruction</description>
157818 <description>Non-secure and non-privileged Master</description>
157823 <description>Non-secure and privileged Master</description>
157828 <description>Secure and non-privileged Master</description>
157833 <description>Secure and privileged Master</description>
157840 <description>Smart DMA (SDMA) Data</description>
157847 <description>Non-secure and non-privileged Master</description>
157852 <description>Non-secure and privileged Master</description>
157857 <description>Secure and non-privileged Master</description>
157862 <description>Secure and privileged Master</description>
157869 <description>CSSV2M</description>
157876 <description>Non-secure and non-privileged Master</description>
157881 <description>Non-secure and privileged Master</description>
157886 <description>Secure and non-privileged Master</description>
157891 <description>Secure and privileged Master</description>
157898 <description>MCAN</description>
157905 <description>Non-secure and non-privileged Master</description>
157910 <description>Non-secure and privileged Master</description>
157915 <description>Secure and non-privileged Master</description>
157920 <description>Secure and privileged Master</description>
157927 <description>PKCM</description>
157934 <description>Non-secure and non-privileged Master</description>
157939 <description>Non-secure and privileged Master</description>
157944 <description>Secure and non-privileged Master</description>
157949 <description>Secure and privileged Master</description>
157956 <description>DSP Data</description>
157963 <description>DSP Instruction</description>
157970 <description>Master Security Level Antipole Lock</description>
157977 …<description>Lock writing to this register, including these (MASTER_SEC_LEVEL_ANTIPOL_LOCK) bits</…
157982 <description>This register can be written</description>
157993 <description>Miscellaneous CPU0 Control Signals</description>
158002 <description>LOCK_NS_VTOR</description>
158009 <description>CM33 (CPU0) LOCKNSVTOR is 1</description>
158014 <description>CM33 (CPU0) LOCKNSVTOR is 0</description>
158021 <description>LOCK_NS_MPU</description>
158028 <description>CM33 (CPU0) LOCK_NS_MPU is 1</description>
158033 <description>CM33 (CPU0) LOCK_NS_MPU is 0</description>
158040 <description>LOCK_S_VTAIRCR</description>
158047 <description>CM33 (CPU0) LOCK_S_VTAIRCR is 1</description>
158052 <description>CM33 (CPU0) LOCK_S_VTAIRCR is 0</description>
158059 <description>LOCK_S_MPU</description>
158066 <description>CM33 (CPU0) LOCK_S_MPU is 1</description>
158071 <description>CM33 (CPU0) LOCK_S_MPU is 0</description>
158078 <description>LOCK_SAU</description>
158085 <description>CM33 (CPU0) LOCK_SAU is 1</description>
158090 <description>CM33 (CPU0) LOCK_SAU is 0</description>
158097 <description>CM33_LOCK_REG_LOCK</description>
158104 <description>CM33_LOCK_REG_LOCK is 1</description>
158109 <description>CM33_LOCK_REG_LOCK is 0</description>
158118 <description>Secure Control Duplicate</description>
158127 <description>Write Lock</description>
158134 …<description>Writes to this register and to the Memory and Peripheral RULE registers are not allow…
158139 …<description>Writes to this register and to the Memory and Peripheral RULE registers are allowed</…
158146 <description>Enable Secure Checking</description>
158153 <description>Enabled (restrictive mode)</description>
158158 <description>Disabled</description>
158165 <description>Enable Secure Privilege Checking</description>
158172 <description>Enabled (restrictive mode)</description>
158177 <description>Disabled</description>
158184 <description>Enable Non-Secure Privilege Checking</description>
158191 <description>Enabled (restrictive mode)</description>
158196 <description>Disabled</description>
158203 <description>Disable Violation Abort</description>
158210 …description>The violation detected by the secure checker will not cause an abort, but a secure_vio…
158215 … <description>The violation detected by the secure checker will cause an abort.</description>
158222 <description>Disable Strict Mode</description>
158229 <description>AHB master in strict mode</description>
158234 …<description>AHB master in tier mode. Can read and write to memories at same or below level.</desc…
158239 <description>AHB master in strict mode</description>
158244 <description>AHB master in strict mode</description>
158251 <description>IDAU All Non-Secure</description>
158258 …<description>IDAU is disabled, which means that all memories are attributed as non-secure memory.<…
158263 <description>IDAU is enabled (restrictive mode)</description>
158272 <description>Secure Control</description>
158281 <description>Write Lock</description>
158288 …<description>Writes to this register and to the Memory and Peripheral RULE registers are not allow…
158293 …<description>Writes to this register and to the Memory and Peripheral RULE registers are allowed</…
158300 <description>Enable Secure Checking</description>
158307 <description>Enabled (restrictive mode)</description>
158312 <description>Disabled</description>
158319 <description>Enable Secure Privilege Checking</description>
158326 <description>Enabled (restrictive mode)</description>
158331 <description>Disabled</description>
158338 <description>Enable Non-Secure Privilege Checking</description>
158345 <description>Enabled (restrictive mode)</description>
158350 <description>Disabled</description>
158357 <description>Disable Violation Abort</description>
158364 …description>The violation detected by the secure checker will not cause an abort, but a secure_vio…
158369 … <description>The violation detected by the secure checker will cause an abort.</description>
158376 <description>Disable Strict Mode</description>
158383 <description>AHB master in strict mode</description>
158388 …<description>AHB master in tier mode. Can read and write to memories at same or below level.</desc…
158393 <description>AHB master in strict mode</description>
158398 <description>AHB master in strict mode</description>
158405 <description>IDAU All Non-Secure</description>
158412 …<description>IDAU is disabled, which means that all memories are attributed as non-secure memory.<…
158417 <description>IDAU is enabled (restrictive mode)</description>
158428 <description>DAC</description>
158443 <description>Version Identifier Register</description>
158452 <description>Feature Identification Number</description>
158459 <description>Minor version number</description>
158466 <description>Major version number</description>
158475 <description>Parameter Register</description>
158484 <description>FIFO size</description>
158491 <description>FIFO depth is 4</description>
158496 <description>FIFO depth is 8</description>
158501 <description>FIFO depth is 16</description>
158506 <description>FIFO depth is 32</description>
158511 <description>FIFO depth is 64</description>
158516 <description>FIFO depth is 128</description>
158521 <description>FIFO depth is 256</description>
158530 <description>Data Register</description>
158539 <description>FIFO entry or Buffer entry</description>
158548 <description>Global Control Register</description>
158557 <description>DAC Enable</description>
158564 <description>The DAC system is disabled.</description>
158569 <description>The DAC system is enabled.</description>
158576 <description>DAC Reference Select</description>
158583 <description>The DAC selects VREFH1 as the reference voltage.</description>
158588 <description>The DAC selects VREFH2 as the reference voltage.</description>
158593 <description>The DAC selects VREFH3 as the reference voltage.</description>
158600 <description>FIFO Enable</description>
158607 …<description>FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes…
158612 …<description>FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conver…
158619 <description>Swing Back Mode</description>
158626 <description>Swing back mode disable</description>
158631 <description>Swing back mode enable</description>
158638 <description>DAC Trigger Select</description>
158645 <description>The DAC hardware trigger is selected.</description>
158650 <description>The DAC software trigger is selected.</description>
158657 <description>DAC periodic trigger mode enable</description>
158664 <description>DAC periodic trigger mode is disabled.</description>
158669 <description>DAC periodic trigger mode is enabled.</description>
158676 <description>Receive trigger from another DAC</description>
158683 … <description>DAC uses self hardware/software trigger as its trigger source.</description>
158688 …<description>DAC uses another DAC's hardware/software trigger as its trigger source. Then the two …
158695 <description>RCLK cycles before data latch</description>
158702 <description>Sync time is 1 RCLK cycle, RCLK <= 25MHz</description>
158707 <description>Sync time is 2 RCLK cycles, 25MHz < RCLK <= 50MHz</description>
158712 <description>Sync time is 3 RCLK cycles, 50MHz < RCLK <= 75MHz</description>
158717 … <description>Sync time is 4 RCLK cycles, 75MHz < RCLK <= 100MHz</description>
158722 … <description>Sync time is 5 RCLK cycles, 100MHz < RCLK <= 125MHz</description>
158727 … <description>Sync time is 6 RCLK cycles, 125MHz < RCLK <= 150MHz</description>
158732 … <description>Sync time is 7 RCLK cycles, 150MHz < RCLK <= 175MHz</description>
158737 … <description>Sync time is 8 RCLK cycles, 175MHz < RCLK <= 200MHz</description>
158742 … <description>Sync time is 9 RCLK cycles, 200MHz < RCLK <= 225MHz</description>
158747 … <description>Sync time is 10 RCLK cycles, 225MHz < RCLK <= 250MHz</description>
158752 … <description>Sync time is 11 RCLK cycles, 250MHz < RCLK <= 275MHz</description>
158757 … <description>Sync time is 12 RCLK cycles, 275MHz < RCLK <= 300MHz</description>
158762 … <description>Sync time is 13 RCLK cycles, 300MHz < RCLK <= 325MHz</description>
158767 … <description>Sync time is 14 RCLK cycles, 325MHz < RCLK <= 350MHz</description>
158772 … <description>Sync time is 15 RCLK cycles, 350MHz < RCLK <= 375MHz</description>
158777 … <description>Sync time is 16 RCLK cycles, 375MHz < RCLK <= 400MHz</description>
158784 <description>Buffer Enable</description>
158791 <description>Opamp is not used as buffer</description>
158796 <description>Opamp is used as buffer</description>
158803 <description>Internal PTAT Current Reference Select</description>
158810 <description>Internal PTAT Current Reference not selected</description>
158815 <description>Internal PTAT Current Reference selected</description>
158822 <description>Internal ZTC Current Reference Select</description>
158829 <description>Internal ZTC Current Reference not selected</description>
158834 <description>Internal ZTC Current Reference selected</description>
158841 <description>OPAMP as buffer, speed control signal</description>
158848 <description>Lower low power mode</description>
158853 <description>Low power mode</description>
158862 <description>DAC FIFO Control Register</description>
158871 <description>Watermark Level</description>
158880 <description>DAC FIFO Pointer Register</description>
158889 <description>FIFO Read Pointer</description>
158896 <description>FIFO Write Pointer</description>
158905 <description>FIFO Status Register</description>
158914 <description>FIFO Full Flag</description>
158921 <description>FIFO is not full</description>
158926 <description>FIFO is full</description>
158933 <description>FIFO Empty Flag</description>
158940 <description>FIFO is not empty</description>
158945 <description>FIFO is empty</description>
158952 <description>FIFO Watermark Status Flag</description>
158959 <description>Data in FIFO is more than watermark level</description>
158964 <description>Data in FIFO is less than or equal to watermark level</description>
158971 <description>Swing Back One Cycle Complete Flag</description>
158979 …<description>No swing back cycle has completed since the last time the flag was cleared.</descript…
158984 …<description>At least one swing back cycle has occurred since the last time the flag was cleared.<…
158991 <description>FIFO Overflow Flag</description>
158999 … <description>No overflow has occurred since the last time the flag was cleared.</description>
159004 …<description>At least one FIFO overflow has occurred since the last time the flag was cleared.</de…
159011 <description>FIFO Underflow Flag</description>
159019 … <description>No underflow has occurred since the last time the flag was cleared.</description>
159024 …<description>At least one trigger underflow has occurred since the last time the flag was cleared.…
159031 <description>Period trigger mode conversion complete flag</description>
159039 <description>PTG mode conversion is not completed or not started.</description>
159044 <description>PTG mode conversion is completed.</description>
159053 <description>Interrupt Enable Register</description>
159062 <description>FIFO Full Interrupt Enable</description>
159069 <description>FIFO Full interrupt is disabled.</description>
159074 <description>FIFO Full interrupt is enabled.</description>
159081 <description>FIFO Empty Interrupt Enable</description>
159088 <description>FIFO Empty interrupt is disabled.</description>
159093 <description>FIFO Empty interrupt is enabled.</description>
159100 <description>FIFO Watermark Interrupt Enable</description>
159107 <description>Watermark interrupt is disabled.</description>
159112 <description>Watermark interrupt is enabled.</description>
159119 <description>Swing back One Cycle Complete Interrupt Enable</description>
159126 <description>Swing back one time complete interrupt is disabled.</description>
159131 <description>Swing back one time complete interrupt is enabled.</description>
159138 <description>FIFO Overflow Interrupt Enable</description>
159145 <description>Overflow interrupt is disabled</description>
159150 <description>Overflow interrupt is enabled.</description>
159157 <description>FIFO Underflow Interrupt Enable</description>
159164 <description>Underflow interrupt is disabled.</description>
159169 <description>Underflow interrupt is enabled.</description>
159176 <description>PTG mode conversion complete interrupt enable</description>
159183 <description>PTG mode conversion complete interrupt is disabled.</description>
159188 <description>PTG mode conversion complete interrupt is enabled.</description>
159197 <description>DMA Enable Register</description>
159206 <description>FIFO Empty DMA Enable</description>
159213 <description>FIFO Empty DMA request is disabled.</description>
159218 <description>FIFO Empty DMA request is enabled.</description>
159225 <description>FIFO Watermark DMA Enable</description>
159232 <description>Watermark DMA request is disabled.</description>
159237 <description>Watermark DMA request is enabled.</description>
159246 <description>Reset Control Register</description>
159255 <description>Software Reset</description>
159262 <description>No effect</description>
159267 <description>Software reset</description>
159274 <description>FIFO Reset</description>
159281 <description>No effect</description>
159286 <description>FIFO reset</description>
159295 <description>Trigger Control Register</description>
159304 <description>Software Trigger</description>
159311 <description>The DAC soft trigger is not valid.</description>
159316 <description>The DAC soft trigger is valid.</description>
159325 <description>Periodic Trigger Control Register</description>
159334 <description>Periodic trigger number</description>
159341 <description>Periodic trigger period width</description>
159350 <description>Test Control Register</description>
159359 <description>Option mux control for ATX bus function</description>
159366 <description>Option mux control is off.</description>
159371 <description>Option mux control is on.</description>
159382 <description>LPCMP</description>
159394 <description>Version ID Register</description>
159403 <description>Feature Specification Number</description>
159410 <description>Round robin feature</description>
159417 <description>Minor Version Number</description>
159424 <description>Major Version Number</description>
159433 <description>Parameter Register</description>
159442 <description>DAC Resolution</description>
159449 <description>4 bit DAC</description>
159454 <description>6 bit DAC</description>
159459 <description>8 bit DAC</description>
159464 <description>10 bit DAC</description>
159469 <description>12 bit DAC</description>
159474 <description>14 bit DAC</description>
159479 <description>16 bit DAC</description>
159488 <description>Comparator Control Register 0</description>
159497 <description>Comparator Enable</description>
159504 … <description>Disable (The analog logic remains off and consumes no power.)</description>
159509 <description>Enable</description>
159516 <description>Comparator STOP Mode Enable</description>
159523 <description>Disable the analog comparator regardless of CMP_EN.</description>
159528 <description>Allow the analog comparator to be enabled by CMP_EN.</description>
159537 <description>Comparator Control Register 1</description>
159546 <description>Windowing Enable</description>
159553 <description>Disable</description>
159558 <description>Enable</description>
159565 <description>Sampling Enable</description>
159572 <description>Disable</description>
159577 <description>Enable</description>
159584 <description>DMA Enable</description>
159591 <description>Disable</description>
159596 <description>Enable</description>
159603 <description>Comparator Invert</description>
159610 <description>Do not invert</description>
159615 <description>Invert</description>
159622 <description>Comparator Output Select</description>
159629 <description>Use COUT (filtered)</description>
159634 <description>Use COUTA (unfiltered)</description>
159641 <description>Comparator Output Pin Enable</description>
159648 <description>Not available</description>
159653 <description>Available</description>
159660 <description>COUTA_OW Enable</description>
159667 <description>COUTA holds the last sampled value</description>
159672 <description>COUTA is defined by the COUTA_OW bit</description>
159679 <description>COUTA Output Level for Closed Window</description>
159686 <description>COUTA is 0</description>
159691 <description>COUTA is 1</description>
159698 <description>WINDOW/SAMPLE Signal Invert</description>
159705 <description>Do not invert</description>
159710 <description>Invert</description>
159717 <description>CMPO Event Window Close</description>
159724 <description>CMPO event cannot close the window</description>
159729 <description>CMPO event can close the window</description>
159736 <description>CMPO Event Select</description>
159743 <description>Rising edge</description>
159748 <description>Falling edge</description>
159753 <description>Both edges</description>
159760 <description>Filter Sample Count</description>
159767 …description>Filter is disabled. If SAMPLE_EN = 0, COUT = COUTA. If SAMPLE_EN = 1, COUT is a logic …
159772 … <description>1 consecutive sample (Comparator output is simply sampled.)</description>
159777 <description>2 consecutive samples</description>
159782 <description>3 consecutive samples</description>
159787 <description>4 consecutive samples</description>
159792 <description>5 consecutive samples</description>
159797 <description>6 consecutive samples</description>
159802 <description>7 consecutive samples</description>
159809 <description>Filter Sample Period</description>
159818 <description>Comparator Control Register 2</description>
159827 <description>CMP High Power Mode Select</description>
159834 <description>Low power(speed) comparison mode</description>
159839 <description>High power(speed) comparison mode</description>
159846 <description>CMP Nano Power Mode Select</description>
159853 <description>Disable (Mode is determined by CMP_HPMD.)</description>
159858 <description>Enable</description>
159865 <description>Comparator Hysteresis Control</description>
159872 <description>Level 0</description>
159877 <description>Level 1</description>
159882 <description>Level 2</description>
159887 <description>Level 3</description>
159894 <description>Plus Input MUX Select</description>
159901 <description>Input 0p</description>
159906 <description>Input 1p</description>
159911 <description>Input 2p</description>
159916 <description>Input 3p</description>
159921 <description>Input 4p</description>
159926 <description>Input 5p</description>
159931 <description>Internal DAC output</description>
159938 <description>Minus Input MUX Select</description>
159945 <description>Input 0m</description>
159950 <description>Input 1m</description>
159955 <description>Input 2m</description>
159960 <description>Input 3m</description>
159965 <description>Input 4m</description>
159970 <description>Input 5m</description>
159975 <description>Internal DAC output</description>
159984 <description>Comparator Control Register 3</description>
159993 <description>DAC Control Register</description>
160002 <description>DAC Enable</description>
160009 <description>Disable</description>
160014 <description>Enable</description>
160021 <description>DAC High Power Mode Select</description>
160028 <description>Disable</description>
160033 <description>Enable</description>
160040 <description>DAC Reference High Voltage Source Select</description>
160047 <description>vrefh0</description>
160052 <description>vrefh1</description>
160059 <description>DAC Output Voltage Select</description>
160068 <description>Interrupt Enable Register</description>
160077 <description>Comparator Flag Rising Interrupt Enable</description>
160084 <description>Disable</description>
160089 <description>Enable: Assert an interrupt when CFR is set.</description>
160096 <description>Comparator Flag Falling Interrupt Enable</description>
160103 <description>Disable</description>
160108 <description>Enable: Assert an interrupt when CFF is set.</description>
160117 <description>Comparator Status Register</description>
160126 <description>Analog Comparator Flag Rising</description>
160134 <description>Not detected</description>
160139 <description>Detected</description>
160146 <description>Analog Comparator Flag Falling</description>
160154 <description>Not detected</description>
160159 <description>Detected</description>
160166 <description>Analog Comparator Output</description>
160175 <description>Test Control Register</description>
160184 <description>DAC output to sense bus connection enable</description>
160191 <description>6 bit DAC output is not connected to sense bus</description>
160196 <description>6 bit DAC output is connected to sense bus</description>
160207 <description>LPCMP</description>
160218 <description>LPCMP</description>
160229 <description>OPAMP</description>
160241 <description>Version ID Register</description>
160250 <description>Feature Specification Number</description>
160257 <description>Minor Version Number</description>
160264 <description>Major Version Number</description>
160273 <description>Parameter Register</description>
160282 <description>PGA Function Option</description>
160289 <description>Core amplifier is enabled.</description>
160294 <description>PGA function is enabled.</description>
160303 <description>OPAMP control register</description>
160312 <description>OPAMP Enable</description>
160319 <description>OPAMP is disabled</description>
160324 <description>OPAMP is enabled</description>
160331 <description>Mode Selection</description>
160338 <description>Low noise mode.</description>
160343 <description>High speed mode.</description>
160350 <description>Bias Current Trim Selection</description>
160357 <description>Default.</description>
160362 <description>Increase current.</description>
160367 <description>Decrease current.</description>
160372 <description>Further decrease current.</description>
160379 <description>Internal Reference Voltage Selection</description>
160386 <description>Select vdda/2.</description>
160391 <description>Select vdda_3v.</description>
160396 <description>Select vssa_3v.</description>
160401 <description>Not allowed.</description>
160408 <description>ADC Channel Switch</description>
160415 <description>Positive Reference Voltage Selection</description>
160422 <description>Select vrefh3.</description>
160427 <description>Select vrefh0.</description>
160432 <description>Select vrefh1.</description>
160439 <description>Positive PGA Selection.</description>
160446 <description>Inverting gain application 2X.</description>
160451 <description>Inverting gain application 3X.</description>
160456 <description>Inverting gain application 5X.</description>
160461 <description>Inverting gain application 9X.</description>
160466 <description>Inverting gain application 17X.</description>
160471 <description>Inverting gain application 34X.</description>
160476 <description>Inverting gain application 65X.</description>
160483 <description>Negative PGA selection</description>
160490 <description>Buffer.</description>
160495 <description>Inverting gain application -1X.</description>
160500 <description>Inverting gain application -2X.</description>
160505 <description>Inverting gain application -4X.</description>
160510 <description>Inverting gain application -8X.</description>
160515 <description>Inverting gain application -16X.</description>
160520 <description>Inverting gain application -33X.</description>
160525 <description>Inverting gain application -64X.</description>
160536 <description>OPAMP</description>
160547 <description>OPAMP</description>
160558 <description>VREF</description>
160569 <description>VREF Version ID</description>
160578 <description>FEATURE</description>
160585 <description>MINOR</description>
160592 <description>MAJOR</description>
160601 <description>VREF Parameter</description>
160610 <description>VREF Control and Status Register</description>
160619 <description>HC Bandgap enabled</description>
160626 <description>HC Bandgap is disabled</description>
160631 <description>HC Bandgap is enabled</description>
160638 <description>Low Power Bandgap enable</description>
160645 <description>LP Bandgap is disabled</description>
160650 <description>LP Bandgap is enabled</description>
160657 <description>Low power buffer enable for lpbg with latch function enable</description>
160664 <description>disable</description>
160669 <description>enable</description>
160676 …<description>Chop oscillator enable. When set, the internal chopping operation is enabled and the …
160683 <description>Chop oscillator is disabled.</description>
160688 <description>Chop oscillator is enabled.</description>
160695 <description>Second order curvature compensation enable</description>
160702 <description>Disabled</description>
160707 <description>Enabled</description>
160714 <description>Regulator enable</description>
160721 <description>Internal 1.75 V regulator is disabled.</description>
160726 <description>Internal 1.75 V regulator is enabled.</description>
160733 <description>Negative channel to ADC select enable</description>
160740 <description>disable</description>
160745 <description>enable</description>
160752 <description>Positive channel to ADC select enable.</description>
160759 <description>disable</description>
160764 <description>enable</description>
160771 <description>Control bits for voltage reference selection</description>
160778 <description>Internal bandgap</description>
160783 <description>Low power buffered 1v</description>
160788 <description>Buffer 2.1v output</description>
160795 <description>Bit for the ground select</description>
160802 <description>vrefl_3v</description>
160807 <description>vssa</description>
160814 <description>Buffer21 mode control</description>
160821 <description>Internal buf21 Enable</description>
160828 <description>buf21 is disabled</description>
160833 <description>buf21 is enabled</description>
160840 <description>Internal HC Voltage Reference stable</description>
160847 <description>The module is disabled or not stable.</description>
160852 <description>The module is stable.</description>
160861 <description>VREF User Trim</description>
160870 <description>VREF 2.1V Trim Bits</description>
160877 <description>VREF Trim bits</description>
160884 <description>Min</description>
160889 <description>Max-31 mV</description>
160894 <description>Max</description>
160903 <description>This register is used to unlock read/write into test registers</description>
160912 <description>Test_unlock status bit</description>
160919 <description>Lock read/write into test register</description>
160924 <description>Unlock read/write into test register</description>
160931 <description>Test unlock value</description>
160940 <description>VREF Func Test reg</description>
160949 <description>Test MUX enable</description>
160956 <description>Disabled</description>
160961 <description>Enabled</description>
160968 <description>Test second order curvature compensation enable</description>
160975 <description>TRES disabled</description>
160980 <description>TRES enabled</description>
160989 <description>VREF Test Trim 0</description>
160998 <description>COMPLSB</description>
161005 <description>COMPMSB</description>
161012 <description>BPLSB</description>
161019 <description>BPMSB</description>
161026 <description>CHOPOSCTRIM</description>
161033 <description>P7_TRIM</description>
161040 <description>VREF 2.1V is enabled</description>
161045 <description>VREF 2.1V is disabled</description>
161052 <description>Amplifier Polarity</description>
161061 <description>VREF Test Trim 1</description>
161070 <description>LP Bandgap Voltage Trim</description>
161077 <description>LP_TCTRIM</description>
161084 <description>IREF_TRIM</description>
161095 <description>DAC</description>
161111 <description>Version Identifier Register</description>
161120 <description>Feature Identification Number</description>
161127 <description>Minor version number</description>
161134 <description>Major version number</description>
161143 <description>Parameter Register</description>
161152 <description>FIFO size</description>
161159 <description>FIFO depth is 4</description>
161164 <description>FIFO depth is 8</description>
161169 <description>FIFO depth is 16</description>
161174 <description>FIFO depth is 32</description>
161179 <description>FIFO depth is 64</description>
161184 <description>FIFO depth is 128</description>
161189 <description>FIFO depth is 256</description>
161198 <description>Data Register</description>
161207 <description>FIFO entry or Buffer entry</description>
161216 <description>Global Control Register</description>
161225 <description>DAC Enable</description>
161232 <description>The DAC system is disabled.</description>
161237 <description>The DAC system is enabled.</description>
161244 <description>DAC Reference Select</description>
161251 <description>The DAC selects VREFH1 as the reference voltage.</description>
161256 <description>The DAC selects VREFH2 as the reference voltage.</description>
161261 <description>The DAC selects VREFH3 as the reference voltage.</description>
161268 <description>FIFO Enable</description>
161275 …<description>FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes…
161280 …<description>FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conver…
161287 <description>Swing Back Mode</description>
161294 <description>Swing back mode disable</description>
161299 <description>Swing back mode enable</description>
161306 <description>DAC Trigger Select</description>
161313 <description>The DAC hardware trigger is selected.</description>
161318 <description>The DAC software trigger is selected.</description>
161325 <description>RCLK cycles before data latch</description>
161332 <description>Sync time is 1 RCLK cycle, RCLK <= 25MHz</description>
161337 <description>Sync time is 2 RCLK cycles, 25MHz < RCLK <= 50MHz</description>
161342 <description>Sync time is 3 RCLK cycles, 50MHz < RCLK <= 75MHz</description>
161347 … <description>Sync time is 4 RCLK cycles, 75MHz < RCLK <= 100MHz</description>
161352 … <description>Sync time is 5 RCLK cycles, 100MHz < RCLK <= 125MHz</description>
161357 … <description>Sync time is 6 RCLK cycles, 125MHz < RCLK <= 150MHz</description>
161362 … <description>Sync time is 7 RCLK cycles, 150MHz < RCLK <= 175MHz</description>
161367 … <description>Sync time is 8 RCLK cycles, 175MHz < RCLK <= 200MHz</description>
161372 … <description>Sync time is 9 RCLK cycles, 200MHz < RCLK <= 225MHz</description>
161377 … <description>Sync time is 10 RCLK cycles, 225MHz < RCLK <= 250MHz</description>
161382 … <description>Sync time is 11 RCLK cycles, 250MHz < RCLK <= 275MHz</description>
161387 … <description>Sync time is 12 RCLK cycles, 275MHz < RCLK <= 300MHz</description>
161392 … <description>Sync time is 13 RCLK cycles, 300MHz < RCLK <= 325MHz</description>
161397 … <description>Sync time is 14 RCLK cycles, 325MHz < RCLK <= 350MHz</description>
161402 … <description>Sync time is 15 RCLK cycles, 350MHz < RCLK <= 375MHz</description>
161407 … <description>Sync time is 16 RCLK cycles, 375MHz < RCLK <= 400MHz</description>
161414 <description>Buffer Enable</description>
161421 <description>Opamp is not used as buffer</description>
161426 <description>Opamp is used as buffer</description>
161433 <description>Internal PTAT Current Reference Select</description>
161440 <description>Internal PTAT Current Reference not selected</description>
161445 <description>Internal PTAT Current Reference selected</description>
161452 <description>Internal ZTC Current Reference Select</description>
161459 <description>Internal ZTC Current Reference not selected</description>
161464 <description>Internal ZTC Current Reference selected</description>
161471 <description>OPAMP as buffer, speed control signal</description>
161478 <description>Lower low power mode</description>
161483 <description>Low power mode</description>
161492 <description>DAC FIFO Control Register</description>
161501 <description>Watermark Level</description>
161510 <description>DAC FIFO Pointer Register</description>
161519 <description>FIFO Read Pointer</description>
161526 <description>FIFO Write Pointer</description>
161535 <description>FIFO Status Register</description>
161544 <description>FIFO Full Flag</description>
161551 <description>FIFO is not full</description>
161556 <description>FIFO is full</description>
161563 <description>FIFO Empty Flag</description>
161570 <description>FIFO is not empty</description>
161575 <description>FIFO is empty</description>
161582 <description>FIFO Watermark Status Flag</description>
161589 <description>Data in FIFO is more than watermark level</description>
161594 <description>Data in FIFO is less than or equal to watermark level</description>
161601 <description>Swing Back One Cycle Complete Flag</description>
161609 …<description>No swing back cycle has completed since the last time the flag was cleared.</descript…
161614 …<description>At least one swing back cycle has occurred since the last time the flag was cleared.<…
161621 <description>FIFO Overflow Flag</description>
161629 … <description>No overflow has occurred since the last time the flag was cleared.</description>
161634 …<description>At least one FIFO overflow has occurred since the last time the flag was cleared.</de…
161641 <description>FIFO Underflow Flag</description>
161649 … <description>No underflow has occurred since the last time the flag was cleared.</description>
161654 …<description>At least one trigger underflow has occurred since the last time the flag was cleared.…
161663 <description>Interrupt Enable Register</description>
161672 <description>FIFO Full Interrupt Enable</description>
161679 <description>FIFO Full interrupt is disabled.</description>
161684 <description>FIFO Full interrupt is enabled.</description>
161691 <description>FIFO Empty Interrupt Enable</description>
161698 <description>FIFO Empty interrupt is disabled.</description>
161703 <description>FIFO Empty interrupt is enabled.</description>
161710 <description>FIFO Watermark Interrupt Enable</description>
161717 <description>Watermark interrupt is disabled.</description>
161722 <description>Watermark interrupt is enabled.</description>
161729 <description>Swing back One Cycle Complete Interrupt Enable</description>
161736 <description>Swing back one time complete interrupt is disabled.</description>
161741 <description>Swing back one time complete interrupt is enabled.</description>
161748 <description>FIFO Overflow Interrupt Enable</description>
161755 <description>Overflow interrupt is disabled</description>
161760 <description>Overflow interrupt is enabled.</description>
161767 <description>FIFO Underflow Interrupt Enable</description>
161774 <description>Underflow interrupt is disabled.</description>
161779 <description>Underflow interrupt is enabled.</description>
161788 <description>DMA Enable Register</description>
161797 <description>FIFO Empty DMA Enable</description>
161804 <description>FIFO Empty DMA request is disabled.</description>
161809 <description>FIFO Empty DMA request is enabled.</description>
161816 <description>FIFO Watermark DMA Enable</description>
161823 <description>Watermark DMA request is disabled.</description>
161828 <description>Watermark DMA request is enabled.</description>
161837 <description>Reset Control Register</description>
161846 <description>Software Reset</description>
161853 <description>No effect</description>
161858 <description>Software reset</description>
161865 <description>FIFO Reset</description>
161872 <description>No effect</description>
161877 <description>FIFO reset</description>
161886 <description>Trigger Control Register</description>
161895 <description>Software Trigger</description>
161902 <description>The DAC soft trigger is not valid.</description>
161907 <description>The DAC soft trigger is valid.</description>
161916 <description>Test Control Register</description>
161925 <description>Option mux control for ATX bus function</description>
161932 <description>Option mux control is off.</description>
161937 <description>Option mux control is on.</description>
161948 <description>DAC</description>
161963 <description>FlexSPI</description>
161978 <description>Module Control Register 0</description>
161987 <description>Software Reset</description>
161994 <description>Module Disable</description>
162001 <description>Sample Clock source selection for Flash Reading</description>
162008 …<description>Dummy Read strobe generated by FlexSPI Controller and loopback internally.</descripti…
162013 …<description>Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.</descrip…
162018 <description>SCLK output clock and loopback from SCLK pad</description>
162023 <description>Flash provided Read strobe and input from DQS pad</description>
162030 …<description>The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter f…
162037 <description>Divided by 1</description>
162042 <description>Divided by 2</description>
162047 <description>Divided by 3</description>
162052 <description>Divided by 4</description>
162057 <description>Divided by 5</description>
162062 <description>Divided by 6</description>
162067 <description>Divided by 7</description>
162072 <description>Divided by 8</description>
162079 <description>Half Speed Serial Flash access Enable.</description>
162086 … <description>Disable divide by 2 of serial flash clock for half speed commands.</description>
162091 … <description>Enable divide by 2 of serial flash clock for half speed commands.</description>
162098 <description>Doze mode enable bit</description>
162105 …<description>Doze mode support disabled. AHB clock and serial clock will not be gated off when the…
162110 …<description>Doze mode support enabled. AHB clock and serial clock will be gated off when there is…
162117 …description>This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_…
162124 <description>Disable.</description>
162129 <description>Enable.</description>
162136 …description>This bit is used to force SCLK output free-running. For FPGA applications, external de…
162143 <description>Disable.</description>
162148 <description>Enable.</description>
162155 …description>This bit is used to enable/disable data learning feature. When data learning is disabl…
162162 <description>Disable.</description>
162167 <description>Enable.</description>
162174 <description>Time out wait cycle for IP command grant.</description>
162181 <description>Timeout wait cycle for AHB command grant.</description>
162190 <description>Module Control Register 1</description>
162199 …description>AHB Read/Write access to Serial Flash Memory space will timeout if not data received f…
162206 …<description>Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Cl…
162215 <description>Module Control Register 2</description>
162224 …description>This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatica…
162231 …<description>AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.…
162236 …<description>AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.</de…
162243 …description>The sampling clock phase selection will be reset to phase 0 when this bit is written w…
162250 …<description>All external devices are same devices (both in types and size) for A1/A2/B1/B2.</desc…
162257 …description>In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be a…
162262 …description>FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. …
162269 …description>B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK).…
162276 …<description>B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.</de…
162281 …<description>B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK…
162288 …<description>Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resu…
162297 <description>AHB Bus Control Register</description>
162306 … <description>Parallel mode enabled for AHB triggered Command (both read and write) .</description>
162313 <description>Flash will be accessed in Individual mode.</description>
162318 <description>Flash will be accessed in Parallel mode.</description>
162325 <description>Enable AHB bus cachable read access support.</description>
162332 …<description>Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether …
162337 …<description>Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hi…
162344 …description>Enable AHB bus bufferable write access support. This field affects the last beat of AH…
162351 …description>Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI …
162356 …description>Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the A…
162363 <description>AHB Read Prefetch Enable.</description>
162370 …<description>AHB Read Address option bit. This option bit is intend to remove AHB burst start addr…
162377 …description>There is AHB read burst start address alignment limitation when flash is accessed in p…
162382 …description>There is no AHB read burst start address alignment limitation. FlexSPI will fetch more…
162389 <description>AHB Read Size Alignment</description>
162396 …<description>AHB read size will be decided by other register setting like PREFETCH_EN</description>
162401 … <description>AHB read size to up size to 8 bytes aligned, no prefetching</description>
162408 …<description>Decides all AHB read/write boundary. All access cross the boundary will be divided in…
162415 <description>No limit</description>
162420 <description>1 KBytes</description>
162425 <description>512 Bytes</description>
162430 <description>256 Bytes</description>
162439 <description>Interrupt Enable Register</description>
162448 … <description>IP triggered Command Sequences Execution finished interrupt enable.</description>
162455 … <description>IP triggered Command Sequences Grant Timeout interrupt enable.</description>
162462 … <description>AHB triggered Command Sequences Grant Timeout interrupt enable.</description>
162469 … <description>IP triggered Command Sequences Error Detected interrupt enable.</description>
162476 … <description>AHB triggered Command Sequences Error Detected interrupt enable.</description>
162483 <description>IP RX FIFO WaterMark available interrupt enable.</description>
162490 <description>IP TX FIFO WaterMark empty interrupt enable.</description>
162497 <description>Data Learning failed interrupt enable.</description>
162504 …<description>SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.<…
162511 …<description>SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.…
162518 … <description>AHB Bus timeout interrupt.Refer Interrupts chapter for more details.</description>
162525 …<description>Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details…
162532 <description>AHB read gcm error interrupt enable.</description>
162541 <description>Interrupt Register</description>
162550 …description>IP triggered Command Sequences Execution finished interrupt. This interrupt is also ge…
162558 <description>IP triggered Command Sequences Grant Timeout interrupt.</description>
162566 <description>AHB triggered Command Sequences Grant Timeout interrupt.</description>
162574 …description>IP triggered Command Sequences Error Detected interrupt. When an error detected for IP…
162582 …description>AHB triggered Command Sequences Error Detected interrupt. When an error detected for A…
162590 <description>IP RX FIFO watermark available interrupt.</description>
162598 <description>IP TX FIFO watermark empty interrupt.</description>
162606 <description>Data Learning failed interrupt.</description>
162614 …<description>SCLK is stopped during command sequence because Async RX FIFO full interrupt.</descri…
162622 …<description>SCLK is stopped during command sequence because Async TX FIFO empty interrupt.</descr…
162630 … <description>AHB Bus timeout interrupt.Refer Interrupts chapter for more details.</description>
162638 <description>Sequence execution timeout interrupt.</description>
162646 <description>AHB read gcm error interrupt.</description>
162656 <description>LUT Key Register</description>
162665 <description>The Key to lock or unlock LUT.</description>
162674 <description>LUT Control Register</description>
162683 <description>Lock LUT</description>
162690 <description>Unlock LUT</description>
162699 <description>AHB RX Buffer 0 Control Register 0</description>
162708 <description>AHB RX Buffer Size in 64 bits.</description>
162715 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162722 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162729 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162738 <description>AHB RX Buffer 1 Control Register 0</description>
162747 <description>AHB RX Buffer Size in 64 bits.</description>
162754 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162761 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162768 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162777 <description>AHB RX Buffer 2 Control Register 0</description>
162786 <description>AHB RX Buffer Size in 64 bits.</description>
162793 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162800 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162807 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162816 <description>AHB RX Buffer 3 Control Register 0</description>
162825 <description>AHB RX Buffer Size in 64 bits.</description>
162832 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162839 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162846 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162855 <description>AHB RX Buffer 4 Control Register 0</description>
162864 <description>AHB RX Buffer Size in 64 bits.</description>
162871 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162878 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162885 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162894 <description>AHB RX Buffer 5 Control Register 0</description>
162903 <description>AHB RX Buffer Size in 64 bits.</description>
162910 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162917 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162924 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162933 <description>AHB RX Buffer 6 Control Register 0</description>
162942 <description>AHB RX Buffer Size in 64 bits.</description>
162949 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162956 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
162963 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
162972 <description>AHB RX Buffer 7 Control Register 0</description>
162981 <description>AHB RX Buffer Size in 64 bits.</description>
162988 …<description>This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).</descriptio…
162995 …<description>This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the high…
163002 …<description>AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.</description>
163011 <description>Flash Control Register 0</description>
163020 <description>Flash Size in KByte.</description>
163027 <description>AHB write access split function control.</description>
163034 <description>AHB read access split function control.</description>
163043 <description>Flash Control Register 0</description>
163052 <description>Flash Size in KByte.</description>
163059 <description>AHB write access split function control.</description>
163066 <description>AHB read access split function control.</description>
163075 <description>Flash Control Register 0</description>
163084 <description>Flash Size in KByte.</description>
163091 <description>AHB write access split function control.</description>
163098 <description>AHB read access split function control.</description>
163107 <description>Flash Control Register 0</description>
163116 <description>Flash Size in KByte.</description>
163123 <description>AHB write access split function control.</description>
163130 <description>AHB read access split function control.</description>
163142 <description>Flash Control Register 1</description>
163151 <description>Serial Flash CS setup time.</description>
163158 <description>Serial Flash CS Hold time.</description>
163165 <description>Word Addressable.</description>
163172 <description>Column Address Size.</description>
163179 <description>CS interval unit</description>
163186 <description>The CS interval unit is 1 serial clock cycle</description>
163191 <description>The CS interval unit is 256 serial clock cycle</description>
163198 …description>This field is used to set the minimum interval between flash device Chip selection dea…
163210 <description>Flash Control Register 2</description>
163219 <description>Sequence Index for AHB Read triggered Command in LUT.</description>
163226 <description>Sequence Number for AHB Read triggered Command in LUT.</description>
163233 <description>Sequence Index for AHB Write triggered Command.</description>
163240 <description>Sequence Number for AHB Write triggered Command.</description>
163247 …description>For certain devices (such as FPGA), it need some time to write data into internal memo…
163254 <description>AWRWAIT unit</description>
163261 <description>The AWRWAIT unit is 2 ahb clock cycle</description>
163266 <description>The AWRWAIT unit is 8 ahb clock cycle</description>
163271 <description>The AWRWAIT unit is 32 ahb clock cycle</description>
163276 <description>The AWRWAIT unit is 128 ahb clock cycle</description>
163281 <description>The AWRWAIT unit is 512 ahb clock cycle</description>
163286 <description>The AWRWAIT unit is 2048 ahb clock cycle</description>
163291 <description>The AWRWAIT unit is 8192 ahb clock cycle</description>
163296 <description>The AWRWAIT unit is 32768 ahb clock cycle</description>
163303 …<description>Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer P…
163312 <description>Flash Control Register 4</description>
163321 …<description>Write mask option bit 1. This option bit could be used to remove AHB write burst star…
163328 …description>DQS pin will be used as Write Mask when writing to external device. There is no limita…
163333 …description>DQS pin will not be used as Write Mask when writing to external device. There is limit…
163340 …description>Write mask enable bit for flash device on port A. When write mask function is needed f…
163347 …<description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external devi…
163352 …<description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output w…
163359 …description>Write mask enable bit for flash device on port B. When write mask function is needed f…
163366 …<description>Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external devi…
163371 …<description>Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output w…
163378 …<description>Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.…
163385 … <description>Disable the address shift logic for lower density of 16 bit PSRAM.</description>
163394 <description>IP Control Register 0</description>
163403 <description>Serial Flash Address for IP command.</description>
163412 <description>IP Control Register 1</description>
163421 <description>Flash Read/Program Data Size (in Bytes) for IP command.</description>
163428 <description>Sequence Index in LUT for IP command.</description>
163435 <description>Sequence Number for IP command: ISEQNUM+1.</description>
163442 <description>Parallel mode Enabled for IP command.</description>
163449 <description>Flash will be accessed in Individual mode.</description>
163454 <description>Flash will be accessed in Parallel mode.</description>
163463 <description>IP Command Register</description>
163472 <description>Setting this bit will trigger an IP Command.</description>
163481 <description>Data Learn Pattern Register</description>
163490 <description>Data Learning Pattern.</description>
163499 <description>IP RX FIFO Control Register</description>
163508 <description>Clear all valid data entries in IP RX FIFO.</description>
163515 <description>IP RX FIFO reading by DMA enabled.</description>
163522 <description>IP RX FIFO would be read by processor.</description>
163527 <description>IP RX FIFO would be read by DMA.</description>
163534 <description>Watermark level is (RXWMRK+1)*64 Bits.</description>
163543 <description>IP TX FIFO Control Register</description>
163552 <description>Clear all valid data entries in IP TX FIFO.</description>
163559 <description>IP TX FIFO filling by DMA enabled.</description>
163566 <description>IP TX FIFO would be filled by processor.</description>
163571 <description>IP TX FIFO would be filled by DMA.</description>
163578 <description>Watermark level is (TXWMRK+1)*64 Bits.</description>
163590 <description>DLL Control Register 0</description>
163599 <description>DLL calibration enable.</description>
163606 …description>Software could force a reset on DLL by setting this field to 0x1. This will cause the …
163613 …description>The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of re…
163620 … <description>Slave clock delay line delay cell number selection override enable.</description>
163627 … <description>Slave clock delay line delay cell number selection override value.</description>
163636 <description>Status Register 0</description>
163645 …<description>This status bit indicates the state machine in SEQ_CTL is idle and there is command s…
163652 …description>This status bit indicates the state machine in ARB_CTL is busy and there is command se…
163659 …description>This status field indicates the trigger source of current command sequence granted by …
163666 <description>Triggered by AHB read command (triggered by AHB read).</description>
163671 … <description>Triggered by AHB write command (triggered by AHB Write).</description>
163676 … <description>Triggered by IP command (triggered by setting register bit IPCMD.TRG).</description>
163681 <description>Triggered by suspended command (resumed).</description>
163688 …<description>Indicate the sampling clock phase selection on Port A after Data Learning.</descripti…
163695 …<description>Indicate the sampling clock phase selection on Port B after Data Learning.</descripti…
163704 <description>Status Register 1</description>
163713 …description>Indicates the sequence index when an AHB command error is detected. This field will be…
163720 …description>Indicates the Error Code when AHB command Error detected. This field will be cleared w…
163727 <description>No error.</description>
163732 … <description>AHB Write command with JMP_ON_CS instruction used in the sequence.</description>
163737 <description>There is unknown instruction opcode in the sequence.</description>
163742 … <description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description>
163747 … <description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description>
163752 <description>Sequence execution timeout.</description>
163759 …description>Indicates the sequence Index when IP command error detected. This field will be cleare…
163766 …<description>Indicates the Error Code when IP command Error detected. This field will be cleared w…
163773 <description>No error.</description>
163778 … <description>IP command with JMP_ON_CS instruction used in the sequence.</description>
163783 <description>There is unknown instruction opcode in the sequence.</description>
163788 … <description>Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.</description>
163793 … <description>Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.</description>
163798 …<description>Flash access start address exceed the whole flash address range (A1/A2/B1/B2).</descr…
163803 <description>Sequence execution timeout.</description>
163808 <description>Flash boundary crossed.</description>
163817 <description>Status Register 2</description>
163826 <description>Flash A sample clock slave delay line locked.</description>
163833 <description>Flash A sample clock reference delay line locked.</description>
163840 … <description>Flash A sample clock slave delay line delay cell number selection .</description>
163847 … <description>Flash A sample clock reference delay line delay cell number selection.</description>
163854 <description>Flash B sample clock slave delay line locked.</description>
163861 <description>Flash B sample clock reference delay line locked.</description>
163868 … <description>Flash B sample clock slave delay line delay cell number selection.</description>
163875 … <description>Flash B sample clock reference delay line delay cell number selection.</description>
163884 <description>AHB Suspend Status Register</description>
163893 … <description>Indicates if an AHB read prefetch command sequence has been suspended.</description>
163900 <description>AHB RX BUF ID for suspended command sequence.</description>
163907 <description>Left Data size for suspended command sequence (in byte).</description>
163916 <description>IP RX FIFO Status Register</description>
163925 <description>Fill level of IP RX FIFO.</description>
163932 <description>Total Read Data Counter: RDCNTR * 64 Bits.</description>
163941 <description>IP TX FIFO Status Register</description>
163950 <description>Fill level of IP TX FIFO.</description>
163957 <description>Total Write Data Counter: WRCNTR * 64 Bits.</description>
163968 <description>IP RX FIFO Data Register x</description>
163977 <description>RX Data</description>
163988 <description>IP TX FIFO Data Register x</description>
163997 <description>TX Data</description>
164008 <description>LUT x</description>
164017 <description>OPERAND0</description>
164024 <description>NUM_PADS0</description>
164031 <description>OPCODE</description>
164038 <description>OPERAND1</description>
164045 <description>NUM_PADS1</description>
164052 <description>OPCODE1</description>
164061 <description>HADDR REMAP START ADDR</description>
164070 <description>AHB Bus address remap function enable</description>
164077 <description>HADDR REMAP Disabled</description>
164082 <description>HADDR REMAP Enabled</description>
164089 <description>HADDR remap range's start addr, 4K aligned</description>
164098 <description>HADDR REMAP END ADDR</description>
164107 <description>HADDR remap range's end addr, 4K aligned</description>
164116 <description>HADDR REMAP OFFSET</description>
164125 …<description>HADDR offset field, remapped address will be ADDR[31:12]=ADDR_original[31:12]+ADDROFF…
164134 <description>IPED function control</description>
164143 <description>Drive IPED interface i_config.</description>
164150 <description>Drive IPED interface i_enable</description>
164157 <description>IP write IPED CTR mode encryption enable</description>
164164 <description>AHB write IPED CTR mode encryption enable</description>
164171 <description>AHB read IPED CTR mode decryption enable</description>
164178 <description>IP GCM mode command write OTA region</description>
164185 <description>IP write GCM mode enable</description>
164192 <description>AHB write IPED GCM mode encryption enable</description>
164199 <description>AHB read IPED GCM mode decryption enable</description>
164208 <description>IPED context control 0</description>
164217 …<description>Controls the RW properties of this field and region 0 context registers (CTX0_xxxx).<…
164224 …<description>Controls the RW properties of this field and region 1 context registers (CTX1_xxxx).<…
164231 …<description>Controls the RW properties of this field and region 2 context registers (CTX2_xxxx).<…
164238 …<description>Controls the RW properties of this field and region 3 context registers (CTX3_xxxx).<…
164245 …<description>Controls the RW properties of this field and region 4 context registers (CTX4_xxxx).<…
164252 …<description>Controls the RW properties of this field and region 5 context registers (CTX5_xxxx).<…
164259 …<description>Controls the RW properties of this field and region 6 context registers (CTX6_xxxx).<…
164266 …<description>Controls the RW properties of this field and region 7 context registers (CTX7_xxxx).<…
164273 …<description>Controls the RW properties of this field and region 8 context registers (CTX8_xxxx).<…
164280 …<description>Controls the RW properties of this field and region 9 context registers (CTX9_xxxx).<…
164287 …<description>Controls the RW properties of this field and region 10 context registers (CTX10_xxxx)…
164294 …<description>Controls the RW properties of this field and region 11 context registers (CTX11_xxxx)…
164301 …<description>Controls the RW properties of this field and region 12 context registers (CTX12_xxxx)…
164308 …<description>Controls the RW properties of this field and region 13 context registers (CTX13_xxxx)…
164315 …<description>Controls the RW properties of this field and region 14 context registers (CTX14_xxxx)…
164322 …<description>Controls the RW properties of this field and region 15 context registers (CTX15_xxxx)…
164331 <description>IPED context control 1</description>
164340 …<description>Controls the RW properties of this field and region 0 context registers (CTX0_xxxx).<…
164347 …<description>Controls the RW properties of this field and region 1 context registers (CTX1_xxxx).<…
164354 …<description>Controls the RW properties of this field and region 2 context registers (CTX2_xxxx).<…
164361 …<description>Controls the RW properties of this field and region 3 context registers (CTX3_xxxx).<…
164368 …<description>Controls the RW properties of this field and region 4 context registers (CTX4_xxxx).<…
164375 …<description>Controls the RW properties of this field and region 5 context registers (CTX5_xxxx).<…
164382 …<description>Controls the RW properties of this field and region 6 context registers (CTX6_xxxx).<…
164389 …<description>Controls the RW properties of this field and region 7 context registers (CTX7_xxxx).<…
164396 …<description>Controls the RW properties of this field and region 8 context registers (CTX8_xxxx).<…
164403 …<description>Controls the RW properties of this field and region 9 context registers (CTX9_xxxx).<…
164410 …<description>Controls the RW properties of this field and region 10 context registers (CTX10_xxxx)…
164417 …<description>Controls the RW properties of this field and region 11 context registers (CTX11_xxxx)…
164424 …<description>Controls the RW properties of this field and region 12 context registers (CTX12_xxxx)…
164431 …<description>Controls the RW properties of this field and region 13 context registers (CTX13_xxxx)…
164438 …<description>Controls the RW properties of this field and region 14 context registers (CTX14_xxxx)…
164445 …<description>Controls the RW properties of this field and region 15 context registers (CTX15_xxxx)…
164454 <description>IPED context0 IV0</description>
164463 <description>Lowest 32 bits of IV for region 0.</description>
164472 <description>IPED context0 IV1</description>
164481 <description>Highest 32 bits of IV for region 0.</description>
164490 <description>Start address of region 0</description>
164499 <description>If this bit is 1, current region is GCM mode region.</description>
164506 …<description>Start address of region 0. Minimal 256 Bytes aligned. It is system address.</descript…
164515 <description>End address of region 0</description>
164524 …<description>End address of region 0. Minimal 256 Bytes aligned. It is system address.</descriptio…
164533 <description>IPED context0 AAD0</description>
164542 <description>Lowest 32 bits of AAD for region 0.</description>
164551 <description>IPED context0 AAD1</description>
164560 <description>Highest 32 bits of AAD for region 0.</description>
164569 <description>IPED context1 IV0</description>
164578 <description>Lowest 32 bits of IV for region 1.</description>
164587 <description>IPED context1 IV1</description>
164596 <description>Highest 32 bits of IV for region 1.</description>
164605 <description>Start address of region 1</description>
164614 <description>If this bit is 1, current region is GCM mode region.</description>
164621 …<description>Start address of region 1. Minimal 256 Bytes aligned. It is system address.</descript…
164630 <description>End address of region 1</description>
164639 …<description>End address of region 1. Minimal 256 Bytes aligned. It is system address.</descriptio…
164648 <description>IPED context1 AAD0</description>
164657 <description>Lowest 32 bits of AAD for region 1.</description>
164666 <description>IPED context1 AAD1</description>
164675 <description>Highest 32 bits of AAD for region 1.</description>
164684 <description>IPED context2 IV0</description>
164693 <description>Lowest 32 bits of IV for region 2.</description>
164702 <description>IPED context2 IV1</description>
164711 <description>Highest 32 bits of IV for region 2.</description>
164720 <description>Start address of region 2</description>
164729 <description>If this bit is 1, current region is GCM mode region.</description>
164736 …<description>Start address of region 2. Minimal 256 Bytes aligned. It is system address.</descript…
164745 <description>End address of region 2</description>
164754 …<description>End address of region 2. Minimal 256 Bytes aligned. It is system address.</descriptio…
164763 <description>IPED context2 AAD0</description>
164772 <description>Lowest 32 bits of AAD for region 2.</description>
164781 <description>IPED context2 AAD1</description>
164790 <description>Highest 32 bits of AAD for region 2.</description>
164799 <description>IPED context3 IV0</description>
164808 <description>Lowest 32 bits of IV for region 3.</description>
164817 <description>IPED context3 IV1</description>
164826 <description>Highest 32 bits of IV for region 3.</description>
164835 <description>Start address of region 3</description>
164844 <description>If this bit is 1, current region is GCM mode region.</description>
164851 …<description>Start address of region 3. Minimal 256 Bytes aligned. It is system address.</descript…
164860 <description>End address of region 3</description>
164869 …<description>End address of region 3. Minimal 256 Bytes aligned. It is system address.</descriptio…
164878 <description>IPED context3 AAD0</description>
164887 <description>Lowest 32 bits of AAD for region 3.</description>
164896 <description>IPED context3 AAD1</description>
164905 <description>Highest 32 bits of AAD for region 3.</description>
164914 <description>IPED context4 IV0</description>
164923 <description>Lowest 32 bits of IV for region 4.</description>
164932 <description>IPED context4 IV1</description>
164941 <description>Highest 32 bits of IV for region 4.</description>
164950 <description>Start address of region 4</description>
164959 <description>If this bit is 1, current region is GCM mode region.</description>
164966 …<description>Start address of region 4. Minimal 256 Bytes aligned. It is system address.</descript…
164975 <description>End address of region 4</description>
164984 …<description>End address of region 4. Minimal 256 Bytes aligned. It is system address.</descriptio…
164993 <description>IPED context4 AAD0</description>
165002 <description>Lowest 32 bits of AAD for region 4.</description>
165011 <description>IPED context4 AAD1</description>
165020 <description>Highest 32 bits of AAD for region 4.</description>
165029 <description>IPED context5 IV0</description>
165038 <description>Lowest 32 bits of IV for region 5.</description>
165047 <description>IPED context5 IV1</description>
165056 <description>Highest 32 bits of IV for region 5.</description>
165065 <description>Start address of region 5</description>
165074 <description>If this bit is 1, current region is GCM mode region.</description>
165081 …<description>Start address of region 5. Minimal 256 Bytes aligned. It is system address.</descript…
165090 <description>End address of region 5</description>
165099 …<description>End address of region 5. Minimal 256 Bytes aligned. It is system address.</descriptio…
165108 <description>IPED context5 AAD0</description>
165117 <description>Lowest 32 bits of AAD for region 5.</description>
165126 <description>IPED context5 AAD1</description>
165135 <description>Highest 32 bits of AAD for region 5.</description>
165144 <description>IPED context6 IV0</description>
165153 <description>Lowest 32 bits of IV for region 6.</description>
165162 <description>IPED context6 IV1</description>
165171 <description>Highest 32 bits of IV for region 6.</description>
165180 <description>Start address of region 6</description>
165189 <description>If this bit is 1, current region is GCM mode region.</description>
165196 …<description>Start address of region 6. Minimal 256 Bytes aligned. It is system address.</descript…
165205 <description>End address of region 6</description>
165214 …<description>End address of region 6. Minimal 256 Bytes aligned. It is system address.</descriptio…
165223 <description>IPED context6 AAD0</description>
165232 <description>Lowest 32 bits of AAD for region 6.</description>
165241 <description>IPED context6 AAD1</description>
165250 <description>Highest 32 bits of AAD for region 6.</description>
165259 <description>IPED context7 IV0</description>
165268 <description>Lowest 32 bits of IV for region 7.</description>
165277 <description>IPED context7 IV1</description>
165286 <description>Highest 32 bits of IV for region 7.</description>
165295 <description>Start address of region 7</description>
165304 <description>If this bit is 1, current region is GCM mode region.</description>
165311 …<description>Start address of region 7. Minimal 256 Bytes aligned. It is system address.</descript…
165320 <description>End address of region 7</description>
165329 …<description>End address of region 7. Minimal 256 Bytes aligned. It is system address.</descriptio…
165338 <description>IPED context7 AAD0</description>
165347 <description>Lowest 32 bits of AAD for region 7.</description>
165356 <description>IPED context7 AAD1</description>
165365 <description>Highest 32 bits of AAD for region 7.</description>
165374 <description>IPED context8 IV0</description>
165383 <description>Lowest 32 bits of IV for region 8.</description>
165392 <description>IPED context8 IV1</description>
165401 <description>Highest 32 bits of IV for region 8.</description>
165410 <description>Start address of region 8</description>
165419 <description>If this bit is 1, current region is GCM mode region.</description>
165426 …<description>Start address of region 8. Minimal 256 Bytes aligned. It is system address.</descript…
165435 <description>End address of region 8</description>
165444 …<description>End address of region 8. Minimal 256 Bytes aligned. It is system address.</descriptio…
165453 <description>IPED context8 AAD0</description>
165462 <description>Lowest 32 bits of AAD for region 8.</description>
165471 <description>IPED context8 AAD1</description>
165480 <description>Highest 32 bits of AAD for region 8.</description>
165489 <description>IPED context9 IV0</description>
165498 <description>Lowest 32 bits of IV for region 9.</description>
165507 <description>IPED context9 IV1</description>
165516 <description>Highest 32 bits of IV for region 9.</description>
165525 <description>Start address of region 9</description>
165534 <description>If this bit is 1, current region is GCM mode region.</description>
165541 …<description>Start address of region 9. Minimal 256 Bytes aligned. It is system address.</descript…
165550 <description>End address of region 9</description>
165559 …<description>End address of region 9. Minimal 256 Bytes aligned. It is system address.</descriptio…
165568 <description>IPED context9 AAD0</description>
165577 <description>Lowest 32 bits of AAD for region 9.</description>
165586 <description>IPED context9 AAD1</description>
165595 <description>Highest 32 bits of AAD for region 9.</description>
165604 <description>IPED context10 IV0</description>
165613 <description>Lowest 32 bits of IV for region 10.</description>
165622 <description>IPED context10 IV1</description>
165631 <description>Highest 32 bits of IV for region 10.</description>
165640 <description>Start address of region 10</description>
165649 <description>If this bit is 1, current region is GCM mode region.</description>
165656 …<description>Start address of region 10. Minimal 256 Bytes aligned. It is system address.</descrip…
165665 <description>End address of region 10</description>
165674 …<description>End address of region 10. Minimal 256 Bytes aligned. It is system address.</descripti…
165683 <description>IPED context10 AAD0</description>
165692 <description>Lowest 32 bits of AAD for region 10.</description>
165701 <description>IPED context10 AAD1</description>
165710 <description>Highest 32 bits of AAD for region 10.</description>
165719 <description>IPED context11 IV0</description>
165728 <description>Lowest 32 bits of IV for region 11.</description>
165737 <description>IPED context11 IV1</description>
165746 <description>Highest 32 bits of IV for region 11.</description>
165755 <description>Start address of region 11</description>
165764 <description>If this bit is 1, current region is GCM mode region.</description>
165771 …<description>Start address of region 11. Minimal 256 Bytes aligned. It is system address.</descrip…
165780 <description>End address of region 11</description>
165789 …<description>End address of region 11. Minimal 256 Bytes aligned. It is system address.</descripti…
165798 <description>IPED context11 AAD0</description>
165807 <description>Lowest 32 bits of AAD for region 11.</description>
165816 <description>IPED context11 AAD1</description>
165825 <description>Highest 32 bits of AAD for region 11.</description>
165834 <description>IPED context12 IV0</description>
165843 <description>Lowest 32 bits of IV for region 12.</description>
165852 <description>IPED context12 IV1</description>
165861 <description>Highest 32 bits of IV for region 12.</description>
165870 <description>Start address of region 12</description>
165879 <description>If this bit is 1, current region is GCM mode region.</description>
165886 …<description>Start address of region 12. Minimal 256 Bytes aligned. It is system address.</descrip…
165895 <description>End address of region 12</description>
165904 …<description>End address of region 12. Minimal 256 Bytes aligned. It is system address.</descripti…
165913 <description>IPED context12 AAD0</description>
165922 <description>Lowest 32 bits of AAD for region 12.</description>
165931 <description>IPED context12 AAD1</description>
165940 <description>Highest 32 bits of AAD for region 12.</description>
165949 <description>IPED context13 IV0</description>
165958 <description>Lowest 32 bits of IV for region 13.</description>
165967 <description>IPED context13 IV1</description>
165976 <description>Highest 32 bits of IV for region 13.</description>
165985 <description>Start address of region 13</description>
165994 <description>If this bit is 1, current region is GCM mode region.</description>
166001 …<description>Start address of region 13. Minimal 256 Bytes aligned. It is system address.</descrip…
166010 <description>End address of region 13</description>
166019 …<description>End address of region 13. Minimal 256 Bytes aligned. It is system address.</descripti…
166028 <description>IPED context13 AAD0</description>
166037 <description>Lowest 32 bits of AAD for region 13.</description>
166046 <description>IPED context13 AAD1</description>
166055 <description>Highest 32 bits of AAD for region 13.</description>
166064 <description>IPED context14 IV0</description>
166073 <description>Lowest 32 bits of IV for region 14.</description>
166082 <description>IPED context14 IV1</description>
166091 <description>Highest 32 bits of IV for region 14.</description>
166100 <description>Start address of region 14</description>
166109 <description>If this bit is 1, current region is GCM mode region.</description>
166116 …<description>Start address of region 14. Minimal 256 Bytes aligned. It is system address.</descrip…
166125 <description>End address of region 14</description>
166134 …<description>End address of region 14. Minimal 256 Bytes aligned. It is system address.</descripti…
166143 <description>IPED context14 AAD0</description>
166152 <description>Lowest 32 bits of AAD for region 14.</description>
166161 <description>IPED context14 AAD1</description>
166170 <description>Highest 32 bits of AAD for region 14.</description>
166179 <description>IPED context15 IV0</description>
166188 <description>Lowest 32 bits of IV for region 15.</description>
166197 <description>IPED context15 IV1</description>
166206 <description>Highest 32 bits of IV for region 15.</description>
166215 <description>Start address of region 15</description>
166224 <description>If this bit is 1, current region is GCM mode region.</description>
166231 …<description>Start address of region 15. Minimal 256 Bytes aligned. It is system address.</descrip…
166240 <description>End address of region 15</description>
166249 …<description>End address of region 15. Minimal 256 Bytes aligned. It is system address.</descripti…
166258 <description>IPED context15 AAD0</description>
166267 <description>Lowest 32 bits of AAD for region 15.</description>
166276 <description>IPED context15 AAD1</description>
166285 <description>Highest 32 bits of AAD for region 15.</description>
166296 <description>PWM</description>
166352 <description>Counter Register</description>
166361 <description>Counter Register Bits</description>
166370 <description>Initial Count Register</description>
166379 <description>Initial Count Register Bits</description>
166388 <description>Control 2 Register</description>
166397 <description>Clock Source Select</description>
166404 …<description>The IPBus clock is used as the clock for the local prescaler and counter.</descriptio…
166409 … <description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
166414 …description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and …
166421 <description>Reload Source Select</description>
166428 <description>The local RELOAD signal is used to reload registers.</description>
166433 …description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting …
166440 …<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodu…
166447 …<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</…
166452 …description>The master force signal from submodule 0 is used to force updates. This setting should…
166457 …<description>The local reload signal from this submodule is used to force updates without regard t…
166462 …description>The master reload signal from submodule0 is used to force updates if LDOK is set. This…
166467 … <description>The local sync signal from this submodule is used to force updates.</description>
166472 …description>The master sync signal from submodule0 is used to force updates. This setting should n…
166477 …<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</de…
166482 …<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</desc…
166489 <description>Force Initialization</description>
166496 <description>FRCEN</description>
166503 <description>Initialization from a FORCE_OUT is disabled.</description>
166508 <description>Initialization from a FORCE_OUT is enabled.</description>
166515 <description>Initialization Control Select</description>
166522 <description>Local sync (PWM_X) causes initialization.</description>
166527 …description>Master reload from submodule 0 causes initialization. This setting should not be used …
166532 …description>Master sync from submodule 0 causes initialization. This setting should not be used in…
166537 <description>EXT_SYNC causes initialization.</description>
166544 <description>PWM_X Initial Value</description>
166551 <description>PWM45 Initial Value</description>
166558 <description>PWM23 Initial Value</description>
166565 <description>Independent or Complementary Pair Operation</description>
166572 <description>PWM_A and PWM_B form a complementary PWM pair.</description>
166577 <description>PWM_A and PWM_B outputs are independent PWMs.</description>
166584 <description>WAIT Enable</description>
166591 <description>Debug Enable</description>
166600 <description>Control Register</description>
166609 <description>Double Switching Enable</description>
166616 <description>Double switching disabled.</description>
166621 <description>Double switching enabled.</description>
166628 <description>PWMX Double Switching Enable</description>
166635 <description>PWMX double pulse disabled.</description>
166640 <description>PWMX double pulse enabled.</description>
166647 <description>Load Mode Select</description>
166654 …<description>Buffered registers of this submodule are loaded and take effect at the next PWM reloa…
166659 …description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL…
166666 <description>Split the DBLPWM signal to PWMA and PWMB</description>
166673 … <description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
166678 <description>DBLPWM is split to PWMA and PWMB.</description>
166685 <description>Prescaler</description>
166692 <description>Prescaler 1</description>
166697 <description>Prescaler 2</description>
166702 <description>Prescaler 4</description>
166707 <description>Prescaler 8</description>
166712 <description>Prescaler 16</description>
166717 <description>Prescaler 32</description>
166722 <description>Prescaler 64</description>
166727 <description>Prescaler 128</description>
166734 <description>Compare Mode</description>
166741 …description>The VAL* registers and the PWM counter are compared using an "equal to" meth…
166746 …description>The VAL* registers and the PWM counter are compared using an "equal to or greater…
166753 <description>Deadtime</description>
166760 <description>Full Cycle Reload</description>
166767 <description>Full-cycle reloads disabled.</description>
166772 <description>Full-cycle reloads enabled.</description>
166779 <description>Half Cycle Reload</description>
166786 <description>Half-cycle reloads disabled.</description>
166791 <description>Half-cycle reloads enabled.</description>
166798 <description>Load Frequency</description>
166805 <description>Every PWM opportunity</description>
166810 <description>Every 2 PWM opportunities</description>
166815 <description>Every 3 PWM opportunities</description>
166820 <description>Every 4 PWM opportunities</description>
166825 <description>Every 5 PWM opportunities</description>
166830 <description>Every 6 PWM opportunities</description>
166835 <description>Every 7 PWM opportunities</description>
166840 <description>Every 8 PWM opportunities</description>
166845 <description>Every 9 PWM opportunities</description>
166850 <description>Every 10 PWM opportunities</description>
166855 <description>Every 11 PWM opportunities</description>
166860 <description>Every 12 PWM opportunities</description>
166865 <description>Every 13 PWM opportunities</description>
166870 <description>Every 14 PWM opportunities</description>
166875 <description>Every 15 PWM opportunities</description>
166880 <description>Every 16 PWM opportunities</description>
166889 <description>Value Register 0</description>
166898 <description>Value Register 0</description>
166907 <description>Fractional Value Register 1</description>
166916 <description>Fractional Value 1 Register</description>
166925 <description>Value Register 1</description>
166934 <description>Value Register 1</description>
166943 <description>Fractional Value Register 2</description>
166952 <description>Fractional Value 2</description>
166961 <description>Value Register 2</description>
166970 <description>Value Register 2</description>
166979 <description>Fractional Value Register 3</description>
166988 <description>Fractional Value 3</description>
166997 <description>Value Register 3</description>
167006 <description>Value Register 3</description>
167015 <description>Fractional Value Register 4</description>
167024 <description>Fractional Value 4</description>
167033 <description>Value Register 4</description>
167042 <description>Value Register 4</description>
167051 <description>Fractional Value Register 5</description>
167060 <description>Fractional Value 5</description>
167069 <description>Value Register 5</description>
167078 <description>Value Register 5</description>
167087 <description>Fractional Control Register</description>
167096 <description>Fractional Cycle PWM Period Enable</description>
167103 <description>Disable fractional cycle length for the PWM period.</description>
167108 <description>Enable fractional cycle length for the PWM period.</description>
167115 <description>Fractional Cycle Placement Enable for PWM_A</description>
167122 <description>Disable fractional cycle placement for PWM_A.</description>
167127 <description>Enable fractional cycle placement for PWM_A.</description>
167134 <description>Fractional Cycle Placement Enable for PWM_B</description>
167141 <description>Disable fractional cycle placement for PWM_B.</description>
167146 <description>Enable fractional cycle placement for PWM_B.</description>
167153 <description>Test Status Bit</description>
167162 <description>Output Control Register</description>
167171 <description>PWM_X Fault State</description>
167178 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
167183 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
167188 <description>Output is tristated.</description>
167193 <description>Output is tristated.</description>
167200 <description>PWM_B Fault State</description>
167207 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
167212 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
167217 <description>Output is tristated.</description>
167222 <description>Output is tristated.</description>
167229 <description>PWM_A Fault State</description>
167236 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
167241 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
167246 <description>Output is tristated.</description>
167251 <description>Output is tristated.</description>
167258 <description>PWM_X Output Polarity</description>
167265 …<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on"…
167270 …<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or …
167277 <description>PWM_B Output Polarity</description>
167284 …<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on"…
167289 …<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or …
167296 <description>PWM_A Output Polarity</description>
167303 …<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on"…
167308 …<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or …
167315 <description>PWM_X Input</description>
167322 <description>PWM_B Input</description>
167329 <description>PWM_A Input</description>
167338 <description>Status Register</description>
167347 <description>Compare Flags</description>
167355 … <description>No compare event has occurred for a particular VALx value.</description>
167360 … <description>A compare event has occurred for a particular VALx value.</description>
167367 <description>Capture Flag X0</description>
167375 <description>Capture Flag X1</description>
167383 <description>Capture Flag B0</description>
167391 <description>Capture Flag B1</description>
167399 <description>Capture Flag A0</description>
167407 <description>Capture Flag A1</description>
167415 <description>Reload Flag</description>
167423 <description>No new reload cycle since last STS[RF] clearing</description>
167428 <description>New reload cycle since last STS[RF] clearing</description>
167435 <description>Reload Error Flag</description>
167443 <description>No reload error occurred.</description>
167448 … <description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
167455 <description>Registers Updated Flag</description>
167462 <description>No register update has occurred since last reload.</description>
167467 …<description>At least one of the double buffered registers has been updated since the last reload.…
167476 <description>Interrupt Enable Register</description>
167485 <description>Compare Interrupt Enables</description>
167492 … <description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
167497 … <description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
167504 <description>Capture X 0 Interrupt Enable</description>
167511 <description>Interrupt request disabled for STS[CFX0].</description>
167516 <description>Interrupt request enabled for STS[CFX0].</description>
167523 <description>Capture X 1 Interrupt Enable</description>
167530 <description>Interrupt request disabled for STS[CFX1].</description>
167535 <description>Interrupt request enabled for STS[CFX1].</description>
167542 <description>Capture B 0 Interrupt Enable</description>
167549 <description>Interrupt request disabled for STS[CFB0].</description>
167554 <description>Interrupt request enabled for STS[CFB0].</description>
167561 <description>Capture B 1 Interrupt Enable</description>
167568 <description>Interrupt request disabled for STS[CFB1].</description>
167573 <description>Interrupt request enabled for STS[CFB1].</description>
167580 <description>Capture A 0 Interrupt Enable</description>
167587 <description>Interrupt request disabled for STS[CFA0].</description>
167592 <description>Interrupt request enabled for STS[CFA0].</description>
167599 <description>Capture A 1 Interrupt Enable</description>
167606 <description>Interrupt request disabled for STS[CFA1].</description>
167611 <description>Interrupt request enabled for STS[CFA1].</description>
167618 <description>Reload Interrupt Enable</description>
167625 <description>STS[RF] CPU interrupt requests disabled</description>
167630 <description>STS[RF] CPU interrupt requests enabled</description>
167637 <description>Reload Error Interrupt Enable</description>
167644 <description>STS[REF] CPU interrupt requests disabled</description>
167649 <description>STS[REF] CPU interrupt requests enabled</description>
167658 <description>DMA Enable Register</description>
167667 <description>Capture X0 FIFO DMA Enable</description>
167674 <description>Capture X1 FIFO DMA Enable</description>
167681 <description>Capture B0 FIFO DMA Enable</description>
167688 <description>Capture B1 FIFO DMA Enable</description>
167695 <description>Capture A0 FIFO DMA Enable</description>
167702 <description>Capture A1 FIFO DMA Enable</description>
167709 <description>Capture DMA Enable Source Select</description>
167716 <description>Read DMA requests disabled.</description>
167721 …description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DM…
167726 … <description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
167731 … <description>A local reload (STS[RF] being set) sets the read DMA request.</description>
167738 <description>FIFO Watermark AND Control</description>
167745 <description>Selected FIFO watermarks are OR'ed together.</description>
167750 <description>Selected FIFO watermarks are AND'ed together.</description>
167757 <description>Value Registers DMA Enable</description>
167764 <description>DMA write requests disabled</description>
167769 <description>Enabled</description>
167778 <description>Output Trigger Control Register</description>
167787 <description>Output Trigger Enables</description>
167794 … <description>PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.</description>
167801 <description>Trigger frequency</description>
167808 …description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded …
167813 …description>Trigger outputs are generated only during the final PWM period prior to a reload oppor…
167820 <description>Mux Output Trigger 1 Source Select</description>
167827 <description>Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.</description>
167832 <description>Route the PWMB output to the PWM_MUX_TRIG1 port.</description>
167839 <description>Mux Output Trigger 0 Source Select</description>
167846 <description>Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.</description>
167851 <description>Route the PWMA output to the PWM_MUX_TRIG0 port.</description>
167860 <description>Fault Disable Mapping Register 0</description>
167869 <description>PWM_A Fault Disable Mask 0</description>
167876 <description>PWM_B Fault Disable Mask 0</description>
167883 <description>PWM_X Fault Disable Mask 0</description>
167892 <description>Deadtime Count Register 0</description>
167901 <description>Deadtime Count Register 0</description>
167910 <description>Deadtime Count Register 1</description>
167919 <description>Deadtime Count Register 1</description>
167928 <description>Capture Control A Register</description>
167937 <description>Arm A</description>
167944 <description>Input capture operation is disabled.</description>
167949 … <description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
167956 <description>One Shot Mode A</description>
167963 <description>Free Running</description>
167968 <description>One Shot</description>
167975 <description>Edge A 0</description>
167982 <description>Disabled</description>
167987 <description>Capture falling edges</description>
167992 <description>Capture rising edges</description>
167997 <description>Capture any edge</description>
168004 <description>Edge A 1</description>
168011 <description>Disabled</description>
168016 <description>Capture falling edges</description>
168021 <description>Capture rising edges</description>
168026 <description>Capture any edge</description>
168033 <description>Input Select A</description>
168040 <description>Raw PWM_A input signal selected as source.</description>
168045 <description>Edge Counter</description>
168052 <description>Edge Counter A Enable</description>
168059 <description>Edge counter disabled and held in reset</description>
168064 <description>Edge counter enabled</description>
168071 <description>Capture A FIFOs Water Mark</description>
168078 <description>Capture A0 FIFO Word Count</description>
168085 <description>Capture A1 FIFO Word Count</description>
168094 <description>Capture Compare A Register</description>
168103 <description>Edge Compare A</description>
168110 <description>Edge Counter A</description>
168119 <description>Capture Control B Register</description>
168128 <description>Arm B</description>
168135 <description>Input capture operation is disabled.</description>
168140 … <description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
168147 <description>One Shot Mode B</description>
168154 <description>Free Running</description>
168159 <description>One Shot</description>
168166 <description>Edge B 0</description>
168173 <description>Disabled</description>
168178 <description>Capture falling edges</description>
168183 <description>Capture rising edges</description>
168188 <description>Capture any edge</description>
168195 <description>Edge B 1</description>
168202 <description>Disabled</description>
168207 <description>Capture falling edges</description>
168212 <description>Capture rising edges</description>
168217 <description>Capture any edge</description>
168224 <description>Input Select B</description>
168231 <description>Raw PWM_B input signal selected as source.</description>
168236 <description>Edge Counter</description>
168243 <description>Edge Counter B Enable</description>
168250 <description>Edge counter disabled and held in reset</description>
168255 <description>Edge counter enabled</description>
168262 <description>Capture B FIFOs Water Mark</description>
168269 <description>Capture B0 FIFO Word Count</description>
168276 <description>Capture B1 FIFO Word Count</description>
168285 <description>Capture Compare B Register</description>
168294 <description>Edge Compare B</description>
168301 <description>Edge Counter B</description>
168310 <description>Capture Control X Register</description>
168319 <description>Arm X</description>
168326 <description>Input capture operation is disabled.</description>
168331 … <description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
168338 <description>One Shot Mode Aux</description>
168345 <description>Free Running</description>
168350 <description>One Shot</description>
168357 <description>Edge X 0</description>
168364 <description>Disabled</description>
168369 <description>Capture falling edges</description>
168374 <description>Capture rising edges</description>
168379 <description>Capture any edge</description>
168386 <description>Edge X 1</description>
168393 <description>Disabled</description>
168398 <description>Capture falling edges</description>
168403 <description>Capture rising edges</description>
168408 <description>Capture any edge</description>
168415 <description>Input Select X</description>
168422 <description>Raw PWM_X input signal selected as source.</description>
168427 <description>Edge Counter</description>
168434 <description>Edge Counter X Enable</description>
168441 <description>Edge counter disabled and held in reset</description>
168446 <description>Edge counter enabled</description>
168453 <description>Capture X FIFOs Water Mark</description>
168460 <description>Capture X0 FIFO Word Count</description>
168467 <description>Capture X1 FIFO Word Count</description>
168476 <description>Capture Compare X Register</description>
168485 <description>Edge Compare X</description>
168492 <description>Edge Counter X</description>
168501 <description>Capture Value 0 Register</description>
168510 <description>CAPTVAL0</description>
168519 <description>Capture Value 0 Cycle Register</description>
168528 <description>CVAL0CYC</description>
168537 <description>Capture Value 1 Register</description>
168546 <description>CAPTVAL1</description>
168555 <description>Capture Value 1 Cycle Register</description>
168564 <description>CVAL1CYC</description>
168573 <description>Capture Value 2 Register</description>
168582 <description>CAPTVAL2</description>
168591 <description>Capture Value 2 Cycle Register</description>
168600 <description>CVAL2CYC</description>
168609 <description>Capture Value 3 Register</description>
168618 <description>CAPTVAL3</description>
168627 <description>Capture Value 3 Cycle Register</description>
168636 <description>CVAL3CYC</description>
168645 <description>Capture Value 4 Register</description>
168654 <description>CAPTVAL4</description>
168663 <description>Capture Value 4 Cycle Register</description>
168672 <description>CVAL4CYC</description>
168681 <description>Capture Value 5 Register</description>
168690 <description>CAPTVAL5</description>
168699 <description>Capture Value 5 Cycle Register</description>
168708 <description>CVAL5CYC</description>
168717 <description>Capture PWMA Input Filter Register</description>
168726 <description>Fault Filter Period</description>
168733 <description>Fault Filter Count</description>
168742 <description>Capture PWMB Input Filter Register</description>
168751 <description>Fault Filter Period</description>
168758 <description>Fault Filter Count</description>
168767 <description>Capture PWMX Input Filter Register</description>
168776 <description>Fault Filter Period</description>
168783 <description>Fault Filter Count</description>
168792 <description>Counter Register</description>
168801 <description>Counter Register Bits</description>
168810 <description>Initial Count Register</description>
168819 <description>Initial Count Register Bits</description>
168828 <description>Control 2 Register</description>
168837 <description>Clock Source Select</description>
168844 …<description>The IPBus clock is used as the clock for the local prescaler and counter.</descriptio…
168849 … <description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
168854 …description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and …
168861 <description>Reload Source Select</description>
168868 <description>The local RELOAD signal is used to reload registers.</description>
168873 …description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting …
168880 …<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodu…
168887 …<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</…
168892 …description>The master force signal from submodule 0 is used to force updates. This setting should…
168897 …<description>The local reload signal from this submodule is used to force updates without regard t…
168902 …description>The master reload signal from submodule0 is used to force updates if LDOK is set. This…
168907 … <description>The local sync signal from this submodule is used to force updates.</description>
168912 …description>The master sync signal from submodule0 is used to force updates. This setting should n…
168917 …<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</de…
168922 …<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</desc…
168929 <description>Force Initialization</description>
168936 <description>FRCEN</description>
168943 <description>Initialization from a FORCE_OUT is disabled.</description>
168948 <description>Initialization from a FORCE_OUT is enabled.</description>
168955 <description>Initialization Control Select</description>
168962 <description>Local sync (PWM_X) causes initialization.</description>
168967 …description>Master reload from submodule 0 causes initialization. This setting should not be used …
168972 …description>Master sync from submodule 0 causes initialization. This setting should not be used in…
168977 <description>EXT_SYNC causes initialization.</description>
168984 <description>PWM_X Initial Value</description>
168991 <description>PWM45 Initial Value</description>
168998 <description>PWM23 Initial Value</description>
169005 <description>Independent or Complementary Pair Operation</description>
169012 <description>PWM_A and PWM_B form a complementary PWM pair.</description>
169017 <description>PWM_A and PWM_B outputs are independent PWMs.</description>
169024 <description>WAIT Enable</description>
169031 <description>Debug Enable</description>
169040 <description>Control Register</description>
169049 <description>Double Switching Enable</description>
169056 <description>Double switching disabled.</description>
169061 <description>Double switching enabled.</description>
169068 <description>PWMX Double Switching Enable</description>
169075 <description>PWMX double pulse disabled.</description>
169080 <description>PWMX double pulse enabled.</description>
169087 <description>Load Mode Select</description>
169094 …<description>Buffered registers of this submodule are loaded and take effect at the next PWM reloa…
169099 …description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL…
169106 <description>Split the DBLPWM signal to PWMA and PWMB</description>
169113 … <description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
169118 <description>DBLPWM is split to PWMA and PWMB.</description>
169125 <description>Prescaler</description>
169132 <description>Prescaler 1</description>
169137 <description>Prescaler 2</description>
169142 <description>Prescaler 4</description>
169147 <description>Prescaler 8</description>
169152 <description>Prescaler 16</description>
169157 <description>Prescaler 32</description>
169162 <description>Prescaler 64</description>
169167 <description>Prescaler 128</description>
169174 <description>Compare Mode</description>
169181 …description>The VAL* registers and the PWM counter are compared using an "equal to" meth…
169186 …description>The VAL* registers and the PWM counter are compared using an "equal to or greater…
169193 <description>Deadtime</description>
169200 <description>Full Cycle Reload</description>
169207 <description>Full-cycle reloads disabled.</description>
169212 <description>Full-cycle reloads enabled.</description>
169219 <description>Half Cycle Reload</description>
169226 <description>Half-cycle reloads disabled.</description>
169231 <description>Half-cycle reloads enabled.</description>
169238 <description>Load Frequency</description>
169245 <description>Every PWM opportunity</description>
169250 <description>Every 2 PWM opportunities</description>
169255 <description>Every 3 PWM opportunities</description>
169260 <description>Every 4 PWM opportunities</description>
169265 <description>Every 5 PWM opportunities</description>
169270 <description>Every 6 PWM opportunities</description>
169275 <description>Every 7 PWM opportunities</description>
169280 <description>Every 8 PWM opportunities</description>
169285 <description>Every 9 PWM opportunities</description>
169290 <description>Every 10 PWM opportunities</description>
169295 <description>Every 11 PWM opportunities</description>
169300 <description>Every 12 PWM opportunities</description>
169305 <description>Every 13 PWM opportunities</description>
169310 <description>Every 14 PWM opportunities</description>
169315 <description>Every 15 PWM opportunities</description>
169320 <description>Every 16 PWM opportunities</description>
169329 <description>Value Register 0</description>
169338 <description>Value Register 0</description>
169347 <description>Fractional Value Register 1</description>
169356 <description>Fractional Value 1 Register</description>
169365 <description>Value Register 1</description>
169374 <description>Value Register 1</description>
169383 <description>Fractional Value Register 2</description>
169392 <description>Fractional Value 2</description>
169401 <description>Value Register 2</description>
169410 <description>Value Register 2</description>
169419 <description>Fractional Value Register 3</description>
169428 <description>Fractional Value 3</description>
169437 <description>Value Register 3</description>
169446 <description>Value Register 3</description>
169455 <description>Fractional Value Register 4</description>
169464 <description>Fractional Value 4</description>
169473 <description>Value Register 4</description>
169482 <description>Value Register 4</description>
169491 <description>Fractional Value Register 5</description>
169500 <description>Fractional Value 5</description>
169509 <description>Value Register 5</description>
169518 <description>Value Register 5</description>
169527 <description>Fractional Control Register</description>
169536 <description>Fractional Cycle PWM Period Enable</description>
169543 <description>Disable fractional cycle length for the PWM period.</description>
169548 <description>Enable fractional cycle length for the PWM period.</description>
169555 <description>Fractional Cycle Placement Enable for PWM_A</description>
169562 <description>Disable fractional cycle placement for PWM_A.</description>
169567 <description>Enable fractional cycle placement for PWM_A.</description>
169574 <description>Fractional Cycle Placement Enable for PWM_B</description>
169581 <description>Disable fractional cycle placement for PWM_B.</description>
169586 <description>Enable fractional cycle placement for PWM_B.</description>
169593 <description>Test Status Bit</description>
169602 <description>Output Control Register</description>
169611 <description>PWM_X Fault State</description>
169618 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
169623 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
169628 <description>Output is tristated.</description>
169633 <description>Output is tristated.</description>
169640 <description>PWM_B Fault State</description>
169647 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
169652 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
169657 <description>Output is tristated.</description>
169662 <description>Output is tristated.</description>
169669 <description>PWM_A Fault State</description>
169676 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
169681 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
169686 <description>Output is tristated.</description>
169691 <description>Output is tristated.</description>
169698 <description>PWM_X Output Polarity</description>
169705 …<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on"…
169710 …<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or …
169717 <description>PWM_B Output Polarity</description>
169724 …<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on"…
169729 …<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or …
169736 <description>PWM_A Output Polarity</description>
169743 …<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on"…
169748 …<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or …
169755 <description>PWM_X Input</description>
169762 <description>PWM_B Input</description>
169769 <description>PWM_A Input</description>
169778 <description>Status Register</description>
169787 <description>Compare Flags</description>
169795 … <description>No compare event has occurred for a particular VALx value.</description>
169800 … <description>A compare event has occurred for a particular VALx value.</description>
169807 <description>Capture Flag X0</description>
169815 <description>Capture Flag X1</description>
169823 <description>Capture Flag B0</description>
169831 <description>Capture Flag B1</description>
169839 <description>Capture Flag A0</description>
169847 <description>Capture Flag A1</description>
169855 <description>Reload Flag</description>
169863 <description>No new reload cycle since last STS[RF] clearing</description>
169868 <description>New reload cycle since last STS[RF] clearing</description>
169875 <description>Reload Error Flag</description>
169883 <description>No reload error occurred.</description>
169888 … <description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
169895 <description>Registers Updated Flag</description>
169902 <description>No register update has occurred since last reload.</description>
169907 …<description>At least one of the double buffered registers has been updated since the last reload.…
169916 <description>Interrupt Enable Register</description>
169925 <description>Compare Interrupt Enables</description>
169932 … <description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
169937 … <description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
169944 <description>Capture X 0 Interrupt Enable</description>
169951 <description>Interrupt request disabled for STS[CFX0].</description>
169956 <description>Interrupt request enabled for STS[CFX0].</description>
169963 <description>Capture X 1 Interrupt Enable</description>
169970 <description>Interrupt request disabled for STS[CFX1].</description>
169975 <description>Interrupt request enabled for STS[CFX1].</description>
169982 <description>Capture B 0 Interrupt Enable</description>
169989 <description>Interrupt request disabled for STS[CFB0].</description>
169994 <description>Interrupt request enabled for STS[CFB0].</description>
170001 <description>Capture B 1 Interrupt Enable</description>
170008 <description>Interrupt request disabled for STS[CFB1].</description>
170013 <description>Interrupt request enabled for STS[CFB1].</description>
170020 <description>Capture A 0 Interrupt Enable</description>
170027 <description>Interrupt request disabled for STS[CFA0].</description>
170032 <description>Interrupt request enabled for STS[CFA0].</description>
170039 <description>Capture A 1 Interrupt Enable</description>
170046 <description>Interrupt request disabled for STS[CFA1].</description>
170051 <description>Interrupt request enabled for STS[CFA1].</description>
170058 <description>Reload Interrupt Enable</description>
170065 <description>STS[RF] CPU interrupt requests disabled</description>
170070 <description>STS[RF] CPU interrupt requests enabled</description>
170077 <description>Reload Error Interrupt Enable</description>
170084 <description>STS[REF] CPU interrupt requests disabled</description>
170089 <description>STS[REF] CPU interrupt requests enabled</description>
170098 <description>DMA Enable Register</description>
170107 <description>Capture X0 FIFO DMA Enable</description>
170114 <description>Capture X1 FIFO DMA Enable</description>
170121 <description>Capture B0 FIFO DMA Enable</description>
170128 <description>Capture B1 FIFO DMA Enable</description>
170135 <description>Capture A0 FIFO DMA Enable</description>
170142 <description>Capture A1 FIFO DMA Enable</description>
170149 <description>Capture DMA Enable Source Select</description>
170156 <description>Read DMA requests disabled.</description>
170161 …description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DM…
170166 … <description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
170171 … <description>A local reload (STS[RF] being set) sets the read DMA request.</description>
170178 <description>FIFO Watermark AND Control</description>
170185 <description>Selected FIFO watermarks are OR'ed together.</description>
170190 <description>Selected FIFO watermarks are AND'ed together.</description>
170197 <description>Value Registers DMA Enable</description>
170204 <description>DMA write requests disabled</description>
170209 <description>Enabled</description>
170218 <description>Output Trigger Control Register</description>
170227 <description>Output Trigger Enables</description>
170234 … <description>PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.</description>
170241 <description>Trigger frequency</description>
170248 …description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded …
170253 …description>Trigger outputs are generated only during the final PWM period prior to a reload oppor…
170260 <description>Mux Output Trigger 1 Source Select</description>
170267 <description>Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.</description>
170272 <description>Route the PWMB output to the PWM_MUX_TRIG1 port.</description>
170279 <description>Mux Output Trigger 0 Source Select</description>
170286 <description>Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.</description>
170291 <description>Route the PWMA output to the PWM_MUX_TRIG0 port.</description>
170300 <description>Fault Disable Mapping Register 0</description>
170309 <description>PWM_A Fault Disable Mask 0</description>
170316 <description>PWM_B Fault Disable Mask 0</description>
170323 <description>PWM_X Fault Disable Mask 0</description>
170332 <description>Deadtime Count Register 0</description>
170341 <description>Deadtime Count Register 0</description>
170350 <description>Deadtime Count Register 1</description>
170359 <description>Deadtime Count Register 1</description>
170368 <description>Capture Control A Register</description>
170377 <description>Arm A</description>
170384 <description>Input capture operation is disabled.</description>
170389 … <description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
170396 <description>One Shot Mode A</description>
170403 <description>Free Running</description>
170408 <description>One Shot</description>
170415 <description>Edge A 0</description>
170422 <description>Disabled</description>
170427 <description>Capture falling edges</description>
170432 <description>Capture rising edges</description>
170437 <description>Capture any edge</description>
170444 <description>Edge A 1</description>
170451 <description>Disabled</description>
170456 <description>Capture falling edges</description>
170461 <description>Capture rising edges</description>
170466 <description>Capture any edge</description>
170473 <description>Input Select A</description>
170480 <description>Raw PWM_A input signal selected as source.</description>
170485 <description>Edge Counter</description>
170492 <description>Edge Counter A Enable</description>
170499 <description>Edge counter disabled and held in reset</description>
170504 <description>Edge counter enabled</description>
170511 <description>Capture A FIFOs Water Mark</description>
170518 <description>Capture A0 FIFO Word Count</description>
170525 <description>Capture A1 FIFO Word Count</description>
170534 <description>Capture Compare A Register</description>
170543 <description>Edge Compare A</description>
170550 <description>Edge Counter A</description>
170559 <description>Capture Control B Register</description>
170568 <description>Arm B</description>
170575 <description>Input capture operation is disabled.</description>
170580 … <description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
170587 <description>One Shot Mode B</description>
170594 <description>Free Running</description>
170599 <description>One Shot</description>
170606 <description>Edge B 0</description>
170613 <description>Disabled</description>
170618 <description>Capture falling edges</description>
170623 <description>Capture rising edges</description>
170628 <description>Capture any edge</description>
170635 <description>Edge B 1</description>
170642 <description>Disabled</description>
170647 <description>Capture falling edges</description>
170652 <description>Capture rising edges</description>
170657 <description>Capture any edge</description>
170664 <description>Input Select B</description>
170671 <description>Raw PWM_B input signal selected as source.</description>
170676 <description>Edge Counter</description>
170683 <description>Edge Counter B Enable</description>
170690 <description>Edge counter disabled and held in reset</description>
170695 <description>Edge counter enabled</description>
170702 <description>Capture B FIFOs Water Mark</description>
170709 <description>Capture B0 FIFO Word Count</description>
170716 <description>Capture B1 FIFO Word Count</description>
170725 <description>Capture Compare B Register</description>
170734 <description>Edge Compare B</description>
170741 <description>Edge Counter B</description>
170750 <description>Capture Control X Register</description>
170759 <description>Arm X</description>
170766 <description>Input capture operation is disabled.</description>
170771 … <description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
170778 <description>One Shot Mode Aux</description>
170785 <description>Free Running</description>
170790 <description>One Shot</description>
170797 <description>Edge X 0</description>
170804 <description>Disabled</description>
170809 <description>Capture falling edges</description>
170814 <description>Capture rising edges</description>
170819 <description>Capture any edge</description>
170826 <description>Edge X 1</description>
170833 <description>Disabled</description>
170838 <description>Capture falling edges</description>
170843 <description>Capture rising edges</description>
170848 <description>Capture any edge</description>
170855 <description>Input Select X</description>
170862 <description>Raw PWM_X input signal selected as source.</description>
170867 <description>Edge Counter</description>
170874 <description>Edge Counter X Enable</description>
170881 <description>Edge counter disabled and held in reset</description>
170886 <description>Edge counter enabled</description>
170893 <description>Capture X FIFOs Water Mark</description>
170900 <description>Capture X0 FIFO Word Count</description>
170907 <description>Capture X1 FIFO Word Count</description>
170916 <description>Capture Compare X Register</description>
170925 <description>Edge Compare X</description>
170932 <description>Edge Counter X</description>
170941 <description>Capture Value 0 Register</description>
170950 <description>CAPTVAL0</description>
170959 <description>Capture Value 0 Cycle Register</description>
170968 <description>CVAL0CYC</description>
170977 <description>Capture Value 1 Register</description>
170986 <description>CAPTVAL1</description>
170995 <description>Capture Value 1 Cycle Register</description>
171004 <description>CVAL1CYC</description>
171013 <description>Capture Value 2 Register</description>
171022 <description>CAPTVAL2</description>
171031 <description>Capture Value 2 Cycle Register</description>
171040 <description>CVAL2CYC</description>
171049 <description>Capture Value 3 Register</description>
171058 <description>CAPTVAL3</description>
171067 <description>Capture Value 3 Cycle Register</description>
171076 <description>CVAL3CYC</description>
171085 <description>Capture Value 4 Register</description>
171094 <description>CAPTVAL4</description>
171103 <description>Capture Value 4 Cycle Register</description>
171112 <description>CVAL4CYC</description>
171121 <description>Capture Value 5 Register</description>
171130 <description>CAPTVAL5</description>
171139 <description>Capture Value 5 Cycle Register</description>
171148 <description>CVAL5CYC</description>
171157 <description>Phase Delay Register</description>
171166 <description>Initial Count Register Bits</description>
171175 <description>Capture PWMA Input Filter Register</description>
171184 <description>Fault Filter Period</description>
171191 <description>Fault Filter Count</description>
171200 <description>Capture PWMB Input Filter Register</description>
171209 <description>Fault Filter Period</description>
171216 <description>Fault Filter Count</description>
171225 <description>Capture PWMX Input Filter Register</description>
171234 <description>Fault Filter Period</description>
171241 <description>Fault Filter Count</description>
171250 <description>Counter Register</description>
171259 <description>Counter Register Bits</description>
171268 <description>Initial Count Register</description>
171277 <description>Initial Count Register Bits</description>
171286 <description>Control 2 Register</description>
171295 <description>Clock Source Select</description>
171302 …<description>The IPBus clock is used as the clock for the local prescaler and counter.</descriptio…
171307 … <description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
171312 …description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and …
171319 <description>Reload Source Select</description>
171326 <description>The local RELOAD signal is used to reload registers.</description>
171331 …description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting …
171338 …<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodu…
171345 …<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</…
171350 …description>The master force signal from submodule 0 is used to force updates. This setting should…
171355 …<description>The local reload signal from this submodule is used to force updates without regard t…
171360 …description>The master reload signal from submodule0 is used to force updates if LDOK is set. This…
171365 … <description>The local sync signal from this submodule is used to force updates.</description>
171370 …description>The master sync signal from submodule0 is used to force updates. This setting should n…
171375 …<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</de…
171380 …<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</desc…
171387 <description>Force Initialization</description>
171394 <description>FRCEN</description>
171401 <description>Initialization from a FORCE_OUT is disabled.</description>
171406 <description>Initialization from a FORCE_OUT is enabled.</description>
171413 <description>Initialization Control Select</description>
171420 <description>Local sync (PWM_X) causes initialization.</description>
171425 …description>Master reload from submodule 0 causes initialization. This setting should not be used …
171430 …description>Master sync from submodule 0 causes initialization. This setting should not be used in…
171435 <description>EXT_SYNC causes initialization.</description>
171442 <description>PWM_X Initial Value</description>
171449 <description>PWM45 Initial Value</description>
171456 <description>PWM23 Initial Value</description>
171463 <description>Independent or Complementary Pair Operation</description>
171470 <description>PWM_A and PWM_B form a complementary PWM pair.</description>
171475 <description>PWM_A and PWM_B outputs are independent PWMs.</description>
171482 <description>WAIT Enable</description>
171489 <description>Debug Enable</description>
171498 <description>Control Register</description>
171507 <description>Double Switching Enable</description>
171514 <description>Double switching disabled.</description>
171519 <description>Double switching enabled.</description>
171526 <description>PWMX Double Switching Enable</description>
171533 <description>PWMX double pulse disabled.</description>
171538 <description>PWMX double pulse enabled.</description>
171545 <description>Load Mode Select</description>
171552 …<description>Buffered registers of this submodule are loaded and take effect at the next PWM reloa…
171557 …description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL…
171564 <description>Split the DBLPWM signal to PWMA and PWMB</description>
171571 … <description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
171576 <description>DBLPWM is split to PWMA and PWMB.</description>
171583 <description>Prescaler</description>
171590 <description>Prescaler 1</description>
171595 <description>Prescaler 2</description>
171600 <description>Prescaler 4</description>
171605 <description>Prescaler 8</description>
171610 <description>Prescaler 16</description>
171615 <description>Prescaler 32</description>
171620 <description>Prescaler 64</description>
171625 <description>Prescaler 128</description>
171632 <description>Compare Mode</description>
171639 …description>The VAL* registers and the PWM counter are compared using an "equal to" meth…
171644 …description>The VAL* registers and the PWM counter are compared using an "equal to or greater…
171651 <description>Deadtime</description>
171658 <description>Full Cycle Reload</description>
171665 <description>Full-cycle reloads disabled.</description>
171670 <description>Full-cycle reloads enabled.</description>
171677 <description>Half Cycle Reload</description>
171684 <description>Half-cycle reloads disabled.</description>
171689 <description>Half-cycle reloads enabled.</description>
171696 <description>Load Frequency</description>
171703 <description>Every PWM opportunity</description>
171708 <description>Every 2 PWM opportunities</description>
171713 <description>Every 3 PWM opportunities</description>
171718 <description>Every 4 PWM opportunities</description>
171723 <description>Every 5 PWM opportunities</description>
171728 <description>Every 6 PWM opportunities</description>
171733 <description>Every 7 PWM opportunities</description>
171738 <description>Every 8 PWM opportunities</description>
171743 <description>Every 9 PWM opportunities</description>
171748 <description>Every 10 PWM opportunities</description>
171753 <description>Every 11 PWM opportunities</description>
171758 <description>Every 12 PWM opportunities</description>
171763 <description>Every 13 PWM opportunities</description>
171768 <description>Every 14 PWM opportunities</description>
171773 <description>Every 15 PWM opportunities</description>
171778 <description>Every 16 PWM opportunities</description>
171787 <description>Value Register 0</description>
171796 <description>Value Register 0</description>
171805 <description>Fractional Value Register 1</description>
171814 <description>Fractional Value 1 Register</description>
171823 <description>Value Register 1</description>
171832 <description>Value Register 1</description>
171841 <description>Fractional Value Register 2</description>
171850 <description>Fractional Value 2</description>
171859 <description>Value Register 2</description>
171868 <description>Value Register 2</description>
171877 <description>Fractional Value Register 3</description>
171886 <description>Fractional Value 3</description>
171895 <description>Value Register 3</description>
171904 <description>Value Register 3</description>
171913 <description>Fractional Value Register 4</description>
171922 <description>Fractional Value 4</description>
171931 <description>Value Register 4</description>
171940 <description>Value Register 4</description>
171949 <description>Fractional Value Register 5</description>
171958 <description>Fractional Value 5</description>
171967 <description>Value Register 5</description>
171976 <description>Value Register 5</description>
171985 <description>Fractional Control Register</description>
171994 <description>Fractional Cycle PWM Period Enable</description>
172001 <description>Disable fractional cycle length for the PWM period.</description>
172006 <description>Enable fractional cycle length for the PWM period.</description>
172013 <description>Fractional Cycle Placement Enable for PWM_A</description>
172020 <description>Disable fractional cycle placement for PWM_A.</description>
172025 <description>Enable fractional cycle placement for PWM_A.</description>
172032 <description>Fractional Cycle Placement Enable for PWM_B</description>
172039 <description>Disable fractional cycle placement for PWM_B.</description>
172044 <description>Enable fractional cycle placement for PWM_B.</description>
172051 <description>Test Status Bit</description>
172060 <description>Output Control Register</description>
172069 <description>PWM_X Fault State</description>
172076 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
172081 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
172086 <description>Output is tristated.</description>
172091 <description>Output is tristated.</description>
172098 <description>PWM_B Fault State</description>
172105 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
172110 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
172115 <description>Output is tristated.</description>
172120 <description>Output is tristated.</description>
172127 <description>PWM_A Fault State</description>
172134 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
172139 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
172144 <description>Output is tristated.</description>
172149 <description>Output is tristated.</description>
172156 <description>PWM_X Output Polarity</description>
172163 …<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on"…
172168 …<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or …
172175 <description>PWM_B Output Polarity</description>
172182 …<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on"…
172187 …<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or …
172194 <description>PWM_A Output Polarity</description>
172201 …<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on"…
172206 …<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or …
172213 <description>PWM_X Input</description>
172220 <description>PWM_B Input</description>
172227 <description>PWM_A Input</description>
172236 <description>Status Register</description>
172245 <description>Compare Flags</description>
172253 … <description>No compare event has occurred for a particular VALx value.</description>
172258 … <description>A compare event has occurred for a particular VALx value.</description>
172265 <description>Capture Flag X0</description>
172273 <description>Capture Flag X1</description>
172281 <description>Capture Flag B0</description>
172289 <description>Capture Flag B1</description>
172297 <description>Capture Flag A0</description>
172305 <description>Capture Flag A1</description>
172313 <description>Reload Flag</description>
172321 <description>No new reload cycle since last STS[RF] clearing</description>
172326 <description>New reload cycle since last STS[RF] clearing</description>
172333 <description>Reload Error Flag</description>
172341 <description>No reload error occurred.</description>
172346 … <description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
172353 <description>Registers Updated Flag</description>
172360 <description>No register update has occurred since last reload.</description>
172365 …<description>At least one of the double buffered registers has been updated since the last reload.…
172374 <description>Interrupt Enable Register</description>
172383 <description>Compare Interrupt Enables</description>
172390 … <description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
172395 … <description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
172402 <description>Capture X 0 Interrupt Enable</description>
172409 <description>Interrupt request disabled for STS[CFX0].</description>
172414 <description>Interrupt request enabled for STS[CFX0].</description>
172421 <description>Capture X 1 Interrupt Enable</description>
172428 <description>Interrupt request disabled for STS[CFX1].</description>
172433 <description>Interrupt request enabled for STS[CFX1].</description>
172440 <description>Capture B 0 Interrupt Enable</description>
172447 <description>Interrupt request disabled for STS[CFB0].</description>
172452 <description>Interrupt request enabled for STS[CFB0].</description>
172459 <description>Capture B 1 Interrupt Enable</description>
172466 <description>Interrupt request disabled for STS[CFB1].</description>
172471 <description>Interrupt request enabled for STS[CFB1].</description>
172478 <description>Capture A 0 Interrupt Enable</description>
172485 <description>Interrupt request disabled for STS[CFA0].</description>
172490 <description>Interrupt request enabled for STS[CFA0].</description>
172497 <description>Capture A 1 Interrupt Enable</description>
172504 <description>Interrupt request disabled for STS[CFA1].</description>
172509 <description>Interrupt request enabled for STS[CFA1].</description>
172516 <description>Reload Interrupt Enable</description>
172523 <description>STS[RF] CPU interrupt requests disabled</description>
172528 <description>STS[RF] CPU interrupt requests enabled</description>
172535 <description>Reload Error Interrupt Enable</description>
172542 <description>STS[REF] CPU interrupt requests disabled</description>
172547 <description>STS[REF] CPU interrupt requests enabled</description>
172556 <description>DMA Enable Register</description>
172565 <description>Capture X0 FIFO DMA Enable</description>
172572 <description>Capture X1 FIFO DMA Enable</description>
172579 <description>Capture B0 FIFO DMA Enable</description>
172586 <description>Capture B1 FIFO DMA Enable</description>
172593 <description>Capture A0 FIFO DMA Enable</description>
172600 <description>Capture A1 FIFO DMA Enable</description>
172607 <description>Capture DMA Enable Source Select</description>
172614 <description>Read DMA requests disabled.</description>
172619 …description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DM…
172624 … <description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
172629 … <description>A local reload (STS[RF] being set) sets the read DMA request.</description>
172636 <description>FIFO Watermark AND Control</description>
172643 <description>Selected FIFO watermarks are OR'ed together.</description>
172648 <description>Selected FIFO watermarks are AND'ed together.</description>
172655 <description>Value Registers DMA Enable</description>
172662 <description>DMA write requests disabled</description>
172667 <description>Enabled</description>
172676 <description>Output Trigger Control Register</description>
172685 <description>Output Trigger Enables</description>
172692 … <description>PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.</description>
172699 <description>Trigger frequency</description>
172706 …description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded …
172711 …description>Trigger outputs are generated only during the final PWM period prior to a reload oppor…
172718 <description>Mux Output Trigger 1 Source Select</description>
172725 <description>Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.</description>
172730 <description>Route the PWMB output to the PWM_MUX_TRIG1 port.</description>
172737 <description>Mux Output Trigger 0 Source Select</description>
172744 <description>Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.</description>
172749 <description>Route the PWMA output to the PWM_MUX_TRIG0 port.</description>
172758 <description>Fault Disable Mapping Register 0</description>
172767 <description>PWM_A Fault Disable Mask 0</description>
172774 <description>PWM_B Fault Disable Mask 0</description>
172781 <description>PWM_X Fault Disable Mask 0</description>
172790 <description>Deadtime Count Register 0</description>
172799 <description>Deadtime Count Register 0</description>
172808 <description>Deadtime Count Register 1</description>
172817 <description>Deadtime Count Register 1</description>
172826 <description>Capture Control A Register</description>
172835 <description>Arm A</description>
172842 <description>Input capture operation is disabled.</description>
172847 … <description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
172854 <description>One Shot Mode A</description>
172861 <description>Free Running</description>
172866 <description>One Shot</description>
172873 <description>Edge A 0</description>
172880 <description>Disabled</description>
172885 <description>Capture falling edges</description>
172890 <description>Capture rising edges</description>
172895 <description>Capture any edge</description>
172902 <description>Edge A 1</description>
172909 <description>Disabled</description>
172914 <description>Capture falling edges</description>
172919 <description>Capture rising edges</description>
172924 <description>Capture any edge</description>
172931 <description>Input Select A</description>
172938 <description>Raw PWM_A input signal selected as source.</description>
172943 <description>Edge Counter</description>
172950 <description>Edge Counter A Enable</description>
172957 <description>Edge counter disabled and held in reset</description>
172962 <description>Edge counter enabled</description>
172969 <description>Capture A FIFOs Water Mark</description>
172976 <description>Capture A0 FIFO Word Count</description>
172983 <description>Capture A1 FIFO Word Count</description>
172992 <description>Capture Compare A Register</description>
173001 <description>Edge Compare A</description>
173008 <description>Edge Counter A</description>
173017 <description>Capture Control B Register</description>
173026 <description>Arm B</description>
173033 <description>Input capture operation is disabled.</description>
173038 … <description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
173045 <description>One Shot Mode B</description>
173052 <description>Free Running</description>
173057 <description>One Shot</description>
173064 <description>Edge B 0</description>
173071 <description>Disabled</description>
173076 <description>Capture falling edges</description>
173081 <description>Capture rising edges</description>
173086 <description>Capture any edge</description>
173093 <description>Edge B 1</description>
173100 <description>Disabled</description>
173105 <description>Capture falling edges</description>
173110 <description>Capture rising edges</description>
173115 <description>Capture any edge</description>
173122 <description>Input Select B</description>
173129 <description>Raw PWM_B input signal selected as source.</description>
173134 <description>Edge Counter</description>
173141 <description>Edge Counter B Enable</description>
173148 <description>Edge counter disabled and held in reset</description>
173153 <description>Edge counter enabled</description>
173160 <description>Capture B FIFOs Water Mark</description>
173167 <description>Capture B0 FIFO Word Count</description>
173174 <description>Capture B1 FIFO Word Count</description>
173183 <description>Capture Compare B Register</description>
173192 <description>Edge Compare B</description>
173199 <description>Edge Counter B</description>
173208 <description>Capture Control X Register</description>
173217 <description>Arm X</description>
173224 <description>Input capture operation is disabled.</description>
173229 … <description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
173236 <description>One Shot Mode Aux</description>
173243 <description>Free Running</description>
173248 <description>One Shot</description>
173255 <description>Edge X 0</description>
173262 <description>Disabled</description>
173267 <description>Capture falling edges</description>
173272 <description>Capture rising edges</description>
173277 <description>Capture any edge</description>
173284 <description>Edge X 1</description>
173291 <description>Disabled</description>
173296 <description>Capture falling edges</description>
173301 <description>Capture rising edges</description>
173306 <description>Capture any edge</description>
173313 <description>Input Select X</description>
173320 <description>Raw PWM_X input signal selected as source.</description>
173325 <description>Edge Counter</description>
173332 <description>Edge Counter X Enable</description>
173339 <description>Edge counter disabled and held in reset</description>
173344 <description>Edge counter enabled</description>
173351 <description>Capture X FIFOs Water Mark</description>
173358 <description>Capture X0 FIFO Word Count</description>
173365 <description>Capture X1 FIFO Word Count</description>
173374 <description>Capture Compare X Register</description>
173383 <description>Edge Compare X</description>
173390 <description>Edge Counter X</description>
173399 <description>Capture Value 0 Register</description>
173408 <description>CAPTVAL0</description>
173417 <description>Capture Value 0 Cycle Register</description>
173426 <description>CVAL0CYC</description>
173435 <description>Capture Value 1 Register</description>
173444 <description>CAPTVAL1</description>
173453 <description>Capture Value 1 Cycle Register</description>
173462 <description>CVAL1CYC</description>
173471 <description>Capture Value 2 Register</description>
173480 <description>CAPTVAL2</description>
173489 <description>Capture Value 2 Cycle Register</description>
173498 <description>CVAL2CYC</description>
173507 <description>Capture Value 3 Register</description>
173516 <description>CAPTVAL3</description>
173525 <description>Capture Value 3 Cycle Register</description>
173534 <description>CVAL3CYC</description>
173543 <description>Capture Value 4 Register</description>
173552 <description>CAPTVAL4</description>
173561 <description>Capture Value 4 Cycle Register</description>
173570 <description>CVAL4CYC</description>
173579 <description>Capture Value 5 Register</description>
173588 <description>CAPTVAL5</description>
173597 <description>Capture Value 5 Cycle Register</description>
173606 <description>CVAL5CYC</description>
173615 <description>Phase Delay Register</description>
173624 <description>Initial Count Register Bits</description>
173633 <description>Capture PWMA Input Filter Register</description>
173642 <description>Fault Filter Period</description>
173649 <description>Fault Filter Count</description>
173658 <description>Capture PWMB Input Filter Register</description>
173667 <description>Fault Filter Period</description>
173674 <description>Fault Filter Count</description>
173683 <description>Capture PWMX Input Filter Register</description>
173692 <description>Fault Filter Period</description>
173699 <description>Fault Filter Count</description>
173708 <description>Counter Register</description>
173717 <description>Counter Register Bits</description>
173726 <description>Initial Count Register</description>
173735 <description>Initial Count Register Bits</description>
173744 <description>Control 2 Register</description>
173753 <description>Clock Source Select</description>
173760 …<description>The IPBus clock is used as the clock for the local prescaler and counter.</descriptio…
173765 … <description>EXT_CLK is used as the clock for the local prescaler and counter.</description>
173770 …description>Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and …
173777 <description>Reload Source Select</description>
173784 <description>The local RELOAD signal is used to reload registers.</description>
173789 …description>The master RELOAD signal (from submodule 0) is used to reload registers. This setting …
173796 …<description>This read/write bit determines the source of the FORCE OUTPUT signal for this submodu…
173803 …<description>The local force signal, CTRL2[FORCE], from this submodule is used to force updates.</…
173808 …description>The master force signal from submodule 0 is used to force updates. This setting should…
173813 …<description>The local reload signal from this submodule is used to force updates without regard t…
173818 …description>The master reload signal from submodule0 is used to force updates if LDOK is set. This…
173823 … <description>The local sync signal from this submodule is used to force updates.</description>
173828 …description>The master sync signal from submodule0 is used to force updates. This setting should n…
173833 …<description>The external force signal, EXT_FORCE, from outside the PWM module causes updates.</de…
173838 …<description>The external sync signal, EXT_SYNC, from outside the PWM module causes updates.</desc…
173845 <description>Force Initialization</description>
173852 <description>FRCEN</description>
173859 <description>Initialization from a FORCE_OUT is disabled.</description>
173864 <description>Initialization from a FORCE_OUT is enabled.</description>
173871 <description>Initialization Control Select</description>
173878 <description>Local sync (PWM_X) causes initialization.</description>
173883 …description>Master reload from submodule 0 causes initialization. This setting should not be used …
173888 …description>Master sync from submodule 0 causes initialization. This setting should not be used in…
173893 <description>EXT_SYNC causes initialization.</description>
173900 <description>PWM_X Initial Value</description>
173907 <description>PWM45 Initial Value</description>
173914 <description>PWM23 Initial Value</description>
173921 <description>Independent or Complementary Pair Operation</description>
173928 <description>PWM_A and PWM_B form a complementary PWM pair.</description>
173933 <description>PWM_A and PWM_B outputs are independent PWMs.</description>
173940 <description>WAIT Enable</description>
173947 <description>Debug Enable</description>
173956 <description>Control Register</description>
173965 <description>Double Switching Enable</description>
173972 <description>Double switching disabled.</description>
173977 <description>Double switching enabled.</description>
173984 <description>PWMX Double Switching Enable</description>
173991 <description>PWMX double pulse disabled.</description>
173996 <description>PWMX double pulse enabled.</description>
174003 <description>Load Mode Select</description>
174010 …<description>Buffered registers of this submodule are loaded and take effect at the next PWM reloa…
174015 …description>Buffered registers of this submodule are loaded and take effect immediately upon MCTRL…
174022 <description>Split the DBLPWM signal to PWMA and PWMB</description>
174029 … <description>DBLPWM is not split. PWMA and PWMB each have double pulses.</description>
174034 <description>DBLPWM is split to PWMA and PWMB.</description>
174041 <description>Prescaler</description>
174048 <description>Prescaler 1</description>
174053 <description>Prescaler 2</description>
174058 <description>Prescaler 4</description>
174063 <description>Prescaler 8</description>
174068 <description>Prescaler 16</description>
174073 <description>Prescaler 32</description>
174078 <description>Prescaler 64</description>
174083 <description>Prescaler 128</description>
174090 <description>Compare Mode</description>
174097 …description>The VAL* registers and the PWM counter are compared using an "equal to" meth…
174102 …description>The VAL* registers and the PWM counter are compared using an "equal to or greater…
174109 <description>Deadtime</description>
174116 <description>Full Cycle Reload</description>
174123 <description>Full-cycle reloads disabled.</description>
174128 <description>Full-cycle reloads enabled.</description>
174135 <description>Half Cycle Reload</description>
174142 <description>Half-cycle reloads disabled.</description>
174147 <description>Half-cycle reloads enabled.</description>
174154 <description>Load Frequency</description>
174161 <description>Every PWM opportunity</description>
174166 <description>Every 2 PWM opportunities</description>
174171 <description>Every 3 PWM opportunities</description>
174176 <description>Every 4 PWM opportunities</description>
174181 <description>Every 5 PWM opportunities</description>
174186 <description>Every 6 PWM opportunities</description>
174191 <description>Every 7 PWM opportunities</description>
174196 <description>Every 8 PWM opportunities</description>
174201 <description>Every 9 PWM opportunities</description>
174206 <description>Every 10 PWM opportunities</description>
174211 <description>Every 11 PWM opportunities</description>
174216 <description>Every 12 PWM opportunities</description>
174221 <description>Every 13 PWM opportunities</description>
174226 <description>Every 14 PWM opportunities</description>
174231 <description>Every 15 PWM opportunities</description>
174236 <description>Every 16 PWM opportunities</description>
174245 <description>Value Register 0</description>
174254 <description>Value Register 0</description>
174263 <description>Fractional Value Register 1</description>
174272 <description>Fractional Value 1 Register</description>
174281 <description>Value Register 1</description>
174290 <description>Value Register 1</description>
174299 <description>Fractional Value Register 2</description>
174308 <description>Fractional Value 2</description>
174317 <description>Value Register 2</description>
174326 <description>Value Register 2</description>
174335 <description>Fractional Value Register 3</description>
174344 <description>Fractional Value 3</description>
174353 <description>Value Register 3</description>
174362 <description>Value Register 3</description>
174371 <description>Fractional Value Register 4</description>
174380 <description>Fractional Value 4</description>
174389 <description>Value Register 4</description>
174398 <description>Value Register 4</description>
174407 <description>Fractional Value Register 5</description>
174416 <description>Fractional Value 5</description>
174425 <description>Value Register 5</description>
174434 <description>Value Register 5</description>
174443 <description>Fractional Control Register</description>
174452 <description>Fractional Cycle PWM Period Enable</description>
174459 <description>Disable fractional cycle length for the PWM period.</description>
174464 <description>Enable fractional cycle length for the PWM period.</description>
174471 <description>Fractional Cycle Placement Enable for PWM_A</description>
174478 <description>Disable fractional cycle placement for PWM_A.</description>
174483 <description>Enable fractional cycle placement for PWM_A.</description>
174490 <description>Fractional Cycle Placement Enable for PWM_B</description>
174497 <description>Disable fractional cycle placement for PWM_B.</description>
174502 <description>Enable fractional cycle placement for PWM_B.</description>
174509 <description>Test Status Bit</description>
174518 <description>Output Control Register</description>
174527 <description>PWM_X Fault State</description>
174534 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
174539 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
174544 <description>Output is tristated.</description>
174549 <description>Output is tristated.</description>
174556 <description>PWM_B Fault State</description>
174563 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
174568 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
174573 <description>Output is tristated.</description>
174578 <description>Output is tristated.</description>
174585 <description>PWM_A Fault State</description>
174592 …<description>Output is forced to logic 0 state prior to consideration of output polarity control.<…
174597 …<description>Output is forced to logic 1 state prior to consideration of output polarity control.<…
174602 <description>Output is tristated.</description>
174607 <description>Output is tristated.</description>
174614 <description>PWM_X Output Polarity</description>
174621 …<description>PWM_X output not inverted. A high level on the PWM_X pin represents the "on"…
174626 …<description>PWM_X output inverted. A low level on the PWM_X pin represents the "on" or …
174633 <description>PWM_B Output Polarity</description>
174640 …<description>PWM_B output not inverted. A high level on the PWM_B pin represents the "on"…
174645 …<description>PWM_B output inverted. A low level on the PWM_B pin represents the "on" or …
174652 <description>PWM_A Output Polarity</description>
174659 …<description>PWM_A output not inverted. A high level on the PWM_A pin represents the "on"…
174664 …<description>PWM_A output inverted. A low level on the PWM_A pin represents the "on" or …
174671 <description>PWM_X Input</description>
174678 <description>PWM_B Input</description>
174685 <description>PWM_A Input</description>
174694 <description>Status Register</description>
174703 <description>Compare Flags</description>
174711 … <description>No compare event has occurred for a particular VALx value.</description>
174716 … <description>A compare event has occurred for a particular VALx value.</description>
174723 <description>Capture Flag X0</description>
174731 <description>Capture Flag X1</description>
174739 <description>Capture Flag B0</description>
174747 <description>Capture Flag B1</description>
174755 <description>Capture Flag A0</description>
174763 <description>Capture Flag A1</description>
174771 <description>Reload Flag</description>
174779 <description>No new reload cycle since last STS[RF] clearing</description>
174784 <description>New reload cycle since last STS[RF] clearing</description>
174791 <description>Reload Error Flag</description>
174799 <description>No reload error occurred.</description>
174804 … <description>Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.</description>
174811 <description>Registers Updated Flag</description>
174818 <description>No register update has occurred since last reload.</description>
174823 …<description>At least one of the double buffered registers has been updated since the last reload.…
174832 <description>Interrupt Enable Register</description>
174841 <description>Compare Interrupt Enables</description>
174848 … <description>The corresponding STS[CMPF] bit will not cause an interrupt request.</description>
174853 … <description>The corresponding STS[CMPF] bit will cause an interrupt request.</description>
174860 <description>Capture X 0 Interrupt Enable</description>
174867 <description>Interrupt request disabled for STS[CFX0].</description>
174872 <description>Interrupt request enabled for STS[CFX0].</description>
174879 <description>Capture X 1 Interrupt Enable</description>
174886 <description>Interrupt request disabled for STS[CFX1].</description>
174891 <description>Interrupt request enabled for STS[CFX1].</description>
174898 <description>Capture B 0 Interrupt Enable</description>
174905 <description>Interrupt request disabled for STS[CFB0].</description>
174910 <description>Interrupt request enabled for STS[CFB0].</description>
174917 <description>Capture B 1 Interrupt Enable</description>
174924 <description>Interrupt request disabled for STS[CFB1].</description>
174929 <description>Interrupt request enabled for STS[CFB1].</description>
174936 <description>Capture A 0 Interrupt Enable</description>
174943 <description>Interrupt request disabled for STS[CFA0].</description>
174948 <description>Interrupt request enabled for STS[CFA0].</description>
174955 <description>Capture A 1 Interrupt Enable</description>
174962 <description>Interrupt request disabled for STS[CFA1].</description>
174967 <description>Interrupt request enabled for STS[CFA1].</description>
174974 <description>Reload Interrupt Enable</description>
174981 <description>STS[RF] CPU interrupt requests disabled</description>
174986 <description>STS[RF] CPU interrupt requests enabled</description>
174993 <description>Reload Error Interrupt Enable</description>
175000 <description>STS[REF] CPU interrupt requests disabled</description>
175005 <description>STS[REF] CPU interrupt requests enabled</description>
175014 <description>DMA Enable Register</description>
175023 <description>Capture X0 FIFO DMA Enable</description>
175030 <description>Capture X1 FIFO DMA Enable</description>
175037 <description>Capture B0 FIFO DMA Enable</description>
175044 <description>Capture B1 FIFO DMA Enable</description>
175051 <description>Capture A0 FIFO DMA Enable</description>
175058 <description>Capture A1 FIFO DMA Enable</description>
175065 <description>Capture DMA Enable Source Select</description>
175072 <description>Read DMA requests disabled.</description>
175077 …description>Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DM…
175082 … <description>A local sync (VAL1 matches counter) sets the read DMA request.</description>
175087 … <description>A local reload (STS[RF] being set) sets the read DMA request.</description>
175094 <description>FIFO Watermark AND Control</description>
175101 <description>Selected FIFO watermarks are OR'ed together.</description>
175106 <description>Selected FIFO watermarks are AND'ed together.</description>
175113 <description>Value Registers DMA Enable</description>
175120 <description>DMA write requests disabled</description>
175125 <description>Enabled</description>
175134 <description>Output Trigger Control Register</description>
175143 <description>Output Trigger Enables</description>
175150 … <description>PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.</description>
175157 <description>Trigger frequency</description>
175164 …description>Trigger outputs are generated during every PWM period even if the PWM is not reloaded …
175169 …description>Trigger outputs are generated only during the final PWM period prior to a reload oppor…
175176 <description>Mux Output Trigger 1 Source Select</description>
175183 <description>Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port.</description>
175188 <description>Route the PWMB output to the PWM_MUX_TRIG1 port.</description>
175195 <description>Mux Output Trigger 0 Source Select</description>
175202 <description>Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port.</description>
175207 <description>Route the PWMA output to the PWM_MUX_TRIG0 port.</description>
175216 <description>Fault Disable Mapping Register 0</description>
175225 <description>PWM_A Fault Disable Mask 0</description>
175232 <description>PWM_B Fault Disable Mask 0</description>
175239 <description>PWM_X Fault Disable Mask 0</description>
175248 <description>Deadtime Count Register 0</description>
175257 <description>Deadtime Count Register 0</description>
175266 <description>Deadtime Count Register 1</description>
175275 <description>Deadtime Count Register 1</description>
175284 <description>Capture Control A Register</description>
175293 <description>Arm A</description>
175300 <description>Input capture operation is disabled.</description>
175305 … <description>Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.</description>
175312 <description>One Shot Mode A</description>
175319 <description>Free Running</description>
175324 <description>One Shot</description>
175331 <description>Edge A 0</description>
175338 <description>Disabled</description>
175343 <description>Capture falling edges</description>
175348 <description>Capture rising edges</description>
175353 <description>Capture any edge</description>
175360 <description>Edge A 1</description>
175367 <description>Disabled</description>
175372 <description>Capture falling edges</description>
175377 <description>Capture rising edges</description>
175382 <description>Capture any edge</description>
175389 <description>Input Select A</description>
175396 <description>Raw PWM_A input signal selected as source.</description>
175401 <description>Edge Counter</description>
175408 <description>Edge Counter A Enable</description>
175415 <description>Edge counter disabled and held in reset</description>
175420 <description>Edge counter enabled</description>
175427 <description>Capture A FIFOs Water Mark</description>
175434 <description>Capture A0 FIFO Word Count</description>
175441 <description>Capture A1 FIFO Word Count</description>
175450 <description>Capture Compare A Register</description>
175459 <description>Edge Compare A</description>
175466 <description>Edge Counter A</description>
175475 <description>Capture Control B Register</description>
175484 <description>Arm B</description>
175491 <description>Input capture operation is disabled.</description>
175496 … <description>Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.</description>
175503 <description>One Shot Mode B</description>
175510 <description>Free Running</description>
175515 <description>One Shot</description>
175522 <description>Edge B 0</description>
175529 <description>Disabled</description>
175534 <description>Capture falling edges</description>
175539 <description>Capture rising edges</description>
175544 <description>Capture any edge</description>
175551 <description>Edge B 1</description>
175558 <description>Disabled</description>
175563 <description>Capture falling edges</description>
175568 <description>Capture rising edges</description>
175573 <description>Capture any edge</description>
175580 <description>Input Select B</description>
175587 <description>Raw PWM_B input signal selected as source.</description>
175592 <description>Edge Counter</description>
175599 <description>Edge Counter B Enable</description>
175606 <description>Edge counter disabled and held in reset</description>
175611 <description>Edge counter enabled</description>
175618 <description>Capture B FIFOs Water Mark</description>
175625 <description>Capture B0 FIFO Word Count</description>
175632 <description>Capture B1 FIFO Word Count</description>
175641 <description>Capture Compare B Register</description>
175650 <description>Edge Compare B</description>
175657 <description>Edge Counter B</description>
175666 <description>Capture Control X Register</description>
175675 <description>Arm X</description>
175682 <description>Input capture operation is disabled.</description>
175687 … <description>Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.</description>
175694 <description>One Shot Mode Aux</description>
175701 <description>Free Running</description>
175706 <description>One Shot</description>
175713 <description>Edge X 0</description>
175720 <description>Disabled</description>
175725 <description>Capture falling edges</description>
175730 <description>Capture rising edges</description>
175735 <description>Capture any edge</description>
175742 <description>Edge X 1</description>
175749 <description>Disabled</description>
175754 <description>Capture falling edges</description>
175759 <description>Capture rising edges</description>
175764 <description>Capture any edge</description>
175771 <description>Input Select X</description>
175778 <description>Raw PWM_X input signal selected as source.</description>
175783 <description>Edge Counter</description>
175790 <description>Edge Counter X Enable</description>
175797 <description>Edge counter disabled and held in reset</description>
175802 <description>Edge counter enabled</description>
175809 <description>Capture X FIFOs Water Mark</description>
175816 <description>Capture X0 FIFO Word Count</description>
175823 <description>Capture X1 FIFO Word Count</description>
175832 <description>Capture Compare X Register</description>
175841 <description>Edge Compare X</description>
175848 <description>Edge Counter X</description>
175857 <description>Capture Value 0 Register</description>
175866 <description>CAPTVAL0</description>
175875 <description>Capture Value 0 Cycle Register</description>
175884 <description>CVAL0CYC</description>
175893 <description>Capture Value 1 Register</description>
175902 <description>CAPTVAL1</description>
175911 <description>Capture Value 1 Cycle Register</description>
175920 <description>CVAL1CYC</description>
175929 <description>Capture Value 2 Register</description>
175938 <description>CAPTVAL2</description>
175947 <description>Capture Value 2 Cycle Register</description>
175956 <description>CVAL2CYC</description>
175965 <description>Capture Value 3 Register</description>
175974 <description>CAPTVAL3</description>
175983 <description>Capture Value 3 Cycle Register</description>
175992 <description>CVAL3CYC</description>
176001 <description>Capture Value 4 Register</description>
176010 <description>CAPTVAL4</description>
176019 <description>Capture Value 4 Cycle Register</description>
176028 <description>CVAL4CYC</description>
176037 <description>Capture Value 5 Register</description>
176046 <description>CAPTVAL5</description>
176055 <description>Capture Value 5 Cycle Register</description>
176064 <description>CVAL5CYC</description>
176073 <description>Phase Delay Register</description>
176082 <description>Initial Count Register Bits</description>
176091 <description>Capture PWMA Input Filter Register</description>
176100 <description>Fault Filter Period</description>
176107 <description>Fault Filter Count</description>
176116 <description>Capture PWMB Input Filter Register</description>
176125 <description>Fault Filter Period</description>
176132 <description>Fault Filter Count</description>
176141 <description>Capture PWMX Input Filter Register</description>
176150 <description>Fault Filter Period</description>
176157 <description>Fault Filter Count</description>
176166 <description>Output Enable Register</description>
176175 <description>PWM_X Output Enables</description>
176182 <description>PWM_X output disabled.</description>
176187 <description>PWM_X output enabled.</description>
176194 <description>PWM_B Output Enables</description>
176201 <description>PWM_B output disabled.</description>
176206 <description>PWM_B output enabled.</description>
176213 <description>PWM_A Output Enables</description>
176220 <description>PWM_A output disabled.</description>
176225 <description>PWM_A output enabled.</description>
176234 <description>Mask Register</description>
176243 <description>PWM_X Masks</description>
176250 <description>PWM_X output normal.</description>
176255 <description>PWM_X output masked.</description>
176262 <description>PWM_B Masks</description>
176269 <description>PWM_B output normal.</description>
176274 <description>PWM_B output masked.</description>
176281 <description>PWM_A Masks</description>
176288 <description>PWM_A output normal.</description>
176293 <description>PWM_A output masked.</description>
176300 <description>Update Mask Bits Immediately</description>
176307 …description>Normal operation. MASK* bits within the corresponding submodule are not updated until …
176312 …description>Immediate operation. MASK* bits within the corresponding submodule are updated on the …
176321 <description>Software Controlled Output Register</description>
176330 <description>Submodule 0 Software Controlled Output 45</description>
176337 …<description>A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.</des…
176342 …<description>A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.</des…
176349 <description>Submodule 0 Software Controlled Output 23</description>
176356 …<description>A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.</des…
176361 …<description>A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.</des…
176368 <description>Submodule 1 Software Controlled Output 45</description>
176375 …<description>A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.</des…
176380 …<description>A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.</des…
176387 <description>Submodule 1 Software Controlled Output 23</description>
176394 …<description>A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.</des…
176399 …<description>A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.</des…
176406 <description>Submodule 2 Software Controlled Output 45</description>
176413 …<description>A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.</des…
176418 …<description>A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.</des…
176425 <description>Submodule 2 Software Controlled Output 23</description>
176432 …<description>A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.</des…
176437 …<description>A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.</des…
176444 <description>Submodule 3 Software Controlled Output 45</description>
176451 …<description>A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.</des…
176456 …<description>A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.</des…
176463 <description>Submodule 3 Software Controlled Output 23</description>
176470 …<description>A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.</des…
176475 …<description>A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.</des…
176484 <description>PWM Source Select Register</description>
176493 <description>Submodule 0 PWM45 Control Select</description>
176500 … <description>Generated SM0PWM45 signal is used by the deadtime logic.</description>
176505 … <description>Inverted generated SM0PWM45 signal is used by the deadtime logic.</description>
176510 <description>SWCOUT[SM0OUT45] is used by the deadtime logic.</description>
176515 <description>PWM0_EXTB signal is used by the deadtime logic.</description>
176522 <description>Submodule 0 PWM23 Control Select</description>
176529 … <description>Generated SM0PWM23 signal is used by the deadtime logic.</description>
176534 … <description>Inverted generated SM0PWM23 signal is used by the deadtime logic.</description>
176539 <description>SWCOUT[SM0OUT23] is used by the deadtime logic.</description>
176544 <description>PWM0_EXTA signal is used by the deadtime logic.</description>
176551 <description>Submodule 1 PWM45 Control Select</description>
176558 … <description>Generated SM1PWM45 signal is used by the deadtime logic.</description>
176563 … <description>Inverted generated SM1PWM45 signal is used by the deadtime logic.</description>
176568 <description>SWCOUT[SM1OUT45] is used by the deadtime logic.</description>
176573 <description>PWM1_EXTB signal is used by the deadtime logic.</description>
176580 <description>Submodule 1 PWM23 Control Select</description>
176587 … <description>Generated SM1PWM23 signal is used by the deadtime logic.</description>
176592 … <description>Inverted generated SM1PWM23 signal is used by the deadtime logic.</description>
176597 <description>SWCOUT[SM1OUT23] is used by the deadtime logic.</description>
176602 <description>PWM1_EXTA signal is used by the deadtime logic.</description>
176609 <description>Submodule 2 PWM45 Control Select</description>
176616 … <description>Generated SM2PWM45 signal is used by the deadtime logic.</description>
176621 … <description>Inverted generated SM2PWM45 signal is used by the deadtime logic.</description>
176626 <description>SWCOUT[SM2OUT45] is used by the deadtime logic.</description>
176631 <description>PWM2_EXTB signal is used by the deadtime logic.</description>
176638 <description>Submodule 2 PWM23 Control Select</description>
176645 … <description>Generated SM2PWM23 signal is used by the deadtime logic.</description>
176650 … <description>Inverted generated SM2PWM23 signal is used by the deadtime logic.</description>
176655 <description>SWCOUT[SM2OUT23] is used by the deadtime logic.</description>
176660 <description>PWM2_EXTA signal is used by the deadtime logic.</description>
176667 <description>Submodule 3 PWM45 Control Select</description>
176674 … <description>Generated SM3PWM45 signal is used by the deadtime logic.</description>
176679 … <description>Inverted generated SM3PWM45 signal is used by the deadtime logic.</description>
176684 <description>SWCOUT[SM3OUT45] is used by the deadtime logic.</description>
176689 <description>PWM3_EXTB signal is used by the deadtime logic.</description>
176696 <description>Submodule 3 PWM23 Control Select</description>
176703 … <description>Generated SM3PWM23 signal is used by the deadtime logic.</description>
176708 … <description>Inverted generated SM3PWM23 signal is used by the deadtime logic.</description>
176713 <description>SWCOUT[SM3OUT23] is used by the deadtime logic.</description>
176718 <description>PWM3_EXTA signal is used by the deadtime logic.</description>
176727 <description>Master Control Register</description>
176736 <description>Load Okay</description>
176743 <description>Do not load new values.</description>
176748 … <description>Load prescaler, modulus, and PWM values of the corresponding submodule.</description>
176755 <description>Clear Load Okay</description>
176762 <description>Run</description>
176769 … <description>PWM counter is stopped, but PWM outputs will hold the current state.</description>
176774 <description>PWM counter is started in the corresponding submodule.</description>
176781 <description>Current Polarity</description>
176788 …<description>PWM23 is used to generate complementary PWM pair in the corresponding submodule.</des…
176793 …<description>PWM45 is used to generate complementary PWM pair in the corresponding submodule.</des…
176802 <description>Master Control 2 Register</description>
176811 <description>Monitor PLL State</description>
176818 …description>Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in c…
176823 …<description>Not locked. Monitor PLL operation to automatically disable the fractional delay block…
176828 …description>Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case …
176833 …description>Locked. Monitor PLL operation to automatically disable the fractional delay block when…
176842 <description>Fault Control Register</description>
176851 <description>Fault Interrupt Enables</description>
176858 <description>FAULTx CPU interrupt requests disabled.</description>
176863 <description>FAULTx CPU interrupt requests enabled.</description>
176870 <description>Fault Safety Mode</description>
176877 …description>Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is …
176882 …description>Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is cl…
176889 <description>Automatic Fault Clearing</description>
176896 …description>Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[F…
176901 …description>Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFP…
176908 <description>Fault Level</description>
176915 … <description>A logic 0 on the fault input indicates a fault condition.</description>
176920 … <description>A logic 1 on the fault input indicates a fault condition.</description>
176929 <description>Fault Status Register</description>
176938 <description>Fault Flags</description>
176945 <description>No fault on the FAULTx pin.</description>
176950 <description>Fault on the FAULTx pin.</description>
176957 <description>Full Cycle</description>
176964 … <description>PWM outputs are not re-enabled at the start of a full cycle</description>
176969 <description>PWM outputs are re-enabled at the start of a full cycle</description>
176976 <description>Filtered Fault Pins</description>
176983 <description>Half Cycle Fault Recovery</description>
176990 … <description>PWM outputs are not re-enabled at the start of a half cycle.</description>
176995 …<description>PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).</descri…
177004 <description>Fault Filter Register</description>
177013 <description>Fault Filter Period</description>
177020 <description>Fault Filter Count</description>
177027 <description>Fault Glitch Stretch Enable</description>
177034 <description>Fault input glitch stretching is disabled.</description>
177039 … <description>Input fault signals will be stretched to at least 2 IPBus clock cycles.</description>
177048 <description>Fault Test Register</description>
177057 <description>Fault Test</description>
177064 <description>No fault</description>
177069 <description>Cause a simulated fault</description>
177078 <description>Fault Control 2 Register</description>
177087 <description>No Combinational Path From Fault Input To PWM Output</description>
177094 …description>There is a combinational link from the fault inputs to the PWM outputs. The fault inpu…
177099 …description>The direct combinational path from the fault inputs to the PWM outputs is disabled and…
177110 <description>PWM</description>
177165 <description>QDC</description>
177193 <description>Control Register</description>
177202 <description>Compare Interrupt Enable</description>
177209 <description>Disabled</description>
177214 <description>Enabled</description>
177221 <description>Compare Interrupt Request</description>
177229 … <description>No match has occurred (the counter does not match the COMP value)</description>
177234 … <description>COMP match has occurred (the counter matches the COMP value)</description>
177241 <description>Watchdog Enable</description>
177248 <description>Disabled</description>
177253 <description>Enabled</description>
177260 <description>Watchdog Timeout Interrupt Enable</description>
177267 <description>Disabled</description>
177272 <description>Enabled</description>
177279 <description>Watchdog Timeout Interrupt Request</description>
177287 <description>No Watchdog timeout interrupt has occurred</description>
177292 <description>Watchdog timeout interrupt has occurred</description>
177299 <description>Use Negative Edge of INDEX Pulse</description>
177306 <description>Use positive edge of INDEX pulse</description>
177311 <description>Use negative edge of INDEX pulse</description>
177318 … <description>INDEX Triggered Initialization of Position Counters UPOS and LPOS</description>
177325 <description>INDEX pulse does not initialize the position counter</description>
177330 <description>INDEX pulse initializes the position counter</description>
177337 <description>INDEX Pulse Interrupt Enable</description>
177344 <description>Disabled</description>
177349 <description>Enabled</description>
177356 <description>INDEX Pulse Interrupt Request</description>
177364 <description>INDEX pulse has not occurred</description>
177369 <description>INDEX pulse has occurred</description>
177376 <description>Enable Signal Phase Count Mode</description>
177383 …<description>Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase qu…
177388 …description>Bypass the quadrature decoder. A positive transition of the PHASEA input generates a c…
177395 <description>Enable Reverse Direction Counting</description>
177402 <description>Count normally</description>
177407 <description>Count in the reverse direction</description>
177414 … <description>Software-Triggered Initialization of Position Counters UPOS and LPOS</description>
177421 <description>No action</description>
177426 …<description>Initialize position counter (using upper and lower initialization registers, UINIT an…
177433 <description>Use Negative Edge of HOME Input</description>
177440 …<description>Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS<…
177445 …<description>Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS<…
177452 <description>Enable HOME to Initialize Position Counters UPOS and LPOS</description>
177459 <description>No action</description>
177464 <description>HOME signal initializes the position counter</description>
177471 <description>HOME Interrupt Enable</description>
177478 <description>Disabled</description>
177483 <description>Enabled</description>
177490 <description>HOME Signal Transition Interrupt Request</description>
177498 <description>No transition on the HOME signal has occurred</description>
177503 <description>A transition on the HOME signal has occurred</description>
177512 <description>Input Filter Register</description>
177521 <description>Input Filter Sample Period</description>
177528 <description>Input Filter Sample Count</description>
177535 <description>prescaler divide IPbus clock to FILT clk</description>
177544 <description>Watchdog Timeout Register</description>
177553 <description>WDOG</description>
177562 <description>Position Difference Counter Register</description>
177571 <description>POSD</description>
177580 <description>Position Difference Hold Register</description>
177589 <description>POSDH</description>
177598 <description>Revolution Counter Register</description>
177607 <description>REV</description>
177616 <description>Revolution Hold Register</description>
177625 <description>REVH</description>
177634 <description>Upper Position Counter Register</description>
177643 <description>POS</description>
177652 <description>Lower Position Counter Register</description>
177661 <description>POS</description>
177670 <description>Upper Position Hold Register</description>
177679 <description>POSH</description>
177688 <description>Lower Position Hold Register</description>
177697 <description>POSH</description>
177706 <description>Upper Initialization Register</description>
177715 <description>INIT</description>
177724 <description>Lower Initialization Register</description>
177733 <description>INIT</description>
177742 <description>Input Monitor Register</description>
177751 <description>HOME</description>
177758 <description>INDEX</description>
177765 <description>PHB</description>
177772 <description>PHA</description>
177779 <description>FHOM</description>
177786 <description>FIND</description>
177793 <description>FPHB</description>
177800 <description>FPHA</description>
177809 <description>Test Register</description>
177818 <description>TEST_COUNT</description>
177825 <description>TEST_PERIOD</description>
177832 <description>Quadrature Decoder Negative Signal</description>
177839 <description>Generates a positive quadrature decoder signal</description>
177844 <description>Generates a negative quadrature decoder signal</description>
177851 <description>Test Counter Enable</description>
177858 <description>Disabled</description>
177863 <description>Enabled</description>
177870 <description>Test Mode Enable</description>
177877 <description>Disabled</description>
177882 <description>Enabled</description>
177891 <description>Control 2 Register</description>
177900 <description>Update Hold Registers</description>
177907 …<description>Disable updates of hold registers on the rising edge of TRIGGER input signal</descrip…
177912 …<description>Enable updates of hold registers on the rising edge of TRIGGER input signal</descript…
177919 <description>Update Position Registers</description>
177926 …<description>No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER</descripti…
177931 … <description>Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER</description>
177938 <description>Enable Modulo Counting</description>
177945 <description>Disable modulo counting</description>
177950 <description>Enable modulo counting</description>
177957 <description>Count Direction Flag</description>
177964 <description>Last count was in the down direction</description>
177969 <description>Last count was in the up direction</description>
177976 <description>Roll-under Interrupt Enable</description>
177983 <description>Disabled</description>
177988 <description>Enabled</description>
177995 <description>Roll-under Interrupt Request</description>
178003 <description>No roll-under has occurred</description>
178008 <description>Roll-under has occurred</description>
178015 <description>Roll-over Interrupt Enable</description>
178022 <description>Disabled</description>
178027 <description>Enabled</description>
178034 <description>Roll-over Interrupt Request</description>
178042 <description>No roll-over has occurred</description>
178047 <description>Roll-over has occurred</description>
178054 <description>Revolution Counter Modulus Enable</description>
178061 … <description>Use INDEX pulse to increment/decrement revolution counter (REV)</description>
178066 …<description>Use modulus counting roll-over/under to increment/decrement revolution counter (REV)<…
178073 <description>Output Control</description>
178080 …<description>POSMATCH pulses when a match occurs between the position counters (POS) and the corre…
178085 … <description>POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read</description>
178092 <description>Simultaneous PHASEA and PHASEB Change Interrupt Enable</description>
178099 <description>Disabled</description>
178104 <description>Enabled</description>
178111 <description>Simultaneous PHASEA and PHASEB Change Interrupt Request</description>
178119 … <description>No simultaneous change of PHASEA and PHASEB has occurred</description>
178124 <description>A simultaneous change of PHASEA and PHASEB has occurred</description>
178133 <description>Upper Modulus Register</description>
178142 <description>MOD</description>
178151 <description>Lower Modulus Register</description>
178160 <description>MOD</description>
178169 <description>Upper Position Compare Register</description>
178178 <description>COMP</description>
178187 <description>Lower Position Compare Register</description>
178196 <description>COMP</description>
178207 <description>QDC</description>
178234 <description>AOI</description>
178246 <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description>
178255 <description>Product term 1, D input configuration</description>
178262 … <description>Force the D input in this product term to a logical zero</description>
178267 <description>Pass the D input in this product term</description>
178272 <description>Complement the D input in this product term</description>
178277 <description>Force the D input in this product term to a logical one</description>
178284 <description>Product term 1, C input configuration</description>
178291 … <description>Force the C input in this product term to a logical zero</description>
178296 <description>Pass the C input in this product term</description>
178301 <description>Complement the C input in this product term</description>
178306 <description>Force the C input in this product term to a logical one</description>
178313 <description>Product term 1, B input configuration</description>
178320 … <description>Force the B input in this product term to a logical zero</description>
178325 <description>Pass the B input in this product term</description>
178330 <description>Complement the B input in this product term</description>
178335 <description>Force the B input in this product term to a logical one</description>
178342 <description>Product term 1, A input configuration</description>
178349 … <description>Force the A input in this product term to a logical zero</description>
178354 <description>Pass the A input in this product term</description>
178359 <description>Complement the A input in this product term</description>
178364 <description>Force the A input in this product term to a logical one</description>
178371 <description>Product term 0, D input configuration</description>
178378 … <description>Force the D input in this product term to a logical zero</description>
178383 <description>Pass the D input in this product term</description>
178388 <description>Complement the D input in this product term</description>
178393 <description>Force the D input in this product term to a logical one</description>
178400 <description>Product term 0, C input configuration</description>
178407 … <description>Force the C input in this product term to a logical zero</description>
178412 <description>Pass the C input in this product term</description>
178417 <description>Complement the C input in this product term</description>
178422 <description>Force the C input in this product term to a logical one</description>
178429 <description>Product term 0, B input configuration</description>
178436 … <description>Force the B input in this product term to a logical zero</description>
178441 <description>Pass the B input in this product term</description>
178446 <description>Complement the B input in this product term</description>
178451 <description>Force the B input in this product term to a logical one</description>
178458 <description>Product term 0, A input configuration</description>
178465 … <description>Force the A input in this product term to a logical zero</description>
178470 <description>Pass the A input in this product term</description>
178475 <description>Complement the A input in this product term</description>
178480 <description>Force the A input in this product term to a logical one</description>
178489 <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description>
178498 <description>Product term 3, D input configuration</description>
178505 … <description>Force the D input in this product term to a logical zero</description>
178510 <description>Pass the D input in this product term</description>
178515 <description>Complement the D input in this product term</description>
178520 <description>Force the D input in this product term to a logical one</description>
178527 <description>Product term 3, C input configuration</description>
178534 … <description>Force the C input in this product term to a logical zero</description>
178539 <description>Pass the C input in this product term</description>
178544 <description>Complement the C input in this product term</description>
178549 <description>Force the C input in this product term to a logical one</description>
178556 <description>Product term 3, B input configuration</description>
178563 … <description>Force the B input in this product term to a logical zero</description>
178568 <description>Pass the B input in this product term</description>
178573 <description>Complement the B input in this product term</description>
178578 <description>Force the B input in this product term to a logical one</description>
178585 <description>Product term 3, A input configuration</description>
178592 … <description>Force the A input in this product term to a logical zero</description>
178597 <description>Pass the A input in this product term</description>
178602 <description>Complement the A input in this product term</description>
178607 <description>Force the A input in this product term to a logical one</description>
178614 <description>Product term 2, D input configuration</description>
178621 … <description>Force the D input in this product term to a logical zero</description>
178626 <description>Pass the D input in this product term</description>
178631 <description>Complement the D input in this product term</description>
178636 <description>Force the D input in this product term to a logical one</description>
178643 <description>Product term 2, C input configuration</description>
178650 … <description>Force the C input in this product term to a logical zero</description>
178655 <description>Pass the C input in this product term</description>
178660 <description>Complement the C input in this product term</description>
178665 <description>Force the C input in this product term to a logical one</description>
178672 <description>Product term 2, B input configuration</description>
178679 … <description>Force the B input in this product term to a logical zero</description>
178684 <description>Pass the B input in this product term</description>
178689 <description>Complement the B input in this product term</description>
178694 <description>Force the B input in this product term to a logical one</description>
178701 <description>Product term 2, A input configuration</description>
178708 … <description>Force the A input in this product term to a logical zero</description>
178713 <description>Pass the A input in this product term</description>
178718 <description>Complement the A input in this product term</description>
178723 <description>Force the A input in this product term to a logical one</description>
178732 <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description>
178741 <description>Product term 1, D input configuration</description>
178748 … <description>Force the D input in this product term to a logical zero</description>
178753 <description>Pass the D input in this product term</description>
178758 <description>Complement the D input in this product term</description>
178763 <description>Force the D input in this product term to a logical one</description>
178770 <description>Product term 1, C input configuration</description>
178777 … <description>Force the C input in this product term to a logical zero</description>
178782 <description>Pass the C input in this product term</description>
178787 <description>Complement the C input in this product term</description>
178792 <description>Force the C input in this product term to a logical one</description>
178799 <description>Product term 1, B input configuration</description>
178806 … <description>Force the B input in this product term to a logical zero</description>
178811 <description>Pass the B input in this product term</description>
178816 <description>Complement the B input in this product term</description>
178821 <description>Force the B input in this product term to a logical one</description>
178828 <description>Product term 1, A input configuration</description>
178835 … <description>Force the A input in this product term to a logical zero</description>
178840 <description>Pass the A input in this product term</description>
178845 <description>Complement the A input in this product term</description>
178850 <description>Force the A input in this product term to a logical one</description>
178857 <description>Product term 0, D input configuration</description>
178864 … <description>Force the D input in this product term to a logical zero</description>
178869 <description>Pass the D input in this product term</description>
178874 <description>Complement the D input in this product term</description>
178879 <description>Force the D input in this product term to a logical one</description>
178886 <description>Product term 0, C input configuration</description>
178893 … <description>Force the C input in this product term to a logical zero</description>
178898 <description>Pass the C input in this product term</description>
178903 <description>Complement the C input in this product term</description>
178908 <description>Force the C input in this product term to a logical one</description>
178915 <description>Product term 0, B input configuration</description>
178922 … <description>Force the B input in this product term to a logical zero</description>
178927 <description>Pass the B input in this product term</description>
178932 <description>Complement the B input in this product term</description>
178937 <description>Force the B input in this product term to a logical one</description>
178944 <description>Product term 0, A input configuration</description>
178951 … <description>Force the A input in this product term to a logical zero</description>
178956 <description>Pass the A input in this product term</description>
178961 <description>Complement the A input in this product term</description>
178966 <description>Force the A input in this product term to a logical one</description>
178975 <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description>
178984 <description>Product term 3, D input configuration</description>
178991 … <description>Force the D input in this product term to a logical zero</description>
178996 <description>Pass the D input in this product term</description>
179001 <description>Complement the D input in this product term</description>
179006 <description>Force the D input in this product term to a logical one</description>
179013 <description>Product term 3, C input configuration</description>
179020 … <description>Force the C input in this product term to a logical zero</description>
179025 <description>Pass the C input in this product term</description>
179030 <description>Complement the C input in this product term</description>
179035 <description>Force the C input in this product term to a logical one</description>
179042 <description>Product term 3, B input configuration</description>
179049 … <description>Force the B input in this product term to a logical zero</description>
179054 <description>Pass the B input in this product term</description>
179059 <description>Complement the B input in this product term</description>
179064 <description>Force the B input in this product term to a logical one</description>
179071 <description>Product term 3, A input configuration</description>
179078 … <description>Force the A input in this product term to a logical zero</description>
179083 <description>Pass the A input in this product term</description>
179088 <description>Complement the A input in this product term</description>
179093 <description>Force the A input in this product term to a logical one</description>
179100 <description>Product term 2, D input configuration</description>
179107 … <description>Force the D input in this product term to a logical zero</description>
179112 <description>Pass the D input in this product term</description>
179117 <description>Complement the D input in this product term</description>
179122 <description>Force the D input in this product term to a logical one</description>
179129 <description>Product term 2, C input configuration</description>
179136 … <description>Force the C input in this product term to a logical zero</description>
179141 <description>Pass the C input in this product term</description>
179146 <description>Complement the C input in this product term</description>
179151 <description>Force the C input in this product term to a logical one</description>
179158 <description>Product term 2, B input configuration</description>
179165 … <description>Force the B input in this product term to a logical zero</description>
179170 <description>Pass the B input in this product term</description>
179175 <description>Complement the B input in this product term</description>
179180 <description>Force the B input in this product term to a logical one</description>
179187 <description>Product term 2, A input configuration</description>
179194 … <description>Force the A input in this product term to a logical zero</description>
179199 <description>Pass the A input in this product term</description>
179204 <description>Complement the A input in this product term</description>
179209 <description>Force the A input in this product term to a logical one</description>
179218 <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description>
179227 <description>Product term 1, D input configuration</description>
179234 … <description>Force the D input in this product term to a logical zero</description>
179239 <description>Pass the D input in this product term</description>
179244 <description>Complement the D input in this product term</description>
179249 <description>Force the D input in this product term to a logical one</description>
179256 <description>Product term 1, C input configuration</description>
179263 … <description>Force the C input in this product term to a logical zero</description>
179268 <description>Pass the C input in this product term</description>
179273 <description>Complement the C input in this product term</description>
179278 <description>Force the C input in this product term to a logical one</description>
179285 <description>Product term 1, B input configuration</description>
179292 … <description>Force the B input in this product term to a logical zero</description>
179297 <description>Pass the B input in this product term</description>
179302 <description>Complement the B input in this product term</description>
179307 <description>Force the B input in this product term to a logical one</description>
179314 <description>Product term 1, A input configuration</description>
179321 … <description>Force the A input in this product term to a logical zero</description>
179326 <description>Pass the A input in this product term</description>
179331 <description>Complement the A input in this product term</description>
179336 <description>Force the A input in this product term to a logical one</description>
179343 <description>Product term 0, D input configuration</description>
179350 … <description>Force the D input in this product term to a logical zero</description>
179355 <description>Pass the D input in this product term</description>
179360 <description>Complement the D input in this product term</description>
179365 <description>Force the D input in this product term to a logical one</description>
179372 <description>Product term 0, C input configuration</description>
179379 … <description>Force the C input in this product term to a logical zero</description>
179384 <description>Pass the C input in this product term</description>
179389 <description>Complement the C input in this product term</description>
179394 <description>Force the C input in this product term to a logical one</description>
179401 <description>Product term 0, B input configuration</description>
179408 … <description>Force the B input in this product term to a logical zero</description>
179413 <description>Pass the B input in this product term</description>
179418 <description>Complement the B input in this product term</description>
179423 <description>Force the B input in this product term to a logical one</description>
179430 <description>Product term 0, A input configuration</description>
179437 … <description>Force the A input in this product term to a logical zero</description>
179442 <description>Pass the A input in this product term</description>
179447 <description>Complement the A input in this product term</description>
179452 <description>Force the A input in this product term to a logical one</description>
179461 <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description>
179470 <description>Product term 3, D input configuration</description>
179477 … <description>Force the D input in this product term to a logical zero</description>
179482 <description>Pass the D input in this product term</description>
179487 <description>Complement the D input in this product term</description>
179492 <description>Force the D input in this product term to a logical one</description>
179499 <description>Product term 3, C input configuration</description>
179506 … <description>Force the C input in this product term to a logical zero</description>
179511 <description>Pass the C input in this product term</description>
179516 <description>Complement the C input in this product term</description>
179521 <description>Force the C input in this product term to a logical one</description>
179528 <description>Product term 3, B input configuration</description>
179535 … <description>Force the B input in this product term to a logical zero</description>
179540 <description>Pass the B input in this product term</description>
179545 <description>Complement the B input in this product term</description>
179550 <description>Force the B input in this product term to a logical one</description>
179557 <description>Product term 3, A input configuration</description>
179564 … <description>Force the A input in this product term to a logical zero</description>
179569 <description>Pass the A input in this product term</description>
179574 <description>Complement the A input in this product term</description>
179579 <description>Force the A input in this product term to a logical one</description>
179586 <description>Product term 2, D input configuration</description>
179593 … <description>Force the D input in this product term to a logical zero</description>
179598 <description>Pass the D input in this product term</description>
179603 <description>Complement the D input in this product term</description>
179608 <description>Force the D input in this product term to a logical one</description>
179615 <description>Product term 2, C input configuration</description>
179622 … <description>Force the C input in this product term to a logical zero</description>
179627 <description>Pass the C input in this product term</description>
179632 <description>Complement the C input in this product term</description>
179637 <description>Force the C input in this product term to a logical one</description>
179644 <description>Product term 2, B input configuration</description>
179651 … <description>Force the B input in this product term to a logical zero</description>
179656 <description>Pass the B input in this product term</description>
179661 <description>Complement the B input in this product term</description>
179666 <description>Force the B input in this product term to a logical one</description>
179673 <description>Product term 2, A input configuration</description>
179680 … <description>Force the A input in this product term to a logical zero</description>
179685 <description>Pass the A input in this product term</description>
179690 <description>Complement the A input in this product term</description>
179695 <description>Force the A input in this product term to a logical one</description>
179704 <description>Boolean Function Term 0 and 1 Configuration Register for EVENTn</description>
179713 <description>Product term 1, D input configuration</description>
179720 … <description>Force the D input in this product term to a logical zero</description>
179725 <description>Pass the D input in this product term</description>
179730 <description>Complement the D input in this product term</description>
179735 <description>Force the D input in this product term to a logical one</description>
179742 <description>Product term 1, C input configuration</description>
179749 … <description>Force the C input in this product term to a logical zero</description>
179754 <description>Pass the C input in this product term</description>
179759 <description>Complement the C input in this product term</description>
179764 <description>Force the C input in this product term to a logical one</description>
179771 <description>Product term 1, B input configuration</description>
179778 … <description>Force the B input in this product term to a logical zero</description>
179783 <description>Pass the B input in this product term</description>
179788 <description>Complement the B input in this product term</description>
179793 <description>Force the B input in this product term to a logical one</description>
179800 <description>Product term 1, A input configuration</description>
179807 … <description>Force the A input in this product term to a logical zero</description>
179812 <description>Pass the A input in this product term</description>
179817 <description>Complement the A input in this product term</description>
179822 <description>Force the A input in this product term to a logical one</description>
179829 <description>Product term 0, D input configuration</description>
179836 … <description>Force the D input in this product term to a logical zero</description>
179841 <description>Pass the D input in this product term</description>
179846 <description>Complement the D input in this product term</description>
179851 <description>Force the D input in this product term to a logical one</description>
179858 <description>Product term 0, C input configuration</description>
179865 … <description>Force the C input in this product term to a logical zero</description>
179870 <description>Pass the C input in this product term</description>
179875 <description>Complement the C input in this product term</description>
179880 <description>Force the C input in this product term to a logical one</description>
179887 <description>Product term 0, B input configuration</description>
179894 … <description>Force the B input in this product term to a logical zero</description>
179899 <description>Pass the B input in this product term</description>
179904 <description>Complement the B input in this product term</description>
179909 <description>Force the B input in this product term to a logical one</description>
179916 <description>Product term 0, A input configuration</description>
179923 … <description>Force the A input in this product term to a logical zero</description>
179928 <description>Pass the A input in this product term</description>
179933 <description>Complement the A input in this product term</description>
179938 <description>Force the A input in this product term to a logical one</description>
179947 <description>Boolean Function Term 2 and 3 Configuration Register for EVENTn</description>
179956 <description>Product term 3, D input configuration</description>
179963 … <description>Force the D input in this product term to a logical zero</description>
179968 <description>Pass the D input in this product term</description>
179973 <description>Complement the D input in this product term</description>
179978 <description>Force the D input in this product term to a logical one</description>
179985 <description>Product term 3, C input configuration</description>
179992 … <description>Force the C input in this product term to a logical zero</description>
179997 <description>Pass the C input in this product term</description>
180002 <description>Complement the C input in this product term</description>
180007 <description>Force the C input in this product term to a logical one</description>
180014 <description>Product term 3, B input configuration</description>
180021 … <description>Force the B input in this product term to a logical zero</description>
180026 <description>Pass the B input in this product term</description>
180031 <description>Complement the B input in this product term</description>
180036 <description>Force the B input in this product term to a logical one</description>
180043 <description>Product term 3, A input configuration</description>
180050 … <description>Force the A input in this product term to a logical zero</description>
180055 <description>Pass the A input in this product term</description>
180060 <description>Complement the A input in this product term</description>
180065 <description>Force the A input in this product term to a logical one</description>
180072 <description>Product term 2, D input configuration</description>
180079 … <description>Force the D input in this product term to a logical zero</description>
180084 <description>Pass the D input in this product term</description>
180089 <description>Complement the D input in this product term</description>
180094 <description>Force the D input in this product term to a logical one</description>
180101 <description>Product term 2, C input configuration</description>
180108 … <description>Force the C input in this product term to a logical zero</description>
180113 <description>Pass the C input in this product term</description>
180118 <description>Complement the C input in this product term</description>
180123 <description>Force the C input in this product term to a logical one</description>
180130 <description>Product term 2, B input configuration</description>
180137 … <description>Force the B input in this product term to a logical zero</description>
180142 <description>Pass the B input in this product term</description>
180147 <description>Complement the B input in this product term</description>
180152 <description>Force the B input in this product term to a logical one</description>
180159 <description>Product term 2, A input configuration</description>
180166 … <description>Force the A input in this product term to a logical zero</description>
180171 <description>Pass the A input in this product term</description>
180176 <description>Complement the A input in this product term</description>
180181 <description>Force the A input in this product term to a logical one</description>
180192 <description>AOI</description>
180203 <description>no description available</description>
180214 <description>Coprocessor Power Control Register</description>
180223 <description>State UNKNOWN 0.</description>
180230 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180235 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180242 <description>State UNKNOWN Secure only 0.</description>
180249 <description>The SU0 field is accessible from both Security states.</description>
180254 <description>The SU0 field is only accessible from the Secure state.</description>
180261 <description>State UNKNOWN 1.</description>
180268 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180273 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180280 <description>State UNKNOWN Secure only 1.</description>
180287 <description>The SU7 field is accessible from both Security states.</description>
180292 <description>The SU7 field is only accessible from the Secure state.</description>
180299 <description>State UNKNOWN 2.</description>
180306 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180311 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180318 <description>State UNKNOWN Secure only 2.</description>
180325 <description>The SU2 field is accessible from both Security states.</description>
180330 <description>The SU2 field is only accessible from the Secure state.</description>
180337 <description>State UNKNOWN 3.</description>
180344 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180349 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180356 <description>State UNKNOWN Secure only 3.</description>
180363 <description>The SU3 field is accessible from both Security states.</description>
180368 <description>The SU3 field is only accessible from the Secure state.</description>
180375 <description>State UNKNOWN 4.</description>
180382 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180387 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180394 <description>State UNKNOWN Secure only 4.</description>
180401 <description>The SU4 field is accessible from both Security states.</description>
180406 <description>The SU4 field is only accessible from the Secure state.</description>
180413 <description>State UNKNOWN 5.</description>
180420 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180425 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180432 <description>State UNKNOWN Secure only 5.</description>
180439 <description>The SU5 field is accessible from both Security states.</description>
180444 <description>The SU5 field is only accessible from the Secure state.</description>
180451 <description>State UNKNOWN 6.</description>
180458 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180463 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180470 <description>State UNKNOWN Secure only 6.</description>
180477 <description>The SU6 field is accessible from both Security states.</description>
180482 <description>The SU6 field is only accessible from the Secure state.</description>
180489 <description>State UNKNOWN 7.</description>
180496 … <description>The coprocessor state is not permitted to become UNKNOWN.</description>
180501 <description>The coprocessor state is permitted to become UNKNOWN.</description>
180508 <description>State UNKNOWN Secure only 7.</description>
180515 <description>The SU7 field is accessible from both Security states.</description>
180520 <description>The SU7 field is only accessible from the Secure state.</description>
180527 <description>State UNKNOWN 10.</description>
180534 … <description>The floating-point state is not permitted to become UNKNOWN.</description>
180539 <description>The floating-point state is permitted to become UNKNOWN</description>
180546 <description>State UNKNOWN Secure only 10.</description>
180553 <description>The SU10 field is accessible from both Security states.</description>
180558 … <description>The SU10 field is only accessible from the Secure state.</description>
180565 <description>State UNKNOWN 11.</description>
180572 <description>State UNKNOWN Secure only 11.</description>
180583 <description>no description available</description>
180596 <description>Interrupt Set Enable Register</description>
180605 <description>Interrupt set-enable bits.</description>
180612 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180617 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180624 <description>Interrupt set-enable bits.</description>
180631 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180636 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180643 <description>Interrupt set-enable bits.</description>
180650 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180655 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180662 <description>Interrupt set-enable bits.</description>
180669 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180674 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180681 <description>Interrupt set-enable bits.</description>
180688 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180693 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180700 <description>Interrupt set-enable bits.</description>
180707 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180712 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180719 <description>Interrupt set-enable bits.</description>
180726 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180731 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180738 <description>Interrupt set-enable bits.</description>
180745 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180750 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180757 <description>Interrupt set-enable bits.</description>
180764 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180769 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180776 <description>Interrupt set-enable bits.</description>
180783 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180788 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180795 <description>Interrupt set-enable bits.</description>
180802 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180807 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180814 <description>Interrupt set-enable bits.</description>
180821 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180826 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180833 <description>Interrupt set-enable bits.</description>
180840 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180845 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180852 <description>Interrupt set-enable bits.</description>
180859 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180864 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180871 <description>Interrupt set-enable bits.</description>
180878 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180883 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180890 <description>Interrupt set-enable bits.</description>
180897 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180902 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180909 <description>Interrupt set-enable bits.</description>
180916 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180921 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180928 <description>Interrupt set-enable bits.</description>
180935 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180940 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180947 <description>Interrupt set-enable bits.</description>
180954 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180959 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180966 <description>Interrupt set-enable bits.</description>
180973 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180978 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
180985 <description>Interrupt set-enable bits.</description>
180992 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
180997 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181004 <description>Interrupt set-enable bits.</description>
181011 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181016 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181023 <description>Interrupt set-enable bits.</description>
181030 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181035 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181042 <description>Interrupt set-enable bits.</description>
181049 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181054 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181061 <description>Interrupt set-enable bits.</description>
181068 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181073 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181080 <description>Interrupt set-enable bits.</description>
181087 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181092 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181099 <description>Interrupt set-enable bits.</description>
181106 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181111 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181118 <description>Interrupt set-enable bits.</description>
181125 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181130 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181137 <description>Interrupt set-enable bits.</description>
181144 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181149 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181156 <description>Interrupt set-enable bits.</description>
181163 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181168 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181175 <description>Interrupt set-enable bits.</description>
181182 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181187 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181194 <description>Interrupt set-enable bits.</description>
181201 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181206 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181217 <description>Interrupt Clear Enable Register</description>
181226 <description>Interrupt clear-enable bits.</description>
181233 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181238 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181245 <description>Interrupt clear-enable bits.</description>
181252 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181257 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181264 <description>Interrupt clear-enable bits.</description>
181271 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181276 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181283 <description>Interrupt clear-enable bits.</description>
181290 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181295 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181302 <description>Interrupt clear-enable bits.</description>
181309 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181314 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181321 <description>Interrupt clear-enable bits.</description>
181328 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181333 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181340 <description>Interrupt clear-enable bits.</description>
181347 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181352 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181359 <description>Interrupt clear-enable bits.</description>
181366 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181371 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181378 <description>Interrupt clear-enable bits.</description>
181385 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181390 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181397 <description>Interrupt clear-enable bits.</description>
181404 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181409 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181416 <description>Interrupt clear-enable bits.</description>
181423 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181428 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181435 <description>Interrupt clear-enable bits.</description>
181442 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181447 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181454 <description>Interrupt clear-enable bits.</description>
181461 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181466 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181473 <description>Interrupt clear-enable bits.</description>
181480 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181485 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181492 <description>Interrupt clear-enable bits.</description>
181499 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181504 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181511 <description>Interrupt clear-enable bits.</description>
181518 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181523 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181530 <description>Interrupt clear-enable bits.</description>
181537 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181542 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181549 <description>Interrupt clear-enable bits.</description>
181556 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181561 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181568 <description>Interrupt clear-enable bits.</description>
181575 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181580 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181587 <description>Interrupt clear-enable bits.</description>
181594 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181599 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181606 <description>Interrupt clear-enable bits.</description>
181613 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181618 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181625 <description>Interrupt clear-enable bits.</description>
181632 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181637 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181644 <description>Interrupt clear-enable bits.</description>
181651 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181656 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181663 <description>Interrupt clear-enable bits.</description>
181670 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181675 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181682 <description>Interrupt clear-enable bits.</description>
181689 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181694 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181701 <description>Interrupt clear-enable bits.</description>
181708 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181713 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181720 <description>Interrupt clear-enable bits.</description>
181727 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181732 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181739 <description>Interrupt clear-enable bits.</description>
181746 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181751 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181758 <description>Interrupt clear-enable bits.</description>
181765 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181770 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181777 <description>Interrupt clear-enable bits.</description>
181784 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181789 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181796 <description>Interrupt clear-enable bits.</description>
181803 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181808 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181815 <description>Interrupt clear-enable bits.</description>
181822 <description>Write: No effect; Read: Interrupt 32n+m disabled</description>
181827 … <description>Write: Enable interrupt 32n+m; Read: Interrupt 32n+m enabled</description>
181838 <description>Interrupt Set Pending Register</description>
181847 <description>Interrupt set-pending bits.</description>
181854 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181859 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181866 <description>Interrupt set-pending bits.</description>
181873 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181878 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181885 <description>Interrupt set-pending bits.</description>
181892 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181897 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181904 <description>Interrupt set-pending bits.</description>
181911 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181916 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181923 <description>Interrupt set-pending bits.</description>
181930 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181935 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181942 <description>Interrupt set-pending bits.</description>
181949 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181954 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181961 <description>Interrupt set-pending bits.</description>
181968 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181973 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181980 <description>Interrupt set-pending bits.</description>
181987 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
181992 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
181999 <description>Interrupt set-pending bits.</description>
182006 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182011 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182018 <description>Interrupt set-pending bits.</description>
182025 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182030 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182037 <description>Interrupt set-pending bits.</description>
182044 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182049 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182056 <description>Interrupt set-pending bits.</description>
182063 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182068 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182075 <description>Interrupt set-pending bits.</description>
182082 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182087 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182094 <description>Interrupt set-pending bits.</description>
182101 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182106 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182113 <description>Interrupt set-pending bits.</description>
182120 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182125 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182132 <description>Interrupt set-pending bits.</description>
182139 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182144 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182151 <description>Interrupt set-pending bits.</description>
182158 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182163 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182170 <description>Interrupt set-pending bits.</description>
182177 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182182 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182189 <description>Interrupt set-pending bits.</description>
182196 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182201 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182208 <description>Interrupt set-pending bits.</description>
182215 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182220 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182227 <description>Interrupt set-pending bits.</description>
182234 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182239 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182246 <description>Interrupt set-pending bits.</description>
182253 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182258 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182265 <description>Interrupt set-pending bits.</description>
182272 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182277 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182284 <description>Interrupt set-pending bits.</description>
182291 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182296 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182303 <description>Interrupt set-pending bits.</description>
182310 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182315 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182322 <description>Interrupt set-pending bits.</description>
182329 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182334 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182341 <description>Interrupt set-pending bits.</description>
182348 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182353 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182360 <description>Interrupt set-pending bits.</description>
182367 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182372 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182379 <description>Interrupt set-pending bits.</description>
182386 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182391 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182398 <description>Interrupt set-pending bits.</description>
182405 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182410 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182417 <description>Interrupt set-pending bits.</description>
182424 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182429 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182436 <description>Interrupt set-pending bits.</description>
182443 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182448 … <description>Write: Pend interrupt 32n+m; Read: Interrupt 32n+m pending</description>
182459 <description>Interrupt Clear Pending Register</description>
182468 <description>Interrupt clear-pending bits.</description>
182475 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182480 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182487 <description>Interrupt clear-pending bits.</description>
182494 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182499 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182506 <description>Interrupt clear-pending bits.</description>
182513 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182518 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182525 <description>Interrupt clear-pending bits.</description>
182532 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182537 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182544 <description>Interrupt clear-pending bits.</description>
182551 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182556 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182563 <description>Interrupt clear-pending bits.</description>
182570 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182575 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182582 <description>Interrupt clear-pending bits.</description>
182589 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182594 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182601 <description>Interrupt clear-pending bits.</description>
182608 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182613 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182620 <description>Interrupt clear-pending bits.</description>
182627 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182632 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182639 <description>Interrupt clear-pending bits.</description>
182646 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182651 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182658 <description>Interrupt clear-pending bits.</description>
182665 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182670 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182677 <description>Interrupt clear-pending bits.</description>
182684 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182689 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182696 <description>Interrupt clear-pending bits.</description>
182703 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182708 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182715 <description>Interrupt clear-pending bits.</description>
182722 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182727 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182734 <description>Interrupt clear-pending bits.</description>
182741 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182746 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182753 <description>Interrupt clear-pending bits.</description>
182760 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182765 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182772 <description>Interrupt clear-pending bits.</description>
182779 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182784 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182791 <description>Interrupt clear-pending bits.</description>
182798 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182803 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182810 <description>Interrupt clear-pending bits.</description>
182817 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182822 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182829 <description>Interrupt clear-pending bits.</description>
182836 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182841 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182848 <description>Interrupt clear-pending bits.</description>
182855 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182860 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182867 <description>Interrupt clear-pending bits.</description>
182874 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182879 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182886 <description>Interrupt clear-pending bits.</description>
182893 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182898 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182905 <description>Interrupt clear-pending bits.</description>
182912 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182917 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182924 <description>Interrupt clear-pending bits.</description>
182931 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182936 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182943 <description>Interrupt clear-pending bits.</description>
182950 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182955 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182962 <description>Interrupt clear-pending bits.</description>
182969 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182974 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
182981 <description>Interrupt clear-pending bits.</description>
182988 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
182993 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
183000 <description>Interrupt clear-pending bits.</description>
183007 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
183012 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
183019 <description>Interrupt clear-pending bits.</description>
183026 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
183031 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
183038 <description>Interrupt clear-pending bits.</description>
183045 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
183050 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
183057 <description>Interrupt clear-pending bits.</description>
183064 <description>Write: No effect; Read: Interrupt 32n+m is not pending</description>
183069 …<description>Write: Clear pending state of interrupt 32n+m; Read: Interrupt 32n+m is pending</desc…
183080 <description>Interrupt Active Bit Register</description>
183089 <description>Active state bits.</description>
183096 <description>The interrupt is not active.</description>
183101 <description>The interrupt is active.</description>
183108 <description>Active state bits.</description>
183115 <description>The interrupt is not active.</description>
183120 <description>The interrupt is active.</description>
183127 <description>Active state bits.</description>
183134 <description>The interrupt is not active.</description>
183139 <description>The interrupt is active.</description>
183146 <description>Active state bits.</description>
183153 <description>The interrupt is not active.</description>
183158 <description>The interrupt is active.</description>
183165 <description>Active state bits.</description>
183172 <description>The interrupt is not active.</description>
183177 <description>The interrupt is active.</description>
183184 <description>Active state bits.</description>
183191 <description>The interrupt is not active.</description>
183196 <description>The interrupt is active.</description>
183203 <description>Active state bits.</description>
183210 <description>The interrupt is not active.</description>
183215 <description>The interrupt is active.</description>
183222 <description>Active state bits.</description>
183229 <description>The interrupt is not active.</description>
183234 <description>The interrupt is active.</description>
183241 <description>Active state bits.</description>
183248 <description>The interrupt is not active.</description>
183253 <description>The interrupt is active.</description>
183260 <description>Active state bits.</description>
183267 <description>The interrupt is not active.</description>
183272 <description>The interrupt is active.</description>
183279 <description>Active state bits.</description>
183286 <description>The interrupt is not active.</description>
183291 <description>The interrupt is active.</description>
183298 <description>Active state bits.</description>
183305 <description>The interrupt is not active.</description>
183310 <description>The interrupt is active.</description>
183317 <description>Active state bits.</description>
183324 <description>The interrupt is not active.</description>
183329 <description>The interrupt is active.</description>
183336 <description>Active state bits.</description>
183343 <description>The interrupt is not active.</description>
183348 <description>The interrupt is active.</description>
183355 <description>Active state bits.</description>
183362 <description>The interrupt is not active.</description>
183367 <description>The interrupt is active.</description>
183374 <description>Active state bits.</description>
183381 <description>The interrupt is not active.</description>
183386 <description>The interrupt is active.</description>
183393 <description>Active state bits.</description>
183400 <description>The interrupt is not active.</description>
183405 <description>The interrupt is active.</description>
183412 <description>Active state bits.</description>
183419 <description>The interrupt is not active.</description>
183424 <description>The interrupt is active.</description>
183431 <description>Active state bits.</description>
183438 <description>The interrupt is not active.</description>
183443 <description>The interrupt is active.</description>
183450 <description>Active state bits.</description>
183457 <description>The interrupt is not active.</description>
183462 <description>The interrupt is active.</description>
183469 <description>Active state bits.</description>
183476 <description>The interrupt is not active.</description>
183481 <description>The interrupt is active.</description>
183488 <description>Active state bits.</description>
183495 <description>The interrupt is not active.</description>
183500 <description>The interrupt is active.</description>
183507 <description>Active state bits.</description>
183514 <description>The interrupt is not active.</description>
183519 <description>The interrupt is active.</description>
183526 <description>Active state bits.</description>
183533 <description>The interrupt is not active.</description>
183538 <description>The interrupt is active.</description>
183545 <description>Active state bits.</description>
183552 <description>The interrupt is not active.</description>
183557 <description>The interrupt is active.</description>
183564 <description>Active state bits.</description>
183571 <description>The interrupt is not active.</description>
183576 <description>The interrupt is active.</description>
183583 <description>Active state bits.</description>
183590 <description>The interrupt is not active.</description>
183595 <description>The interrupt is active.</description>
183602 <description>Active state bits.</description>
183609 <description>The interrupt is not active.</description>
183614 <description>The interrupt is active.</description>
183621 <description>Active state bits.</description>
183628 <description>The interrupt is not active.</description>
183633 <description>The interrupt is active.</description>
183640 <description>Active state bits.</description>
183647 <description>The interrupt is not active.</description>
183652 <description>The interrupt is active.</description>
183659 <description>Active state bits.</description>
183666 <description>The interrupt is not active.</description>
183671 <description>The interrupt is active.</description>
183678 <description>Active state bits.</description>
183685 <description>The interrupt is not active.</description>
183690 <description>The interrupt is active.</description>
183701 <description>Interrupt Target Non-secure Register</description>
183710 <description>Interrupt Targets Non-secure bits.</description>
183717 <description>The interrupt targets Secure state.</description>
183722 <description>The interrupt targets Non-secure state.</description>
183729 <description>Interrupt Targets Non-secure bits.</description>
183736 <description>The interrupt targets Secure state.</description>
183741 <description>The interrupt targets Non-secure state.</description>
183748 <description>Interrupt Targets Non-secure bits.</description>
183755 <description>The interrupt targets Secure state.</description>
183760 <description>The interrupt targets Non-secure state.</description>
183767 <description>Interrupt Targets Non-secure bits.</description>
183774 <description>The interrupt targets Secure state.</description>
183779 <description>The interrupt targets Non-secure state.</description>
183786 <description>Interrupt Targets Non-secure bits.</description>
183793 <description>The interrupt targets Secure state.</description>
183798 <description>The interrupt targets Non-secure state.</description>
183805 <description>Interrupt Targets Non-secure bits.</description>
183812 <description>The interrupt targets Secure state.</description>
183817 <description>The interrupt targets Non-secure state.</description>
183824 <description>Interrupt Targets Non-secure bits.</description>
183831 <description>The interrupt targets Secure state.</description>
183836 <description>The interrupt targets Non-secure state.</description>
183843 <description>Interrupt Targets Non-secure bits.</description>
183850 <description>The interrupt targets Secure state.</description>
183855 <description>The interrupt targets Non-secure state.</description>
183862 <description>Interrupt Targets Non-secure bits.</description>
183869 <description>The interrupt targets Secure state.</description>
183874 <description>The interrupt targets Non-secure state.</description>
183881 <description>Interrupt Targets Non-secure bits.</description>
183888 <description>The interrupt targets Secure state.</description>
183893 <description>The interrupt targets Non-secure state.</description>
183900 <description>Interrupt Targets Non-secure bits.</description>
183907 <description>The interrupt targets Secure state.</description>
183912 <description>The interrupt targets Non-secure state.</description>
183919 <description>Interrupt Targets Non-secure bits.</description>
183926 <description>The interrupt targets Secure state.</description>
183931 <description>The interrupt targets Non-secure state.</description>
183938 <description>Interrupt Targets Non-secure bits.</description>
183945 <description>The interrupt targets Secure state.</description>
183950 <description>The interrupt targets Non-secure state.</description>
183957 <description>Interrupt Targets Non-secure bits.</description>
183964 <description>The interrupt targets Secure state.</description>
183969 <description>The interrupt targets Non-secure state.</description>
183976 <description>Interrupt Targets Non-secure bits.</description>
183983 <description>The interrupt targets Secure state.</description>
183988 <description>The interrupt targets Non-secure state.</description>
183995 <description>Interrupt Targets Non-secure bits.</description>
184002 <description>The interrupt targets Secure state.</description>
184007 <description>The interrupt targets Non-secure state.</description>
184014 <description>Interrupt Targets Non-secure bits.</description>
184021 <description>The interrupt targets Secure state.</description>
184026 <description>The interrupt targets Non-secure state.</description>
184033 <description>Interrupt Targets Non-secure bits.</description>
184040 <description>The interrupt targets Secure state.</description>
184045 <description>The interrupt targets Non-secure state.</description>
184052 <description>Interrupt Targets Non-secure bits.</description>
184059 <description>The interrupt targets Secure state.</description>
184064 <description>The interrupt targets Non-secure state.</description>
184071 <description>Interrupt Targets Non-secure bits.</description>
184078 <description>The interrupt targets Secure state.</description>
184083 <description>The interrupt targets Non-secure state.</description>
184090 <description>Interrupt Targets Non-secure bits.</description>
184097 <description>The interrupt targets Secure state.</description>
184102 <description>The interrupt targets Non-secure state.</description>
184109 <description>Interrupt Targets Non-secure bits.</description>
184116 <description>The interrupt targets Secure state.</description>
184121 <description>The interrupt targets Non-secure state.</description>
184128 <description>Interrupt Targets Non-secure bits.</description>
184135 <description>The interrupt targets Secure state.</description>
184140 <description>The interrupt targets Non-secure state.</description>
184147 <description>Interrupt Targets Non-secure bits.</description>
184154 <description>The interrupt targets Secure state.</description>
184159 <description>The interrupt targets Non-secure state.</description>
184166 <description>Interrupt Targets Non-secure bits.</description>
184173 <description>The interrupt targets Secure state.</description>
184178 <description>The interrupt targets Non-secure state.</description>
184185 <description>Interrupt Targets Non-secure bits.</description>
184192 <description>The interrupt targets Secure state.</description>
184197 <description>The interrupt targets Non-secure state.</description>
184204 <description>Interrupt Targets Non-secure bits.</description>
184211 <description>The interrupt targets Secure state.</description>
184216 <description>The interrupt targets Non-secure state.</description>
184223 <description>Interrupt Targets Non-secure bits.</description>
184230 <description>The interrupt targets Secure state.</description>
184235 <description>The interrupt targets Non-secure state.</description>
184242 <description>Interrupt Targets Non-secure bits.</description>
184249 <description>The interrupt targets Secure state.</description>
184254 <description>The interrupt targets Non-secure state.</description>
184261 <description>Interrupt Targets Non-secure bits.</description>
184268 <description>The interrupt targets Secure state.</description>
184273 <description>The interrupt targets Non-secure state.</description>
184280 <description>Interrupt Targets Non-secure bits.</description>
184287 <description>The interrupt targets Secure state.</description>
184292 <description>The interrupt targets Non-secure state.</description>
184299 <description>Interrupt Targets Non-secure bits.</description>
184306 <description>The interrupt targets Secure state.</description>
184311 <description>The interrupt targets Non-secure state.</description>
184322 <description>Interrupt Priority Register</description>
184331 <description>no description available</description>
184338 <description>no description available</description>
184345 <description>no description available</description>
184352 <description>no description available</description>
184361 <description>Software Trigger Interrupt Register</description>
184370 … <description>Interrupt ID of the interrupt to trigger, in the range 0-479.</description>
184381 <description>no description available</description>
184392 <description>Application Interrupt and Reset Control Register</description>
184401 …description>Reserved for Debug use. This bit reads as 0. When writing to the register you must wri…
184408 …description>System reset request. This bit allows software or a debugger to request a system reset…
184415 <description>Do not request a system reset.</description>
184420 <description>Request a system reset.</description>
184427 …description>System reset request, Secure state only. The value of this bit defines whether the SYS…
184434 … <description>SYSRESETREQ functionality is available to both Security states.</description>
184439 … <description>SYSRESETREQ functionality is only available to Secure state.</description>
184446 …description>Interrupt priority grouping field. This field determines the split of group priority f…
184453 …description>BusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether …
184460 <description>BusFault, HardFault, and NMI are Secure.</description>
184465 …<description>BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.</desc…
184472 …description>Prioritize Secure exceptions. The value of this bit defines whether Secure exception p…
184479 … <description>Priority ranges of Secure and Non-secure exceptions are identical</description>
184484 <description>Non-secure exceptions are de-prioritized</description>
184491 … <description>Data endianness bit. This bit is not banked between Security states.</description>
184498 <description>Little-endian.</description>
184503 <description>Big-endian</description>
184510 …description>Register key: Reads as 0xFA05. On writes, write 0x5FA to VECTKEY, otherwise the write …
184519 … <description>The SCR controls features of entry to and exit from low-power state.</description>
184528 …description>Indicates sleep-on-exit when returning from Handler mode to Thread mode. Setting this …
184535 <description>Do not sleep when returning to Thread mode.</description>
184540 <description>Enter sleep, or deep sleep, on return from an ISR</description>
184547 …<description>Controls whether the processor uses sleep or deep sleep as its low-power mode. This b…
184554 <description>Sleep.</description>
184559 <description>Deep sleep.</description>
184566 …description>Controls whether the SLEEPDEEP bit is only accessible from the Secure state. This bit …
184573 … <description>The SLEEPDEEP bit is accessible from both Security states.</description>
184578 …<description>The SLEEPDEEP bit behaves as RAZ/WI when accessed from the Non-secure state.</descrip…
184585 …description>Send Event on Pending bit. When an event or interrupt enters pending state, the event …
184592 …<description>Only enabled interrupts or events can wakeup the processor, disabled interrupts are e…
184597 …<description>Enabled events and all interrupts, including disabled interrupts, can wakeup the proc…
184606 <description>System Handler Control and State Register</description>
184615 <description>MemManage exception active.</description>
184622 <description>MemManage exception is not active.</description>
184627 <description>MemManage exception is active.</description>
184634 <description>BusFault exception active.</description>
184641 <description>BusFault exception is not active.</description>
184646 <description>BusFault exception is active.</description>
184653 <description>HardFault exception active.</description>
184660 <description>HardFault exception is not active.</description>
184665 <description>HardFault exception is active.</description>
184672 <description>UsageFault exception active.</description>
184679 <description>UsageFault exception is not active.</description>
184684 <description>UsageFault exception is active.</description>
184691 <description>SecureFault exception active</description>
184698 <description>SecureFault exception is not active.</description>
184703 <description>SecureFault exception is active.</description>
184710 <description>NMI exception active.</description>
184717 <description>NMI exception is not active.</description>
184722 <description>NMI exception is active.</description>
184729 <description>SVCall active.</description>
184736 <description>SVCall exception is not active.</description>
184741 <description>SVCall exception is active.</description>
184748 <description>Debug monitor active.</description>
184755 <description>Debug monitor exception is not active.</description>
184760 <description>Debug monitor exception is active.</description>
184767 <description>PendSV exception active.</description>
184774 <description>PendSV exception is not active.</description>
184779 <description>PendSV exception is active.</description>
184786 <description>SysTick exception active.</description>
184793 <description>SysTick exception is not active.</description>
184798 <description>SysTick exception is active.</description>
184805 <description>UsageFault exception pending.</description>
184812 <description>UsageFault exception is not pending.</description>
184817 <description>UsageFault exception is pending.</description>
184824 <description>MemManage exception pending.</description>
184831 <description>MemManage exception is not pending.</description>
184836 <description>MemManage exception is pending.</description>
184843 <description>BusFault exception pending.</description>
184850 <description>BusFault exception is pending.</description>
184855 <description>BusFault exception is not pending.</description>
184862 <description>SVCall pending.</description>
184869 <description>SVCall exception is not pending.</description>
184874 <description>SVCall exception is pending.</description>
184881 <description>MemManage enable.</description>
184888 <description>MemManage exception is disabled.</description>
184893 <description>MemManage exception is enabled.</description>
184900 <description>BusFault enable.</description>
184907 <description>BusFault is disabled.</description>
184912 <description>BusFault is enabled.</description>
184919 <description>UsageFault enable.</description>
184926 <description>UsageFault is disabled.</description>
184931 <description>UsageFault is enabled.</description>
184938 <description>SecureFault exception enable.</description>
184945 <description>SecureFault exception is disabled.</description>
184950 <description>SecureFault exception is enabled.</description>
184957 <description>SecureFault exception pended state bit.</description>
184964 <description>SecureFault exception modification is disabled.</description>
184969 <description>SecureFault exception modification is enabled.</description>
184976 <description>HardFault exception pended state</description>
184983 <description>HardFault exception modification is disabled.</description>
184988 <description>HardFault exception modification is enabled.</description>
184997 <description>Non-secure Access Control Register</description>
185006 <description>CP0 access.</description>
185013 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185018 <description>Non-secure access to this coprocessor permitted.</description>
185025 <description>CP1 access.</description>
185032 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185037 <description>Non-secure access to this coprocessor permitted.</description>
185044 <description>CP2 access.</description>
185051 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185056 <description>Non-secure access to this coprocessor permitted.</description>
185063 <description>CP3 access.</description>
185070 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185075 <description>Non-secure access to this coprocessor permitted.</description>
185082 <description>CP4 access.</description>
185089 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185094 <description>Non-secure access to this coprocessor permitted.</description>
185101 <description>CP5 access.</description>
185108 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185113 <description>Non-secure access to this coprocessor permitted.</description>
185120 <description>CP6 access.</description>
185127 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185132 <description>Non-secure access to this coprocessor permitted.</description>
185139 <description>CP7 access.</description>
185146 … <description>Non-secure accesses to this coprocessor generate a NOCP UsageFault.</description>
185151 <description>Non-secure access to this coprocessor permitted.</description>
185158 <description>CP10 access.</description>
185165 …<description>Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault.</desc…
185170 … <description>Non-secure access to the Floatingpoint Extension permitted.</description>
185177 <description>CP11 access.</description>
185188 <description>no description available</description>
185199 <description>Security Attribution Unit Control Register</description>
185208 …<description>Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemente…
185215 <description>The SAU is disabled.</description>
185220 <description>The SAU is enabled.</description>
185227 <description>All Non-secure.</description>
185234 … <description>Memory is marked as Secure and is not Non-secure callable.</description>
185239 <description>Memory is marked as Non-secure.</description>
185248 <description>Security Attribution Unit Type Register</description>
185257 <description>SAU regions. The number of implemented SAU regions.</description>
185266 <description>Security Attribution Unit Region Number Register</description>
185275 <description>Region number.</description>
185284 <description>Security Attribution Unit Region Base Address Register</description>
185293 …description>Base address. Holds bits[31:5] of the base address for the selected SAU region. Bits[4…
185302 <description>Security Attribution Unit Region Limit Address Register</description>
185311 <description>Enable. SAU region enable.</description>
185318 <description>SAU region is enabled.</description>
185323 <description>SAU region is disabled.</description>
185330 …<description>Non-secure callable. Controls whether Non-secure state is permitted to execute an SG …
185337 <description>Region is not Non-secure callable.</description>
185342 <description>Region is Non-secure callable.</description>
185349 …description>Limit address. Holds bits[31:5] of the limit address for the selected SAU region. Bits…
185358 <description>Secure Fault Status Register</description>
185367 <description>Invalid entry point.</description>
185374 <description>Error has not occurred.</description>
185379 <description>Error has occurred.</description>
185386 <description>Invalid integrity signature flag.</description>
185393 <description>Error has not occurred.</description>
185398 <description>Error has occurred.</description>
185405 <description>Invalid exception return flag.</description>
185412 <description>Error has not occurred.</description>
185417 <description>Error has occurred.</description>
185424 <description>Attribution unit violation flag.</description>
185431 <description>Error has not occurred.</description>
185436 <description>Error has occurred.</description>
185443 <description>Invalid transition flag.</description>
185450 <description>Error has not occurred.</description>
185455 <description>Error has occurred.</description>
185462 <description>Lazy state preservation error flag.</description>
185469 <description>Error has not occurred.</description>
185474 <description>Error has occurred.</description>
185481 <description>Secure fault address valid.</description>
185488 <description>SFAR content not valid.</description>
185493 <description>SFAR content valid.</description>
185500 <description>Lazy state error flag.</description>
185507 <description>Error has not occurred</description>
185512 <description>Error has occurred.</description>
185521 <description>Secure Fault Address Register</description>
185530 …<description>When the SFARVALID bit of the SFSR is set to 1, this field holds the address of an ac…