Lines Matching refs:DMA0
48 #define RTE_USART0_DMA_TX_DMA_BASE DMA0
50 #define RTE_USART0_DMA_RX_DMA_BASE DMA0
55 #define RTE_USART1_DMA_TX_DMA_BASE DMA0
57 #define RTE_USART1_DMA_RX_DMA_BASE DMA0
62 #define RTE_USART2_DMA_TX_DMA_BASE DMA0
64 #define RTE_USART2_DMA_RX_DMA_BASE DMA0
69 #define RTE_USART3_DMA_TX_DMA_BASE DMA0
71 #define RTE_USART3_DMA_RX_DMA_BASE DMA0
76 #define RTE_USART4_DMA_TX_DMA_BASE DMA0
78 #define RTE_USART4_DMA_RX_DMA_BASE DMA0
83 #define RTE_USART5_DMA_TX_DMA_BASE DMA0
85 #define RTE_USART5_DMA_RX_DMA_BASE DMA0
90 #define RTE_USART6_DMA_TX_DMA_BASE DMA0
92 #define RTE_USART6_DMA_RX_DMA_BASE DMA0
97 #define RTE_USART7_DMA_TX_DMA_BASE DMA0
99 #define RTE_USART7_DMA_RX_DMA_BASE DMA0
122 #define RTE_I2C0_Master_DMA_BASE DMA0
125 #define RTE_I2C1_Master_DMA_BASE DMA0
128 #define RTE_I2C2_Master_DMA_BASE DMA0
131 #define RTE_I2C3_Master_DMA_BASE DMA0
134 #define RTE_I2C4_Master_DMA_BASE DMA0
137 #define RTE_I2C5_Master_DMA_BASE DMA0
140 #define RTE_I2C6_Master_DMA_BASE DMA0
143 #define RTE_I2C7_Master_DMA_BASE DMA0
171 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0
173 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0
179 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0
181 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0
187 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0
189 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0
195 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0
197 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0
203 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0
205 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0
211 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0
213 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0
219 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0
221 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0
227 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0
229 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0