Lines Matching refs:DMA0
49 #define RTE_USART0_DMA_TX_DMA_BASE DMA0
51 #define RTE_USART0_DMA_RX_DMA_BASE DMA0
56 #define RTE_USART1_DMA_TX_DMA_BASE DMA0
58 #define RTE_USART1_DMA_RX_DMA_BASE DMA0
63 #define RTE_USART2_DMA_TX_DMA_BASE DMA0
65 #define RTE_USART2_DMA_RX_DMA_BASE DMA0
70 #define RTE_USART3_DMA_TX_DMA_BASE DMA0
72 #define RTE_USART3_DMA_RX_DMA_BASE DMA0
77 #define RTE_USART4_DMA_TX_DMA_BASE DMA0
79 #define RTE_USART4_DMA_RX_DMA_BASE DMA0
84 #define RTE_USART5_DMA_TX_DMA_BASE DMA0
86 #define RTE_USART5_DMA_RX_DMA_BASE DMA0
91 #define RTE_USART6_DMA_TX_DMA_BASE DMA0
93 #define RTE_USART6_DMA_RX_DMA_BASE DMA0
98 #define RTE_USART7_DMA_TX_DMA_BASE DMA0
100 #define RTE_USART7_DMA_RX_DMA_BASE DMA0
123 #define RTE_I2C0_Master_DMA_BASE DMA0
126 #define RTE_I2C1_Master_DMA_BASE DMA0
129 #define RTE_I2C2_Master_DMA_BASE DMA0
132 #define RTE_I2C3_Master_DMA_BASE DMA0
135 #define RTE_I2C4_Master_DMA_BASE DMA0
138 #define RTE_I2C5_Master_DMA_BASE DMA0
141 #define RTE_I2C6_Master_DMA_BASE DMA0
144 #define RTE_I2C7_Master_DMA_BASE DMA0
172 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0
174 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0
180 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0
182 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0
188 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0
190 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0
196 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0
198 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0
204 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0
206 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0
212 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0
214 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0
220 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0
222 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0
228 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0
230 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0