Lines Matching refs:op2
1021 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
1023 op2 %= 32U; in __ROR()
1024 if (op2 == 0U) in __ROR()
1028 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1621 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1625 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1629 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1633 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1637 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1641 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
1645 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) in __UADD8() argument
1649 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD8()
1653 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) in __UQADD8() argument
1657 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD8()
1661 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) in __UHADD8() argument
1665 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD8()
1670 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) in __SSUB8() argument
1674 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB8()
1678 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) in __QSUB8() argument
1682 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB8()
1686 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) in __SHSUB8() argument
1690 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB8()
1694 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) in __USUB8() argument
1698 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB8()
1702 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) in __UQSUB8() argument
1706 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB8()
1710 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) in __UHSUB8() argument
1714 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB8()
1719 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) in __SADD16() argument
1723 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD16()
1727 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) in __QADD16() argument
1731 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD16()
1735 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) in __SHADD16() argument
1739 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD16()
1743 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) in __UADD16() argument
1747 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD16()
1751 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) in __UQADD16() argument
1755 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD16()
1759 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) in __UHADD16() argument
1763 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD16()
1767 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) in __SSUB16() argument
1771 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB16()
1775 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) in __QSUB16() argument
1779 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB16()
1783 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) in __SHSUB16() argument
1787 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB16()
1791 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) in __USUB16() argument
1795 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB16()
1799 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) in __UQSUB16() argument
1803 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB16()
1807 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) in __UHSUB16() argument
1811 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB16()
1815 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) in __SASX() argument
1819 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SASX()
1823 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) in __QASX() argument
1827 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QASX()
1831 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) in __SHASX() argument
1835 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHASX()
1839 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) in __UASX() argument
1843 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UASX()
1847 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) in __UQASX() argument
1851 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQASX()
1855 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) in __UHASX() argument
1859 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHASX()
1863 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) in __SSAX() argument
1867 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSAX()
1871 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) in __QSAX() argument
1875 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSAX()
1879 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) in __SHSAX() argument
1883 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSAX()
1887 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) in __USAX() argument
1891 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAX()
1895 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) in __UQSAX() argument
1899 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSAX()
1903 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) in __UHSAX() argument
1907 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSAX()
1911 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) in __USAD8() argument
1915 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAD8()
1919 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) in __USADA8() argument
1923 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __USADA8()
1949 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) in __UXTAB16() argument
1953 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UXTAB16()
1965 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) in __SXTAB16() argument
1969 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SXTAB16()
1973 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) in __SMUAD() argument
1977 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUAD()
1981 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) in __SMUADX() argument
1985 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUADX()
1989 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLAD() argument
1993 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLAD()
1997 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLADX() argument
2001 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLADX()
2005 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLALD() argument
2014 …ld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLALD()
2016 …ld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLALD()
2022 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLALDX() argument
2031 …dx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLALDX()
2033 …dx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLALDX()
2039 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) in __SMUSD() argument
2043 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSD()
2047 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) in __SMUSDX() argument
2051 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSDX()
2055 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSD() argument
2059 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSD()
2063 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSDX() argument
2067 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSDX()
2071 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLSLD() argument
2080 …ld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLSLD()
2082 …ld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLSLD()
2088 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLSLDX() argument
2097 …dx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLSLDX()
2099 …dx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLSLDX()
2105 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) in __SEL() argument
2109 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SEL()
2113 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) in __QADD() argument
2117 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
2121 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) in __QSUB() argument
2125 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB()
2154 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
2158 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()