Lines Matching refs:op2
901 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR() argument
903 op2 %= 32U; in __ROR()
904 if (op2 == 0U) in __ROR()
908 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
1365 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) in __SADD8() argument
1369 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
1373 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) in __QADD8() argument
1377 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
1381 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) in __SHADD8() argument
1385 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
1389 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) in __UADD8() argument
1393 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD8()
1397 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) in __UQADD8() argument
1401 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD8()
1405 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) in __UHADD8() argument
1409 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD8()
1414 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) in __SSUB8() argument
1418 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB8()
1422 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) in __QSUB8() argument
1426 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB8()
1430 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) in __SHSUB8() argument
1434 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB8()
1438 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) in __USUB8() argument
1442 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB8()
1446 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) in __UQSUB8() argument
1450 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB8()
1454 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) in __UHSUB8() argument
1458 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB8()
1463 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) in __SADD16() argument
1467 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD16()
1471 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) in __QADD16() argument
1475 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD16()
1479 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) in __SHADD16() argument
1483 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD16()
1487 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) in __UADD16() argument
1491 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD16()
1495 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) in __UQADD16() argument
1499 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD16()
1503 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) in __UHADD16() argument
1507 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD16()
1511 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) in __SSUB16() argument
1515 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB16()
1519 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) in __QSUB16() argument
1523 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB16()
1527 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) in __SHSUB16() argument
1531 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB16()
1535 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) in __USUB16() argument
1539 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB16()
1543 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) in __UQSUB16() argument
1547 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB16()
1551 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) in __UHSUB16() argument
1555 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB16()
1559 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) in __SASX() argument
1563 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SASX()
1567 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) in __QASX() argument
1571 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QASX()
1575 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) in __SHASX() argument
1579 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHASX()
1583 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) in __UASX() argument
1587 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UASX()
1591 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) in __UQASX() argument
1595 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQASX()
1599 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) in __UHASX() argument
1603 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHASX()
1607 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) in __SSAX() argument
1611 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSAX()
1615 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) in __QSAX() argument
1619 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSAX()
1623 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) in __SHSAX() argument
1627 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSAX()
1631 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) in __USAX() argument
1635 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAX()
1639 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) in __UQSAX() argument
1643 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSAX()
1647 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) in __UHSAX() argument
1651 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSAX()
1655 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) in __USAD8() argument
1659 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAD8()
1663 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) in __USADA8() argument
1667 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __USADA8()
1693 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) in __UXTAB16() argument
1697 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UXTAB16()
1709 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) in __SXTAB16() argument
1713 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SXTAB16()
1717 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) in __SMUAD() argument
1721 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUAD()
1725 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) in __SMUADX() argument
1729 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUADX()
1733 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLAD() argument
1737 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLAD()
1741 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLADX() argument
1745 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLADX()
1749 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLALD() argument
1758 …ld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLALD()
1760 …ld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLALD()
1766 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLALDX() argument
1775 …dx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLALDX()
1777 …dx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLALDX()
1783 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) in __SMUSD() argument
1787 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSD()
1791 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) in __SMUSDX() argument
1795 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSDX()
1799 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSD() argument
1803 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSD()
1807 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) in __SMLSDX() argument
1811 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSDX()
1815 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLSLD() argument
1824 …ld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLSLD()
1826 …ld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLSLD()
1832 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) in __SMLSLDX() argument
1841 …dx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0])… in __SMLSLDX()
1843 …dx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1])… in __SMLSLDX()
1849 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) in __SEL() argument
1853 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SEL()
1857 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) in __QADD() argument
1861 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
1865 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) in __QSUB() argument
1869 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB()
1879 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1883 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()